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2023-05-07sb/intel/i82801ix: Drop __ASSEMBLER__ guardKyösti Mälkki
No longer needed, this was used with old SMM relocate code. Change-Id: I7c913e10eb965419c7d2ddede744f8140a5b7976 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-07sb/intel: Drop redundant definesKyösti Mälkki
Change-Id: I7655de5a8fcd5ac5c820938059bbb8b1ad877db7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-07sb/intel/common: Fix corner-case with KconfigKyösti Mälkki
To select COMMON_SMM should not imply COMMON_PMBASE, it's really a depencency. Select them both explicitly for i82801dx. Change-Id: I387ade9cfd38b6555ed9e37c1b9178a6da2d7260 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-06mb/intel/kblrvp: Clean smihandlerKyösti Mälkki
Change-Id: I0ada381883aa65d36434486dcce6b2331599e5c3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-06mb/google/jecht: Clean smihandlerKyösti Mälkki
Change-Id: I47ec05aa87e4e7c02b19817b2f703eca492008e6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-06soc/intel: Do CSE sync in romstage, unless ramstage chooses otherwiseSubrata Banik
This patch makes CSE sync in romstage default enabled unless ramstage config (SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE) chooses to override it. TEST=Able to build google/marasov with this change where CSE sync is performed early inside romstage. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3f5017fbcf917201eaf8233089050bd31c3d1917 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-05-06mb/google/rex/var/screebo: Add DDR DQ map configKun Liu
Add DDR DQ map config for screebo BUG=b:276814951,b:272218757 TEST=emerge-rex coreboot Change-Id: I993ae4024689b9cedbea247689a760bd83cd0d45 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74961 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-05-05mb/google/myst: Add variant makefileJon Murphy
Add variant makefile to support including the memory folder for Myst. BUG=b:273383819 TEST=Builds in chromium with blobs Change-Id: I03b0cd91dd66f357b15522da36f5118867b6b14c Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74964 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-05mb/google/fizz: Override SMBIOS product name based on OEM IDMatt DeVillier
Use the OEM ID from CBI to determine the correct OEM board name. ID mapping taken from ChromeEC source, branch firmware-fizz-10139.B. TEST=build/boot multiple fizz variants, check that board name reported correctly in SMBIOS tables. Change-Id: I06251974ac73570b911920ed566a175e8e733710 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74819 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-05-05mb/google/poppy/var/nami: Override SMBIOS product nameMatt DeVillier
Override SMBIOS product name with sub-variant name based on board SKU. TEST=build/boot multiple nami variants, verify SMBIOS product name reports correctly. Change-Id: I2125bfb6436469405378f9c983d7cfcb2f85f916 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-05-05vc/google: Decouple DSM_CALIB from CHROMEOSMatt DeVillier
DSM (Dynamic Speaker Management) uses calibration parameters stored in a VPD (Vital Product Data) FMAP region to configure the audio output via an ACPI _DSD table. This has no dependency on a ChromeOS, and can be used by Linux/Windows drivers if appropriately configured. Remove the dependency of DSM_CALIB (and the calibration file) on CHROMEOS and replace it with VPD, so that non-CHROMEOS builds can utilize this feature as well. Move files from underneath vc/google/chromeos to underscore the point. TEST=build/boot google/nightfury, dump ACPI, verify DSM calibraton parameters present in _DSD table. Change-Id: I643b3581bcc662befc9e30736dae806f94b055af Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74812 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-05-05Convert literal uses of CONFIG_MAINBOARD_{VENDOR,PART_NUMBER}Kyösti Mälkki
Only expand these strings in lib/identity.o. Change-Id: I8732bbeff8cf8a757bf32fdb615b1d0f97584585 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-05soc/amd/cmn/acpi/sleepstates.asl: Align with sb/amdAngel Pons
Adjust a few things so that the sleepstates.asl file is the same for sb/amd and soc/amd. These adjustments don't have a functional impact. Change-Id: I0cc9462b326cdc371ffdbf5759d8adc42456ce74 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74960 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-05{sb,soc}/amd/cmn/acpi/sleepstates.asl: Hook up configsAngel Pons
Commit cbc5d3f34b87db779829eabc90c32780a3865a56 ("soc/intel: Don't report _S1 state when unsupported") added the `ACPI_S1_NOT_SUPPORTED` option and commit 0eb5974def63a2fc0dce6dfdad62b0b4c6f4b865 ("acpigen: Add a runtime method to override exposed _Sx sleep states") added a mechanism to override the enabled sleep states at runtime. However, these were only hooked up to Intel sleepstates. so the options would not have any effect on AMD platforms. Apply the changes from these two commits to AMD sleepstates so that both options can be used on AMD platforms as well. Change-Id: I7d5ef2361e36659ac5c6f54b2c236d48713a07c9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74959 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-05src/soc/intel: Document meaning of variablesMaximilian Brune
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Iaf88f34cedd09e2461bb05050392e178ec84d5d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-05mb/google/brya/var/marasov: Disable Tccold HandshakeFrank Chu
The patch disables Tccold Handshake to prevent possible display flicker issue for marasov board. Please refer to Intel doc#723158 for more information. BUG=b:279117758 BRANCH=firmware-brya-14505.B TEST=Boot to OS on marasov. Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I286e88e5bec240d64e6c801648f6483ad2b0939c Reviewed-on: https://review.coreboot.org/c/coreboot/+/74931 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-05mb/purism/librem_cnl: Configure SuperIO for Librem Mini v1/v2Jonathon Hall
Configure the SuperIO and logical devices in the device tree. This overrides the power-on default state. UART1 was already enabled, and if ENABLE_EC_UART1 was selected in Kconfig, the LPC UART1 I/O range was also already enabled. The RTC/BRAM interface was enabled (and the BRAM1 base was 0x360 by default), but the LPC I/O range was not opened previously. Now it is open and BRAM bank 1 is accessible. Mouse/Keyboard are not wired to anything on this board and are now disabled. UART2, SMFI, power channel 1, and power channel 2 were enabled previously, but their LPC I/O ranges were not opened and they were not accessible to the OS. Fan control is performed by the EC on this board so there is no change. SWUC and power channels 3-5 were disabled by default, no change. Change-Id: I58a5a427737f4a2caa64326c110eb53ec00b347d Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-05-05mb/google/poppy/variant/nami - Move FPMCU IO setup back to ramstageTarun Tuli
variant_board_sku() is missing dependences in order to work correctly in romstage. Rather than more intrusive rework as its use is limited, move the FPMCU early GPIO init back to ramstage. We still meet sufficient power off time to fully power cycle the MCU. BUG=b:245954151 TEST=Confirmed FPMCU is still functional on Nami and FP tests all pass Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: Ia428ec5aec1a0438e91bc48903bda043046b740e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74695 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-05mb/google/octopus: Disable unused devices in devicetreeMatt DeVillier
The image processing unit/GMM and xDCI are not used on octopus boards; additionally, enabling xDCI can cause some problems with USB ports in both booting from the payload and in the OS. Change-Id: I1ee99b5c45881a4cf3624bf487bc9d83fb3d07a1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-05soc/intel/spr: Fix copy paste issue in error messagesFelix Singer
The commit a0b199c6b483 ("soc/intel/xeon_sp/spr: Add soc set_cmos_mrc_cold_boot_flag") introduced a copy-paste issue in two error messages. The error messages should mention the Intel platform SPR instead of CPX. Fix that. Change-Id: I4de61ec2cf9fbd98263a7a7a588938d548148656 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74956 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-04mb/google/puff: Add SOF chip driverMatt DeVillier
Add SOF chip driver entries for all variants, so that the correct audio config is passed to the OS drivers. TEST=build, boot Windows on wyvern variant, verify headphone output and microphone functional under Windows using coolstar's SOF drivers. Change-Id: I421c070eac321c2fc160b8f26868bcb1ec13001e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74815 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-05-04mb/google/volteer: Add SOF chip driverMatt DeVillier
Add SOF chip driver entries for all variants, so that the correct audio config is passed to the OS drivers. TEST=build, boot Windows on several volteer variants, verify audio functional under Windows using coolstar's SOF drivers. Change-Id: I62a96149cec9eeb7b2da8a2337083969a1b0fce0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74816 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-05-04mb/google/brya: Add SOF chip driverMatt DeVillier
Add SOF chip driver entries for all variants, so that the correct audio config is passed to the OS drivers. TEST=build, boot Windows on banshee and osiris variants, verify audio functional under Windows using coolstar's SOF drivers. Change-Id: I12614b85f9779cc40d83a9c868cc46b110f26af6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74817 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-05-04mb/google/dedede: Add SOF chip driverMatt DeVillier
Add all SOF chip drivers to baseboard and use FW_CONFIG to determine the correct option, to ensure the correct audio config is passed to the SOF OS drivers. TEST=build, boot Windows on several dedede variants, verify audio functional under Windows using coolstar's SOF drivers. Change-Id: I9452b11af614d8727aa8dd448e37f7a06faa450d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74818 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-05-04soc/amd/common/block/lpc/lpc: simplify index handling in read resourcesFelix Held
Now that we don't need to find a specific resource in the set resources function any more, there's no need to use hard-coded indices for the fixed resources. Instead use an index variable that gets incremented after each fixed resource got added. The index now starts at 0 instead of at 1, but now the only requirement is that those indices are unique. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ida5f1f001c622da2e31474b62832782f5f303a32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74849 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-05-04mb/siemens/mc_ehl: Remove subdir 'spd' from MakefileMario Scheithauer
Since commit 833bb448c521 ("mb/siemens/mc_ehl: Remove spd.bin from CBFS"), the subdir 'spd' is no longer necessary. Change-Id: Ibaf44e3181b2167aa83cffcc59835196e4cb5cdb Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-05-03mb/purism/librem_cnl: Remove unneeded explicit PNP enable for UARTJonathon Hall
Remove explicit PNP 6e.1 configuration for UART. This had no effect, the SuperIO is actually on I/O port 2e. Enabling the 8250IO driver is sufficient to use the UART, the UART device is enabled by default. Test: Build Mini v2 with and without CONFIG_ENABLE_EC_UART1, boot and check output on serial. Change-Id: Idbb39c81cadd633f4718f0682d231dc578d20325 Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74362 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-03ec/starlabs/merlin: Change the fallback value for fn_ctrl_swapSean Rhodes
Change the fallback value of the `fn_ctrl_swap` option to 0, which is disabled. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I76329ec59ba630c987a122bffb8045150facdf08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-05-03soc/amd/common/block/lpc/lpc: drop custom lpc_set_resourcesFelix Held
Drop the custom lpc_set_resources implementation that does some register access that has no effect and then calls pci_dev_set_resources and use pci_dev_set_resources for set_resources in amd_lpc_ops instead. The SPI controller's base address got configured early in boot in the lpc_set_spibase call and the enable bits got set early in boot in the lpc_enable_spi_rom call. TEST=The contents of the SPI_BASE_ADDRESS_REGISTER at the beginning and at the end of the call stay the same, so it's simply a no-op. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7a5e3e00b2e38eeb3e9dae6d6c83d11ef925ce22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-03soc/amd/common/block/lpc/lpc: report HPET MMIOFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I77471d464dddffc63bb2f005fef3a33c84ff5f5e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-03soc/amd/common/block/lpc/lpc: use mmio_range to report FCH IOAPIC MMIOFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I813a27e392a842188dc474018f82e10309783260 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-03soc/amd/common/block/lpc/lpc: report eSPI MMIOFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I63fb70da3e9ded6c05354f94ee69bc6dd04e58f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-03soc/amd/common/block/lpc/lpc: increase size of SPI BAR to 4kByteFelix Held
The memory map granularity for those devices is 4kByte. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8806128bdce8988f5cd7c8fa8a342fdb01eb7f42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-03soc/amd/common/block/lpc/lpc: report mapped SPI flash as MMIO rangeFelix Held
Since the 16MByte of memory-mapped SPI flash region right below the 4GB boundary is both a fixed region and isn't decoded on a device below the LPC device, but assumed to be decoded by the LPC device itself, it shouldn't be reported as a subtractive resource, but as an MMIO resource instead. TEST=On mandolin the 16MByte MMIO-mapped SPI flash now show up as a reserved region in the e820 memory map which wasn't the case before: 13. 00000000ff000000-00000000ffffffff: RESERVED The Linux kernel doesn't show any new or possibly related errors. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: Ib52df2b2d79a1e6213c3499984a5a1e0e25c058a Reviewed-on: https://review.coreboot.org/c/coreboot/+/74839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-03mb/google/brya/var/omnigul: Adjust I2C3 and I2C5 Waveform meet to SPECJamie Chen
Tuning i2c frequency ,timing ,Waveform meet to SPEC i2c frequency : I2C0=>399.8khz / Setup Time:1765ns / Hold Time:82.35ns. I2C1=>390.4khz / Setup Time:1.788us / Hold Time:70.58ns. I2C3=>308.7khz / Setup Time:1.482us / Hold Time:0.4us. I2C5=>390.8khz / Setup Time:1.218us / Hold Time:0.405us. BUG=b:275061994 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot, EE check OK with test FW and TP function is normal. Change-Id: I5b77cd3fd3ff00804f1b8dd5828dc831a9732566 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74880 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2023-05-03mainboard/intel/mtlrvp: Refactor the kconfig selectionsSridhar Siricilla
The patch orders MTL RVP board Kconfigs alphabetically. TEST=Build the code for mtlrvp Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ib8557aab2848a384fba5203e5f3d62407b2566ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/74838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2023-05-03Drop many cases of CONFIG_MAINBOARD_PART_NUMBERKyösti Mälkki
We have largely dropped from filling in mainboard_ops.name as unnecessary. A common place should be decided where or if this information is added in the console log. Change-Id: I917222922560c6273b4be91cd7d99ce2ff8e4231 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-03mb/google/hatch: Add SOF chip driverMatt DeVillier
Add SOF chip driver entries for all variants, so that the correct audio config is passed to the OS drivers. TEST=build, boot Windows on several hatch variants, verify audio functional under Windows using coolstar's SOF drivers. Change-Id: Ie791fa873fc7bbab84644f5ea5743bdcdc124908 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-05-03drivers/sof: Add new driver to generate ACPI _DSD tableMatt DeVillier
Add a new chip driver for boards which use SOF (Sound Open Firmware) OS drivers, which will be attached to the HDAS device and generate entries in an ACPI _DSD table for the OS driver to use. This will allow the OS drivers to easily determine the correct topology for the speaker and jack amplifiers and correct microphone configuration. TEST=tested with rest of patch train Change-Id: Ie0431b2002287f35245cbf959828e931d7f375b2 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-05-03soc/amd/phoenix: Add default vBIOS ID and locationMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Iadc32f4dbf8bd48d8666a213d7b5f3ba42175a90 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-03mb/google/reef: Disable unused devices in devicetreesMatt DeVillier
The image processing unit (Iunit) and SoC UARTS are not used on any reef boards. Change-Id: Iacdf93b4952cbc63fc465f07d440463106527b8d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-03mb/google/reef: Disable Intel Trace Hub PCI deviceMatt DeVillier
It's not particularly useful to end users, and shows up as an unknown PCI device under Windows Device Manager. TEST=build reef, boot Windows, verify unknown PCI device no longer present in Device Manager. Change-Id: Ie8ec46e2e07b6635bfe9766812ce08b866c71d66 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-02mb/google/myst: Inject SPD binaries to APCBKarthikeyan Ramasubramanian
Add rules to inject the variant specific SPD binaries into APCB. BUG=b:273383819 TEST=Build Myst BIOS image. Currently no APCB is present. So no SPD is injected into APCB. Change-Id: Ic511cdc4fe0989c9abc0cd0531cc0cae40f8dc34 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74746 Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-05-02mb/google/myst: Add initial memory configurationKarthikeyan Ramasubramanian
Generate the RAM Strap IDs based on the initial memory configuration. BUG=b:272746814 TEST=Build Myst BIOS image. Change-Id: I8a4fe9a41f101ac10391756f1b815220c8b98612 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-05-02soc/intel/alderlake: Disable C1E on RPL CPUsJoey Peng
Since disabling C1E could improve acoustic noise for RPL, add judgement in SOC code to disable C1E on RPL CPUs and enabling it on ADL CPUs . BUG=b:278654939 TEST:emerge-brya coreboot Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Ic2d2d5d6075de25141c1d08ec18838731c63a342 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-05-02Kconfig: Group dependency on X86EMU_DEBUGElyes Haouas
Change-Id: I6b53536a3d673350fa1b46891da2766b0bc149e8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-05-02soc/intel/alderlake: Select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN configSubrata Banik
At present the problem has only been reported with Alder Lake and Raptor Lake FSP where MultiPhaseSiInit API is unable to return any ERROR status. Hence, this patch ensures to select applicable W/A config to read FSP return status from the FSP Reset HOB. BUG=b:278665768 TEST=Able to select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN for ADL/RPL SoC code and call into this API to know the return status from MultiPhaseSiInit FSP API. Without this patch: IshInit() Start IshDisable() Start IshPerformGlobalReset() .... .... FSP returning control to Bootloader with reset required return status 40000003 FspMultiPhaseSiInit Index-1 returned 0 <-- after control returns into coreboot, the `status` from the FSP API is reset to `0` instead 0x40000003. Hence, coreboot avoid hitting the reset. With this patch: IshInit() Start IshDisable() Start IshPerformGlobalReset() .... .... FSP returning control to Bootloader with reset required return status 40000003 FSP: handling reset type 40000003 <-- coreboot is able to understand the reset request in proper. GLOBAL RESET! global_reset() called! HECI: Global Reset(Type:1) Command Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I18a918cca7e19e03ed6020c55c86c64a94212963 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74785 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-02drivers/intel/fsp2_0: Apply FSP Reset Status W/A for MultiPhaseSiInitSubrata Banik
This patch calls into fsp_get_pch_reset_status() to get the MultiPhaseSiInit API return status if FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN is enabled. Ideally FSP API should be able to return the status (both success and error code) upon exiting the FSP API but unfortunately there are some scenarios in ADL/RPL FSP where MultiPhaseSiInit API is unable to return any ERROR status. Hence, this function can be considered as an additional hook to read the FSP reset status by reading the dedicated HOB without relying on the FSP API exit status code. Any SoC platform that selects the FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN config will call into this newly added API to get the FSP return status from MultiPhaseSiInit. BUG=b:278665768 TEST=Able to select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN for ADL/RPL SoC code and call into this API to know the return status from MultiPhaseSiInit FSP API. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I749c9986e17e4cbab333b29425c9a4a4ba4128fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/74784 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
2023-05-02soc/intel/common: Introduce API to get the FSP Reset StatusSubrata Banik
This patch creates a function to read the FSP API Reset Status. This function relies on the FSP Scheduled Reset HOB which holds the reset type (warm/cold/shutdown) information along with any platform specific reset need (like global reset). Ideally FSP API should be able to return the status (both success and error code) upon exiting the FSP API but unfortunately there are some scenarios in ADL/RPL FSP where MultiPhaseSiInit API is unable to return any ERROR status. Hence, this function provides an additional hook to read the FSP reset status by reading the dedicated HOB without relying on the FSP API exit status code. Additionally, create FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN config option to handle broken FSP API return status issue. Any SoC platform that selects the `FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN` config will call into this newly added API to get the FSP return status from MultiPhaseSiInit. BUG=b:278665768 TEST=Able to select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN for ADL/RPL SoC code and call into this API to know the return status from MultiPhaseSiInit FSP API. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ief5d79736cc11a0a31ca2889128285795f8b5aae Reviewed-on: https://review.coreboot.org/c/coreboot/+/74783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-01protectcli/vault_bsw: Drop USB power control bits in GNVSKyösti Mälkki
There is no platform-level implementation for USB port power management in various sleepstates. This mainboard never evaluates the set GNVS variables S3U0, S3U1, S5U0 and S5U1 in ASL or in its SMI handlers. Change-Id: Ic7af2d608d95c6691f31ef1b8af72f96da20787c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-01mainboard/*: Drop USB power control bits in GNVSKyösti Mälkki
There is no platform-level implementation for USB port power management in various sleepstates. The mainboards changed here never evaluate the set GNVS variables S3U0, S3U1, S5U0 and S5U1 in ASL or in their SMI handlers. Change-Id: Ia1bc5969804a7346caac4ae93336efd9f0240c87 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
2023-05-01SMBIOS: Group Kconfig dependencyKyösti Mälkki
Change-Id: I5a75a7230fd78c0a9926adc491059f55647cc9a3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-01mb/google/volteer/Kconfig: Alphabetize variants, Kconfig selectionsMatt DeVillier
Change-Id: I634af65cd41e0d70e673d550ed8063abc6eea6d4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-05-01mb/google/volteer: Add VBT data files for variantsMatt DeVillier
Add data.vbt files for all variants supported by current volteer recovery image. Several boards use the same VBT, so place the "common" VBT under the baseboard directory and set it as the default. For variants with a unique VBT, override the default and use the file in their respective variant directory. Select INTEL_GMA_HAVE_VBT for all variants which have a VBT file. TEST=build/boot various volteer variants Change-Id: I728ab81938c78f600ff8931a8073d1f7de152c09 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74852 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-01soc/intel/adl: Unhide PMC, IOM ACPI devices from OSMatt DeVillier
These were hidden because no Windows drivers existed, but now that they do, the ACPI devices need to be visible in order for the drivers to properly attach. TEST=build google/banshee, boot Windows, verify Windows drivers correctly attach to PCM/IOM devices. Change-Id: Idbbaee29bffb49059d8450abd09e0c3f7b490fae Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74850 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-05-01soc/intel/tgl: Unhide PMC, IOM ACPI devices from OSMatt DeVillier
These were hidden because no Windows drivers existed, but now that they do, the ACPI devices need to be visible in order for the drivers to properly attach. TEST=build google/drobit, boot Windows, verify Windows drivers correctly attach to PCM/IOM devices. Change-Id: I1520a71e318674baa234fc6a2126d1d17933d983 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-05-01soc/amd/stoney/acpi: Unhide PCI0 root device from OSMatt DeVillier
In order for Windows to detect/load drivers for any child devices, the PCI0 root device status must be enabled and visible. TEST=build google/liara, boot Windows, verify PCI child devices visible in Device Manager. Change-Id: I3fb1ba11247f0811120a4cf8a4fd99342ae201de Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-01soc/intel/cmn/cse: Decouple ME_RW compression from CSE RW SyncAnil Kumar
The change 'commit Iac37aaa5ede5e1cd ("Add Kconfigs to indicate when CSE FW sync is performed")' adds support to choose CSE FW update to be performed in ROMSTAGE or RAMSTAGE. The patch also introduced a dependency on ME_RW firmware compression. This patch removes the dependency between CSE FW sync in RAMSTAGE and ME_RW firmware compression as these two are not related and should be decoupled to support CSE FW sync in RAMSTAGE without the requirement to compress ME_FW. Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I5ca4e4a993e4c4cc98b8829cbefff00b28e31549 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74796 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-05-01acpi: Add missing cbfs_unmap()Grzegorz Bernacki
cbfs_map() can allocate memory, so cbfs_unmap() should be called before leaving the function. BUG=b:278264488 TEST=Built and run with additional debugs on Skyrim device to confirm that data are correctly unmapped Change-Id: Ibf7ba6842f42404ad8bb415f8e7fda10403cbe2e Signed-off-by: Grzegorz Bernacki <bernacki@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-05-01mb/google/nissa/var/craask: avoid camera LED blinking during bootJimmy Su
Camera LED will blink several times as sensor is being probed during kernel boot. Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips initial probe during kernel boot and prevent privacy LED blink. BUG=b:274634319 TEST=Build and boot on Craask. Verify & observe Camera LED blinking behavior. Change-Id: I78ed5efe1e2c071d817c1e0455271886e89e63c7 Signed-off-by: Jimmy Su <jimmy.su@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74728 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-01mb/siemens/mc_ehl: Remove wrong comment regarding spd.binWerner Zeh
The support for a spd.bin from CBFS was removed for all mc_ehl boards in commit 833bb448c5213 (mb/siemens/mc_ehl: Remove spd.bin from CBFS). There is still a remaining comment in romstage_fsp_params.c referring to the removed capability. This fix removes the spd.bin related part of the comment to stay consistent with the code. Change-Id: I669ee1c33d1d1c47764640982f71129195e63f14 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74801 Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-05-01vendorcode/mediatek/mt8192: Cast enum typesArthur Heymans
Clang warns about using the wrong enum types as arguments. Change-Id: Idfebf2f6deec7d531cbda6667384b5f591bdc3cb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74546 Reviewed-by: Xixi Chen <xixi.chen@mediatek.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-05-01mb/prodrive/atlas: Enable/disable sleep states based on ECArthur Heymans
With the profile ATLAS_PROF_REALTIME_PERFORMANCE it is desired to not have the option to be able to enter sleep. The reason is that Microsoft Windows goes to sleep after 30min of inactivity by default. TEST: See that Microsoft Windows 11 has no 'Sleep' option in the start menu. Change-Id: I424db7e712a705c628aa3a10a486d3313404987a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74421 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-01acpigen: Add a runtime method to override exposed _Sx sleep statesArthur Heymans
This allows mainboards to override available sleep states at runtime. This is done by adding a IntObj in SSDT that DSDT consumes to override the available _Sx states. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ic21830c1ef9c183b1e3005cc1f8b7daf7e9ea998 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74762 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-29mb/starlabs/starbook: Let coreboot configure ASPMSean Rhodes
FSP is fractionally faster at configuring ASPM (1,118,688 vs 1,122,205) but coreboot's configuration results in lower power consumption of approximately 0.5W when idling - the reason why is unknown. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib15eaede956f0aa55118d093fdff0fd9487df250 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74520 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-29asus/p2b, emu/qemu-i440fx: Use acpigen_write_processor_device()Kyösti Mälkki
FADT duty_width/duty_offset fields, together with P_CNT (previously P_BLK) IO address are provided with _PTC entry. FADT p_lvl2/3_lat fields had values that disabled C2/C3 state transitions so _CST entries are not required. Change-Id: I629cd0793f6a64e955e197400efaa7d9d898e775 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-29mb/google/poppy/variant/nami - Ensure power cycle of FPMCU on startupTarun Tuli
Add functionality to ensure that the FPMCU is power cycled long enough on boot to ensure proper reset. This solution relies solely on coreboot to sequence the power and reset signals appropriately (150ms on boot). -Confirmed power is off for 150ms on boot. -Confirmed RCC_CSR of FPMCU indicates power cycle occurred. -Confirmed reset is de-asserted approx 3ms after power application (target >2.5ms) BUG=b:245954151 TEST=Confirmed FPMCU is still functional on Nami and timings are as expected. Change-Id: I0a23bda96bc2ea90be81a2310605f75c55c0a839 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-29mb/google/poppy: Add support for variant SKU romstage GPIO configsTarun Tuli
Add functionality that allows a variant SKU to have a specific set of GPIO configs in romstage (modeled after the existing one in ramstage) BUG=b:245954151 TEST=builds Change-Id: I593a23951306908fadc00e6bc8d9d310f09c5e4b Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-29mb/google/rex/variants/screebo: Generate RAM IDsKapil Porwal
Generate RAM IDs for - MT62F512M32D2DR-031 WT:B (LP5) H9JCNNNBK3MLYR-N6E (LP5) MT62F1G32D2DS-026 WT:B(LP5x) H58G56BK7BX068 (LP5X) BUG=b:276814951 TEST=Run part_id_gen tool without any errors Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I0fb2e488c06ed74d3fd493e5ca0ab89a825a9349 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74802 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-29sb,soc/amd,intel: Drop include <cpu/x86/smm.h>Kyösti Mälkki
I forgot to remove these in commit 0fe36db154eb ("ACPI: Make FADT entries for SMI architectural"). Change-Id: Ib1bc1dad6053ddb0454d4510917fd2bcf0901f35 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74811 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-29ACPI: Make FADT entries for RTC/CMOS architecturalKyösti Mälkki
For AMD, replace name RTC_ALT_CENTURY with RTC_CLK_ALTCENTURY that points to same offset. Since the century field inside RTC falls within the NVRAM space, and could interfere with OPTION_TABLE, it is now guarded with config USE_PC_CMOS_ALTCENTURY. There were no reference for the use of offset 0x48 for century. Change-Id: I965a83dc8daaa02ad0935bdde5ca50110adb014a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74601 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-28soc/amd/phoenix: Populate type 0x63 entry with right MRC CacheFred Reitberger
On boards with RECOVERY_MRC_CACHE FMAP section, populate type 0x63 BIOS directory entry in RO with that section. If the RECOVERY_MRC_CACHE section is not present, then fall back to RW_MRC_CACHE. BUG=b:270569389 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ic5ac87685eaa5fec717e3efa4df7af511b4ce8aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/73257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-04-28soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct PCI MMIO BAR windowFelix Held
This ports back commit d75ee46d3ce6 ("soc/amd/picasso/acpi: Change PCI0 BAR window") to Stoneyridge so that the correct end of the non-fixed MMIO region gets reported in PCI0's _CRS method. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I19153947cbb1b1b684291765eb1902caac65b9ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/74809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-04-28soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct number of PCI busesFelix Held
This ports commit 8c28e51a16e1 ("soc/amd/picasso: fix host bridge bus numbers") back to Stoneyridge so that the correct number of PCI buses gets reported from PCI0's _CRS method. The MCFG ACPI table already had the correct last bus number. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I40121ab0e0438281192b6a0bec8dbecdc1749379 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-04-28mb/starlabs/starbook/adl: Correct the number of NID entriesSean Rhodes
The number of NID entries was too high for the Realtek and Intel sound cards, preventing the verb table from loading. Now the values are correct; it loads as intended. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I79825313a4801c120a0a2a321cbabab7c728aa71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-04-28ec/starlabs/merlin: Change the fallback value for fn_ctrl_swapSean Rhodes
Change the fallback value of the `fn_ctrl_swap` option to 0, which is disabled. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9fcbb497f14ed0c97ff05c6c01a3929522786781 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-28ec/starlabs/merlin/acpi: Don't attempt to change EC valuesSean Rhodes
The EC will constantly update the battery variables approximately every 60 seconds; they should be used unmodified, rather than trying to change them. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3cff0ac6a322018cbca33b5f90dd62b3475da25c Reviewed-on: https://review.coreboot.org/c/coreboot/+/74186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-28mb/starlabs/starbook/adl: Correct port for Hot PlugSean Rhodes
Commit 5103b87a4d7b ("mb/starlabs/starbook/adl: Add an option to enable Hot Plug") introduced an option to enable Hot Plug for the SSD. The port was set to 4 (RP5) which is the wireless card. Change this to 8 (RP9) which is the SSD. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I884f4997d73e31bd422477952466f168afad66a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74738 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-28soc/intel/common/block/pmc: Sort Kconfig in alphabetical orderChristian Walter
Change-Id: I7392ede4226a940896c805fc0b0bc0dd615a964c Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74810 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-28treewide: Add missing include guards to chip.hJan Samek
Some of the chip.h files in the tree are missing the include guards. This patch adds them in order to avoid potential redefinions of symbols contained in these headers, when they are included multiple times in static.c generated by sconfig. Change-Id: I550a514e72a8dd4db602e7ceffccd81aa36446e3 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-28mb/google/rex/var/screebo: Add initial setup for gpio configKun Liu
add the initial gpio configuration for screebo initial variant BUG=b:276814951 TEST=emerge-rex coreboot Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Change-Id: Ib96e03f47bc1d6e5628ae459c3e1eb4dc18849c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74475 Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-28vga: Change the arguments of vga_write_text to support extended ASCIIHsuan Ting Chen
VGA defined the extended ASCII set based on CP437, but the function vga_write_text() accepts a signed char array. This will cause unnecessary confusion that if we want to print u with umlaut (code=129 in CP437), we need to explicitly cast it to -127 in signed char. Since we still want to leverage the built-in string utilities which only accepts const char*, we still need to cast it to signed char while processing, and cast it back to unsigned once we write into the frame buffer. BRANCH=brya BUG=b:264666392 TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: If555bbc05f40ce3f02339c0468afff6dda8b7ded Reviewed-on: https://review.coreboot.org/c/coreboot/+/73099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-04-28mb/google/skyrim: Enable SPL fusing on MarkarthJohn Su
Because SPL fuse needs to be set before the FW lock. So enable Markarth project to send the fuse SPL (security patch level) command to the PSP. BUG=b:279499511 BRANCH=none TEST=FW_NAME="Markarth" emerge-skyrim coreboot chromeos-bootimage Then get "PSP: SPL Fusing Update Requested." in the firmware log. Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I8fbbd89d11b1bdb2c95c761955c10bedb366fd70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74753 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-27arch/x86: Disable walkcbfs_asm code when CONFIG_CBFS_VERIFICATION is setJulius Werner
walkcbfs_asm is a simple CBFS implementation in assembly to find a file on a system with memory-mapped SPI flash. It seems to be mostly unused nowadays and is only still called for early microcode loading on some old systems (e.g. FSP 1.1 and older). Using this implementation with CONFIG_CBFS_VERIFICATION is unsafe because it does not verify the hashes the way the normal CBFS code does. Therefore, to avoid potential security vulnerabilities from creeping in, this patch makes sure the code cannot be compiled in when CBFS_VERIFICATION is active. That means it won't be supported on the old boards using this for microcode loading. Ideally CONFIG_CBFS_VERIFICATION should have a `depends on` to make this dependency more obvious in menuconfig, but the configs actually using this code are not easy to untangle (e.g. CONFIG_MICROCODE_UPDATE_PRE_RAM is just set everywhere by default although only very few boards are really using it, and a lot of different old Intel CPU models are linking in src/cpu/intel/car/non-evict/cache_as_ram.S without being united under a single Kconfig so that's not easy to change). To keep things simple, this patch will just prevent the code from being built and result in a linker error if a bad combination of Kconfigs is used together. Later patches can clean up the Kconfigs to better wrap that dependency if the affected boards are still of enough interest to be worth that effort. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I614a1b05881aa7c1539a7f7f296855ff708db56c Reviewed-on: https://review.coreboot.org/c/coreboot/+/74243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-04-27mb/google/skyrim/var/winterhold: Add support for K3KL6L60GM-MGCTRex Chou
Update Samsung 4G K3KL6L60GM-MGCT support BRANCH=None BUG=b:243337816 TEST=emerge-skyrim coreboot Change-Id: I89b9798c16635a32dff12f1c0b65737d3c16cd59 Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-04-27mb/google/rex: Add USB4 ANX7452 Rev 2 to USB_DB FW_CONFIGSubrata Banik
This patch adds new USB_DB FW_CONFIG to enable support for USB4 ANX7452 Rev 2. BUG=b:279647370 TEST=Able to build and boot google/rex with Proto 2 SKU Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I878b591e5919d05d3c5fc2eefdeb492e95d4f7b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-27mb/google/skyrim/var/winterhold: adjust the eDP panel power sequenceChris Wang
Set edp_panel_t9_ms to 8ms which means it will delay 8ms between backlight off and vary backlight off. BUG=b:271704149 BRANCH=Skyrim TEST=Build; Verify the UPD was passed to system integrated table; Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I952d05b18e29cf30256f43562a5052007c5c6268 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74790 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-27soc/amd/mendocino: update FSP parameters for eDP power sequence adjustmentChris Wang
Add UPD parameter for eDP power sequence adjustment. The edp_panel_t9_ms parameter is set for bloff to varybloff. BUG=b:271704149 BRANCH=Skyrim TEST=Build; Verify the UPD was pass to system integrated table. Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Id651c9cc4d6f4e27f6c78ca10ca12936d66ef43b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74789 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-27vc/amd/fsp/mendocino/FspmUpd: Add UPD to set eDP panel T9 vauleChris Wang
Add UPD edp_panel_t9_ms for eDP panel sequence adjustment. BUG=b:271704149 BRANCH=Skyrim Test=Build/Boot to ChromeOS Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Idc1a212e9c203584a6497fd6cbd3f995eeb030f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74788 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-27soc/amd/mendocino: rename pwr_on_vary_bl_to_blon to edp_panel_t8_msChris Wang
Rename the UPD pwr_on_vary_bl_to_blon to edp_panel_t8_ms to match the eDP sequence timing in milliseconds. BUG=b:271704149 BRANCH=Skyrim Test=Build/Boot to ChromeOS Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Iecdfe47cd9142d8a1ddeee0ec988d37b2a11028e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74787 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-27arch/x86/include/pci_io_cfg: introduce PCI_IO_CONFIG_[INDEX,DATA] defineFelix Held
Instead of having multiple instances of the same magic numbers in the code, introduce and use the PCI_IO_CONFIG_INDEX and PCI_IO_CONFIG_DATA definitions. TEST=Timeless build for Mandolin results in identical image. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If6f6f058180cf36cae7921ce3c7aaf1a0c75c7b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-27mb/google/nissa/var/yavilla: Add elan touchscreen supportTony Huang
Update devicetree to support ELAN I2C generic touchscreen. BUG=b:273791621 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I2779c2930d89ff42233f9b20bd8abdf6dc00c0e0 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74776 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-04-27drivers/intel/fsp2_0: Inject newline after printing EFI GUIDSubrata Banik
TEST=fsp_print_guid() output doesn't get cobbled with other serial output and now separated by a newline character. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8d47dbc5d493f86f14a1bbcf9cb5c16c0e12b841 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74781 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-27mb/google/corsola: Report SKU and panel ID for unprovisioned devicesRuihai Zhou
The MIPI panels will be used on the detachable variant starmie, and there will be different MIPI panels used on starmie. In order to make the different panels functional on unprovisioned devices, it needs to pass the SKU ID and panel ID to the payload to load the matched device tree for kernel. From the schematic, the starmie variant will read the LCM ID from ADC channel 5. BRANCH=corsola BUG=b:275470328 TEST=boot starmie and see FW screen display Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: I6339dc3c177fb8982f77fb3bd32dc00da735fce4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
2023-04-27ACPI: Make FADT entries for SMI architecturalKyösti Mälkki
Change-Id: I80aa71b813ab8e50801a66556d45ff66804ad349 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74600 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-27soc/amd: Drop acpi_fill_madt_irqoverride()Kyösti Mälkki
It is unused. The use of field irq is problematic as it should appear relative to IOAPIC GSI bases in the devicetree. Change-Id: I460fd5fde3a7fba5518ccfc153a266d097a95a39 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-27mb/google/brya/variants/hades: Correct and swap NV33 signalsTarun Tuli
The signals for the NV33 regulator were swapped (enable and power good). Switch these back to the way they should be: GPIO_NV33_PWR_EN GPP_E1 GPIO_NV33_PG GPP_E2 BUG=b:269371363 TEST=builds Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: Ic2a53103e1feadd7ecebd4bed02dcc34410b8e3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-04-26mb/amd/mayan: Update DXIO descriptors per schematicsAnand Vaikar
Change-Id: I8b536f8a1ff4eab06f37aec0f25704525dc1b64e Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-04-26mb/google/skyrim/var/winterhold: Change to read the eMMC clkreq insteadEricKY Cheng
Because WD SSD drive isn't holding the clock low for some reason. So we change to read eMMC clkreq signal instead. BRANCH=none BUG=b:274377518 TEST=emerge-skyrim coreboot chromeos-bootimage and verify ok. Change-Id: I1329386631dc54209db54ac146e4aafe95b6a3ac Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-04-26intel/mtl: Add get_cse_ver_from_cbfs functionAshish Kumar Mishra
This patch implements helper function get_cse_ver_from_cbfs() to retrieve the CSE Lite version from CBFE RW's metadata and calls the helper function from cse_check_update_status() TEST=Verified CSE Lite version in coreboot boot log Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Change-Id: Ie1bf186adfc3f87826a7ce9b0167a6bbe6767299 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74755 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>