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2024-07-11soc/intel/meteorlake: Conditional selection of CSE Lite PSRSubrata Banik
This patch makes the selection of `SOC_INTEL_CSE_LITE_PSR` conditional on both `MAINBOARD_HAS_CHROMEOS` and `SOC_INTEL_CSE_LITE_SKU` being enabled. This ensures that CSE Lite PSR is only active when both ChromeOS is the target platform and CSE sync is performed inside coreboot. BUG=b:305898363 TEST=Able to build google/rex. Change-Id: I7199c034bbe6e7f077650417da67fa544f0b49d5 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83396 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-11soc/intel: Extend CSE RW Update and ME read access for payload syncSubrata Banik
Modify the dependencies for `SOC_INTEL_CSE_RW_UPDATE` and `ME_REGION_ALLOW_CPU_READ_ACCESS` config options to include `SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD`. This allows these features to be enabled even when CSE sync is performed in the payload, not just within coreboot (when `SOC_INTEL_CSE_LITE_SKU` config is enabled). BUG=b:305898363 TEST=Builds and boots successfully: * google/rex0 with SOC_INTEL_CSE_LITE_SKU * google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD Change-Id: Id6ec19d74237f278e8383c89923523871b2cc2db Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-07-11soc/intel/meteorlake: Conditionally update CSE sync UPDs in FSP-MSubrata Banik
This patch updates FSP-M UPDs conditionally to ensure CSE firmware updates and VGA initialization control only when `SOC_INTEL_CSE_LITE_SKU` config is enabled. This ensures eSOL rendering is tied to CSE sync performed in coreboot, preventing unnecessary setup when sync is deferred to the payload. Deferring CSE sync to the payload results in the depthcharge screen. BUG=b:305898363 TEST=Builds and boots successfully: * google/rex0 with SOC_INTEL_CSE_LITE_SKU * google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD Change-Id: Iffdd4b1be4abba8c57e28542058a575cc6de674c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-07-11soc/intel/cmn/cse: Refactor CBMEM ID handling for flexibilitySubrata Banik
This patch refactors the handling of CSE CBMEM IDs to enable platforms to choose whether to perform CSE sync operations within coreboot or defer it to the payload. This separation improves code organization, ensuring `cse_lite.c` focuses on coreboot-specific CSE Lite tasks. Now, platforms can select: * `SOC_INTEL_CSE_LITE_SKU` for CSE sync within coreboot * `SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD` for deferred payload sync This change ensures mutually exclusive options, avoiding unnecessary SPI flash size increases. BUG=b:305898363 TEST=Builds and boots successfully: * google/rex0 with SOC_INTEL_CSE_LITE_SKU * google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD Change-Id: I74f70959715f9fd6d4d298faf310592874cc35d4 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83393 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-11mainboard/dell: Add new mainboard XPS 8300 (Sandy Bridge)Ronald Claveau
Mainboard is identified as 0Y2MRG. The version tested is with Nvidia dGPU (gfx 560ti). The flash is a 4MiB Winbond W25Q32BVSIG. It can be flashed internally with flashrom. Add a strap on the service mode pin of the mainboard for internal flash. Tested working: - SeaBIOS - All USB ports - SATA - dGPU - Ethernet - Environment control - GPIOs - S3 Sleep mode - WakeOnLan Change-Id: I7d394794fec580bc7aed3f6396ceb47d4a6fd059 Signed-off-by: Ronald Claveau <sousmangoosta@aliel.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-07-11drivers/qemu: Clarify config option name for QEMU display resolutionAlper Nebi Yasak
A previous commit splits out Cirrus display support from Bochs display support, with both using the pre-existing Bochs config options for the requested display resolution. Rename these config names to clarify they are not only specific to the Bochs display driver. Change-Id: Ie0a5e75731231bb768d7728867196c9ab5c53a00 Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-07-11drivers/qemu: Split Cirrus display support from Bochs display supportAlper Nebi Yasak
QEMU's Cirrus display device is supported along with the Bochs driver since commit 7905f9254ebc ("qemu: cirrus native video init"). It is no longer the default since QEMU 2.2. The code supporting it can work independently of the Bochs display driver and depends more heavily on port I/O and VGA support code, so split it from that code to make it easier to support the Bochs driver in other architectures. Change-Id: Ic9492b501ed4fdcbda6886db60b1e5348715e667 Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-07-11mainboard/qemu-aarch64: Set CONFIG_PCI_IOBASE to 0x3eff0000Alper Nebi Yasak
Define the PCI I/O base address necessary to use port I/O functions on the qemu-aarch64 mainboard, so that we can get the VGA display devices working. The config value is from hw/arm/virt.c [1]: [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, [1] https://gitlab.com/qemu-project/qemu/-/blob/v8.2.3/hw/arm/virt.c#L164 Change-Id: I85439ba68740d64f789983b37d9c95f849ce4f72 Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82059 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-11sb/intel/smbus: Implement smbus_send_byte()Nico Huber
Allows to use this driver for the SMBus console without sending an index byte for every sent char (i.e. !CONSOLE_I2C_SMBUS_HAVE_DATA_REGISTER). Tested with WiP VIA CX700-M2 port and FT4222H as receiver. Change-Id: Ic368ef379039b104064c9a91474b188646388dd2 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82763 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-11soc/amd/phoenix: Fix APOB NV size/base for non-vboot buildsMatt DeVillier
The APOB NV size/base are embedded into the amdfw binary and read by the PSP. These need to be synchronized with the FMAP region used by coreboot to store the APOB data. soc_update_apob_cache() will only use RECOVERY_MRC_CACHE if supported and if vboot is enabled, so the NV base passed to the PSP needs to reflect that as well. This fixes the issue of RAM training running on every boot on non-vboot builds for Myst boards. TEST=untested, but same change as made for Mendocino Change-Id: Ib4a78a39badf0a067e22eebe5869e5ea51723f35 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2024-07-11soc/amd/mendocino: Fix APOB NV size/base for non-vboot buildsMatt DeVillier
The APOB NV size/base are embedded into the amdfw binary and read by the PSP. These need to be synchronized with the FMAP region used by coreboot to store the APOB data. soc_update_apob_cache() will only use RECOVERY_MRC_CACHE if supported and if vboot is enabled, so the NV base passed to the PSP needs to reflect that as well. This fixes the issue of RAM training running on every boot on non-vboot builds for Skyrim boards. TEST=build/boot Skyrim (Frostflow), verify RAM training only run on first boot after flashing. Change-Id: I9be1699d675331b46ee9c42570700c2b72588025 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83400 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2024-07-11console/i2c_smbus: Allow to send data w/o register offsetNico Huber
Not every I2C target requires a register address. Not sending one for every console char saves us a lot of overhead. Change-Id: I1c714768fdd4aea4885e40a85d21fa42414ce32c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82762 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-10console: Fix I2C/SMBus console if it's the only slow oneNico Huber
Change-Id: Ie44fdac6904a4467e408882bb8a5e08e6ff73f32 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82761 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-07-10cbmem_top: Change the return value to uintptr_tElyes Haouas
Change-Id: Ib757c0548f6f643747ba8d70228b3d6dfa5182cd Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82752 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-10mb/google/brask/var/bujia: Add wireless and memory thermal sensorShon Wang
Bujia has 4 thermal sensors, so add two missing sensors settings. BUG=b:351917517 BRANCH=firmware-brya-14505.B TEST= USE="-project_all project_bujia" emerge-brask coreboot. check ACPI SSDT table have new TSR info. $ cat /sys/firmware/acpi/tables/SSDT > SSDT $ iasl -d SSDT check SSDT.dsl Change-Id: Id9a17a22a717faac829e6b5e300351187a62dd43 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-10emulation/qemu-q35: Remove redefine TSEG_SZ_MASKElyes Haouas
TSEG_SZ_MASK is already defined in "q35.h" Change-Id: I32ea08c18e1c41d16137ea14a1643f8c8d527722 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83386 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-09ec/google/chromeec: Stop checking CBI for UCSIAbhishek Pandit-Subedi
The ucsi_enabled flag is no longer used by the EC. Update coreboot to only use only EC_FEATURE_UCSI_PPM to determine whether UCSI is enabled. BUG=b:319124515 TEST=emerge-brox coreboot chromeos-bootimage Cq-Depend: chromium:5664227 Change-Id: Ia9d820c637e56a527fd90f45b1848158a960dee7 Signed-off-by: Abhishek Pandit-Subedi <abhishekpandit@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83252 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Forest Mittelberg <bmbm@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-09mb/asrock/z97_extreme6: Fix EDID mapping for DVI-IAngel Pons
This board has a DVI-I connector, which supports both digital and analog display outputs. The I2C bus to retrieve the EDID is shared between both outputs, so `select GFX_GMA_ANALOG_I2C_HDMI_B` to describe this. Can't currently test this due to lack of hardware. Change-Id: Ib8239917e2f7ee5bb982621752ec406c2d3ca302 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82753 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-07-08chromeec: support reading long battery stringsPeter Marheine
The Chrome EC currently supports two ways to read battery strings on ACPI platforms: * Read up to 8 bytes from EC shared memory BMFG, BMOD, ... * Send a EC_CMD_BATTERY_GET_STATIC host command and read strings from the response. This is assumed to be exclusively controlled by the OS, because host commands' use of buffers is prone to race conditions. To support readout of longer strings via ACPI mechanisms, this change adds support for EC_ACPI_MEM_STRINGS_FIFO (https://crrev.com/c/5581473) and allows ACPI firmware to read strings of arbitrary length (currently limited to 64 characters in the implementation) from the EC and to determine whether this function is supported by the EC (falling back to shared memory if not). BUG=b:339171261 TEST=on yaviks, the EC console logs FIFO readout messages when used in ACPI and correct strings are shown in the OS. If EC support is removed, correct strings are still shown in the OS. BRANCH=nissa Change-Id: Ia29cacb7d86402490f9ac458f0be50e3f2192b04 Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-07-08cpu/intel/model_206ax: Allow PL1/PL2 configurationAnastasios Koutian
Tested on ThinkPad T420 with the i7-3940XM. Change-Id: I064af25ec4805fae755eea52c4c9c6d4386c0aee Signed-off-by: Anastasios Koutian <akoutian2@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-07-08mb/google/brox/var/lotso: Update DTT settings for thermal controlKun Liu
update DTT settings for thermal control,according to b:348285763#comment6. BUG=b:348285763 TEST=emerge-brox coreboot Change-Id: I67e16a2596884d501273a5787119406dff7a20f9 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83304 Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-08mb/google/brya: Select Intel PDC to PMC CONFIGURATION for orisaAmanda Huang
Orisa uses PDC<->PMC direct connection for USBC mux configuration. Select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION to enable it. BUG=b:345070027 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I3f740bedc8ff667d15f077fa57d201ab0d42ebf8 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83324 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
2024-07-08mb/google/trulo/var/orisa: Add fw_config field for PDC controlAmanda Huang
Add a new fw config field to determine which firmware edition shall be flashed to the PDC. BUG=b:334793686 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I817e9415aca1d2f68b484d8e23b581e1a75d6f84 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83353 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-05tgl mainboards: Move PCIe root port settings into their device scopeFelix Singer
Change-Id: I110cc95d536cb0fd3b5db85b84cca7a96e31401c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83253 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-05mb/google/brox/var/lotso: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFSWentao Qin
SKU1 is UFS, SKU2 is NON-UFS, it needs to select this config to disable the MPHY clock in the SKU2 configuration to ensure that S0ix functions normally. BUG=b:350609955 BRANCH=None TEST=Boot image on SKU1/SKU2 and check S0ix working. Change-Id: I2fbcc7ffaabf3c085a3345ec94a8d45b225b3450 Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-04soc/amd/common/acpi/ivrs: use PCI_DEVFN macroFelix Held
Use the PCI_DEVFN macro to make the calculation of the ivhd->device_id value a bit clearer. TEST=Timeless build results in identical binary for Mandolin Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7b7949ad3524790e7d7d527c488a32e785f55bc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83343 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-04mb/google/lotso: Add hid report address for gt7986uKun Liu
Add hid report address for gt7986u. BUG=b:342932183 BRANCH=None TEST=Verify touchscreen work normal. Change-Id: I464c2691505083314528519f608108c8a31e6cc0 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83201 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-07-04drivers/spi/acpi: Update generic property listKun Liu
Update generic property list for build test result fail https://qa.coreboot.org/job/coreboot-gerrit/259702/ BUG=b:342932183 BRANCH=None TEST=emerge-brox coreboot Change-Id: Iecd8573343706184dce5edfc12fe7a143390e0e9 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83301 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
2024-07-04mb/google/nissa/var/domika: Create a domika variantWisley Chen
This patch creates a new domika variant which is a Twin Lake platform. This variant uses Yavilla board mounted with the Twin Lake SOC and hence the plan is to reuse the existing yavilla code. BUG=b:350399367 BRANCH=firmware-nissa-15217.B TEST=build, and boot into OS Change-Id: I42c56770f8b8d6018592253d2bb16b8166eb5719 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-04mb/google/brya: disable early EC sync for orisaAmanda Huang
Disable VBOOT_EARLY_EC_SYNC for all trulo boards. BUG=b:345112878 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I10b027d19dedbb190fc960b949017f9e4830d52a Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83303 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-07-03soc/intel/xeon_sp/gnr: Add soc_pci_domain_fill_ssdtShuo Liu
Domain device objects are created with HID/CID/UID/_OSC/_PXM Dynamic domain SSDT generation could benefit the support of SoCs with multiple SKUs, or the case where one set of codes supports multiple SoCs. One possible side-effect might be the extra performance cost for generating these tables, which should not bring big impact on high performance server CPUs. GNR codes run with dynamic domain SSDT generation to fit for both GraniteRapids and SierraForest SoCs. TEST=Build on intel/avenuecity CRB TEST=Build on intel/beechnutcity CRB Change-Id: I28bfdf74d8044235f79f67d832860d8b4306670c Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-07-03mb/asrock: Add Z97E-ITX/ac (Haswell/Broadwell)Jan Philipp Groß
This is a rudimentary port of this board. It was done with Haswell Autoport, wherein some adjustments for Broadwell were made (Thanks to Angel Pons!). The VBT was copied from /sys/kernel/debug/dri/1/i915_vbt on version 2.20 of the vendor firmware. Working: - Broadwell MRC.bin - S3 suspend and resume - All DIMM slots - Libgfxinit - HDMI-Out Port - DVI-I Port (including passive DVI to VGA adapter) - USB 2.0 Ports - USB 3.1 Gen1 - RJ-45 LAN Port - SATA3 6.0 Gb/s Connectors - m.2 PCIe SSD - mPCIe WiFi slot - x16 PCIe slot - USB 3.1 Gen1 Header - Front Panel Audio Connector - edk2 Not yet tested: - SATA Express 10 Gb/s Connector - HDMI-In Port - DisplayPort 1.2 - Optical SPDIF Out Port - PS/2 Mouse/Keyboard Port - USB 2.0 Headers Not working: - Broadwell CPUs, see commit f5105313cf69 (mb/asrock/z97_extreme6: Add new mainboard) Special thanks to Angel Pons for guiding me through the process of porting this board and pushing it to Gerrit! Change-Id: I3b940e9281814e8360900221714c0dfa3ae39540 Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82760 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-07-03mb/google/rex: Set cnvi_wifi bluetooth companion deviceJeremy Compostella
To publish the Bluetooth Regulator Domain Settings under the right ACPI device scope, the wifi generic driver requires the bluetooth companion to be set accordingly. BUG=b:348345301 BRANCH=firmware-rex-15709.B TEST=BRDS method is added to the CNVW device and return the data supplied by the SAR binary blob Change-Id: I7f56ab8ac88c1fbc0b223b4286d2a998e424a46e Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83299 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-03drivers/wifi: Support 320Mhz Bandwidth Enablement per MCCPoornima Tom
Add support for the configuration of 320MHz Bandwidth per MCC based on countries. The implementation follows document #559910 Intel Connectivity Platforms BIOS Guidelines revision 8.3. BUG=b:333804562 BRANCH=firmware-rex-15709.B TEST=WBEM method is added to the CNVW device and return the data supplied by the SAR binary blob Change-Id: Ie76794825f1a0104d199c078aa4ffc714aa95b17 Signed-off-by: Poornima Tom <poornima.tom@intel.com> Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81790 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-03drivers/wifi: Support Bluetooth Regulator Domain SettingsJeremy Compostella
The 'Bluetooth Increased Power Mode - SAR Limitation' feature provides ability to utilize increased device Transmit power capability for Bluetooth applications in coordination with Wi-Fi adhering to product SAR limit when Bluetooth and Wi-Fi run together. This commit introduces a `bluetooth_companion' field to the generic Wi-Fi drivers chip data. This field can be set in the board design device tree to supply the bluetooth device for which the BRDS function must be created. This feature is required for Meteor Lake rex karis variant. The implementation follows document 559910 Intel Connectivity Platforms BIOS Guideline revision 8.3 specification. BUG=b:348345301 BRANCH=firmware-rex-15709.B TEST=BRDS method is added to the CNVW device and return the data supplied by the SAR binary blob Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e209 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83200 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-03mb/asrock: Add Fatal1ty Z87 Professional (Haswell)Jan Philipp Groß
This port was done via autoport and subsequent manual tweaking. Thanks to Angel Pons for helping me with the misbehaving ASM1061 ASPM! The board features two socketed DIP-8 SPI flash chips, as well as a BIOS selection via jumper and onboard Power and Reset switches. Working: - Haswell MRC.bin - All four DDR3/DDR3L DIMM slots - S3 suspend and resume - Libgfxinit - HDMI-Out Port - both RJ-45 Gigabit LAN Ports - USB 2.0 Ports - USB 3.1 Gen1 Ports - both USB 3.1 Gen1 headers - HD Audio Jack (audio output) - all six SATA3 6.0 Gb/s connectors by Intel - all four SATA3 6.0 Gb/s connectors by ASMedia ASM1061 - all three PCI Express 3.0 x16 slots - PCI Express 2.0 x1 slot - half mini-PCI Express slot Working (board-specific) - Power Switch with LED (functional, yet no LED) - Reset Switch with LED (functional, yet no LED) - BIOS Selection via jumper not (yet) tested: - IR header - COM Port header - DisplayPort - eSATA connector - USB 2.0 headers - PS/2 Mouse/Keyboard Port - HDMI-In Port - PCI slots not (yet) working: - Front panel audio connector - Software fan control: While the Nuvoton chip is correctly discovered, the numbering of the fan connectors is faulty, resulting in the wrong fan being controlled. - Dr. Debug: on vendor firmware, the LEDs turn off after successful boot. On coreboot, the LED shows two bright zeros after boot. Change-Id: Iae0b73d8e81be90ec3a2d5463df3ed170f603266 Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-07-03mb/google/geralt: Replace GERALT_USE_MAX98390 with FW_CONFIG for TAS2563Rui Zhou
Use FW_CONFIG to differentiate MAX98390 and TAS2563. Since config GERALT_USE_MAX98390 is no longer needed after using FW_CONFIG, we remove GERALT_USE_MAX98390 from Kconfig. BUG=b:345629159 BRANCH=none TEST=emerge-GERALT coreboot TEST=Verify beep function through deploy in depthcharge successfully. Change-Id: Ie9f0cbc30dd950b85581fc1924fa351efe1e0aab Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-07-03mb/google/ovis/variants/deku: Add K3KL9L90CM-MGCT to RAM ID tableTony Huang
Add RAM ID for K3KL9L90CM-MGCT 0 (0000) BUG=b:320203629 BRANCH=firmware-rex-15709.B TEST=Run part_id_gen tool without any errors Change-Id: Icb84838a6964b9318ded0573ad58a4fd1221867f Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83300 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-03mb/google/brox/var/lotso: Tune I2C frequency for 400 kHzJing Tong
Before: I2C0 - 401kHz I2C4 - 405kHz After: I2C0 - 392kHz I2C4 - 395kHz HW: Change R8409/R8411 to 33ohm. BUG=b:349743464,b:349735055 TEST=emerge-brox sys-boot/coreboot Test pass by EE Change-Id: I985837b1b80e973f148529b446905580c0f95e98 Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83290 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
2024-07-03soc/intel/xeon_sp/gnr: Support fast bootGang Chen
Fast boot will used pre-saved hardware configuration data to accelerate the boot process, e.g. DDR training is skipped by using pre-saved training data. Enable fast boot on cold and warm resets by default. Change-Id: Ib5dc76176b16ea1be5dd9b05a375c9179411f590 Signed-off-by: Gang Chen <gang.c.chen@intel.com> Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-07-03security/vboot: Set VBOOT_ALWAYS_ENABLE_DISPLAY if BMP_LOGOYu-Ping Wu
If BMP_LOGO is set, currently display_init_required() will always return 1, so that platform code will always initialize display. However, that information isn't passed to vboot, which may result in unnecessary extra reboots, for example when the payload needs to request display init (by vb2api_need_reboot_for_display()). Since there is already a Kconfig option VBOOT_ALWAYS_ENABLE_DISPLAY to tell vboot that "display is available on this boot", enable it by default if BMP_LOGO is set. BUG=b:345085042 TEST=none BRANCH=none Change-Id: I20113ec464aa036d0498dedb50f0e82cb677ae93 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-07-03mb/gigabyte/ga-h61m-series: Initial GA-H61M-S2P-R3 bringupPugzAreCute
Working: - Both DIMM slots - All Rear USB 2.0 ports - Integrated graphics (libgfxinit) - Realtek RTL8111F GbE - Flashing internally with flashrom (Note: Works from stock too due to Gigabyte not following Intel recommendations, confusing ME) - SeaBIOS (1.16.3) to boot Arch Linux Installer - EDK II (uefipayload_202309, MrChromebox) to boot Arch Linux Installer - Audio output (green jack, rear) - S3 suspend/resume - VBT Untested for now (i.e. should work, will eventually test): - EHCI debug - Front USB 2.0 ports - The other audio jacks - PCIe ports - Non-Linux OSes Untestable (i.e. cannot test due to unavailable hardware): - PS/2 port - Serial port - SATA ports Not working: - USB 3.0 ports: The on-board VLI VL805 does not have a flash chip, so its firmware needs to be loaded on each boot. However, documentation about the (chip-specific) firmware loading procedure is nowhere to be found. - Super I/O automatic fan control: not yet implemented in coreboot. To control fans, use software fan control methods in the meantime. Change-Id: I106c195c890823f07227739c6b30133b996f6510 Signed-off-by: PugzAreCute <me@pugzarecute.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83267 Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-07-03soc/intel/common: Skip ME version log for Lite SKUSubrata Banik
This change skips the ME firmware version logging in print_me_fw_version() if the ME firmware SKU is detected as Lite SKU. The reasoning is that the RO (BP1) and RW (BP2) versions are already logged by the cse_print_boot_partition_info() function for Lite SKUs, making the additional log redundant. The check for the Lite SKU has been moved to print_me_fw_version(), where the decision to print the version is made, instead of in get_me_fw_version(), where the version information is retrieved. TEST=Able to build and boot google/rex. w/o this patch: [DEBUG] ME: Version: Unavailable w/ this patch: Unable to see such debug msg. Change-Id: Ic3843109326153d5060c2c4c25936aaa6b4cddda Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-07-03soc/intel/cmn/cse: Make ME firmware version query function staticSubrata Banik
This change modifies the get_me_fw_version() function to be statically scoped within src/soc/intel/common/block/cse/cse.c, as it is only used by the print_me_fw_version() function in the same file. The function declaration is also removed from intelblocks/cse.h. The order of the function definitions in cse.c was also changed to be more logical, with the now static helper function get_me_fw_version() defined first, before it is used. TEST=Able to build google/rex. Change-Id: Idd3a6431cfa824227361c7ed4f0d5300f1d04846 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83257 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-03soc/intel/cmn/cse: Conditionally disable ME status reportingSubrata Banik
This patch disables the ME status reporting functionality (dump_me_status, print_me_fw_version) in the CSE driver when SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD is defined. This is likely intended for platforms or configurations where the CSE communication is only limited to payload. BUG=b:305898363 TEST=Able to build google/rex. Change-Id: I5e360408a7847968117df475ff244d79ceafa23f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83233 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-03drivers/intel/ish: Skip ISH version call if CSE sync is done by payloadSubrata Banik
This patch skips the ISH firmware version print when CSE sync is done by payload. The payload is responsible to dump the ISH version as ISH version resides into the CSE boot partition table. BUG=b:305898363 TEST=Able to build google/rex. Change-Id: I1895a4d3c44838a9cc6380912f09aa4f0e6687bd Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-03soc/intel/cmn/cse: Skip CSE version call if sync is done by payloadSubrata Banik
This patch skips the CSE firmware version print when CSE sync is done by payload. The payload is responsible to dump the CSE version. BUG=b:305898363 TEST=Able to build google/rex. Change-Id: I1a9e5583c79ebd81291a4b3ae24529b4582502cb Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-03soc/intel/cmn/cse: Modify dependency on CSE EOP configsSubrata Banik
Refactor CSE lite End-of-Post (EOP) configs to support the alternative of sending CSE communication from the payload. When the SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD config is selected, coreboot will skip initiating CSE EOP operations and rely on the payload CSE driver implementation. The following configs are modified to ensure coreboot skips CSE communication when SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD is enabled: - SOC_INTEL_CSE_SEND_EOP_EARLY - SOC_INTEL_CSE_SEND_EOP_LATE - SOC_INTEL_CSE_SEND_EOP_ASYNC - SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD BUG=b:305898363 TEST=Able to build google/rex. Change-Id: Ia6b616163d02be8d637b134fd3728c391fc63c90 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83229 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-03soc/intel/cmn/cse: Modify dependency on CSE lite configsSubrata Banik
Refactor CSE lite configs (specifically CSE sync related) to support the alternative of sending CSE communication from the payload. When the SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD config is selected, coreboot will skip initiating CSE sync operations and rely on the payload CSE driver implementation. The following configs are modified to ensure coreboot skips CSE communication when SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD is enabled: - SOC_INTEL_CSE_LITE_PSR - SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY - SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE - SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE BUG=b:305898363 TEST=Able to build google/rex. Change-Id: I5ddaf6e29949231db84b14bf7ea2d34866bb8e6c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83228 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-07-03tree: Use <console/console.h> only when usedElyes Haouas
Change-Id: I3cb1f11beba61afdf2be6188bde9ff135f8ace50 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-07-02mb/asrock: Add Z87M OC Formula (Haswell)Jan Philipp Groß
This port was done via autoport and subsequent manual tweaking. Special thanks to Nicholas Chin! This port would have never succeeded without his help. The board features two socketed DIP-8 SPI flash chips, as well as a BIOS selection switch and onboard Power and Reset switches. Working: - Haswell MRC.bin - All four DDR3/DDR3L DIMM slots - S3 suspend and resume - Libgfxinit - HDMI-Out Port - USB 2.0 Ports - Vertical Type A USB 2.0 - USB 3.1 Gen1 Ports - HD Audio Jack (audio output) - Front panel audio connector (audio output) - RJ-45 Gigabit LAN Port - SATA3 6.0 Gb/s connectors - mSATA/mini-PCI Express slot - half mini-PCI Express slot - PCI Express 3.0 x16 slots (both) - PCI Express 2.0 x4 slot - PCI Express 2.0 x1 slot Working (board-specific) - Power Switch with LED (functional, yet no LED) - Reset Switch with LED (functional, yet no LED) - BIOS Selection Switch - Slow Mode Switch (locks the CPU at 800MHz) not (yet) tested: - IR header - COM Port header - Power LED header - eSATA connector - USB 2.0 headers - PS/2 Mouse/Keyboard Port - HDMI-In Port - Optical SPDIF Out Port not (yet) working: - Software fan control: While the Nuvoton chip is correctly discovered, the numbering of the fan connectors is faulty, resulting in the wrong fan being controlled. - Dr. Debug: on vendor firmware, the LEDs turn off after successful boot. On coreboot, the LED shows two bright zeros after boot. - Post Status Checker (PSC) Change-Id: Iaa156b34ed65e66dd5de5a26010409999a5f8746 Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-07-023rdparty/fsp: Update submodule to upstream masterFelix Singer
The filename of the Elkhart Lake FSP binary changed in the FSP repository. It's unlikely that it will be renamed to the original name soon. Thus, update the filename in the coreboot repository. Updating from commit id cc6399e: 2024-03-04 15:40:41 +0800 - (IoT MTL-UH & MTL-PS PV (3471_49) FSP) to commit id 800c857: 2024-06-25 15:47:28 +0800 - (Update Fsp.fd) This brings in 23 new commits: 800c857 Update Fsp.fd 41e4590 NEX AZB IPU24.4 (5254_00) FSP 0efd8a3 IoT RPL-PS PV (5045_47) FSP 196e3fe Update README.md 380afd8 Update README.md 5dc88ca NEX ADL-PS IPU24.3/MR6 (5045_02) FSP 22762e9 Merge branch 'master' of https://github.com/intel/FSP 8134dbd Elkhart Lake IPU2024.3 FSP 3819544 add required SECURITY.md file for OSSF Scorecard compliance a6ee963 Delete AlderLakeFspBinPkg.dec 9d819ea Deprecate Client/AlderLakeFspBinPkg f963690 Raptor Lake FSP C.1.C8.50 f67f9ef Raptor Lake FSP C.0.C8.50 68c3cfa NEX ADL-PS IPU 2024.3 (5045_02) FSP f0d04d9 NEX ADL-P IPU 2024.3 (5045_02) FSP 6fa139c NEX ADL-S IPU 2024.3 (5045_02) FSP c4af5ac NEX TGL IPU 2024.3 (7092_01) FSP 8cf0372 IoT ADL-N MR4 (5061_00) e5ceb0b Merge branch 'master' of https://github.com/intel/FSP aada6a5 Elkhart Lake IPU2024.2 FSP 90d1d3b Update README.md 1a5a3ee Testing 61c069a NEX RPL-S MR3 (4445_03) FSP Change-Id: I47013bce65054f2c496c9aa7c16e55b51d65e5fe Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83294 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-01nb/intel/sandybridge/chipset.cb: Add alias for `cpu_cluster`Angel Pons
Define a devicetree alias for `cpu_cluster` so that it can be referenced in C code as `DEV_PTR(cpu_bus)`. Change-Id: Id6ead3d98d8fc17cab44ecf0b2af60a23187e036 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-07-01commonlib/bsd/lz4_wrapper.c: Fix misaligned accessMaximilian Brune
Currently the HiFive Unleashed produces the following exception: [DEBUG] Exception: Load address misaligned [DEBUG] Hart ID: 0 [DEBUG] Previous mode: machine [DEBUG] Bad instruction pc: 0x080010d0 [DEBUG] Bad address: 0x08026ab3 [DEBUG] Stored ra: 0x080010c8 [DEBUG] Stored sp: 0x08010cc8 The coreboot LZ4 decompression code does some misaligned access during decompression which the FU540 apparently does not support in SRAM. Make the compiler generate code that adheres to natural alignment by fixing the LZ4_readLE16() function and creating LZ4_readLE32(). Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Id165829bfd35be2bce2bbb019c208a304f627add Reviewed-on: https://review.coreboot.org/c/coreboot/+/81910 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-01drivers/spi/acpi: Add generic property listKun Liu
The touchscreen vendor (Goodix) needs to use this value (hid-report-addr) in the touch driver, and this value needs to be changed later.So add generic property list to allow populating vendor specific device properties to ACPI SSDT table. BUG=b:342932183 BRANCH=None TEST=emerge-brox coreboot Change-Id: I8b18e0a2925e6fd36e3a470bde9910661b7558b8 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83139 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-01soc/nvidia: Remove unneeded white spacesElyes Haouas
Change-Id: Ifd19cdcfbdf0b01984e0db0aa880fdcb256663b4 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-07-01mb/google/corsola/var/wugtrio: Add LCE_LMFBX101117480 MIPI panelYang Wu
Add LCE_LMFBX101117480 MIPI panel for Wugtrio. Datasheet: LMFBX101117480-10.1-TLCM-24.05.20-2.pdf BUG=b:331870701 TEST=emerge-staryu coreboot chromeos-bootimage BRANCH=corsola Change-Id: I863e172400ffb26b5c9c240a21d15c6a2240b4ad Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-07-01drivers/mipi: Add support for LCE_LMFBX101117480 panelYang Wu
Add STA panel LCE_LMFBX101117480 serializable data to CBFS. Datasheet: LMFBX101117480-10.1-TLCM-24.05.20-2.pdf About the init code, we communicated with the vendor through the datasheet to confirm the writing method of each register value. BUG=b:331870701 TEST=build and check the CBFS includes the panel BRANCH=None Change-Id: I60858109e4b07f720461e320212d7b197ec1130c Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-07-01mb/intel/tglrvp/dt: Remove superfluous USB2_PORT_EMPTY settingsFelix Singer
Configuring USB2_PORT_EMPTY is equal to just not setting it. So remove it to clean up a bit. Change-Id: I6854f4a0d3e7b51b242549556a5838d4183d3473 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-29tgl mainboards: Move audio related settings into hda device scopeFelix Singer
Change-Id: I1992c20dcdc5e974143690d44ee199d7c3394cfd Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-06-29tgl mainboards: Move genx_dec settings into eSPI device scopeFelix Singer
Change-Id: I6d7bcd298408e15677f27d1a9797a490c57c9fc9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-06-29tgl mainboards: Move usb{2,3}_ports settings into XHCI device scopeFelix Singer
Change-Id: Ide5126c6e642ca16249efeaf46321724f2ddce9a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-06-28tgl mainboards: Drop disabled audio settings from dtFelix Singer
Configuring them to 0 is equal to not configuring them at all. So remove them to clean up a bit. Change-Id: I9a9eb370e8e9e8874ad8b4b8ac0f43d61c1a4b9b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-06-28tgl mainboards: Move SATA related settings into SATA device scopeFelix Singer
Change-Id: I03508c50fe56fd85f8bf89f724863e546d4140e9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-06-28mb/google/volteer/baseboard: Drop disabled SATA settings from dtFelix Singer
Configuring them to 0 is equal to not configuring them at all. So remove them to clean up a bit. Change-Id: I18134ac784fffb703e1fe513e5914f05faa749c9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83248 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-28mb/intel/tglrvp/dt: Make use of device alias namesFelix Singer
Also, remove superfluous comments from devices which repeat their name. Change-Id: I009330042b59c9e6e78aa6f3819546b771b26ff0 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-06-28include/device_tree.h: Fix function name fdt_node_nameMaximilian Brune
Rename fdt_node_name to the actual function name and also rename the references. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I527146df26264a0c3af1ad01c21644d751b80236 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83084 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-28device/azalia_device.c: Always read-write GCAPAngel Pons
In the HD Audio Specification Rev. 1.0a, every bitfield in the GCAP register is RO (Read Only). However, it is known that in some Intel PCHs (e.g 6-series and 7-series, documents 324645 and 326776), some of the bitfields in the GCAP register are R/WO (Read / Write Once). GCAP is RO on 5-series PCHs; 8-series and 9-series PCHs have a lock bit for GCAP elsewhere. Lock GCAP by reading GCAP and writing back the same value. This has no effect on platforms that implement GCAP as a RO register or lock GCAP through a different mechanism. Change-Id: Id61e6976a455273e8c681dbeb4bad35d57b1a8a2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-28soc/intel/xeon_sp: Reserve MMIO for Gen1 SoCShuo Liu
For Gen1 SoCs, the range starting from the end of VTd BAR to the end of 32-bit domain MMIO resource window is reserved for unknown devices. Get them reserved. TEST=Build and boot on intel/archercity CRB Change-Id: Ie133fe3173ce9696769c7247bd2524c7b21b1cf8 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-28soc/intel/xeon_sp: Reserve MMIO range for VTd BAR dynamicallyShuo Liu
vtd_probe_bar_size is used to decide the BAR size. TEST=Build and boot on intel/archercity CRB Change-Id: Ie45dd29e386cbfcb136ce2152aba2ec67757ee3c Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82431 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-28acpi: Add support for DRHD size reportingShuo Liu
VT-d spec 4.0 supports size definition for DRHD BAR to support DRHD sizes larger than 4KB. If the value in the field is N, the size of the register set is 2^N 4 KB pages. Some latest OS (e.g. Linux kernel 6.5) will have VTd driver trying to use the beyond 4KB part of the DRHD BAR if they exist. They need the DRHD size field to set up page mapping before access those registers. Re-add acpi_create_dmar_drhd with a size parameter to support the needs. TEST=Build and boot on intel/archercity CRB Change-Id: I49dd5de2eca257a5f6240e36d05755cabca96d1c Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Gang Chen <gang.c.chen@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82429 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-28mb/google/brox/variants/brox/fw_config.c: Remove unused macroElyes Haouas
Change-Id: I8ce94c8bc7ed137eaace12d6cb0befa6c0d39a37 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82925 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-28mb/google/nissa/var/nivviks: Disable CNVi Bluetooth based on fw_configPoornima Tom
When CNVi based Wifi6 is disabled, CNVi based Bluetooth must be turned off, based on fw_config. Otherwise, when device boots without the cbi settings for wifi6, boot may fail with assertion error for line 817 & 819 of file 'src/soc/intel/alderlake/fsp_params.c'. BUG=b:345596420 BRANCH=NONE TEST=Dut boots fine with both Wifi6 & Wifi7 based cbi settings, along with enumeration of corresponding BT device. Change-Id: I03fde02fa4b36f4e47d6f0e95675feddb3bee7cd Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-28mb/google/nissa/var/nivviks: Enable PCIe Wifi GPIOs based on fw_configPoornima Tom
PCIe based GPIOs of Wifi7 module are enabled based on firmware config. BUG=b:345596420 BRANCH=NONE TEST= Based on fw config configured, wifi6 or wifi7 along with bluetooth ports are detected. Change-Id: If0584e91b5143c6df742961657d242c046409b3a Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-06-28mb/google/nissa/var/nivviks: Enable Bluetooth for PCIEPoornima Tom
PCIe based Bluetooth is on port8. This cl enables bluetooth for PCIe based Wifi7 module. BUG=b:345596420 BRANCH=NONE TEST=With proper FW config enabled, BT gets detected on port8 Change-Id: I989cf6122f2555cc89f622e4ce5d21b574d0458e Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83076 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-28mb/google/nissa/var/nivviks: Enable wifi7 on pcie root portPoornima Tom
Enable pcie based, discreete wifi7 on root port4. BUG=b:345596420 BRANCH=NONE TEST=Verified Wifi7 module detection based on cbi settings Change-Id: I8c2f4a750a1cb00c587bce21bc83ee583d0f4341 Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83075 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-28mb/google/nissa/var/nivviks: Add fw_config fields for wifi6 and wifi7Poornima Tom
Add a new fw config field for wifi category as WIFI_6, which is CNVi based and WIFI_7, which is PCIe based. Also, enable WIFI_6 for existing CNVi based wifi port as well as bluetooth port. BUG=b:345596420 BRANCH=NONE TEST=Verified Wifi6 module detection Change-Id: I4b218f772405bdb1b741b4d5e640d7b4f145cd76 Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83074 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-06-28mb/google/nissa/var/nivviks: Update config for CNViPoornima Tom
Add wake configuration and set 'add_acpi_dma_property'=true for CNVi. Also, add "set 'add_acpi_dma_property' to true to tell the OS to enforce DMA protection for this device. BUG=b:345596420 BRANCH=NONE TEST=SSDT dump showed below: Scope (\_SB.PCI0.RP01.WF00) { Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x23, 0x03 }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"), Package (0x01) { Package (0x02) { "DmaProperty", One } } Change-Id: If04539fe8dceb5c2edfc06a324ede11147b78b6d Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83138 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-27arch/x86/mpspec: Use uintptr_t for mpc_apicaddrElyes Haouas
Change-Id: I6cc2b3947a2c79e8962985e035e7cc74c2deb307 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83215 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-06-27mb/google/brask/var/bujia: Configure Serial IO UARTs ModeShon Wang
This patch configures Serial IO UARTs mode as below. UART0 and UART1 in PCI mode and keep UART2 disable as per hardware design. BUG=b:338917836 BRANCH=firmware-brya-14505.B TEST= USE="-project_all project_bujia" emerge-brask coreboot Change-Id: I5617331aaf505b97e25a717b145fb70dc53f5a38 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83205 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-06-27mb/google/brox/var/lotso: GPP_B14 used for buzzerJing Tong
ALC257 does not supoort built-in digtal buzzer, So use external pwm to PCBEEP for beep sound. BUG=b:346956771 BRANCH=None TEST=emerge-brox coreboot sys-boot/chromeos-bootimage firmware-shell: devbeep -> can output beep normally. Change-Id: If924f9f27f229420e78015f418a97b2d5daf62e5 Signed-off-by: Jing Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-06-27drivers/wifi: Support Wi-Fi 7 11be EnablementRavi Sarawadi
Add 802.11be (aka. Wi-Fi 7) enable/disable support based on document 559910 Intel Connectivity Platforms BIOS_Guidelines revision 8.3. There are countries where Wi-Fi 7 should be disabled by default. This adds capability for OEM to enable or disable by updating the board specific Specific Absorption Rate (SAR) binary. BUG=b:348345300 BRANCH=firmware-rex-15709.B TEST=SSDT dump shows that the _DSM method returns the value supplied by the SAR binary for function 12 Change-Id: Ifa1482d7511f48f5138d4c68566f07ce79f37a7a Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: YH Lin <yueherngl@google.com>
2024-06-27lib/string: use size_t for local variable in strncmpFelix Held
Since the 'maxlen' parameter's type is changed to size_t, the type of the local variable 'i' which this is compared against should also be changed to size_t. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibe35d3741bc6d8a16a3bad3ec27aafc30745d931 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83224 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-06-27lib/string: change return types to match C standardFelix Held
The return type of strspn and strcspn is supposed to be a size_t and not a signed integer. TEST=Now the openSIL code can be built with the coreboot headers without needing to add '-Wno-builtin-declaration-mismatch' or '-Wno-incompatible-library-redeclaration' to the cflags. Before the build would error out with various 'mismatch in return type of built-in function' errors. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0ff612e2eee4f556f5c572b02cbc600ca411ae20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83223 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-06-27lib/string: change parameter types to match C standardFelix Held
The third parameter of strncpy and strncmp is supposed to be a size_t and not a signed int. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I485e45e18232a0d1625d4d626f923ec66cfbe4a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83222 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-06-27device/azalia_device.c: Use `azalia_enter_reset()`Angel Pons
Use the existing `azalia_enter_reset()` function instead of explicitly clearing the bit (and having to explain in a comment what this means). Change-Id: I04924e68420a93a1ad46f5a7ab359e38c0f7e210 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83217 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-27commonlib/device_tree: Improve node and property allocation speedJulius Werner
Now that the device tree code has been made available in libpayload, we should reintroduce the node and property allocation optimization for libpayload's memory allocator that was originally dropped when porting this code from depthcharge to coreboot. On a Qualcomm SC7180 unflattening a normal ChromeOS kernel device tree, this saves roughly ~145ms. The total scratch space used is about ~1350 nodes and ~5200 properties, so we leave a little room to grow with the constants hardcoded here. Change-Id: I0f4d80a8b750febfb069b32ef47304ccecdc35af Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2024-06-26mb/google/fatcat: Add minimal code support for fatcatSubrata Banik
This patch adds initial code block required to build google/fatcat board with Intel Meteor Lake Silicon. Later after the initial board power-on is successful, we shall switch to Panther Lake silicon to build the google/fatcat reference design. BUG=b:347669091 TEST=Able to build the google/fatcat and able to hit power-on reset using Intel Meteor Lake SoC platform. Change-Id: Iad78aec51b2f0f240991c9c35842764a60be988e Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-06-26acpi: Rename acpi_create_dmar_drhdShuo Liu
For most of SoCs, DRHD is by default with the size of 4KB. However, larger sizes are allowed as well. Rename acpi_create_dmar_drhd to acpi_create_dmar_drhd_4k to support the default case while a later patch will re-add acpi_create_dmar_drhd with a size parameter. TEST=intel/archercity CRB Change-Id: Ic0a0618aa8e46d3fec2ceac7a91742122993df91 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-26mb/google/trulo/var/orisa: Add STORAGE_NVME in fw_config storage fieldAmanda Huang
Follow nissa baseboard setting for storage field. option STORAGE_EMMC 0 option STORAGE_NVME 1 option STORAGE_UFS 2 BUG=b:333486830 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I75b4b3037c245f7d517cb33d487f71da98f6c4e8 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-26mb/google/brox/lotso: Add Fn key scancodeWen Zhang
The Fn key on Lotso emits a scancode of 94 (0x5e). BUG=b:322721490 TEST=Flash Lotso, boot to Linux kernel, and verify that KEY_FN is generated when pressed using `evtest`. Change-Id: I999627f0ea9db1d79376150a04920ac877a48447 Signed-off-by: Wen Zhang <zhangwen6@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83204 Reviewed-by: Dengwu Yu <yudengwu@huaqin.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-06-26mb/google/brox: Disable Touchscreen for hardware board version 1Karthikeyan Ramasubramanian
On board version 1 and later, touchscreen is not stuffed. Hence configure the relevant GPIOs as not connected, disable the concerned I2C bus in the devicetree as well as SoC chip config for board version 1. BUG=b:347333500 TEST=Build Brox BIOS image and boot to OS. Ensure that there are no peripherals detected in I2C 1 bus through i2cdetect tool. Ensure that no touchscreen devices are exported through ACPI SSDT table. Ensure that other I2C peripherals - eg. Trackpad and Ti50 are functional. Ensure that the device is able to suspend and resume for 25 cycles. Change-Id: Ia0578b90b0e8158ae28bcc51add637844ba6acf6 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83199 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-26mb/google/brox: Add default ACPI brightness levelsKarthikeyan Ramasubramanian
Kernel need the default brightness steps. Otherwise following error messages are observed in the kernel: [Firmware Bug]: ACPI(GFX0) defines _DOD but not _DOS ACPI BIOS Error (bug): Could not resolve symbol [^^XBCL], AE_NOT_FOUND ACPI Error: Aborting method \_SB.PCI0.GFX0.LCD0._BCL due to previous error (AE_NOT_FOUND) BUG=b:346807006 TEST=Build Brox BIOS image and boot to OS. Ensure that the concerned error messages are resolved. Ensure that the backlight controls are functional. Change-Id: Icd569b0efef31908edb1b7dc384e60a16fc5bd0c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-06-26skl mainboards/dt: Move SsicPortEnable setting into XHCI device scopeFelix Singer
Change-Id: I64ffba35303c1291f56ae6a038325a7482158ad3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83189 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-26skl mainboards/dt: Move serirq setting into LPC device scopeFelix Singer
Change-Id: I84da5365907664ce223dec4adb22a8f1a6e2a144 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83188 Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2024-06-26skl mainboards/dt: Move SATA related settings into SATA device scopeFelix Singer
Change-Id: I50706d7a077767d2295d6d5f209c30109d607277 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83179 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-26skl mainboards/dt: Move genx_dec settings into LPC device scopeFelix Singer
Change-Id: Iecb4851bedb7c9ed7793763d80acbcbb068e8832 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83172 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-26skl mainboards/dt: Move usb{2,3}_ports settings into XHCI device scopeFelix Singer
Change-Id: I22ba991a9d559b0ecc7b3ceddcfd099890dd6c3a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
2024-06-25soc/intel/common: Extend WAIT_FOR_DP_MODE_ENTRY_TIMEOUT_MS to 1500msTony Huang
Some dongles require more time to be ready, this CL extedns the DP mode entry timeout from 0.5s to 1.5s and make sure the tested dongle display works. Before: [WARN ] DP not ready after 500ms. Abort. After: [INFO ] DP ready after 1211 ms BUG=b:348309582 TEST=emerge coreboot verify tested dongles and monitors display works Change-Id: I22d7800b50f6f7de9f147ae6998a5015d0dc0be9 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83206 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2024-06-25device/azalia: Separate codec checking and initializationNicholas Sudsgaard
This also changes how debug messages will be printed. I focused on reducing clutter on the screen and made the style of the messages consistent. Before: azalia_audio: Initializing codec #5 codec not ready. azalia_audio: Initializing codec #4 codec not valid. azalia_audio: Initializing codec #3 azalia_audio: viddid: ffffffff azalia_audio: verb_size: 4 azalia_audio: verb loaded. After: azalia_audio: codec #5 not ready azalia_audio: codec #4 not valid azalia_audio: initializing codec #3... azalia_audio: - vendor/device id: 0xffffffff azalia_audio: - verb size: 4 azalia_audio: - verb loaded Change-Id: I92b6d184abccdbe0e1bfce98a2c959a97a618a29 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80332 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-15 18:55:29 +0000