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2019-11-22src/console: Bring back support for printf'ing 64bit intsPatrick Georgi
commit f96d9051c2 (Remove MIPS Architecture) accidentally enabled a MIPS special case to not support 64bit integers in printf for all platforms. This removes that MIPS-only special case entirely. Change-Id: I5245bb32b45f9bd37bd012a7b15a64fba24a4cb7 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-22sb/intel/ibexpeak: Decode more LPC IO rangesArthur Heymans
3b452e0 "nb/intel/nehalem: Move PCH init to sb/intel/ibexpeak" introduced a regression where the GAME_L decode range was not set up, which is used by the WACOM digitizer on the Thinkpad X201T. Change-Id: Ie569d567a65010aa5372323f8610a1b8b5d2599d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36994 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-22cpu/intel/gen1/smmrelocate: Fix stale commentArthur Heymans
Change-Id: I91ed5f7cbcfa5c510bb8e74049ec860397d7dbba Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-11-22cpu/intel/smm: Drop em64t save stateArthur Heymans
This save state is just plainly wrong in many regards and em64t100 should be used. Checked with a model 0x17 core2 CPU. Change-Id: I4d89691e87c91dd12b34a44b74849b18b4ac5369 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-22sb/i82801ix: Use macros instead of hard-coded IDsFelix Singer
This patch replaces hard-coded PCI IDs with macros from pci_ids.h and cleans up some code. Change-Id: Ie6ea72ac49eb015ef5cbaa98ed2b3400072000b5 Signed-off-by: Felix Singer <felix.singer@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36705 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-22soc/intel/icelake: Make CpuMpPpi implementation default for ICLSubrata Banik
TEST=Could able to build and boot ICL DE system Change-Id: Icd71ec99f06434896c73cff5a52cd3a5ad6ce5f3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-22drivers/ipmi: Add IPMI get system GUID supportJohnny Lin
Tested on OCP Mono Lake. Change-Id: I541a23341ccce3d45239babb3f0a8a8c8542b226 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-11-22soc/intel/common/intelblocks: Define PAD_CFG0_MODE_NF7Nick Vaccaro
BUG=b:142961277 BRANCH=none TEST=none Change-Id: Ibe0991b2e0d13e07d65906201597f9021cfc7156 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-11-22cpu/x86/smm: Use PRIxPTR to print uintptr_tJacob Garber
Since 'base' is a uintptr_t, it needs the PRIxPTR format specifier. This fixes a compilation error when targeting x86_64 or using Clang 9.0.0. Change-Id: Ib806e2b3cbb255ef208b361744ac4547b8ba262f Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-11-22device/hypertransport: Drop unused codeArthur Heymans
Change-Id: I6a8b176fa6f8832f6f7bb37118861d530fdefd5e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37066 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-22mb/lenovo/t410: Fix I2C SPD addressPatrick Rudolph
Use correct address for second DIMM. Tested on Lenovo T410: * Both DIMMs are found and are usable Change-Id: I8bace47f04a0e185c2901695879d4d4e12d4ce6a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37105 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-22mb/google/hatch/variant/kohaku: Config MEM_STRAP GPIOsShelley Chen
Kohaku always used the default MEM_STRAPs in hatch baseboard. Adding explicit configuration for Kohaku in the event that MEM_STRAP is set differently in the baseboard gpio file. BUG=b:144895517 BRANCH=hatch TEST=None ./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I8f7105b3925f17c1741660d84c83c5d15f398a8d Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37106 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-22src/drivers/ipmi: Implement BMC Get Self Test Result functionMorgan Jang
According to IPMI SPEC, it is recommended that BIOS includes provisions for checking and reporting on the basic health of BMC by executing the Get Self Test Results command and checking the result. TEST=Check the result in response data to confirm the BMC status is fine or not. Change-Id: I20349cec2e8e9420d177d725de2a5560d354fe47 Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-11-22purism/librem_skl: add/use VBT fileMatt DeVillier
Add VBT file extracted from vendor (AMI) firmware, use by default to ensure functional display after resume from S3 when using libgfxinit. Test: build/boot Librem 13v2/3/4,15v3/4 boards, verify functional display after resume from S3 when using libgfxinit. Change-Id: I6bc5dab60e3601d56dae4300efee255d7c58329d Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37068 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-22mb/lenovo/{x201,x60}/smihandler: Use mdelay instead of udelay for large valuesPeter Lemenkov
Change-Id: I7d20a850f8c2a1fcdee358c9e73d4c04eb3d7de8 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37006 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-22arch/acpigen.h: Correct PARENT_PREFIX encoding valueElyes HAOUAS
The encoding value for PARENT_PREFIX is 0x5e. (ACPI specification version 6.3 page 1073) Change-Id: Ibbacb8b445157b377772f09572f87f8300a278dd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36652 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-22intel/smm: Provide common smm_relocation_paramsKyösti Mälkki
Pull in all copies of smm_relocation_params structs defined for intel platforms. Pull in all the inlined MSR accessors to the header file. Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-22Makefiles: Remove -D__PRE_RAM__Kyösti Mälkki
All cases of testing for __PRE_RAM__ have been converted to equivalent ENV_xxx definitions from <rules.h>. Change-Id: Ib6cd598f17109cc1072818cebe4791f7410c3428 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-22soc/intel/skylake: Refactor pch_early_init() codeUsha P
This patch keeps required pch_early_init() function like ABASE programming, GPE and RTC init into bootblock and moves remaining functions like TCO configuration and SMBUS init into romstage/pch.c in order to maintain only required chipset programming for bootblock and verstage. TEST=Able to build and boot soraka. Change-Id: Idf7b04edc3fce147f7857591ce7d5a0cd03f43fe Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-11-22arch/x86: Remove spinlocks inside CARKyösti Mälkki
This was only used with amdfam10h-15h, where cache coherency between nodes was supposed to be guaranteed with this code. We could want a cleaner and more generic approach for this, possibly utilising .data sections. Change-Id: I00da5c2b0570c26f2e3bb464274485cc2c08c8f0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-22drivers/pc80/rtc: Remove CMOS spinlockKyösti Mälkki
This was only used with amdfam10h-15h, and only in romstage while commentary elsewhere says concurrent CMOS and CBFS access caused issues. We would want a cleaner approach on this, if re-implemented. Change-Id: I8512196cb55ff2b4542b1421a1bbae540450115a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-22cpu/amd/microcode: Remove microcode update routineKyösti Mälkki
This was only used with native amdfam10h-15h. Change-Id: Id8e06b25c6ec716c07aee46fce10903c62b6d684 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-21device/pci: Reduce scope of dev_find_slot()Kyösti Mälkki
We only keep it around because soc/intel debugging still depends on it. Change-Id: I3ea37c097bbcc3cf5c0574c7d727eae4f5bee307 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-21arch/x86: Remove copy_and_run()Kyösti Mälkki
Nothing but a wrapper for run_ramstage() with an ugly name. Change-Id: Ie443a27cf18f829496ddadcc19c4ebec6a0b5a59 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-21drivers/crb: Replace __RAMSTAGE_ guardsKyösti Mälkki
Change-Id: Ie2e6cdddc1edb95c442a4240267fe1fd6a11d37e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36698 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-21drivers/pc80/tpm: Replace __RAMSTAGE_ guardsKyösti Mälkki
Change-Id: Ia6e161c3b4fc44292cdac692a2918c522680d60d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36631 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-21cpu/amd/fam10: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I3c69f158a5667783292161815f9ae61195b5e03b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36963 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-21cpu/x86/lapic/lapic_cpu_init.c: Drop unused guardsArthur Heymans
Both model_2065x and model_206ax use the parallel mp init codepath. Change-Id: I6440d413761361ee8b69d5c76b69409bd7528b5d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37065 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-21Kconfig: Remove not found sourcesElyes HAOUAS
Change-Id: I3691a4162eecbd48321348e136f72b73da74e225 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37078 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-21drivers/intel/fsp1_0: Drop supportArthur Heymans
No platform is using this. Change-Id: I3ea6df4d9ce9043755f319f699adc189d754df1f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-11-21soc/intel/fsp_broadwell_de: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I8b6502b0894f9e2b8b1334871d7b6cde65cba7d4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-11-21mb/*/*: Remove BROADWELL_DE boardsArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I3d9b6bb48bfd15c0182448f774e9af1e0c944fd5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-11-21soc/intel/fsp_baytrail: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I0b0344f1ebed12207a77c985f27893a1353c0925 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-11-21mb/*/*: Drop FSP_BAYTRAIL supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I08c21fd7e5cf8996911c3912bdbaf12d6450db42 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-11-21nb/sb/cpu: Drop Intel Rangeley supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I41589118579988617677cf48af5401bc35b23e05 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-11-21mb/*/*: Drop Intel Rangeley mainboardsArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: Id38eada2d08426520261d4824990a49f8302976b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-11-20device: Add back dummy HT_CHAIN_UNITID_BASEKyösti Mälkki
This should be defined by mainboard. Add a dummy default to fix master while HyperTransport files are still around referencing this. Change-Id: I58188a200a2cad5fa20affee1844117ba71ac338 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37036 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20nb/amd/fam10: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: If36ef0749dbb661f731fb04829bd7e2202ebb422 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-20sb/nvidia/mcp55: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which platforms using this code lack. Change-Id: I7cd33316140f2cdc83949aa5db7e6f1565982543 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36973 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20sb/nvidia/ck804: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which platforms using this code lack. Change-Id: I56cb6d0a04056b10af1e53afb697883329235c87 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36972 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20sb/broadcom/bcm21000: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which platforms using this code lack. Change-Id: I5e9250a7c7adb7dffd64422637ba760155d966d2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36971 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20sb/broadcom/bcm5785: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which platforms using this code lack. Change-Id: I2305e0d9de0d4b1768e171f4c65d07306e7c3801 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-20sb/amd/sr5650: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which platforms using this code lack. Change-Id: I63551b9ad861fecb689036c9f26c3b0950a8b8e9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36969 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20sb/amd/sb800: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which platforms using this code lack. Change-Id: I1c25837f1ba05ecd58309b63a471001f4aee2fff Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36968 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20mb/*/*: Use proper header for pm_iowrite()Arthur Heymans
These boards don't include any from sb/amd/sb800. Change-Id: I2dbe39df6e4c5a86a0714b396bb89b03bbafd164 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36987 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20sb/amd/sb700: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which platforms using this code lack. Change-Id: Iffa4f54b2d1b43b6710447e69061c6ed433bff1d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36967 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20sb/amd/rs780: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which platforms using this code lack. Change-Id: I00d260f22badb712a963b907f7beb8fbb5b71eac Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36966 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20sb/amd/amd8132: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I83d7025280b75088c37049f34564610612996e1b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36965 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20sb/amd/amd8111: Remove supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I5d7f3bfca47b86e4fd761f9462bc7297b487fdee Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36964 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20mb/*/*: Drop AMDFAM10 mainboardsArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: Ic00ca18de3d73a17041a3a2839307149ad7902b2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36961 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20sb/via/common: Drop unused codeArthur Heymans
Change-Id: I803b9bba4067435e471e9565d3286f11a0a361a3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36960 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20nb/via/vx900: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: Ie971893da06fd3b1ac41dda398b1caeec3ee32db Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-20cpu/via/nano: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I6d9771e97619c3775f8325daf4b8453cd51d6571 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-20mb/via/epia-m850: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: Id6aa669542bcfd774fa5571d790f59f156a39a4b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-20soc/intel/skylake: lockdown: lock global resetMichael Niewöhner
There are four chipsets selecting PMC_GLOBAL_RESET_ENABLE_LOCK but only one (apollolake) is actually calling the code. Add the missing call. Also fix the register offset in a comment in reset code. Tested successfully on X11SSM-F by reading ETR3. Change-Id: If190c3c66889ede105d958b423b38ebdcb698332 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36573 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20soc/intel/icelake: lockdown: lock global resetMichael Niewöhner
There are four chipsets selecting PMC_GLOBAL_RESET_ENABLE_LOCK but only one (apollolake) is actually calling the code. Add the missing call. Change-Id: I3e450a473ccdf99221e82e0f857879039d78991b Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36572 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20soc/intel/cannonlake: lockdown: lock global resetMichael Niewöhner
There are four chipsets selecting PMC_GLOBAL_RESET_ENABLE_LOCK but only one (apollolake) is actually calling the code. Add the missing call. Change-Id: I6aba9bcb2ad09e6ae0e02d8c0b552e34bdb3fa72 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36571 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20soc/intel/common: pmclib: make use of the new ETR address APIMichael Niewöhner
Make use of the new ETR address API in the ETR3 register related functions. Further, disabling and locking of global reset is now done at once to save one read-modify-write cycle, thus the function was renamed accordingly and the now redundant disabling in soc/apl got removed. Change-Id: I49f59efb4a7c7d3d629ac54a7922bbcc8a87714d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-20soc/intel/skylake: add soc implementation for ETR address APIMichael Niewöhner
Add soc implementation for the new ETR address API. Change-Id: Iae54af09347d693620b631721576e4b916ea0f0f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-20include/device: add a comment to pci mmio cfg addr helpers and cachingMichael Niewöhner
Add a comment to the newly introduced MMIO address helpers for PCI config registers, that the pointer returned may change during the boot processs and, thus, must not be cached. Change-Id: Ieb90ae9d67a3b944d35587dec54756a17c27c86f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-20purism/librem_bdw: add/use VBT fileMatt DeVillier
Add VBT file extracted from vendor (AMI) firmware, use by default to ensure functional display after resume from S3 when using libgfxinit. Test: build/boot Librem 13v1/15v2 boards, verify functional display after resume from S3 when using libgfxinit. Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: I44d75486da3083cd1f07ea82dc18688db84a621e Reviewed-on: https://review.coreboot.org/c/coreboot/+/36916 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20mb/lenovo/x201: Remove unnecessary GPIO settingsArthur Heymans
GPIO49 is strapped high, so setting it low likely increases power usage. GPIO53 is hooked to a testpad so there is no reason to set it here. Change-Id: I00fb38c90417b673c2b36191c20279474eb0dc21 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-20/mb/google/hatch: Create jinlon variantWisley Chen
Create new variant for jinlon BUG=b:144150654 TEST=emerge-hatch coreboot chromeos-bootimage and boot on jinlon proto board Change-Id: I8deb29041475e38cbbf2f54519940f62b9f21822 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36681 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20cpu/intel/car: Add EC software sync to Intel romstageTim Wawrzynczak
Perform EC software sync in romstage, before memory training is started. Because the ChromeOS EC will not currently perform USB-PD negotiation until it jumps to running its RW code, this allows the system to get access to more power earlier in the boot flow. This is guarded by CONFIG_VBOOT_EARLY_EC_SYNC. BUG=b:112198832 BRANCH=none TEST=EC software sync works in update and non-update case. No significant effect on boot time (~6 ms). Change-Id: I31f3407a2afcbf288461fab1397f965f025bc07c Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36211 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20security/vboot: Build vboot library with same .a that depthcharge usesTim Wawrzynczak
Currently, depthcharge and coreboot are using two different vboot libraries. coreboot is using "fwlib20", while depthcharge uses "fwlib". The only difference between the two libraries is the inclusion of vboot1-only compilation units in fwlib, which are now deprecated. Therefore, coreboot may as well use fwlib too. Vboot is expected to converge on a single firmware library soon. BUG=none BRANCH=none TEST=compiles and runs verstage correctly Change-Id: I905b781c3596965ec7ef45a2a7eafe15fdd4d9cc Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36341 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20security/vboot/sync_ec: Add timestampsTim Wawrzynczak
Add 4 new timestamps to the EC software sync flow: 1) Beginning of EC software sync 2) EC finished calculating Vboot hash 3) EC is no longer requesting power limiting 4) End of EC software sync BUG=none BRANCH=none TEST=verified timestamps show up in cbmem log Change-Id: I6e5703c146b5ec27d01700fdb39cb3d2092ea8a8 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-20security/vboot: Add vboot callbacks to support EC software syncTim Wawrzynczak
Use the new functions introduced into the EC driver to support performing EC software sync via vboot callbacks. NOTE: This patch assumes that the EC image is added to CBFS uncompressed. Streaming decompression of the image will be added in a future patch. Also adds a new Kconfig option VBOOT_EARLY_EC_SYNC. The new Kconfig option compiles EC software sync into romstage, dependent upon having a CrOS EC. BUG=b:112198832 BRANCH=none TEST=Successful EC software sync Change-Id: I9b1458a45ab3ed5623af50f78036c4f88461b226 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36208 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20cbfs: switch to region_device for location APIsAaron Durbin
Drop struct cbfs_props and replace with struct region_device object. The goal of the cbfs locator APIs are to determine the correct region device to find the cbfs files. Therefore, start directly using struct region_device in the cbfs location paths. Update the users of the API and leverage the default boot region device implementation for apollolake. Change-Id: I0158a095cc64c9900d8738f8ffd45ae4040575ea Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-20security/vboot: Remove selected_region from struct vboot_working_dataYu-Ping Wu
Since we already have pre-RAM cache for FMAP (CB:36657), calling load_firmware() multiple times is no longer a problem. This patch replaces vboot_get_selected_region() usage with vboot_locate_firmware(), which locates the firmware by reading from the CBMEM cache. In addition, returning false from vboot_is_slot_selected() implies the recovery path was requested, i.e., vb2_shared_data.recovery_reason was set. Therefore, we simply remove the vboot_is_slot_selected() check from vboot_check_recovery_request(). BRANCH=none BUG=chromium:1021452 TEST=emerge-kukui coreboot Change-Id: I27cb1a2175beb189053fc3e44b17b60aba474bb0 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-20security/vboot: Remove buffer_size from struct vboot_working_dataYu-Ping Wu
Since buffer_size is no longer used, remove it from struct vboot_working_data. BRANCH=none BUG=chromium:1021452 TEST=emerge-kukui coreboot Change-Id: Ie770e89b4a45e0ec703d5bbb8fb6a298ce915056 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-20vc/amd/agesa: Remove fam12Joe Moore
With removal of Torpedo mainboard, this code is no longer necessary. Will resolve some unique Coverity issues. Change-Id: I2927245c426566a8f80863a109d015ebf6176803 Signed-off-by: Joe Moore <awokd@danwin1210.me> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-11-20cpu/nb/sb: Remove fam12Joe Moore
With removal of Torpedo mainboard, this code is no longer necessary. This also removes fam12 support from northbridge and SB900 from southbridge. Change-Id: I8a30461278844d0d9ad4320f0e952774c4fd644f Signed-off-by: Joe Moore <awokd@danwin1210.me> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-11-20mainboard/amd: Remove AMD Torpedo mainboardJoe Moore
This also permits removal of vc/amd/agesa/f12, as it was the only mainboard using it. That will in turn allow resolving some unique Coverity issues reported against that source. Change-Id: I73f570f01fcb5ba0e306508a569ea97f432596b3 Signed-off-by: Joe Moore <awokd@danwin1210.me> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-11-20Remove MIPS architectureJulius Werner
The MIPS architecture port has been added 5+ years ago in order to support a Chrome OS project that ended up going nowhere. No other board has used it since and nobody is still willing or has the expertise and hardware to maintain it. We have decided that it has become too much of a mainenance burden and the chance of anyone ever reviving it seems too slim at this point. This patch eliminates all MIPS code and MIPS-specific hacks. Change-Id: I5e49451cd055bbab0a15dcae5f53e0172e6e2ebe Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34919 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20Remove imgtec/pistachio SoCJulius Werner
After removing urara no board still uses this SoC, and there are no plans to add any in the future (I'm not sure if the chip really exists tbh...). Change-Id: Ic4628fdfacc9fb19b6210394d96431fdb5f8e8f1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36491 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-19Remove google/urara mainboardJulius Werner
This board never really existed and nobody has any hardware left over for it. Change-Id: Icdba4f5209725995e4a55dcdbc299a9e91a5869a Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-19security/vboot: Remove vboot_named_region_device(_rw)Yu-Ping Wu
Remove vboot_named_region_device(_rw) and use fmap_locate_area_as_rdev(_rw) directly. BRANCH=none BUG=none TEST=emerge-kukui coreboot Change-Id: I244ac4e01ae5b80285162b3baffc0b30aa057bfb Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-19mb/google/octopus: Disable fmap cache for meepPatrick Georgi
By removing this code, we get approximately back to where the board was before the fmap cache feature was added, which is small enough for the Chromium OS default configuration for the board to fit into the 32KB that the bootblock can use on the chipset again. Change-Id: I52c0c30a14929913ded144bf086c12938e9c2699 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-19sb/amd/hudson: Fix typo in GEC firmware nameMarshall Dawson
Correct what looks to be errant characters in the makefile variable for the Gigabit Ethernet Controller. This should have no effect on any mainboards as none select the HUDSON_GEC_FWM symbol. Change-Id: Icb861d872973aaf2b653440cae00057d5ad89b20 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-19lib/fmap: Disable pre-RAM cache for FSP 1.0Julius Werner
Due to the way CAR teardown is handled in FSP 1.0, the results of car_get_var_ptr() aren't always reliable, which can break things when running with FMAP cache. It might be possible to fix this but would make the code rather complicated, so let's just disable the feature on these platforms and hope they die out soon. Also allow this option to be used by platforms that don't have space for the cache and want to save a little more code. Change-Id: I7ffb1b8b08a7ca3fe8d53dc827e2c8521da064c7 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-19mmio: Fix buffer_to_fifo32() order of argumentsJulius Werner
buffer_to_fifo32() is a simple wrapper to buffer_to_fifo32_prefix(), but unfortunately its arguments are swapped. This patch fixes the issue. Change-Id: I6414bf51dd9de681b3b87bbaf4ea4efc815f7ae1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36942 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-18include: Make stdbool.h a separate fileJulius Werner
This patch moves the traditional POSIX stdbool.h definitions out from stdint.h into their own file. This helps for using these definitions in commonlib code which may be compiled in different environments. For coreboot everything should chain-include this stuff via types.h anyway so nothing should change. Change-Id: Ic8d52be80b64d8e9564f3aee8975cb25e4c187f5 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-18ipq40xx: Run python script without explicit 'python' callJulius Werner
This patch changes the ipq40xx Makefile.inc to follow established coreboot practice of calling Python scripts directly rather than invoking the 'python' interpreter explicitly. This has the added effect of honoring the scripts shebang (which in this case is set to 'python2'). Change-Id: If96e8313527c411ef1bb6386e03b6a209c750131 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-18nb/intel/sandybridge/mrc: Handle P2P disabling via devicetreeNico Huber
Some Sandy Bridge boards disabled the PCI-to-PCI bridge early to avoid probing by the MRC. We can do that for all boards instead, based on the devicetree setting. Change-Id: Ie64774628fde77db2a379bdba6a921a31e52fa0d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-18sb/intel/bd82x6x: Handle enabling of GbENico Huber
The integrated GbE port is toggled via the Backed-Up Control (BUC) register. We already disable it according to the devicetree setting but never enabled it. This could lead to the confusing situation that it was disabled before (different build, vendor BIOS, etc.) but shouldn't be anymore. As we need a full reset after enabling GbE, do it in early PCH init. Change-Id: I9db3d1923684b938d2c9f5b369b0953570c7fc15 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-18mb/intel/dcp847ske: Disable xHCI via devicetreeNico Huber
This is supported by generic PCH code now. Change-Id: Id5d764c97e47cdb08a68d03002ebebd996769914 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-18mb/sapphire/pureplatinumh61: Don't write BUC and beyondNico Huber
The BUC register is actually only 8 bits wide and setting bit 5 (disabling GbE) is already done by generic code. Change-Id: I729a2a28f4b0d94eddd070dc89b7341ac0c35e4a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-18mb/samsung: Clean up LPC and IOAPIC configurationNico Huber
Don't overwrite the LPC decode config of the generic PCH code, move UART init into bootblock_mainboard_early_init() and don't enable the IOAPIC, which is already done by generic code. Change-Id: I90d090f5bff29174e68981fea3c3f04c666b1d28 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-18mb/lenovo/s230u: Don't write BUC and beyondNico Huber
The BUC register is actually only 8 bits wide and setting bit 5 (disabling GbE) is already done by generic code. Change-Id: I4b8e14606c319e8bfc48d6757087f28af1bd5dfb Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-18mb/intel/emeraldlake2: Revise early initNico Huber
Move UART initialization to bootblock_mainboard_early_init() and don't override the generic LPC decode settings. Change-Id: Icdab36ae0324175d3d51a050784b94a53d4b3b7c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-18mb/hp/revolve_810_g1: Don't clear BUC and beyondNico Huber
The BUC register is actually 8 bits wide and shouldn't be bluntly cleared. Change-Id: I2ffd2d161005e839e730102b56af4f66efeb551e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-18mb/google(sandybrige): Clean up LPC and IOAPIC configurationNico Huber
Only set LPC decode bits that the generic PCH code doesn't set yet. And don't enable the IOAPIC, which is already done by generic code. Change-Id: I9d2f6a9ad3f5d83573e07596f2763edc75f4ee64 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-18mb/gigabyte/ga-b75m-d3h: Drop useless function-disable settingNico Huber
This bit is already cleared by a reset. Change-Id: Ib71496011c9621476a7327ba309f367c7fa971e4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-18mb/{gigabyte,lenovo}: Remove spurious setting of ETR3 bit 16Nico Huber
This bit is used to indicate xHCI routing across reboots. If anything, coreboot should act on it, not set it during boot. ASL code would be supposed to set it. Change-Id: Id14647ac4e591cfa042ca8aad6dfc6ccda35c74a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-18mb/compulab/intense_pc: Clean PCH and super-i/o config upNico Huber
The generic PCH code already enables a superset of LPC decoding. Move UART setup to bootblock_mainboard_early_init() where it is expected. Last but not least, remove an odd write to BUCs (RCBA+0x3414) and beyond, as it's an 8-bit register and shouldn't be bluntly zeroed. Change-Id: I24a4ccf6a529460a83f48522d2e05e6ad6614f81 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-18mb/asus/p8h61-m*: Drop unnecessary PCH configNico Huber
The generic PCH code already sets up a superset of these decodings. Change-Id: I90bca37c46b89c35f323225fc3c087f1630397e4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-18mb/apple/macbookair4_2: Drop unnecessary PCH configNico Huber
mainboard_pch_lpc_setup() and mainboard_late_rcba_config() did 4 things here on top of the generic PCH code: 1. Enabling LPC decoding for gameports. It seems unlikely that anything is using these ports and there is no code to support gameports. 2. Decoding of COM3 instead of COM2. What COM? 3. Premature locking of ETR3/global reset. Bad idea. 4. Disabling the GbE port in BUC. Already done by PCH code. Change-Id: Ie92dbf5c6813435995c4d24ed807ffc8d125953a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-18nb/intel/sandybridge: Set up console in bootblockArthur Heymans
Change-Id: Ia041b63201b2a4a2fe6ab11e3497c460f88061d1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-18ec/hp/kbc1126: Include early_init.c in bootblockArthur Heymans
Change-Id: I198709efe1eb5d2022d0fbd640901238e696eaa6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-11-18nb/intel/sandybridge: Move to C_ENVIRONMENT_BOOTBLOCKArthur Heymans
There is some overlap between romstage and bootblock. LPC setup and BAR initialization is now done twice. The rationale is that the romstage should not depend too much on the bootblock, since it can reside in a RO fmap region. Enabling the console will be done in a followup patch. Change-Id: I4d0ba29111a5df6f19033f5ce95adcc0d9adc1fd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 12:35:56 +0000