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When asked to place cbmem_top(), FSP does not seem to care about
alignment. It can return an address that is MTRR poison, which will
exhaust all variable MTRRs when trying to set up caching for CBMEM.
This will make memory-mapped flash and TSEG caching fail as well.
Safeguard against this by aligning the region to cache to half of its
size, and move it upwards to compensate. It is assumed that caching
memory above the provided bootloader TOLUM address is inconsequential.
TEST=Boot Purism Librem Mini WHL, observe no MTRR exhaustion error
messages in console. The boot process also feels more fluid.
Change-Id: Ic64fd6d3d9e8ab4c78d68b910a476f9c4eb2d353
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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When getting the address of a structure's member that is not on
offset 0, GCC9+ assumes that the address can never be NULL. However
the code relied on the fact that it can be NULL by letting the pointer
intentionally overflow.
Manually calculate the address using uintptr_t. This allows to
gracefully terminate the list_for_each MACRO instead of crashing at the
end of the list.
Tested on qemu-system-arm:
coreboot no longer crashed in the devicetree parser and is able to boot
Linux 5.5.
Change-Id: I0d569b59a23d1269f8575fcbbe92a5a6816aa1f7
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I7adf430e6ce5f78f68a0c73af841fbdc62bb5dc9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47057
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fix compilation on x86_64.
Tested on HP Z220:
* Still boots on x86_32.
Change-Id: Id7190d24172803e40acaf1495ce20f3ea38016b0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44675
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Initialize timestamp table with data from psp_verstage on bootblock.
PSP keeps its own timestamp and pass it in transfer_buffer. However PSP
timestamp and TSC may be out of sync so we can't just merge two tables
without modification.
info->timestamp contains PSP's clock value (in us) when x86 processor
released and base_timestamp contains TSC value when bootblock is
started. The time between x86 release and bootblock entry should be very
short so we can think those two happened at the same time and use them
for sync.
In some cases there will be underflow in timestamp entries but cbmem
utility can handle wrap-over in entries. Few timestamp values including
1st timestamp can be very large but we can still get the time spent on
boot without any problem.
BUG=b:159220781, b:167148121, b:171422583
BRANCH=zork
TEST=boot to kernel, run 'cbmem -t' and check verstage timestamps are
included in the result.
Change-Id: I5e89bb54f478153fb40ba51b5ab61fa20af3b99a
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45059
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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On Zork(picasso) platform we run verstage on the PSP. It has its own
timer, but the frequency is not matched with TSC.
To ease the work to merge timestamps from the PSP and TSC, add a layer
around tsc to have microsecond granularity for timestamp table. PSP
already records timestamp in microseconds.
BUG=b:159220781
BRANCH=zork
TEST=build, flash and boot, check timestamps are correct
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Ifced4a84071be8da547e252167ec21cd42f20ccc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46058
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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With Innolux panel timings, the fetch_start has evaluated to be more than
v_total which is invalid. Add a check to accommodate the extra h_total addition
in fetch_start calculation. Secondly, made the prefill line requirement
same as Kernel driver.
Change-Id: If7624c0b28421759fdf47dd92f23214a78058199
Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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two different modem regions wifi and lte to be handled in QC_SEC and modem
Change-Id: Ib4592ca66d3d0db4c4768be4cd27422fe9f786b8
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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SCONFIG complains because of the duplicate devicetree entry.
Change-Id: Ibdd60efdbcee5bda7c570d4b98f29cc8ede584cb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jes Klinke <jbk@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Add the USB ports to the devicetree for describing them in ACPI,
including defining the port relationships and defining the reset
GPIO for the bluetooth device.
BUG=b:151731851
TEST=tested on volteer, all other boards were checked against the
latest available schematic.
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: Ia1e5b71e7750a478ff79372c48616bbf5c21b79c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This patch removes all redundant reset code block from each SoC
and make use of common reset code block(fsp_reset.c) based on
SOC_INTEL_COMMON_FSP_RESET.
Respective SoC Kconfig to choose correct FSP global reset type as
per FSP integration guide.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I71531f4cf7a40efa9ec55c48c2cb4fb6ea90531f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Create SOC_INTEL_COMMON_FSP_RESET Kconfig to have IA common code block
to handle platform reset request raised by FSP. The FSP will use the
FSP EAS v2.0 section 12.2.2 (OEM Status Code) to indicate that a reset
is required.
Make FSP_STATUS_GLOBAL_RESET depends on SOC_INTEL_COMMON_FSP_RESET.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I934b41affed7bb146f53ff6a4654fdbc6626101b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The `HDA_GCTL_CRST` corresponds to bit zero, so this is equivalent.
Change-Id: I5f4455aa1255f8954ac8b5f1ea5cf8f0874f77a4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46728
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Instead of checking whether the return value equals -1, just check if it
is negative. Some Azalia implementations already do it, but most do not.
Change-Id: I43ce72a01c07eff62d645db28c09584b386532ff
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46727
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tested with BUILD_TIMELESS=1, Google Wolf does not change.
Change-Id: Iaed0ba1c14e3f6fac1c9d71f1d4334efc4f0f4e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46726
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This sequence used to be an array of reg-and-or triplets, but can be
simplified. The resulting sequence is closer to what Broadwell does.
Change-Id: I21e79cbc1e995707b87c40187ddf03b872d02058
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46725
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Define option value 6 for DB_USB where there is a Type-A port but
no Type-C port on the daughterboard.
BUG=b:151731851
TEST=build volteer boards
Change-Id: I489d24316556dedfecd821e502f1461010b1400f
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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As an intermediate step for CB:45150, add an additional Kconfig option
which is used to configure bus mastering for any devices and use
PCI_ALLOW_BUS_MASTER to allow coreboot setting the bus mastering bit in
general.
Change-Id: I33b37a79022007a16e97350db61575b63fa8256b
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45149
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Kakadu project will be using eMCP board design.
BUG=b:171841122
TEST=Boots on chromebook Kakadu successfully.
Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com>
Change-Id: I44668ce630758e49fbf2c6028f56c01f83ff08f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46871
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In order to support the common PMC functions this device needs to
be able to be located with the common lookup macro.
BUG=b:160996445
TEST=build intel/harcuvar board
Change-Id: If04a82582c07c15bf841d0baa84e31561d211502
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46642
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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variant_smi_sleep is called in smm stage so we need to add
variant.c into smm stage. Otherwise it will call the dummy one.
BUG=b:168075958
BRANCH=octopus
TEST=build image passed.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I41df1a30b119ab3e04f9ae01955b6044f137527f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46847
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For development of the firmware to run on the Dauntless TPM, a number of
Volteer2 devices are being reworked to replace the H1 chip with probe
wires to connect to an external Dauntless development board.
Some modification to the AP firmware is required, not least because the
Dauntless chip is connected via I2C bus, instead of SPI. Most of the
Dauntless developers will not otherwise have a Chrome OS chroot.
Because of the above, I think it makes sense to have a new variant, for
the reworked devices, which I intend to create with this CL.
BUG=b:169526865
TEST=abuild -t GOOGLE_VOLTEER2_TI50 -c max -x
Change-Id: Ibdcd6c2ce3941c229518f21f0e479890b5d76dd1
Signed-off-by: Jes Bodi Klinke <jbk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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* Use heap for linker script calculated constant to fix relocation
symbols in mixed assembly code.
Tested on HPZ220:
* Still boots in x86_32.
Tested on Lenovo T410:
* Doesn't need the MMX register fix in long mode.
Change-Id: I3e72a0bebf728fb678308006ea3a3aeb92910a84
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory part being added is:
MT53E512M32D2NP-046 WT:E
K4U6E3S4AA-MGCR
H9HCNNNBKMMLXR-NEE
MT53E1G32D2NP-046 WT:A
K4UBE3D4AA-MGCR
BUG=b:169813211
TEST=Build the metaknight board.
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Change-Id: I0d0d22f4790f66b5265803e4dcf01234a16b1993
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Set "GpioOverride" config to override FSP gpio
configuration. FSP will not configure any GPIOs
and rely on GPIO settings programmed before moved to FSP.
BUG=b:150666058
TEST=Build and boot JSLRVP
Cq-Depend: TBD
Change-Id: Ia4036cf0be3a6036d70920743958dc327a652077
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45901
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable SaGv for terrador.
BUG=b:171763116
BRANCH=volteer
TEST="emerge-volteer coreboot" compiles successfully.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ie00166a619424a67f70f870e55822ae2cc6d023d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Change-Id: I5131cf350d5b8c2a45f8d8245c0df26742c0d732
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45533
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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System76 EC firmware supports setting charging thresholds for a single
battery.
Change-Id: I3d656291c096f320d469274677e9fe6c74819d25
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45532
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I83a4a3ad8a9fcb6071e0c700bf2be1676847aa9e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
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Change-Id: I6abbf98398057b9774fcfd9046ba933b5286e4cd
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Configure board specific DPTF parameters for delbin
BUG=b:168958222
BRANCH=volteer
TEST=build and verify by thermal team
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46676
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create the voema variant of the volteer reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.2.0).
BUG=b:171755775
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_VOEMA
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I4e1872d1ebff6fefdfb232f1ff82fce95a1ec643
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47007
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add G2Touch touchscreen support for dood.
BUG=b:171526389
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage, and check touchscreen
work.
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: Ica7d893de285c2dd1efcd43ac74919bdd5d5ac17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46675
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This allows for ccopts symbols and preprocessor to be used inside the
smm.ld linker script.
Change-Id: I4262c09ca52c1fca43c1c115530efe489a722c32
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44321
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add ELAN touch support and update Goodix settings.
BUG=b:157265632
BRANCH=zork
TEST=emerge coreboot and check both touch screen are workable.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Icfc2421061e8b3163d7d5108673351bc17df20ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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The stack needs to be in the coreboot defined region to not collide
with other symbols.
Change-Id: I02a379d2ac73ae30239bd45859c3f09de1a9d0e0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Change-Id: I03841f8263203ee306f83b8f8e859ec03edc3bd3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46885
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This allows to compare the FSP-T output in %ecx and %edx to coreboot's
CAR symbols:
Change-Id: I8d79f97f8c12c63ce215935353717855442a8290
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This change adds the dependency on SOC_INTEL_CSE_LITE_SKU for the
following configs:
1. SOC_INTEL_CSE_FMAP_NAME
2. SOC_INTEL_CSE_RW_CBFS_NAME
3. SOC_INTEL_CSE_RW_FILE
These configs aren't really useful for platforms not using CSE Lite
SKU.
Change-Id: Id48ab36b7e75301d50122916d153f494d755ae77
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46905
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change replaces the checks for dev->enabled with the helper
function `is_dev_enabled()`.
Change-Id: Iacceda396c9300bbfa124e76fb9c99d86313ea0f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46904
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change drops the PCI IDs for Jefferson Peak and Harrison Peak
CNVi modules from wifi/generic drivers as well as pci_ids.h. These IDs
actually represent the CNVi WiFi controller PCI IDs and are now
supported by intel/common/block/cnvi driver.
The only ID that is being dropped without adding support in
intel/common/block/cnvi driver is
PCI_DEVICE_ID_HrP_6SERIES_WIFI(0x2720) since this was not found in the
list of PCI IDs for any SoC.
Change-Id: I82857a737b65a6baa94fb3c2588fe723412a7830
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46866
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change reorganizes the CNVi device entries in mainboard
devicetree/overridetree and SoC chipset tree to make it consistent
with how other SoC internal PCI devices are represented i.e. without a
chip driver around the SoC controller itself.
Before:
chip drivers/wifi/generic
register "wake" = "..."
device pci xx.y on end
end
After:
device pci xx.y on
chip drivers/wifi/generic
register "wake" = "..."
device generic 0 on end
end
end
Change-Id: I22660047a3afd5994400341de0ca461bbc0634e2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
This change adds a common block driver for CNVi WiFi/BT controllers in
Intel SoCs. This driver uses the common PCI dev operations in addition
to generating ACPI device node and returning ACPI name for the
controller device.
This change also selects this driver for CML, GLK, ICL, JSL and TGL.
Change-Id: I69a832be918d4b9f4fbe3a40913d4542a457a77c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
This change adds PCI IDs for CNVi WiFi/BT controllers for CML, GLK,
ICL, JSL and TGL.
Change-Id: Id45f65d0ef5a7782c08ddd70eb22b26072c8ef4b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
This change reorganizes drivers/wifi/generic to add a new
device_operations structure for dummy CNVi device. This is done to
make the organization of CNVi PCI device in devicetree consistent
with all the other internal PCI devices of the SoC i.e. without a chip
around the PCI device.
Thus, with this change, CNVi entry in devicetree can be changed from:
```
chip drivers/wifi/generic
register "wake" = "xxyyzz"
device pci xx.y on end # CNVi PCI device
end
```
to:
```
device pci xx.y on
chip drivers/wifi/generic
register "wake" = "xxyyzz"
device generic 0 on end # Dummy CNVi device
end
end # CNVi PCI device
```
The helper functions for ACPI/SMBIOS generation are also accordingly
updated to include _pcie_ and _cnvi_ in the function name.
Change-Id: Ib3cb9ed9b81ff8d6ac85a9aaf57b641caaa2f907
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46862
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change splits `wifi_generic_fill_ssdt()` into following two
functions:
1. `wifi_ssdt_write_device()`: This function writes the device, its
address, _UID and _DDN.
2. `wifi_ssdt_write_properties()`: This function writes the properties
for WiFi device like _PRW, regulatory domain and SAR.
This split is done so that the device write can be skipped for
CNVi devices in follow-up CLs. It will allow the SoC controller
representation for CNVi PCI device to be consistent with other
internal PCI devices in the device tree i.e. not requiring a
chip driver for the PCI device.
Because of this change, _PRW and SAR will be seen in a separate
block in SSDT disassembly, but it does not result in any functional
change.
Observed difference:
Before:
Scope (\_SB.PCI0.PBR1)
{
Device (WF00)
{
Name (_UID, 0xAA6343DC)
Name (_DDN, "WIFI Device")
Name (_ADR, 0x0000000000000000)
Name (_PRW, Package() { 0x08, 0x03 })
}
}
After:
Device (\_SB.PCI0.PBR1.WF00)
{
Name (_UID, 0xAA6343DC)
Name (_DDN, "WIFI Device")
Name (_ADR, 0x0000000000000000)
}
Scope (\_SB.PCI0.PBR1.WF00)
{
Name (_PRW, Package() { 0x08, 0x03 })
}
Change-Id: I8ab5e4684492ea3b1cf749e5b9e2008e7ec8fa28
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
This change reorganizes the WiFi generic driver to move the ACPI
functions to a separate file. This change is done to reduce the noise
in generic.c file and improve readability of the file.
Change-Id: If5fafb5452fb5bad327be730fcfc43d8a5d3b8ec
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
This change reorganizes the WiFi generic driver to move the SMBIOS
functions to a separate file. This change is done to reduce the noise
in generic.c file and improve readability of the file.
Change-Id: I38ed46f5ae1594945d2078b00e8315d9234f36d7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
This change uses the helper function `acpigen_write_ADR_pci_device()`
to write _ADR object for the WiFi device.
Change-Id: I3ba38f3ec4d8024209840e93bebf2d39bbef7685
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
Instead of having the same linker layout for the transfer buffer between
the x86 & PSP linker layout scripts, put the common layout into a file
shared between the other linker scripts.
BUG=None
TEST=Boot zork board, verify the buffers are aligned.
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ib9d9d8b046bc9e9e7a4ee939324960bfc44c3508
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Terrador and Todor are fanless design, so disable DPTF active policy.
BUG=b:171019363,b:170699797
BRANCH=volteer
TEST=build and verify by thermal team
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I53a33b8706d7a7d4013a2a5627a620223fcffc3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46874
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
HP EliteBook Folio 9480m uses the HP KBC1126 EC ACPI interface, but
with a different GPE, so add a Kconfig option to support using a
different GPE.
Change-Id: I3b78567e1387c96bf173e4370aa3c836bbddac0b
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45576
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update FSP headers for Tiger Lake platform generated based on FSP
version 3425. Previous version was 3373.
BUG=b:172045149
BRANCH=none
TEST=build and boot delbin
Cq-Depend:chrome-internal:3373431
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I58d165d452c8c6ae2eec92524109a568f7e581a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47041
Reviewed-by: Dossym Nurmukhanov <dossym@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Clarify what the function does by renaming it from do_lapic_init() to
lapic_virtual_wire_mode_init().
Change-Id: Ie4430bf0f6c6bf0081b6aaeace351092bcf7f4ac
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Tested with BUILD_TIMELESS=1, Google Wolf does not change.
Change-Id: I029ab0dccbf7b61d641cccf79b491fabf97ab74a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46720
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
With BUILD_TIMELESS=1, Asrock B85M Pro4 and Google Wolf do not change.
Change-Id: I9ba4097cd82c4ff68315a40e1e955e4ed9a43862
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46719
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
There's no need to reinvent the wheel.
Change-Id: If6b90c9a7a00af0322c6dd15d2c4ecf2c513d0cc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46977
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The "Nominal Performance" is not the same as the "Guaranteed
Performance", but is defined as the performance a processor can deliver
continously under ideal environmental conditions.
According to edk2, this is the "Maximum Non-Turbo Ratio", which needs to
be read from MSR_PLATFORM_INFO instead of IA32_HWP_CAPABILITIES.
Correct the entry in the CPPC package.
Test: dumped SSDT from Supermicro X11SSM-F and checked decompiled
version
Change-Id: Ic2c27fd3e14af18aa4101c0acd7a5ede15d1f3a9
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46464
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
GPIO D4 was used for camera reset for both front and rear cameras
(RCAM_RST_L/FCAM_RST_L) in RIPTO. For later volteer versions,
GPIO F15 is dedicated to the rear camera reset (RCAM_RST_L).
Before, BOARD_GOOGLE_VOLTEER flag was used for setting the right
RCAM_RST_L per volteer version. However, we don't support RIPTO
anymore. Also using flags for different volteer version support can
be error-prone. Removing RIPTO support.
BUG=b:171726823
BRANCH=none
TEST=Build and boot volteer proto2 or later version. Camera should
work without an issue.
Signed-off-by: Daniel Kang <daniel.h.kang@intel.com>
Change-Id: I961fc17092887b4807c12c95f7139bb7e7b33e91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46826
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The assembler is warning that the bts instruction is ambiguous, so use
the correct suffix btsl. See also commit 693315160e
(cpu/x86/sipi_vector.S: Use correct op suffix)
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I2eded0af1258e90926009544683b23961d99887b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
The min86 example SoC code along with the example mainboard
should serve as a minimal example how a buildable x86 SoC code
base can look like.
This can serve, for instance, as a basis to add new SoCs to
coreboot. Starting with a buildable commit should help with
the review of the actual code, and also avoid any regressions
when common coreboot code changes.
As the example code itself is build-tested, it should advance
with coreboot and can't rot like documentation might. It also
serves as a check what APIs need to be implemented with the
default Kconfig settings.
Change-Id: Id76ab15fe77ae3e405c43f9c8677694f178be112
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45710
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The camera privacy LED blinks during the boot and this gives a wrong
impression to the users that the camera is being used during the power
up. The blink happens when the camera module is probed and a series of
kernel patches and coreboot patches are being submitted to resolve the
issue.
The kernel patches are submitted to the chromium gerrit.
https://chromium-review.googlesource.com/2403386
https://chromium-review.googlesource.com/2403387
https://chromium-review.googlesource.com/2403385
https://chromium-review.googlesource.com/2403384
https://chromium-review.googlesource.com/2403383
https://chromium-review.googlesource.com/2403382
https://chromium-review.googlesource.com/2403381
https://chromium-review.googlesource.com/2403380
This is to separate the power resource for the VCM so that it can be
controlled by the driver and suppress the LED turn on.
BUG=b:169049942
BRANCH=none
TEST=Build and boot volteer board. Monitor camera privacy LED
and check if it blinks. It should not blink.
Signed-off-by: Daniel Kang <daniel.h.kang@intel.com>
Change-Id: Id51c98e42c5f20e231d8096c9d2d98deebc7c968
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tomasz Figa <tfiga@google.com>
|
|
LTE module Fibocom L850-GL is lost after idle overnight,
with this workaround, host will not initiate U3 wakeup
at the same time with device, which will avoid the race condition.
If this option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR +
offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0.
BUG=b:169645448
BRANCH=octopus
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
the image to the device. Run following command to check if
bits[7:4] is set 0:
>iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I3a04320b0e2441dce540a5afdc461f12de45c41b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
|
|
Use a common function to get the number of CPUs for each soc. This
removes a #if for different function names in the common code.
Change-Id: I3348d37fcae72247731e465ec2a65d9583a2f180
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Prepare for common ACPI. Combine cpx and skx acpi.c into a single
file in xeon_sp. This is almost the last step in using common/block
acpi.
Change-Id: I5f40eb7909bb796907682c548219c7515f2ae4d1
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46600
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Prepare for common ACPI. This primarily makes the skx madt table
generation match cpx. There are a few other small changes to remove
unused code and make the files match.
Change-Id: I71a59181226d79c40a4af405653c50c970fb720b
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46599
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Increase timeout for CPUs to check in after 2nd SIPI completion
from 10ms to 100ms.
Update logging level for mp init failure cases from BIOS_DEBUG
to BIOS_ERR.
Without this patch, "mp initialization failure" happens on some
reboots on DeltaLake server. As consequence, not all 52 cpus
come up in Linux:
[root@localhost ~]# lscpu
...
CPU(s): 40
Also following Hardware Errors are seen:
[ 4.365762] mce: [Hardware Error]: Machine check events logged
[ 4.366565] mce: [Hardware Error]: CPU 0: Machine Check: 0 Bank 9: ee2000000003110a
[ 4.367561] mce: [Hardware Error]: TSC 0 ADDR fe9e0000 MISC 228aa040101086
[ 4.368563] mce: [Hardware Error]: PROCESSOR 0:5065b TIME 948438164 SOCKET 0 APIC 0 microcode 700001d
With this patch, no such failure is observed with 370 reboots.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Iab10f116dd4af152c24d5d8f999928c038a5b208
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46898
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enable the USB4 XHCI driver and remove the ACPI name entry from the
SOC level function.
Define aliases for the USB2/3 ports on north and south XHCI devices in
chipset.cb so they can be referenced in the mainboard devicetree.
BUG=b:151731851
TEST=define usb ports by reference in volteer devicetree and ensure
they get properties added in SSDT for both north and south XHCI device.
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I724ca874d3a3f6a2b43a700b0b10f77f25c53ee0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
In order to generate ACPI entries for USB devices attached to the
USB4/TBT/TCSS/North XHCI device it needs to have a driver that will
enumerate static devices on the bus. This driver does that and nothing
else.
BUG=b:151731851
TEST=boot on volteer and check for USB devices on \_SB.PCI0.TXHC.RHUB
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I5a2ff1cd1bed557e793d45119232cf87032ddd7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46851
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Move CPX and SKX read_msr_ppin() to common util.c file.
Update drivers/ocp/smbios #include to match.
Change-Id: I4c4281d2d5ce679f5444a502fa88df04de9f2cd8
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Move common CPX and SKX chip.c code to chip_common.c.
Change-Id: I158882ab15659858c2b13b4a3e02a26ef8d4ed3c
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Use a simpler pci_domain_read_resource for the stacks. This
makes it the same as the cpx function, since both get the stack
information from the FSP.
This will be merged with common xeon cpx/skx in a later patch.
Change-Id: I0130ce671fe9ff04e48021a0c5841551210aa827
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46308
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add and use resource allocator helper functions from cpx. It also
simplifies the allocator by removing IORESOURCE_PCI64 from the resource
type check. It isn't needed since it is an attribute of IO and MEM and
will be added with the appropriate type.
This clean up matches CPX and will help with merging in the future.
Change-Id: I5812b07ba00eeafb4d1e826e9cdf9a659b0248bb
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46306
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
There are currently 3 different strapping ID entries in the coreboot
table, which adds overhead. The new fw_config field is also desired in
the coreboot table, which is another kind of strapping id. Therefore,
this patch deprecates the 3 current strapping ID entries (board ID, RAM
code, and SKU ID), and adds a new entry ("board_config") which provides
board ID, RAM code, SKU ID, as well as FW_CONFIG together.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I1ecec847ee77b72233587c1ad7f124e2027470bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Further patches will make use of this raw 64-bit value.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I161893c09da6a44265299f6ae3c3a81249a96084
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46604
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We all knew this was coming, 32 bits is never enough. Doing this early
so that it doesn't affect too much code yet. Take care of every usage of
fw_config throughout the codebase so the conversion is all done at once.
BUG=b:169668368
TEST=Hacked up this code to OR 0x1_000_0000 with CBI-sourced FW_CONFIG
and verify the console print contained that bit.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I6f2065d347eafa0ef7b346caeabdc3b626402092
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45939
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Now that soc_get_pmc_mux_device() is gone, the PMC MUX connector devices
can be hooked up together via devicetree aliases.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ib51764da5b3c029f9ac7ac60199a0aedfc7f29b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45878
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Now that device aliases can be used in the devicetree, the hacky function
'soc_get_pmc_mux_device' can be removed and replaced with pointers to the
devices the function was supposed to return (1 for each port).
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie00834c79bd5304998adaccb388ae74a108192b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45747
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Guard CPU code using CPU Kconfig symbols instead of northbridge symbols.
Change-Id: I0e5d7fc2e042381b96d2fbdfa34a3d4bf58201f9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46943
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The current I2C5 bus frequency is 367 kHZ, which does not meet the spec.
This change updates scl_lcnt, scl_hcnt, scl_hcnt value for I2C5 to bring
the bus frequency closer to 400kHz.
BUG=b:153588771
TEST=Verified that I2C5 frequency is between 389-396kHz.
Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com>
Change-Id: If0803a74ba9071acf15486ce4038261c1681a92f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The last argument for acpi_fill_mcfg() is the last PCI bus, which is
an uint8_t, not the total number of busses, which overflows the
argument if CONFIG_MMCONF_BUS_NUMBER is 256.
Change-Id: I8887e14128dbe54688eb6e803d6694b7c29956c1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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Replace the initial bl_errorcodes_public.h (a temporary, minimal
version) with the full version released by AMD.
BUG=None
TEST=Build
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I82585c74d74139a96419b9bffe1df3b8c344eb5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Align coreboot's PSP MboxBiosCmdSmmInfo setup to how AGESA's PSP
library was implemented. The trigger address must be an SMI trigger
register. Assign one of the reserved triggers to the PSP.
The #define of SMITYPE_PSP 33 is still correct and is intentionally
unmodified.
This patch should be innocuous as the system doesn't currently support
SMI-based features of the PSP. The call only exists so the PSP will
honor a mailbox command during S3 suspend.
BUG=b:171815390
TEST=Run SST on Morphius
BRANCH=Zork
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I74029271a522a4f23e54fd76f99a8e3eb0dd4d55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46854
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To verify the consistency, see if timeless builds with and without
this patch result in identical coreboot.rom files.
BUG=b:154032833
TEST=Build & boot on mandolin
Change-Id: Icae73d0730106aab687486e555ba947796e5e757
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This patch hooks coreboot up to the new commonlib/bsd CBFS
implementation. This is intended as the "minimum viable patch" that
makes the new implementation useable with the smallest amount of changes
-- that is why some of this may look a bit roundabout (returning the
whole metadata for a file but then just using that to fill out the rdevs
of the existing struct cbfsf). Future changes will migrate the higher
level CBFS APIs one-by-one to use the new implementation directly
(rather than translated into the results of the old one), at which point
this will become more efficient.
Change-Id: I4d112d1239475920de2d872dac179c245275038d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38422
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds a new CBFS implementation that is intended to replace
the existing commonlib/cbfs.c. The new implementation is designed to
meet a bunch of current and future goals that in aggregate make it
easier to start from scratch than to adapt the exisiting implementation:
1. Be BSD-licensed so it can evetually be shared with libpayload.
2. Allow generating/verifying a metadata hash for future CBFS per-file
verification (see [1][2]).
3. Be very careful about reading (not mmaping) all data only once, to be
suitable for eventual TOCTOU-safe verification.
4. Make it possible to efficiently implement all current and future
firmware use cases (both with and without verification).
The main primitive is the cbfs_walk() function which will traverse a
CBFS and call a callback for every file. cbfs_lookup() uses this to
implement the most common use case of finding a file so that it can be
read. A host application using this code (e.g. coreboot, libpayload,
cbfstool) will need to provide a <cbfs_glue.h> header to provide the
glue to access the respective CBFS storage backend implementation.
This patch merely adds the code, the next patch will integrate it into
coreboot.
[1]: https://www.youtube.com/watch?v=Hs_EhewBgtM
[2]: https://osfc.io/uploads/talk/paper/47/The_future_of_firmware_verification_in_coreboot.pdf
(Note: In early discussions the metadata hash was called "master hash".)
Change-Id: Ica64c1751fa37686814c0247460c399261d5814c
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38421
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Bug=None
Test=Enabled the device on TGLY RVP and tested that the codec is
reflected in SSDT. Checked sound card binding works
and soundwire drivers are enabled in kernel.
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: Ia7358927fe8531e609ebe070bef259a2bbc09093
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Tested on out-of-tree Acer Aspire E5-573, still boots.
Change-Id: I3b9ae75842e3ec1ecd02323d104a9f1d45564172
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46710
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I94a4194e935fddb99645ed2929bdd70583c2fd5b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46709
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It is only used in a single file, on two functions that already check
whether coreboot is running on a Haswell or a Broadwell processor.
Change-Id: I86e1061f722e6d6855190c2fd863d85fc24a1ee0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46708
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These functions are small and used in various stages. Inline them.
Change-Id: I0d15012f264dbb0ae2eff8210f79176b350b6e7f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46707
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Icb57eb89b4f225298e43ae27970dc1e27fb6e222
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46706
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Flesh out the PCH configuration into a separate chip. Keep it within the
Broadwell SoC directory for now, to ease moving files around. The boards
were prepared beforehand and the devicetrees require next to no changes.
Tested on out-of-tree Acer Aspire E5-573, still boots.
Change-Id: I28d948f3e6d85e669d12b29516d867c1d1ae9e1a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46700
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit fa42d568a00e5daadd35722790c529539227130e.
Reason for revert: Passes in an incompatible structure and only happens
to boot by chance. Moreover, Broadwell will soon be merged with Haswell
and this requires Broadwell to not depend on any Intel common SoC code.
Tested on out-of-tree Acer Aspire E5-573, PL values are correct again.
Change-Id: I6e8e000dba8ff09fab4e6f174ab703348dcd6a96
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45011
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Commit 360684b (soc/intel/common: add TCC activation functionality) made
Broadwell use common SoC code. However, this makes Broadwell depend on
SoC code, which prevents splitting Broadwell into CPU, northbridge and
southbridge, a stepping stone before merging with Haswell and Lynxpoint.
Tested on out-of-tree Acer E5-573, still boots.
Change-Id: Ib7ab4e75bd4416dde4612e67405a871da569008a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46731
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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`chip` entries are only hooked up via device nodes to the tree. A `chip`
without a `device` below it does nothing. To allow variants to override
SATA tuning parameters, ensure a device exists under the PCH chip scope.
Without this change, some variants would not properly override the SATA
tuning parameters after extracting the PCH parts into a different chip.
TEST=Sanity-check static.c and verify overridetrees override properly.
Change-Id: I013dbe1403567b93c8ee0e66f76481f2a3f42796
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46769
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tested with BUILD_TIMELESS=1, all variants remain identical.
Change-Id: I0fe6de35f7471ce173df40db1444153623544f00
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46705
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tested with BUILD_TIMELESS=1, coreboot.rom remains identical.
Change-Id: I75d6594f9576c96a585526c652a070cb9616dbe9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46704
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tested with BUILD_TIMELESS=1, all variants remain identical.
Change-Id: I0fa486b8a0fc8be974f37d0bb4eb77a254e8cd86
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46703
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:170604353
BRANCH=volteer
TEST=emerge-volteer coreboot, and boot into kernel.
Change-Id: If354aa158f3ad60193268f38278a44f9c99bf3db
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46770
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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