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2023-01-12soc/intel/skylake/Makefile.inc: Remove path to non-existent directoriesElyes Haouas
Fix: cc1: error: 3rdparty/blobs/mainboard/asrock/h110m: No such file or directory [-Werror=missing-include-dirs] cc1: error: 3rdparty/blobs/mainboard/acer/aspire_vn7_572g: No such file or directory [-Werror=missing-include-dirs] ... Change-Id: Icc43e40514a12944fa180197ffe3230ff9800de9 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-12soc/intel/braswell/Makefile.inc: Remove path to non-existent directoriesElyes Haouas
Found using 'Wmissing-include-dirs' command option. Change-Id: I420b60341dfd0119b14e8492722af62e49fceff8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-12vc/eltan/security/Makefile.inc: Remove path to non-existent directoryElyes Haouas
Fix: cc1: error: ../../src/vendorcode/eltan/security/include: No such file or directory [-Werror=missing-include-dirs] Change-Id: I806b106c641d0d93ed18c87cf6d863c1cce04b03 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71298 Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-12mb/intel/jasperlake_rvp/Makefile.inc: Remove path to non-existent directoryElyes Haouas
Fix: cc1: error: src/mainboard/intel/jasperlake_rvp/variants/jslrvp/include: No such file or directory [-Werror=missing-include-dirs] Change-Id: I5fee0053ab0281b713c33dbc5862c1d4587e854e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-12mb/intel/elkhartlake_crb/Makefile.inc: Remove path to non-existent directoryElyes Haouas
Fix: cc1: error: src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/include: No such file or directory [-Werror=missing-include-dirs] Change-Id: I1c6f6d99cfb3bc08966d662282c023e22e111f90 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-12treewide: Remove unused <cpu/x86/smm.h>Elyes Haouas
Change-Id: Iba5b39c6189d3224ba209c7985153701fe8896fb Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-12treewide: Remove unused <cpu/amd/mtrr.h>Elyes Haouas
Change-Id: Ibff33c08a1d583b19b205a66d5a4267df65ced75 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-12mb/google/skyrim/var/markarth: Update devicetree settingJohn Su
Update devicetree based on the schematic_20230105. BUG=b:263534907, b:263216451 BRANCH=None TEST=FW_NAME=markarth emerge-skyrim coreboot Change-Id: I437425ac4a7cdb883dc213f5f6bb5f8a33a5577b Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71714 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
2023-01-123rdparty/amd_blobs:Advance submodule pointerJason Glenesk
This picks up the following changes: acf73954 phoenix: rename morgana to phoenix a2c15297 mendocino: Upgrade SMU to 90.35.166 28983855 Update Picasso FSP binaries This also updates the phoenix fw.cfg file that points to the submodule. Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I1d04d6232307dc913645a3d60ac3711018e2bdfb Reviewed-on: https://review.coreboot.org/c/coreboot/+/71803 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12soc/amd: Change Morgana codename to PhoenixMartin Roth
Now that the next generation of APUs is officially announced, we can unmask morgana. The chip formerly known as Morgana is actually Phoenix. Surprise! This patch just changes the name across the entire codebase. Note that the fw.cfg file will stay pointing to the 3rdparty/amd_blobs/morgana/psp directory until the amd_blobs_repo is updated. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Ie9492a30ae9ff9cd7e15e0f2d239c32190ad4956 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71731 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12soc/intel/common/block/early_graphics: Introduce a 200 ms delayJeremy Compostella
It has been reported that the PEIM graphics driver may temporarily fail communication with the display if the time between libgfxinit turning off the displays and the PEIM driver initialization is too short. 200 ms has been identified as a safe delay. This is a temporary workaround and an investigation is in progress to come up with a better and long term solution. BUG=b:264526798 BRANCH=firmware-brya-14505.B TEST=Developer screen is systematically seen Change-Id: I4ea15123eed1a4355c5ff7d815925032d4151de1 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71656 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12soc/intel/alderlake: Inform user of memory trainingJeremy Compostella
If memory training is going to happen and early graphics is supported by the mainboard, an on-screen text message is displayed to inform the end user. Memory training can take a while and an impatient end user facing a black screen for a while may reset the device unnecessarily. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=On screen text message during MRC training observed on skolas Change-Id: I4ea15123eed1a4355c5ff7d815925032d4151de0 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70300 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12mb/google/brya: Add romstage early graphics for bryaJeremy Compostella
BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=On-screen text message seen during MRC training on skolas with a few extra patches Change-Id: I41c9cccb09dea52e2318f8f9ebeeda3697a7b514 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71696
2023-01-12soc/intel/alderlake: Add romstage early graphics supportJeremy Compostella
BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=Verify that VGA text mode is functional in romstage Change-Id: I727b28bbe180edc2574e09bf03f1534d6282bdb2 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70303 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12drivers/intel/gma: Enable Alder Lake libgfxinit supportJeremy Compostella
This CL requires the following libgfxinit patches: - https://review.coreboot.org/c/libgfxinit/+/65087 - https://review.coreboot.org/c/libgfxinit/+/65178 - https://review.coreboot.org/c/libgfxinit/+/67489 - https://review.coreboot.org/c/libgfxinit/+/65140 - https://review.coreboot.org/c/libgfxinit/+/67490 - https://review.coreboot.org/c/libgfxinit/+/67491 - https://review.coreboot.org/c/libgfxinit/+/67492 - https://review.coreboot.org/c/libgfxinit/+/67493 - https://review.coreboot.org/c/libgfxinit/+/67494 - https://review.coreboot.org/c/libgfxinit/+/67495 - https://review.coreboot.org/c/libgfxinit/+/67496 - https://review.coreboot.org/c/libgfxinit/+/67497 - https://review.coreboot.org/c/libgfxinit/+/67498 - https://review.coreboot.org/c/libgfxinit/+/67499 - https://review.coreboot.org/c/libgfxinit/+/67500 - https://review.coreboot.org/c/libgfxinit/+/67800 - https://review.coreboot.org/c/libgfxinit/+/67801 - https://review.coreboot.org/c/libgfxinit/+/67802 - https://review.coreboot.org/c/libgfxinit/+/69341 BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=libgfxinit is compiled with the Alder Lake configuration Change-Id: I2de94556f8105447788aaa02340ad669fb68ca0c Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70301 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Zhixing Ma <zhixing.ma@intel.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12soc/intel/common/block: Add Intel VGA early graphics supportJeremy Compostella
This patch introduces an early graphics driver which can be used in romstage in cache-as-ram mode. The implementation relies on `libgfxinit' and provide VGA text mode support. SoCs wanting to take advantage of this driver must implement the `early_graphics_soc_panel_init' function to set the panel power sequence timing parameters. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=Graphics bring up observed on skolas with extra patches Change-Id: Ie4ad1215e5fadd0adc1271b6bd6ddb0ea258cb5b Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70299 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Maulik Vaghela <maulikvaghela@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11mb/google/brya: Enable eNEM support for Tanik and SkolasSubrata Banik
TEST=Able to build and boot Google/Tanik and Skolas to OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4a21122dbc324d3a396e8934e21d42f471cdb0bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/71567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-11mb/siemens/mc_ehl1: Enable real-time tuningWerner Zeh
Enable the real-time tuning to improve performance in the real-time environment for this mainboard. Change-Id: I91ad7ca58add92b5cc66148aff8378890ee217eb Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71234 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11soc/intel/elkhartlake: Provide a way to enable real-time tuningWerner Zeh
Intel provides a Real-Time Tuning Guide for Elkhart Lake to improve real-time behaviour of the SoC (see Intel doc #640979). It describes, amongst knobs for the OS, a couple of firmware settings that need to be set properly to reduce latencies in all the subsystems. Things like clock and power gating as well as low power states for peripherals and buses are disabled in this scenario. This patch takes the mentioned UEFI parameters from the guide and translates them to FSP-M and FSP-S parameters. In addition, a chip config switch guards this tuning which can be selected on mainboard level if needed. When this real-time tuning is enabled, the overall system performance in a real-time environment can be increased by 2-3%. Change-Id: Ib524ddd675fb3ea270bacf8cd06cb628e895b4b6 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-01-11soc/intel/meteorlake: Move ME firmware status register structures toDinesh Gehlot
pertinent header file This patch moves ME host firmware status register structures to ME header file. It also marks unused structure fields to reserved. The idea here is to decouple ME specification defined structures from the source file `.c` and keep those into header files so that in future those spec defined header can move into common code. The current and future SoC platform will be able to select the correct ME spec header based on the applicable config. It might be also beneficial if two different SoC platforms would like to use the same ME specification and not necessarilly share the same SoC directory. BUG=b:260309647 Test=Able to build and boot Google/rex Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ib3dafd6c030c0c848aa82b03bb336cc8fad14de3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71627 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-11soc/intel/alderlake: Move ME firmware status register structures toDinesh Gehlot
pertinent header file This patch moves ME host firmware status register structures to ME header file. It also marks unused structure fields to reserved. The idea here is to decouple ME specification defined structures from the source file `.c` and keep those into header files so that in future those spec defined header can move into common code. The current and future SoC platform will be able to select the correct ME spec header based on the applicable config. It might be also beneficial if two different SoC platforms would like to use the same ME specification and not necessarilly share the same SoC directory. BUG=b:260309647 Test=Able to build and boot Google/brya. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ic14305b0479a8c57531d9930946eded7ac518b09 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71625 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11src/sbom/Makefile.inc: Remove quotes on CONFIG_SBOM_ pathsMaximilian Brune
Make will not find the build targets unless quotes are removed. Change-Id: Iddf4e0cd8a11eaf327d6f55baf38a30c566d0f28 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71519 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11device/Kconfig: Fix selection of software connection managerMartin Roth
The patch that introduced the selection of software connection manager, CB:64561 - 060df17f1d (soc/intel/alderlake/acpi: Add Kconfig options for SCM and FCM) added a default to enable the software configuration manager directly in the choice. This leads to warnings when running make menuconfig: src/soc/intel/alderlake/Kconfig:439: warning: defaults for choice values not supported src/soc/intel/meteorlake/Kconfig:337: warning: defaults for choice values not supported src/soc/intel/tigerlake/Kconfig:299: warning: defaults for choice values not supported I'm not sure why the Kconfig linter didn't catch this, but this issue is currently breaking the build for me. This patch fixes it so that instead of setting the default directly, a new Kconfig value is selected that then sets the default correctly. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I674046a93af8f7c2f3003900804deefa89dae295 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71776 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-01-11ec/google/chromeec: Add retimer flag for mux devicePrashant Malani
Not all ports have retimers. Add a property to denote that a particular port has a retimer (instead of assuming that all ports have retimers). BUG=b:263964979 TEST=Verified on guybrush; SSDT shows retimer-switch on port1 when device tree is updated accordingly. Change-Id: I754323236d2912777b63cede0fce2ccf7882cfea Signed-off-by: Prashant Malani <pmalani@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71663 Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11security/tpm/tspi/log.c: fix strncpy() usageSergii Dmytruk
Change-Id: Ib24129829bef3764a8ba1e2c0d92bc42c5cfbc8d Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-01-11security/tpm: make tspi/crtm.c agnostic to log formatSergii Dmytruk
Change-Id: I3013bd5f29f1412fbe646dc74d8946704b750a66 Ticket: https://ticket.coreboot.org/issues/423 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-01-11treewide: stop calling custom TPM log "TCPA"Sergii Dmytruk
TCPA usually refers to log described by TPM 1.2 specification. Change-Id: I896bd94f18b34d6c4b280f58b011d704df3d4022 Ticket: https://ticket.coreboot.org/issues/423 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-01-11mb/google/geralt: Use BOE_TV110C9M_LL0 as default mipi panelBo-Chen Chen
We will use BOE_TV110C9M_LL0 for geralt proto board, so update the panel setting. BUG=none TEST=emerge-geralt coreboot; see panel-BOE_TV110C9M_LL0 in coreboot.rom Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I28e9dd87350b55fdc609dd2c562c5a2ad578187c Reviewed-on: https://review.coreboot.org/c/coreboot/+/71786 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11mb/google/geralt: Keep booting even if MIPI panel not foundBo-Chen Chen
We should keep booting even failed to get the MIPI panel. BUG=none TEST=emerge-geralt coreboot; Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I39d9e04e5908f669ae2a1a8ce8858b93cae20654 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71785 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11mb/google/skyrim/var/frostflow: Update I2C setting for touchpadRex Chou
Update setting for touchpad I2C frequency. And meet touchpad i2c SPEC (380 ~ 400 kHz). BUG=b:261159229 TEST=On frostflow, touchpad i2c spec from EE measure Frequencies: I2C0 (Touchpad): 389 kHz Change-Id: Ie9efd4e597e2701c98064185e5b39a6e256a5f1c Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71772 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-01-11drivers/ocp/vpd: add get_cxl_mode_from_vpd()Johnny Lin
cxl_mode VPD variable supports 3 modes: CXL_DISABLED, CXL_SYSTEM_MEMORY and CXL_SPM. Change-Id: Ib3bf85fbe687680db3c11efa908c4fb351be9c44 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-01-11soc/intel/xeon_sp: Setup DPR for all VT-d devicesJonathan Zhang
The Data Protected Range (DPR) needs to be set for all DPR devices, not only the root device. Separate the setup from the memory resource map reservation. Change-Id: I7e49db23960e3938e8e158082be3c5ecf3cf95f3 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-01-11soc/intel/{alderlake,tigerlake}: Fix typo in gpio_defs.hJakub Czapiga
Alder Lake and Tiger Lake had unnecessary lower-case 'i' in GPP_C0_IRQ define name. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ida892b00e5a28544950cb9863d0ff2408a514576 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71819 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2023-01-11drivers/intel/gma: Hook up libgfxinit in romstageJeremy Compostella
A mainboard port needs to: - select `CONFIG_MAINBOARD_HAS_EARLY_LIBGFXINIT' - implement the Ada package `GMA.Mainboard' with a single function `ports' that returns a list of ports to be probed for displays. - set the desired `GFX_GMA_DEFAULT_MMIO' IO memory address to use in romstage (and ramstage) for the graphic device. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=libgfxinit compiles in romstage. libgfxinit successfully executes in romstage and ramstage using the requested MMIO setting on skolas. Change-Id: I3c2101de10dc5df54fe873e43bbe0f1c4dccff44 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70276 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11soc/intel/meteorlake: Define SA_DEV_IGD for common codeJeremy Compostella
SA_DEV_IGD is used by the early graphics feature implemented by the Intel common block. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=Compilation Change-Id: Ic9f0fe1683d55a53c705ae717fe9e40fd8873d1f Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-11soc/intel/elkhartlake/chip.h: Include types.h instead of stdint.hWerner Zeh
As the used 'bool' type is defined in stdbool.h, include types.h (instead of stdint.h) which includes all needed header files. Change-Id: I3f75776575a7a5f70484411b9f3458530f706ec4 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71790 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11mb/intel/mtlrvp: Configure USB devices for MTL-RVPHarsha B R
This patch adds OC configuration of USB devices for MTL-RVP as per MTL-RVP design specification, USB 2.0 usb2_ports0 -> OC0 usb2_ports1 -> OC0 usb2_ports2 -> OC0 usb2_ports3 -> OC0 usb2_ports4 -> OC0 usb2_ports5 -> OC0 usb2_ports6 -> OC_SKIP usb2_ports7 -> OC_SKIP usb2_ports8 -> OC_SKIP usb2_ports9 -> OC_SKIP USB 3.2 Gen 2x1 usb3_ports0 -> OC0 usb3_ports1 -> OC0 TCPx tcss_ports0 -> OC0 tcss_ports1 -> OC0 tcss_ports2 -> OC0 tcss_ports3 -> OC0 BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp to chromeOS (on top of CB: 66190). Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: If1a0c31b7bf0f3fc06f039ad76b0cdd41f7cdd90 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-01-11mb/google/nissa/var/craask: Disable storage devices based on fw_configReka Norman
Disable devices in variant.c instead of adding probe statements to devicetree because storage devices need to be enabled when fw_config is unprovisioned, and devicetree does not currently support this (it disables all probed devices when fw_config is unprovisioned). BUG=b:263920313 TEST=Boot to OS on craask eMMC and NVMe SKUs with both unprovisioned fw_config and fw_config set correctly. Change-Id: I4167ee4d00b9ae8fe074c6f5e7a2d5a7382bfe6d Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2023-01-11mb/google/nissa/var/yaviks: Disable storage devices based on fw_configReka Norman
Disable devices in variant.c instead of adding probe statements to devicetree because storage devices need to be enabled when fw_config is unprovisioned, and devicetree does not currently support this (it disables all probed devices when fw_config is unprovisioned). BUG=b:251055188 TEST=Boot to OS on yaviks eMMC and UFS SKUs with both unprovisioned fw_config and fw_config set correctly. On UFS SKU with fw_config set, eMMC no longer shows up in lspci. (On eMMC SKU, UFS and ISH were already disabled by the coreboot PCI scan so there's no change in behaviour.) Change-Id: I31402cb49cffefd98b6fed971f249528448b1d0d Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2023-01-11mb/google/brya/var/omnigul: Add memory parts supportAmanda Huang
Add new memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: 1) Samsung K3KL8L80CM-MGCT 2) Hynix H58G56BK7BX068 3) Micron MT62F1G32D2DS-026 WT:B 4) Micron MT62F512M32D2DR-031 WT:B BUG=b:264340545 BRANCH=firmware-brya-14505.B TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I699070596a77c975254660a1ba74b0f40026186d Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-01-10soc/amd/common/fsp/Makefile: Fix an error messageAkihiko Odaki
It used to say "FSP-M binary larger than FSP_M_FILE", but FSP_M_FILE is the binary itself. The binary file size is actually compared with FSP_M_SIZE. Signed-off-by: Akihiko Odaki <akihiko.odaki@gmail.com> Change-Id: If58069944aea8e68117f2ee1d320726d8c6fdfc8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65440 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-10mb/intel/mtlrvp: Add romstage and configure DDR5 memory partsJamie Ryu
This patch adds initial romstage code and spd data for DDR5 memory parts for MTL-RVP. This also configures memory based on the board id. Memory - x32 DDR5 SBS SODIMM 1DPC Vendor/Model - SK-Hynix/HMCG66MEBSA092N BUG=b:224325352 TEST=Able to boot intel/mtlrvp (DDR5 SKU) to ChromeOS Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: I0e1a26d99e170311a89412f44b7cbb0430788f58 Signed-off-by: Harsha B R <harsha.b.r@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-01-10mb/google/dedede/var/dibbi: Generate SPD ID for supported partsLiam Flaherty
Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. BUG=b:260934724, b:255447299 BRANCH=dedede TEST=build Change-Id: I8c95ced79e14bb4a99aa1fa5f4fc3bc0681cc1cc Signed-off-by: Liam Flaherty <liamflaherty@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71710 Reviewed-by: Adam Mills <adamjmills@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-10mb/google/brya/var/marasov: Update DPTF parametersFrank Chu
Add the first version DPTF parameters. BUG=b:264217345 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I55a3066ef61ce461f40b425a6549d083c29256e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71634 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Kyle Lin <kylelinck@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-10soc/intel: Add Kconfigs to define scaling factor for coresSridhar Siricilla
The patch adds Kconfigs to define scaling factor for Efficient and Performance cores instead of using hard coded values in the soc code. Also, the patches uses the Kconfigs directly to calculate the core's nominal performance. So, we don't need to implement soc function soc_get_scaling_factor() to get the scaling factor data for different core types. Hence, soc_get_scaling_factor() function is removed. TEST=Build the code for Gimble and Rex. Also, I have verified that build system logs error when the Kconfigs are undefined. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I55e4d815116ef40c5f33be64ab495e942bf35ee8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71687 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-10soc/intel/meteorlake: Use common gpio.h includeDinesh Gehlot
Replace the intelblocks/gpio.h, soc/gpio.h and soc/gpio_defs.h includes with the common gpio.h which will include soc/gpio.h which will include intelblocks/gpio.h which will include soc/gpio_defs.h BUG=b:261778357 TEST=Able to build and boot Google/rex. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I58e428cde5e13f4f0dfe528d798c0613b7f8a94a Reviewed-on: https://review.coreboot.org/c/coreboot/+/71630 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-10soc/mediatek/common: Reset the watchdog timer before triggering resetRunyang Chen
When the watchdog timer reaches 0, the timer value won't reset to the default value unless there is an external reset or a kick. It will result in the watchdog failing to trigger the reset signal. We kick the watchdog to reset the timer to the default value. Also, because WDT hardware needs about 94us to synchronize the registers, add a 100us delay before triggering the reset signal. BUG=b:264003005, b:264017048 BRANCH=corsola TEST= Reboot successfully with the following cmd stop daisydog sleep 60 > /dev/watchdog& Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com> Signed-off-by: Kuan-Hsun Cheng <allen-kh.cheng@mediatek.com> Change-Id: Ic4964103d54910c4a1e675b59c362e93c2213b19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71754 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-10chromeos/cr50_enable_update.c: Clear EC AP_IDLE flagDerek Huang
When AP boots up after Cr50 firmware update and reboot, AP finds that Cr50 reset is required for Cr50 to pick the new firmware so it trigger Cr50 reset and power off the system, AP expects system will power on automatically after Cr50 reset. However this is not the case for Chromebox, Chromebox EC set AP_IDLE flag when system is shutting down, when AP_IDLE flag is set in EC, the system stays at S5/G3 and wait for power button presssend. It cause an issue in factory that the operator needs to press power button to power on the DUT after Cr50 firmware update. This patch sends EC command to direct EC to clear AP_IDLE flag after AP shutdown so AP can boot up when Cr50 reset. BUG=b:261119366 BRANCH=firmware-brya-14505.B TEST=DUT boots up after Cr50 firmware update in factory test flow Change-Id: If97ffbe65f4783f17f4747a87b0bf89a2b021a3b Signed-off-by: Derek Huang <derekhuang@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70773 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-10mb/google/brya: Allow respective variant to choose NEM configSubrata Banik
This patch introduces a new config named `DEFAULT_ADL_NEM` and allows respective brya variants with Alder Lake ESx samples to choose NEM over eNEM as eNEM was fuse disabled till ESx. TEST=The boot flow related to eNEM and NEM behaviour remains the same with and without this patch. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ibbd492a3d210739120c7ad16415cb7912f5b70ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/71743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-10mb/google/brya/var/marasov: Disable touch panel power for non-touch skuFrank Chu
Disable touch panel power for non-touch sku by fw_config TOUCH field. BUG=b:263452842 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I4736f94481512806377b733b26fdc7290046c555 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71691 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kyle Lin <kylelinck@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-10mb/siemens/mc_ehl1: Limit SATA speed to Gen 2Werner Zeh
Due to mainboard restrictions a SATA link at Gen 3 (6 Gbps) can cause issues as the margin is not big enough. Limit SATA speed to Gen 2 to achieve a more robust SATA connection. Change-Id: Ia79998db5f959528a4e8e29e570a7f55283adee1 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71230 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-01-10soc/intel/elkhartlake: Make SATA speed limit configurableWerner Zeh
In cases where there are limitations on the mainboard it can be necessary to limit the used SATA speed even though both, the SATA controller and disk drive support a higher speed rate. The FSP parameter 'SataSpeedLimit' allows to set the speed limit. This patch provides a chip config so that this FSP parameter can be set as needed in the devicetree on mainboard level. Change-Id: I610263b34b0947378d2025211ece4a9ec8fbfef6 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71229 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-01-09treewide: Remove unused <cpu/amd/msr.h>Elyes Haouas
Change-Id: Id24a7c7db24f49672df9d5ceefec5b7596f23e09 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-09mb/google/dedede: Use runtime detection for touchscreensMatt DeVillier
Now that power sequencing has been implemented, switch from using ACPI "probed" flag to "detect" flag for all i2c touchscreens. This removes non-present devices from the SSDT and relieves the OS of the burden of probing. BUG=b:121309055 TEST=build/boot Windows/linux on multiple dedede variants, verify all touchscreens functional in OS, dump ACPI and verify only i2c devices actually present on the board have entries in the SSDT. Change-Id: I91e03bd1d96a6b2f0c3813665910133db0d6c308 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-01-09mb/google/dedede: Set touchscreen IRQs to LEVEL vs EDGEMatt DeVillier
The GPIOs themselves are configured as level triggered, and the drivers (both Linux and Windows) work better with LEVEL vs EDGE triggering. TEST=tested with rest of patch train Change-Id: I212533ffdfb05f841e722c130b52c2976272e670 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-01-09mb/google/dedede: Implement touchscreen power sequencingMatt DeVillier
For touchscreens on dedede variants, drive the enable GPIO high starting in romstage, then disable the reset GPIO in ramstage. This will allow coreboot to detect the presence of i2c touchscreens during ACPI SSDT generation (implemented in a subsequent commit). Since the fast majority of dedede variants have a touchscreen option, and those that do use the same GPIOs for enable/reset, set the GPIOs for touchscreen operation in the baseboard and then override for the few (3) variants that do not have a touchscreen. BUG=b:121309055 TEST=tested with rest of patch train Change-Id: Ib95e23545cc3e8589ddbd9e18cd0533bec9333e0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-01-09mb/google/dedede: Add method to set GPIOs in romstageMatt DeVillier
Add method variant_romstage_gpio_table() with empty weak implementation to allow variants to override as needed for touchscreen power sequencing (to be implemented in a subsequent commit). Call method in romstage to program any GPIOs the variant may need to set. TEST=tested with rest of patch train Change-Id: Ic216827a4b53d1d35913efca63a43d4672791c54 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-01-09soc/amd: Remove dummy SOC_SPECIFIC_OPTIONSElyes Haouas
Change-Id: I080b7b579338c3cf342beabda54f43f525d8b65c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-09soc/amd/morgana: Double max number of cpus for morganaRitul Guru
Change-Id: I5169a900345e2aabefcf1e2c249ee4bce6dc8fc5 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-09soc/amd/morgana: update morgana cpuidRitul Guru
Change-Id: Ieaad72a6b964f4b2ab572733694def88e30888a3 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-09soc/amd/mendocino/Kconfig: Remove TODO after reviewFred Reitberger
Remove TODO comments after reviewing against mendocino ppr #57243, rev 3.00 BUG=263563246 TEST=build skyrim Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ie56d481dd8b6b4e0a1e3d50f4ce75f50231fe4dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/71719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-09soc/amd/common/block/graphics: Fix whitespace consistencyFred Reitberger
Replace spaces with tabs for consistency. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I65b9bec7443094dfd2f6b0d6b11e0100023873b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-09soc/intel/xeon_sp/skx: Remove nested check for ACPI supportMarc Jones
Remove redundant nested check for ACPI support. Change-Id: Ie4b40382d304028135bcdd7851e2f48333570421 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-09sb/intel/common/spi: Fix building for 64bitArthur Heymans
This avoids the warning of casting pointers to integers of different size. Change-Id: I7bcb6dbf286438115c854d618eaa2da21c81400d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69389 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-09mb/google/brya: Increase Resizable BAR address space limit to 33 bitsTarun Tuli
The dGPU used for some Brya projects requests 33 bits of address space for one of its BARs via the Resizable BAR mechanism (requires 6GB). This Kconfig is currently set at 32 bits for brya, so the allocation currently is capped at 32 bits (4GB). This patch sets the limit to 33 bits for brya boards, which is enough for the GPU. BUG=b:214443809 TEST=all of the dGPU PCI BARs on agah can be successfully allocated Change-Id: Ia791be5108fb07a256ae62fc2aee2f057909ef12 Signed-off-by: Tarun Tuli <tarun@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-01-09mb/google/brya/var/lisbon: Update RTL8168 LAN LED configRobert Chen
Adjust LAN LED config to 0x060f. BUG=b:246657849 TEST=emerge-brask coreboot Change-Id: Idd5ed2bf7eb4ee5990f2a842cba43f967ae3825e Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71698 Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com>
2023-01-09mb/google/brya/var/gladios: Update RTL8168 LAN LED configRobert Chen
Adjust LAN LED config to 0x060f. BUG=b:239513596 TEST=emerge-brask coreboot Change-Id: I17b844b89569fb7653454fd08782fc961c715817 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71697 Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com>
2023-01-09soc/intel/common: Fix cpu index calculationSridhar Siricilla
get_cpu_index() helper function returns cpu's index based on it's APIC id position from the ascending order list of cpus' APIC IDs. In order to calculate the cpu's index, the helper function needs to traverse through each cpu node to find their APIC IDs. So, the function traverse the CPU node list from the cpu whose APIC ID is 0 assuming it is the first cpu node in the list. This logic works fine where BSP's APIC ID is 0. But, starting from MTL, APIC ID for BSP need not be 0 as APIC ID numbering first get assigned for CPU Die Efficient cores, then Performance cores. Please refer section# 6.1 of doc#643504 for more details on APIC IDs. Considering the APIC Id allotment for MTL cores, as existing code traversing begins from the cpu that has APIC Id#0 which may not be the first cpu node in the list so index calculation results in wrong value. The patch addresses above described issue by traversing all the CPU nodes to calculate the cpu index. Also, prevents inconsistent report of /sys/devices/system/cpu/cpu*/cpufreq/* and /sys/devices/system/cpu/cpuXX/acpi_cppc on each reboot. TEST=Verified that the get_cpu_index helper function returns the correct index id for a CPU on Rex. The coreboot log with code instrumentation, before this patch: [DEBUG] my_apic_id:0x10 cpu_index: 0x6 [DEBUG] my_apic_id:0x11 cpu_index: 0x6 [DEBUG] my_apic_id:0x42 cpu_index: 0x6 [DEBUG] my_apic_id:0x21 cpu_index: 0x6 [DEBUG] my_apic_id:0x40 cpu_index: 0x6 [DEBUG] my_apic_id:0x31 cpu_index: 0x6 [DEBUG] my_apic_id:0x39 cpu_index: 0x6 [DEBUG] my_apic_id:0xa cpu_index: 0x3 [DEBUG] my_apic_id:0x0 cpu_index: 0x0 [DEBUG] my_apic_id:0x8 cpu_index: 0x2 [DEBUG] my_apic_id:0x4 cpu_index: 0x2 [DEBUG] my_apic_id:0x28 cpu_index: 0x6 [DEBUG] my_apic_id:0x2 cpu_index: 0x1 [DEBUG] my_apic_id:0x38 cpu_index: 0x6 [DEBUG] my_apic_id:0x29 cpu_index: 0x6 [DEBUG] my_apic_id:0xe cpu_index: 0x5 [DEBUG] my_apic_id:0x6 cpu_index: 0x2 [DEBUG] my_apic_id:0x20 cpu_index: 0x6 [DEBUG] my_apic_id:0x30 cpu_index: 0x6 [DEBUG] my_apic_id:0x19 cpu_index: 0x6 [DEBUG] my_apic_id:0xc cpu_index: 0x4 [DEBUG] my_apic_id:0x18 cpu_index: 0x6 We can see same cpu_index for multiple cores before fix. After this patch.. [DEBUG] my_apic_id:0x10 cpu_index: 0x8 [DEBUG] my_apic_id:019 cpu_index: 0xb [DEBUG] my_apic_id:0x11 cpu_index: 0x9 [DEBUG] my_apic_id:0x18 cpu_index: 0xa [DEBUG] my_apic_id:0x40 cpu_index: 0x14 [DEBUG] my_apic_id:0x30 cpu_index: 0x10 [DEBUG] my_apic_id:0x42 cpu_index: 0x15 [DEBUG] my_apic_id:0xc cpu_index: 0x6 [DEBUG] my_apic_id:0x2 cpu_index: 0x1 [DEBUG] my_apic_id:0x29 cpu_index: 0xf [DEBUG] my_apic_id:0xe cpu_index: 0x7 [DEBUG] my_apic_id:0x20 cpu_index: 0xc [DEBUG] my_apic_id:0x0 cpu_index: 0x0 [DEBUG] my_apic_id:0x31 cpu_index: 0x11 [DEBUG] my_apic_id:0x28 cpu_index: 0xe [DEBUG] my_apic_id:0x21 cpu_index: 0xd [DEBUG] my_apic_id:0xa cpu_index: 0x5 [DEBUG] my_apic_id:0x38 cpu_index: 0x12 [DEBUG] my_apic_id:0x8 cpu_index: 0x4 [DEBUG] my_apic_id:0x4 cpu_index: 0x2 [DEBUG] my_apic_id:0x39 cpu_index: 0x13 Change-Id: I69e5e6231dd18b43d439340aaed50eb9edeca3b7 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70751 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-09soc/intel/alderlake: Disable Intel TXT based on `INTEL_TXT` configSubrata Banik
This patch makes the call into TXT lib in order to disable the TXT if SoC user haven't selected the `INTEL_TXT` config. Disabling TXT would be helpful to access VGA framebuffer prior calling into FSP-M. TEST=Able to perform disable_txt and unlock memory which helped to access VGA framebuffer prior calling into FSP-M. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9dd7c5492a5f45eef0dd9e836cc2da1844c78919 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71575 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-09security/intel/txt: Add helper function to disable TXTSubrata Banik
Add a function to disable TXT as per TXT BIOS spec Section 6.2.5. AP firmware can disable TXT if TXT fails or TPM is already enabled. On platforms with TXT disabled, the memory can be unlocked using MSR 0x2e6. TEST=Able to perform disable_txt on SoC SKUs with TXT enabled. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I27f613428e82a1dd924172eab853d2ce9c32b473 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-09mb/google/skyrim/var/markarth: Enable DPTC supportJohn Su
Enable DPTC support for markarth. BUG=b:263216451 TEST=emerge-skyrim coreboot Change-Id: I18c2c840037f65f4f2ca92054247cece28843e45 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71720 Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-09mb/google/nissa/var/xivu: Update DPTF parametersIan Feng
Follow thermal table from thermal team. 1. Enable TS3 thermal sensor. 2. Set TS3 passive policy to 63. 3. Set TS3 critical policy to 73. 4. Modify TSR2 passive policy to CPU. BUG=b:263554342 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Ia1fcaee15a8b58b755ce0a48a1978e795b66efd7 Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71658 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: AlanKY Lee <alanky_lee@compal.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-09mb/google/brya/var/gladios: Add ACPI DmaProperty for RTL8168 ethernetRobert Chen
Add ACPI DmaProperty for gladios. BUG=b:239513596 TEST=Verified SSDT on gladios unit. Before: Scope (\_SB.PCI0.RP01) { Device (RLTK) { Name (_HID, "R8168") // _HID: Hardware ID Name (_UID, 0xD0E889DD) // _UID: Unique ID Name (_DDN, "Realtek r8168") // _DDN: DOS Device Name Name (_ADR, 0x00000000) // _ADR: Address Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x07, 0x03 }) } } After: Scope (\_SB.PCI0.RP01) { Device (RLTK) { Name (_HID, "R8168") // _HID: Hardware ID Name (_UID, 0xD0E889DD) // _UID: Unique ID Name (_DDN, "Realtek r8168") // _DDN: DOS Device Name Name (_ADR, 0x00000000) // _ADR: Address Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x07, 0x03 }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"), Package (0x01) { Package (0x02) { "DmaProperty", One } } }) } } Change-Id: I1c4f6ff7b3eda114f4f365a963c089fe584d8aee Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71699 Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-08soc/intel/common: Untie PRMRR from SGXPratikkumar Prajapati
PRMRR is used by many Intel SOC features, not just Intel SGX. As of now SGX and Key Locker are the features that need PRMRR. Untie it from Intel SGX specific files and move to common cpulib. Also rename PRMRR size config option. Use the renamed PRMRR size config option to set the PRMRR size. TEST=Able to set PRMRR size using config. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: I0cd49a87be0293530705802fd9b830201a5863c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70819 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-01-08security/intel/txt: Create Intel TXT lib with helper functionsSubrata Banik
This patch decouples useful TXT related operations from the romstage.c file alone and moves them into a helper txtlib.c. This effort will be helpful for SoC users to perform TXT related operations (like Disabling TXT) even without selecting INTEL_TXT config. At present, those helper functions are only available upon selecting INTEL_TXT which is not getting enabled for most of the SoC platform in the scope of the Chromebooks. TEST=Able to access functions from txtlib.c even without selecting INTEL_TXT config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iff5b4e705e18cbaf181b4c71bfed368c3ed047ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/71573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-01-08include/memory_info.h: Add soc_num to dimm_info structTim Chu
Sometimes, server platforms may have more than one socket on server board. However, there's no field to store information about which socket the DIMM comes from in dimm_info structure. This patch adds soc_num field in dimm_info structure to store socket ID of the DIMM. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I1b9e2b87fda2d7c32ecb8ce9d989795c8b869cea Reviewed-on: https://review.coreboot.org/c/coreboot/+/70662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2023-01-08soc/intel/xeon_sp: select SCO_INTEL_COMMON_BLOCK_TCOJohnny Lin
Also disable TCO timer through calling tco_configure(). If tco_configure() is not called, the TCO timeout would trigger SMI periodically about every 2 seconds with SMM log: "TCO_STS: BIT18 TIMEOUT" Tested=On AC CRB, does not see periodic SMI log. Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: I2d307ad16109ae11862dd5e5acc0f12f47b22582 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2023-01-08soc/intel/xeon_sp: Improve final MTRR solutionJonathan Zhang
If cbmem_top is not 1M aligned there will be a hole between DPR base and cbmem_top that the allocator will consider as unassigned memory. Resources could incorrectly be assigned to that region and the final MTRR solution will also try to skip that hole, therefore using a lot more variable MTRRs than needed. TESTED on Archer City 2S system: Uses 1 variable MTRR in the final setup instead of 7. Change-Id: I198f8d83bcfcdca3a770bd7f9a7060d5782a49fe Signed-off-by: Arthur Heymans <arthur.heymans@9elements.com> Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2023-01-08arch/x86/smbios: Replace SMBIOS type4 processor upgrade fieldsLi, Jincheng
values by macros Macro definitions are from DMTF System Management BIOS (SMBIOS) Reference Specification (DSP0134) Chapter 7.5.5. Change-Id: Ifed1d773b0b349f878648b8172fd770a397e9686 Signed-off-by: Li, Jincheng <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-08soc/intel/alderlake/acpi: Add Kconfig options for SCM and FCMSean Rhodes
Software Connection Manager doesn't work with Linux 5.13 or later, resulting in TBT ports timing out. Not advertising this results in Firmware Connection Manager being used and TBT works correctly. Add Kconfig options to chose between SCM (Software Connection Manager) and FCM (Firmware Connection Manager). FCM is primary, as it's more compatible save for ChromeOS devices as ChromeOS uses SCM. Linux patch: torvalds/linux@c6da62a c6da62a219d028de10f2e22e93a34c7ee2b88d03 Tested with StarBook Mk VI (i7-1260P). Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Iac31d37c0873f41f7b14e1051fe214466d1ebdd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-08soc/intel/meteorlake: Add support to configure package c-state demotionKapil Porwal
This patch adds the support to enable/disable package c-state demotion feature from the devicetree based on mainboard requirement. Port of commit 4be8d9e80deb ("soc/intel/adl: Add support to configure package c-state demotion") BUG=none TEST=Boot to the OS on Google/Rex. Snippet from FSP log: [SPEW ] PkgCState Demotion : 0x1 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I0a4b0b181349ce41035524482add4336cf83a68b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-01-08soc/intel/meteorlake: Set max Pkg C-states to AutoKapil Porwal
This patch configures max Pkg C-state to Auto which limits the max C-state to deep C-state. Port of commit af42906efa72 ("soc/intel/alderlake: Set max Pkg C-states to Auto") BUG=none TEST=Boot to the OS on Google/Rex. Snippet from FSP log: [SPEW ] PkgCStateLimit : 0xFF Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ic403ab83a594b04920d5cf600432939687a2598b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-01-08drivers/amd: Update to use defined post codesMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I2d5700534c07e89b3908a2e6b827db919a48795d Reviewed-on: https://review.coreboot.org/c/coreboot/+/71591 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-08mb/google/skyrim: Switch from LZMA to LZ4 compression for ramstageMartin Roth
Because skyrim is loading ramstage from SPI with the DMA engine, the size of the compressed image is less important to load speed than decompression time. Because the LZ4 decompression is so much faster than LZMA, compressing with LZ4 saves us roughly 30ms in boot time. For size, we're spending roughly 57KiB: fallback/ramstage 0x9b00 stage 130864 LZMA (305316 decompressed) fallback/ramstage 0x9b00 stage 189126 LZ4 (305316 decompressed) Right now we have 2MiB empty space in Skyrim's RO before this change, and roughly 550KiB empty space in RW, so there aren't currently any size worries. Just for fun, I also tested uncompressed ramstage, and it was still 18ms faster than LZMA, but that makes it roughly 12ms slower than LZ4. BUG=b:264409477 TEST=Boot skyrim, look at boot speed. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Iedde6fc2db9d702c0ff2b0081e7baa254ac6699f Reviewed-on: https://review.coreboot.org/c/coreboot/+/71675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-01-08src/lib: Include LZMA in romstage for FSP-MMartin Roth
Previously, LZMA was included in romstage because it was almost always needed to decompress ramstage. When compressing ramstage with LZ4, but using LZMA compression for FSP-M, we still need the LZMA decompression to be present, so update when the Makefile includes the LZMA decoder. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Id52d25a13420f05db8b2b563de0448f9d44638e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-01-08Kconfig: Add option to compress ramstage with LZ4Martin Roth
When ramstage is loaded asynchronously, as on the skyrim boards, the faster decompression of LZ4 allows for faster boot times than the tighter compression of LZMA. To make this change, the name of the existing ramstage_compression option needs to be updated. BUG=b:264409477 TEST=Boot skyrim, look at boot speed Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I27dd1a8def024e0efd466cef9ffd9ca71717486a Reviewed-on: https://review.coreboot.org/c/coreboot/+/71673 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-08mb/google/dedede: Create dibbi variantLiam Flaherty
Create the dibbi variant of the waddledee reference board by copying the template files to a new directory. BUG=b:260934018 BRANCH=dedede TEST=util/abuild/abuild -p none -t google/dedede -x -a includes GOOGLE_DIBBI Change-Id: I3b8d4e7f8a53323f56567cbbc03bab7f8804f286 Signed-off-by: Liam Flaherty <liamflaherty@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71709 Reviewed-by: Adam Mills <adamjmills@google.com> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-08mb/google/skyrim/var/markarth: Update RAM ID tableJohn Su
Add new ram_id:0000 for Micron MT62F1G32D2DS-026 WT:B. Add new ram_id:0010 for Micron MT62F512M32D2DR-031 WT:B The RAM ID table has been assigned as: DRAM Part Name ID to assign K3KL8L80CM-MGCT 0 (0000) H58G56BK7BX068 0 (0000) MT62F1G32D2DS-026 WT:B 0 (0000) K3KL9L90CM-MGCT 1 (0001) H58G66BK7BX067 1 (0001) MT62F2G32D4DS-026 WT:B 1 (0001) MT62F512M32D2DR-031 WT:B 2 (0010) BUG=b:263296326, b:263216451 BRANCH=None TEST=FW_NAME=markarth emerge-skyrim coreboot Change-Id: I3a0d3edb813ef91bfdc68f7400be64fb679dfc04 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
2023-01-08mb/google/nissa: Enable eNEMReka Norman
Enable eNEM for all nissa variants. This is mostly done to be consistent with other recent Intel platforms. It's not strictly necessary since on nissa the LLC size is larger than the total code + data size used in CAR. There is no change in boot time. BUG=None TEST=Boot to OS on craask Change-Id: Iad48976e405403ab61c71d8f72e0616ea8b85ebd Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-01-08mb/google/nissa/var/craask: remove SAR UNUSED fw_configEric Lai
This bit is dropped in factory. All skus can use table ID_0. BUG=b:251287101 TEST=build passed. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I4298376899f881dd2265aef5a0bbc5bcc46728a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71690 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-08mb/google/brya/var/kano: Set the ov2740 to 0 and the hi556 to 1 for SSFCDavid Wu
When EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG is enabled and SSFC is not set, it will treat missing SSFC as zero, so Kano needs to set the ov2740 to 0 to avoid probing wrong mipi camera. Before patch >fw_config match found: UFC=UFC_MIPI_OVTI2740 >fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S >fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S >fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S >fw_config match found: UFC=UFC_MIPI_OVTI2740 >fw_config match found: ZYDRON_UFC=UFC_MIPI_HI556 >fw_config match found: UFC=UFC_MIPI_OVTI2740 >fw_config match found: STYLUS=STYLUS_PRESENT After patch >fw_config match found: UFC=UFC_MIPI_OVTI2740 >fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S >fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S >fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S >fw_config match found: UFC=UFC_MIPI_OVTI2740 >I2C: 00:20 disabled by fw_config >fw_config match found: UFC=UFC_MIPI_OVTI2740 >fw_config match found: STYLUS=STYLUS_PRESENT BUG=b:262939431 TEST=Boot on kano and check functional with ov2740 camera. Change-Id: I46fac6c820d6006956680a07198db82225630905 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-07drivers/pc80/vga: Add legacy VGA romstage supportJeremy Compostella
This is support for adding legacy VGA support into romstage. Support for this is being provided by libgfxinit. The current use case allows us to initialize the display before memory init (prior to physical memory init) to inform the user when lengthy memory training is needed. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=VGA code compiles for romstage Change-Id: I81309871e8db71657b2a9816708141f121d767d3 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70278 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-07mb/google/rex: Disable stage cacheSubrata Banik
This patch disables the stage cache to save boot time. Note: S3 is not POR for Intel MTL mobile skus. Boot time is reduced by ~8ms. Boot time before: 4:end of romstage 1,391,225 (13,724) 100:start of postcar 1,403,339 (12,114) Boot time after: 4:end of romstage 1,380,262 (5,618) 100:start of postcar 1,392,323 (12,060) Change-Id: I9775fc628f345a514894f30435a374e2ffa057c1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-07mb/amd: Update pademelon to eval boardMartin Roth
While pademelon may be a desktop board, it's not available for purchase, which means it should be presented here as an eval board. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I5038935bb6f2ba530ea6e16ac84c1746efec8e48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-07mb/starlabs: Remove the bios_version functionSean Rhodes
Remove smbios_mainboard_bios_version so that the default CONFIG_LOCALVERSION can be used. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ia94f8683a54a98f4e3b1f51521db7e3ccb56ba48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-01-07vc/google: Add and use POST_CODE_CLEAR definitionMartin Roth
The CR50 code clears the post code value. Add this as a #define. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If3b73a3159ac8ac9ab08c6ff705b0ca289ab453c Reviewed-on: https://review.coreboot.org/c/coreboot/+/71592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-06soc/intel/: Rename small and big cores referencesSridhar Siricilla
The patch addresses Intel heterogeneous cores as `Efficient` and `Performance` cores instead of `small` and `big` cores. It is to ensure coreboot code has uniform reference to the heterogeneous cores. So, the patch renames all `small` and `big` core references to `efficient` (eff) and `performance` (perf) cores respectively. TEST=Build the code for Brya and Rex boards Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I98c9c0ed86b211d736a0a1738b47410faa13a39f Reviewed-on: https://review.coreboot.org/c/coreboot/+/71639 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-01-06soc/intel/common: Check PRMRR dependent featuresPratikkumar Prajapati
Add below mentioned functions: is_sgx_configured_and_supported(): Checks if SGX is configured and supported is_keylocker_configured_and_supported(): Checks if Key Locker is configured and supported check_prm_features_enabled(): Checks if any of the features that need PRM are configured and supported. As of now SGX and Key Locker are the only features that need PRM. Also, call check_prm_features_enabled() from get_valid_prmrr_size() to make sure PRM dependent features are enabled and configured before returning PRMRR size. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: I51d3c144c410ce4c736f10e3759c7b7603ec3de9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-06soc/intel/common: Add Kconfig option for Intel Key LockerPratikkumar Prajapati
Add INTEL_KEYLOCKER Kconfig option. Disable it by default. The specification of Key Locker can be found via document #343965 on Intel's site. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: Ia78e9bfe7ba2fd4e45b4821c95b19b8e580dccab Reviewed-on: https://review.coreboot.org/c/coreboot/+/71118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-01-06mb/amd/mandolin/Makefile.inc: Remove path to non-existent directoryElyes Haouas
Fix: cc1: error: src/mainboard/amd/mandolin/acpi: No such file or directory [-Werror=missing-include-dirs] Change-Id: Ifbe6fda12088ddf51b6a177116aa542dbacc7672 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 08:32:56 +0000