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2021-08-09mb/google/dedede/var/storo: Fixed iasl can not run on DutTao Xia
The TSR1._PSV has been redefined. It will report errors when disassembling the ACPI tables with the iasl. It is OK when Removing the TSR1._PSV and adding the TSR0._PSV BUG=b:194509417 BRANCH=dedede TEST=The iasl can run on Dut successfully Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I524255c79d3c71573d122944da5058389f79d95d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Evan Green <evgreen@chromium.org>
2021-08-09mb/intel/adlrvp: Support VBT binaries for LP4 and LP5Bernardo Perez Priego
This will enable to include multiple VBT binaries in a single image and load corresponding file according to HW configuration. BUG=None TEST= Boot device on LP5/LP4, corresponding VBT file should be loaded. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: Iace0e5e0783b2074393a537da8cc645102d2acda Reviewed-on: https://review.coreboot.org/c/coreboot/+/55969 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-09mb/amd/bilby: Set Clk always on for x4 and x8 external PCIe SlotAamir Bohra
Keep the clock source for PCIe slots as always on. Also turn off the unused (0/1/5/6) clock sources. Currently bilby only uses clock sources 2, 3 and 4, out of which clock source 3 and 4 are routed for PCIe external slot. And clock source 2 is routed for M.2 PCIe slot. TEST:Verify end devices enumerate on D:F 1.1/1.2 RPs over warm reboot. Signed-off-by: Aamir Bohra <aamirbohra@gmail.com> Change-Id: Ida485b06279b0a8659c8d00873c3d6023d1e542f Reviewed-on: https://review.coreboot.org/c/coreboot/+/56826 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-09mb/google/brya/variants/taeko: Configure GPIOs according to schematicsJoey Peng
Update initial gpio configuration for taeko BUG=b:195252436 TEST=FW_NAME=taeko emerge-brya coreboot Change-Id: Ida1edbf874c93f6efac45c276920ead9311ac6f2 Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-09mb/google/brya/variants/brya0: set power limits for thermalSumeet Pawnikar
Set power limits for brya0 variant board based on CPU SKUs which is detectable at runtime. BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya0 variant board with below messages, On brya (282): Overriding DPTF power limits PL1 (3000, 15000) PL2 (39000, 39000) On brya (482): Overriding DPTF power limits PL1 (4000, 28000) PL2 (43000, 43000) Change-Id: I4c07319af756b10e5d22f320e97ff956fb4a14c6 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56622 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-09gimble: enable elan touchscreenScott Chao
Enable Elan touchscreen and remove Goodix touchscreen. We also get confirmation by Elan that address is 0x15. BUG=b:195494292 BRANCH=none TEST=build coreboot and dmesg | grep hid, it showed i2c-ELAN9050:00. Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I20a7fd0b370803c14990b77bab302727af197ccb Reviewed-on: https://review.coreboot.org/c/coreboot/+/56801 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-09soc/intel/common/pcie/rtd3: Update _S0W to use symbol instead of 4Tim Wawrzynczak
The code is clearer when ACPI_DEVICE_SLEEP_D3_COLD is used instead of the number 4. Change-Id: I4b0ade1cd0b4b9cdb59f90f8d455269d0b69ed86 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-09drivers/uart/acpi: Update _S0W return value to D3hotTim Wawrzynczak
In order to support wake from D3cold, most devices require extra circuitry and possibly out-of-band communications to the host. Therefore, assume that most UARTs that do have wake capabilities support wake from D3hot rather than D3cold. BUG=b:187228954 TEST=compile Change-Id: I24d6d0e81d980fc9c910d8f47f557c88990b6400 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-09drivers/spi/acpi: Update _S0W return value to D3hotTim Wawrzynczak
In order to support wake from D3cold, most devices require extra circuitry and possibly out-of-band communications to the host. Therefore, assume that most SPI peripherals that do have wake capabilities support wake from D3hot rather than D3cold. This also allows coreboot to expose a power resource to perform power sequencing for a SPI peripheral that is intended to retain power in S3/S0ix. If support for a device with d3cold wake support is needed, it could be added in later as an option. BUG=b:187228954 TEST=compile Change-Id: I1d739b49c1a43007eb0199fe39b3b7d7375e6577 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-09drivers/i2c/da7219: Update _S0W to D3hotTim Wawrzynczak
The DA7219 does not support wake from D3cold, therefore update the return value of _S0W from D3cold to D3hot. BUG=b:187228954 TEST=compile Change-Id: If03f83bb00ec90a2a6646d2c99d8bcc7e5533ac2 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-09mb/google/brya: create dynamic power limits mechanism for thermalSumeet Pawnikar
Add dynamic power limits selection mechanism for brya board based on CPU SKUs which is detectable at runtime. BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya with below messages, On brya (282): Overriding DPTF power limits PL1 (3000, 15000) PL2 (39000, 39000) On brya (482): Overriding DPTF power limits PL1 (4000, 28000) PL2 (43000, 43000) Change-Id: I86619516adeec13642f02ba7faf9fc4945ad774e Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-09mb/system76/oryp6: Drop DIMM_SPD_SIZETim Crawford
The board uses the default size specified in the SoC. Change-Id: Ie71a0fea1ff9de6c4f1ce8db2db09bb3cd35d04d Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-08-09mb/*/jslrvp/dedede: Remove hardcoding of BSP APIC IDMAULIK V VAGHELA
coreboot always assumes that BSP APIC ID will be 0 and core enumeration logic will look for lapic id from the mainboard. As per Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 3: 8.4.1 BSP and AP Processors, this assumption might not hold true and we may have any other core as BSP. To handle this, we need to remove hardcoding of APIC ID 0 from mainboard. BUG=None BRANCH=None TEST=Check if there is no functional impact on the board. Change-Id: I726d70b4ffc35a28a654abbd20c866f1410e1aee Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-09soc/intel/common/cpu: Handle non-zero BSP APIC ID in init_cpusMAULIK V VAGHELA
coreboot always assumes that BSP APIC ID will always be 0 but as per Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 3: 8.4.1 BSP and AP Processors, it says that BSP can be any processor whose index/APIC ID might not be 0. To handle this situation, init_cpu call is required to modify to handle dynamic detection of APIC ID from BSP instead of hardcoding always through devicetree. Function has been updated to create a new node with actual BSP APIC ID when devicetree doesn't contain APIC ID defined. In case APID ID is defined, function will use a node with the APIC ID defined in devicetree. Changes also requires to remove "lapic 0" hardcoding from devicetree to allow code to fill BSP APIC ID dynamically. Otherwise coreboot will create an extra node for CPU with APIC ID 0 and it'll show as a extra node in kernel. This will cause kernel to report wrong (extra) core count information then actually present. BUG=None BRANCH=None TEST=Boot the JSL system and observe there is no functional impacts. Without this CL kernel core count in `lscpu` = 3 With this CL, kernel core count is corrected to 2. Change-Id: Ib14a5c31b3afb0d773284c684bd1994a78b94445 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-09vc/mediatek/mt8195: Optimize DRAM init time by reducing I2C I/ORyan Chuang
Disable reading of vdram/vddq/vmddr to reduce access of I2C to reduce DRAM init time by about 30ms. The values were only needed by HQA report and not needed on production units. BUG=b:195274787 Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: I32cd68fb8b52cec6e145d6772475fde0130ca6ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/56850 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-09vc/mediatek/mt8195: Optimize DRAM init time by limiting frequency countRyan Chuang
Support the config MEDIATEK_DRAM_DVFS_LIMIT_FREQ_CNT to limit DRAM frequency counts to reduce DRAM initialization time by about 100ms. BUG=b:195274787 Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: Ibcb9a50c24f428358ef682b64946d4c91ebd81d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-08-09mb/google/cherry: Improve boot time by raising little CPU frequencyRex-BC Chen
Raise little CPU to 2GHz at romstage to improve boot time by about 100 ms. BUG=b:195274787 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Id6aac8f9db86a6c1e61ea94863f2cbde12c0482e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-08-09soc/mediatek/common: add mt6359p vcore supportJames Lo
Add mt6359p vcore set/get support. To adjust frequency of little core, we need to adjust voltage of vcore. Signed-off-by: James Lo <james.lo@mediatek.corp-partner.google.com> Change-Id: Ibf49390ba78870b834c6d0b64e3f0f30f3494f18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-08-09mb/google/cherry: early-init eMMCWenbin Mei
Some eMMCs need 80+ms for CMD1 to complete. And the payload may need to access eMMC in the very early stage (for example, Depthcharge needs it 20ms after started) so we have to start initialization in coreboot. BUG=b:195274787 TEST=emerge-cherry coreboot BRANCH=cherry Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Change-Id: Idc86f9121fa4a34f09a683f7a81087c13ea3dd42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-08-09mb/google/cherry: select mmc storage configWenbin Mei
Select mmc storage config for cherry. BUG=b:195274787 TEST=emerge-cherry coreboot BRANCH=cherry Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Change-Id: I67c8795b6e6fc121e8fe61c40da05593faa02d94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-08-06mb/google/auron/var/lulu: Uniformise dual-channel handlingAngel Pons
Lulu is the only variant that does not disable channel 1 in pei_data when the SPD index indicates it is unused. For consistency with the other variants that use SPD files, disable channel 1 explicitly. Change-Id: I8c613c5d90075495d2f76d33abf15d74ac63c125 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55802 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-06mb/google/dedede/var/cappy2: Add camera supportSunwei Li
Add camera support in devicetree and associated GPIO configuration. BUG=b:193397569 BRANCH=dedede TEST=Camera function is OK Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com> Change-Id: I3275ab408f6a03735a35eaa8025c36df09c9898c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-06ec/google/chromeec: Add code for KEY_MICMUTE and KEY_KBD_BKLIGHT_TOGGLEScott Chao
- Chromebook have some platform need support MICMUTE and KBDILLUMTOGGLE. - Sync ec_commands.h This change syncs the coreboot version of google ec_commands.h with the ec_commands.h from the google ec repository. This is a straight copy except for the the copyright header. BUG=b:194146863 BRANCH=none TEST=check on evtest type 4 (EV_MSC), code 4 (MSC_SCAN), value 9e type 1 (EV_KEY), code 228 (KEY_KBDILLUMTOGGLE), 1 type 4 (EV_MSC), code 4 (MSC_SCAN), value 9b type 1 (EV_KEY), code 248 (KEY_MICMUTE), value 1 Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: Ie4fa3e627f448265f72279704d258b2d3fe8fc17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56710 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-06arch/x86/acpi: rename KEY_KBDILLUMTOGGLE to KEY_KBD_BKLIGHT_TOGGLEScott Chao
Also change scan code from e02b to e01e. This is trying to fill the gaps in the standard table. The advise from Googler is using e01e for the keyboard backlight toggle key. BUG=b:194146863 BRANCH=none TEST=check on evtest Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I402192ff354f30da35aec43202df9f1407911d34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56763 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-06soc/mediatek/mt8192: initialize DFDRex-BC Chen
DFD (Design for Debug) is a debugging tool, which scans flip-flops and dumps to internal RAM on the WDT reset. After system reboots, those values could be showed for debugging. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I39a4391c1d1e832d77b709f8f899bb1c6dcacd69 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-08-06mb/prodrive/hermes: Update HDA codec subvendor IDAngel Pons
Tested on prodrive/hermes. Change-Id: I72be8bde59d9eb0c1eff8c65dc734c6805732e09 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56086 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: <wouter.eckhardt@prodrive-technologies.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-05soc/amd/common/block/spi: Enable host burst to 4 DWORD when using DMAKarthikeyan Ramasubramanian
Disabling the 4 DWORD bursts causes SPI DMA operations to stall, so leave it enabled when SPI DMA is used. BUG=b:194919326 TEST=Build and boot to OS in Guybrush. Change-Id: I363acdcdb4178a10e4f7eb2bbcbd6d0ca7924f2d Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-08-05soc/amd/common/block/spi: introduce SOC_AMD_COMMON_BLOCK_SPI_4DW_BURSTFelix Held
Add a new Kconfig option to enable or disable the 4 DWORD burst support of the SPI controller and use this setting to determine if the corresponding feature bit in SPI100_HOST_PREF_CONFIG will be set or cleared. Since fch_spi_disable_4dw_burst can now enable or disable the feature, rename it to fch_spi_configure_4dw_burst. On Stoneyridge the SPI_RD4DW_EN_HOST bit needs to be cleared (see the Rd4dw_en_host bit definition in the SPIx2C SPI100 Host Prefetch Config register in the public BKDG #55072 Rev 3.09), so add a SoC dependency to the Kconfig option. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id754fa8d5f9554ed25cf9f3341bfdd1968693788 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-08-05util/elogtool: add tool to print elog eventsRicardo Quesada
Add a new tool that that prints elog events. The tool, as input, accepts either a file with the RW_ELOG contents, or if the file is not provided it reads the contents of RW_ELOG by calling the "flashrom" tool. The tool is based on "mosys eventlog list"[1]. For the moment it only supports "list", but future commits will add additional functionality. This commit also adds missing ELOG defines needed for the tool. These defines are added with the rest of the ELOG defines, in include/commonlib/bsd/elog.h The tool is placed inside util/cbfstool. The rationale behind the decision, is that this tool shares a lot in common with the other tools located in cbfstool: vboot dependency, shared files like common.o and valstr.o, and in spirit is similar to some of the tools located in cbfstool/. As an example, you call the tool like the following: $ elogtool list -f rw_elog_dump.bin [1]: https://chromium.googlesource.com/chromiumos/platform/mosys/+/refs/heads/main/lib/eventlog/elog.c BUG=b:172210863 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Change-Id: Ia1fe1c9ed3c4c6bda846055d4b10943b54463935 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
2021-08-05Move ELOG defines/struct to commonib/bsd/elog.hRicardo Quesada
Move ELOG defines and structs from include/elog.h to include/comonlib/bsd/elog.h. This is needed because the will be used from util/ (in a future commit). It also replaces uNN types with uintNN_t types, for the reason described above. BUG=b:172210863 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Change-Id: I4f307f599a311810df2367b7c888f650cff1214a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-05soc/intel/alderlake: Add GFx Device ID 0x46aaBora Guvendik
This CL adds support for new ADL-M graphics Device ID 0x46aa. TEST=boot to OS Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ib24b494b0eedad447f3b2a3d1d80c9941680c25d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-05mb/intel/adlrvp: Add probed fw_configs to SMBIOS OEM stringsAnil Kumar
This feature was added in ADL-M RVP for discovering correct audio topology using OEM string e.g., "ADL_MAX98373_ALC5682I_I2S" for discovering boards having audio expansion card Bug=None Test= With CBI FW_CONFIG set to 0x100 localhost /home/root # dmidecode -t 11 Getting SMBIOS data from sysfs. SMBIOS 3.0 present. Handle 0x0009, DMI type 11, 5 bytes OEM Strings String 1: ADL_MAX98373_ALC5682I_I2S Change-Id: I05887d9d654eae6d9d2da731d8ab4cf4a05c287f Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55368 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-05mb/intel/adlrvp_m: Enable SaGv supportBora Guvendik
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I80f11b8f0c2a1fdccbc322c3c4783c61684ff37a Reviewed-on: https://review.coreboot.org/c/coreboot/+/55634 Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-05mb/google/brya/variants/gimble: add TcssAuxOriScott Chao
Gimble don't have retimer on port0, the port need to be configured for the SOC to handle Aux orientation flipping. Also add "typec_aux_bias_pads" lets the SoC IOM firmware control the Aux DC bias voltages. BUG=b:195087071 BRANCH=none TEST=check both orientation can output display on type-c monitor. Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I057048c14110bb81bf5b5fd0e3151deb031ca5d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-05mb/amd/majolica:Enable IOMMU Device for majolicaJason Glenesk
Enable IOMMU PCIe device. BUG=b:194173037 TEST=lspci shows IOMMU device 00:00.2 IOMMU: Advanced Micro Devices, Inc. [AMD] Device 1631 Cq-Depend: chrome-internal:4027293,4027294 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Change-Id: Ia84276ca98163158d818a0efc3e021b93ab365de Reviewed-on: https://review.coreboot.org/c/coreboot/+/56771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-05soc/amd/cezanne/fsp_m_params:Configure the iommu_support UPDJason Glenesk
Configure the IOMMU support upd if iommu is enabled. BUG=b:194173037 Cq-Depend: chrome-internal:4027293,4027294 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Change-Id: I56b433cdc1ca5459c51b4b764e22292bd27b8892 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-05soc/amd/cezanne: Generate IVRS for cezanneJason Glenesk
Generate IVRS for cezanne using common IVRS generation code. BUG=b:190515051 TEST=Build cezanne coreboot image. Compare IVRS table with agesa generated tables. Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Change-Id: Ie15addba62ec7da25a7452512b6871e46c61b0a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-05soc/amd/picasso: Move IVRS generation code to commonJason Glenesk
Move IVRS acpi table generation code to common, so that it can be shared by other programs. BUG=b:190515051 TEST=Build picasso coreboot image. Compare IVRS tables before/after change. Change-Id: Icd5fec3a9d66e8301e267312020e726d9bc1aa70 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-05mb/google/dedede: Create bugzzy variantRaymond Chung
Create the bugzzy variant of the waddledoo reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:192521391 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_BUGZZY Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Change-Id: I851b9a75c387586d2fb84b762788e962f33472b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56762 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-05mb/google/brya/variants/primus: enable PS2 interfaceCasper Chang
BUG=b:187969783 Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I1e063524cfa4121c38cfed23e95557953511d884 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-04mb/google/brya/variants/gimble: Remove DPTF fan controlScott Chao
BUG=b:195378817 BRANCH=none TEST=Check fan is able to control by EC Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I84c020e470194072bb796f75f8a1304832504469 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56768 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-04mb/google/dedede/var/magolor: Modify SSFC for camera and touchscreenRen Kuo
The all shipped magolor and maglia has SSFC= 0x840. The value is defined as 5M MIPI camera.But the value:0x840 will conflict with the updated touchscreen field. It will cause some touchscreen no function if make auto-update new firmware.The CL would correct the field error. The original fields: CAMERA_WFC 38 40 TS_SOURCE 41 44 Correct fields: MIPI Cam CAMERA_WFC 38 40 CAMERA_UFC 41 42 CAMERA_VCM 43 44 Touch-screen TS_SOURCE 45 48 The SSFC value of Magolor: CAMERA_OVTI5675 5M AF (SSFC = 0x840) CAMERA_OVTI8856 8M AF (SSFC = 0x880) BUG=b:194639170 TEST=Build firmware and verify on camera and touch-screen devices Change-Id: I13d76ce8b932f483e20ca5388f1c67eb39ba12a1 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56685 Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-04mb/amd/bilby: Add support for HDMI displayAamir Bohra
DDI 0/1 ports are shared for DP and HDMI. This implementation adds support for HDMI display when HDMI is set as connector type in ddi descriptors. TEST=verify display over HDMI(0 and 1) in OS. Signed-off-by: Aamir Bohra <aamirbohra@gmail.com> Change-Id: I9697211c556f12d1fc0d49418b227fbe6b342673 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-04acpi/acpigen_ps2_keyb: Align comments using tabsPaul Menzel
Fixes: ffd80fd2 ("arch/x86/acpi: Add code for KEY_MICMUTE and KEY_KBDILLUMTOGGLE") Change-Id: I2cca8cdbbd3607acca88da7b273ca6b080db9e7c Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-04mb/google/brya/variants/gimble: Update overridetree for gimbleMark Hsieh
According to the schematic diagram of proto, added drivers/i2c/max98390 to device ref i2c0 and deleted device ref hda. BUG=b:191811888 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I0f0a8c84db3fbc963797d11246c5d31b395bb744 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-04Move elog_internal.h to commonlib/bsd/includeRicardo Quesada
Move elog_internal.h to commonlib/bsd/include/bsd/. And rename it from elog_internal.h to elog.h. Since this file will be included from util/ it also converts the "uNN" types into "uintNN_t" types. The two defines that are not used by util/ are moved to drivers/elog/elog.c, the only file that includes them. Move also the function elog_verify_header() from drivers/elog/, to commonlib/bsd/elog.c since this function will be called from util/ as well. The rationale behind moving elog's defines & structs to commonlib/bsd/include is to make them available to util/ tools and/or payloads (should it be needed in the future). The files that are being relicensed to BSD were coded by Duncan Laurie, and he is Ok with the relicense. BUG=b:172210863 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Change-Id: Ia1aefea705ddd417a1d9e978bb18ab6d9a60cad6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-04Move post_codes.h to commonlib/console/Ricardo Quesada
Move post_codes.h from include/console to commonlib/include/commonlib/console. This is because post_codes.h is needed by code from util/ (util/ code in different commit). Also, it sorts the #include statements in the files that were modified. BUG=b:172210863 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Change-Id: Ie48c4b1d01474237d007c47832613cf1d4a86ae1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56403 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-04mb/amd/bilby: Enable DP2 and DP3 enumerationAamir Bohra
DP2 and DP2 is muxed with USBC port. This implementation configures mux for DP functioanlity. TEST=Verify display over DP2 and DP3. Signed-off-by: Aamir Bohra <aamirbohra@gmail.com> Change-Id: If0c8dfbb47175789bb27d4506c1e8b45c425c76a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-04console/hw-debug_sink: Update for fast/slow console distinctionNico Huber
Change-Id: I9ac110c7b812f912f0f87cbe4aa218d4a78e6aaf Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-04soc/intel/cannonlake: Allow to configure maximum package C stateNico Huber
Sometimes it's preferable or even necessary (e.g. stability issues) to limit the maximum package C state. Let's add a devicetree option that keeps the current behavior if it is left unset. Change-Id: I0dc254d34f46de4c65cb85cc92e4b7f26618888d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-04soc/intel/cannonlake: Disable `TccOffsetClamp` if no offset is givenNico Huber
Change-Id: I4f9b62fd944d8a91d53bc584c88797f23de1e5ca Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-04soc/intel/cannonlake/vr_config: Print configured valuesNico Huber
These values are quite important and our default tables sometimes have holes. We should at least make it visible what the resulting settings are. Change-Id: Ic716d073da1c2638c4b16f2eac01b83a0768d22f Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-04soc/intel/cannonlake/vr_config: Add TDC values for CFL-H 6+2Nico Huber
Values were taken from PDG (571391), 51.3 IMVP8 Voltage and Current Requirements. Change-Id: Iffa29386cb7da333353dafd0ba3a61ca61a0ccac Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-04soc/mediatek/mt8195: Add devapc basic driversNina Wu
Add basic devapc (device access permission control) drivers. DAPC driver is used to set up bus fabric security and data protection among hardwares. DAPC driver groups the master hardwares into different domains and gives secure and non-secure property. The slave hardware can configure different access permissions for different domains via DAPC driver. 1. Initialize devapc. 2. Set master domain and secure side band. 3. Set domain remap. 4. Set default permission. Change-Id: I3677657a117caed0d73526f78b0ebe8180148335 Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-08-03mb/google/brya: Add RTD3 for WWANThejaswani Putta
Enable the PCIe RTD3 driver for WWAN device attached to PCIe Root Port 6 and provide the reset GPIO / src clk pins. BUG=None BRANCH=None TEST=Build and boot the coreboot image, check if device is enumerated in the lspci list after warm/cold reboot cycles, run suspend cycles and check if WWAN is entering L2 LPM. Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com> Change-Id: Ie9d1ce55cc1297ea0e1069979bbecfaac8f8de05 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2021-08-03sc7180: Add display support for mipi panelsVinod Polimera
- configure TROGDOR_HAS_MIPI_PANEL to "n" by default, it can be updated for mipi panels. - add simple rm69299 panel as an example to append new mipi panels. - use existing edid struct to update mipi panel parameters. - add dsi command tx interface for mipi panel on commands. Change-Id: Id698265a4e2399ad1c26e026e9a5f8ecd305467f Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org> Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52662 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-03mb/google/brya/variants/primus: configure correct type-c portScott Chao
BUG=b:195274799 TEST=USE="project_primus" emerge-brya coreboot and verify it builds without error. Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I4abf7b2d98b188735ef79f8ffbee4c02099ec021 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56583 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-03soc/intel/*: Allow configuring 8254 timer via CMOSSean Rhodes
Currently, the `USE_LEGACY_8254_TIMER` Kconfig option is the only way to enable or disable the legacy 8254 timer. Add the `legacy_8254_timer` CMOS option to allow enabling and disabling the 8254 timer without having to rebuild and reflash coreboot. If options are not enabled or the option is missing in cmos.layout, the Kconfig setting is used. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ic82c7f25cdf6587de5c40f59441579cfc92ff2f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-03mb/google/brya: Introduce new baseboard braskZhuohao Lee
This patch initiates the brask setting which includes the gpio and device tree setting. BUG=b:191472401 BRANCH=None TEST=build pass Change-Id: I1bb42c7bb2492402de0810bc4ab2e8d8c0e2392b Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-03Revert "mb/google/dedede/var/cret: Disable SDCard controller"Dtrain Hsu
This reverts commit f29437862269de24f85392d49f6afa6fa60ac43e. Reason for revert: It makes cret can't boot to os without depthcharge change. The depthcharge change related with fw_config and will effect other variants. BUG=b:194961854 TEST=Build and boot to OS. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I929369c9419375e74be61a4ff3e5566b0f41ce65 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-03mb/google/brya: Disable crashlog on bryaMAULIK V VAGHELA
Crashlog is a debug feature and not used in normal mode of operation. Disabling this feature will allow us to disable unused IPs and also provide boot time savings of ~5-7 ms. BUG=b:195327879 BRANCH=None TEST=Platform boots and no function impact Change-Id: I1f7def4ea41ff7a566aada080be1e791c11766e6 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56654 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-03mb/google/brya: Create felwinter variantIan Feng
Create the felwinter variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:194431541 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_FELWINTER Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: Iff2b9daec40995a013f9fe0dd76ad667d1807d1b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56765 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02mb/google/brya/variants/redrix: Init devicetree for redrixWisley Chen
Init basic override devicetree based on schematics BUG=b:192052098 TEST=FW_NAME=redrix emerge-brya coreboot chromeos-bootimage Change-Id: I9fb752fe8280893b84c172d8a519578fa4220184 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-08-02mb/google/brya/variants/gimble: configure correct type-c portScott Chao
Change TypeC port1 usb3 port="3". BUG=b:194472269 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: Iaba27aad2adfb0a9e83058ac756ca46a762107bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/56545 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02soc/intel/broadwell: Drop early BAR macrosAngel Pons
They are used at most once. Use the actual values and drop the macros. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I9c1c3ebbbfa64a5eeea3bd5551c3d0068ac0dab2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55799 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02soc/intel/broadwell: Replace soc/intel/common includeAngel Pons
Broadwell now uses the Lynx Point hda_verb.c and should thus use the corresponding header as well. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I9b8ca91bed67be9c6850bd51f4c81e002a0f5aef Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55797 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02soc/intel/broadwell/pch/pch.c: Drop unused includeAngel Pons
For some reason, this change makes ramstage slightly smaller. Change-Id: I5564e06b797d787f0d1093bd9bd572d1ee7b2d54 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55583 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02soc/intel/broadwell: Drop unused function declarationsAngel Pons
These functions are never defined. Remove the unused declarations. Change-Id: I4204265680d06bf83fc42f061fd7270ff8e3305e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55798 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02soc/intel/broadwell: Rename `ramstage.h`Angel Pons
This file only contains the `broadwell_run_reference_code()` function prototype (either a declaration or an inline stub definition). Rename this file to refcode.h and only include it where necessary. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I6513f45b8914a84312b27ef4860870a89fd0aab3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55582 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02mb/siemens/mc_ehl: Enable master bit in PCI config space if allowedWerner Zeh
Some legacy devices need to have the master bit set in the PCI config due to old drivers not setting it correctly. Set the master bit if the feature is enabled via Kconfig switch PCI_ALLOW_BUS_MASTER_ANY_DEVICE. For now, the PCI devices with the ID 110a:403e and 110a:403f needs this master bit to be set. Change-Id: Id3f6bda97e5f47d0613a1db8f8adac0b158ab8b1 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56632 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02mb/siemens/mc_ehl: Add code to wait for legacy devices before PCI scanWerner Zeh
Boards based on mc_ehl have, just like some mc_apl variants, legacy devices on the PCI bus which take longer to boot. In order to ensure that they will be enumerated correctly wait for them to come up before PCI scan starts. TEST=Checked that the new message is visible in the log. Change-Id: If2f935b69ddaa9364566deacfada5e7d41fcdabd Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56631 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02mb/google/kukui: Add new config 'pico' in corebootLucas Chen
Add new board 'pico' and set correct ram_id offset. BUG=b:194985056 TEST=None BRANCH=kukui Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Change-Id: I33c37d99fa0451239bc6626e71bfddb29a11e97b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-08-02helpers: Add GENMASK macroYu-Ping Wu
The GENMASK is defined in multiple files (with various names such as MASKBIT), which sets certain consecutive bits to 1 and leaves the others to 0. To avoid duplicate macros, add GENMASK macro to helpers.h. GENMASK(high, low) sets bits from `high` to `low` (inclusive) to 1. For example, GENMASK(39, 21) gives us the 64-bit vector 0x000000ffffe00000. Remove duplicate macro definitions. Also utilize GENMASK for _BF_MASK in mmio.h. BUG=none TEST=make tests/commonlib/bsd/helpers-test TEST=emerge-cherry coreboot BRANCH=none Change-Id: If2e7c4827d8a7d27688534593b556a72f16f0c2b Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-08-02mb/google/brya: Update entries for UFC to support IMX208Varshit B Pandya
1. Replace OV5675 ACPI entries with IMX208 2. Replace FW_CONFIG name 3. Add support for NVM inside UFC BUG=b:190674542 TEST=Build and boot to OS on Brya, raw capture on UFC Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I6a3bf13ec844fb46e11ce58382057fcc7187c135 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-08-02mb/google/brya: Configure H21 as GPO and A17 as lowVarshit B Pandya
As per the schematics, UFC has on card oscillator so we donot need H21 in NF1 that is IMGCLKOUT H21 is used to enable this oscialltor so configuring it as 1 A17 is configured as high while _ON method is called by driver and it is configured as low when _OFF method is called by driver. Hence coreboot should configure it as low on boot. BUG=b:190674542 Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I745169a5ab6a9c20b6e1bda792a43193d04ac48d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56655 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02mb/google/dedede/var/cappy2: Disable external bypass VRSunwei Li
The cappy2 removed the anpec apw8738bqbi and "disable_external_bypass_vr" should be set to "1" to disable BUG=b:194146867 BRANCH=dedede TEST=VCCIN_AUX is disable Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com> Change-Id: Ieb4182a989459db629e3b69757c293ca26e8b0cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/56687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aseda Aboagye <aaboagye@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
2021-08-02mb/google/dedede/var/cappy2: Add Tpm2.0 device supportSunwei Li
Using Tpm2.0 device instead of the Cr50 in cappy2 BUG=b:191743435 BRANCH=dedede TEST=tpm2.0 device function is ok Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com> Change-Id: I216ceb6386ad57c9f1982187a4525d89869fa9c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56658 Reviewed-by: Aseda Aboagye <aaboagye@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02soc/intel/broadwell: Rename `SA_DEV_ROOT`Angel Pons
For consistency with Haswell, rename this macro to `HOST_BRIDGE`. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I4319f04c67aec8df118fa539e00c7328128f0700 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55528 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02soc/intel/broadwell: Drop helper functionsAngel Pons
Done for consistency with Haswell in order to ease unification. Change-Id: I445f086cfcb65a6001ced3326fb9f25a4188b888 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55527 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02nb/intel/haswell: Move MRC glue code into a subfolderAngel Pons
Put the Haswell MRC glue code inside a `haswell_mrc` subfolder. Future commits will move the Broadwell MRC/refcode glue code to be in Haswell northbridge scope, so plan in advance. Tested on Asrock B85M Pro4, still boots. Change-Id: Id3e26ec1c2d5ccce928083d7ce41445908df8cf3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55523 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02nb/intel/haswell/gma.c: Add ULX PCI device IDsAngel Pons
Change-Id: Ida3d2dcdf89342b084c8e1fbf3fae7e47a7238d2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50137 Reviewed-by: Jamal Wright <Crabstorage@getbackinthe.kitchen> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-31soc/amd/common/block/acpi: Add IVRS kconfigJason Glenesk
Add new IVRS kconfig option to control IVRS generation. BUG=b:190515051 Change-Id: Iad0c6401dbccd2f3f75464a69e4c27f64d3507a5 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-31arch/x86/acpi: Add code for KEY_MICMUTE and KEY_KBDILLUMTOGGLEScott Chao
Chromebook have some platform need support MICMUTE and KBDILLUMTOGGLE. BUG=b:194146863 BRANCH=none TEST=check on evtest type 4 (EV_MSC), code 4 (MSC_SCAN), value ab type 1 (EV_KEY), code 228 (KEY_KBDILLUMTOGGLE), 1 type 4 (EV_MSC), code 4 (MSC_SCAN), value 9b type 1 (EV_KEY), code 248 (KEY_MICMUTE), value 1 Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: Ic39ecb3118e885c9e6d84d7b78bf435cb903d17e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao
2021-07-31mb/google/dedede/var/boten: Set the xHCI LFPS period sampling off time to 0msstanley.wu
LTE module L850-GL may encounter U3 wakeup race condition with the host. Setting xHCI LFPS periodic sampling off time to 0ms so that the host would not miss the device-initiated U3 wakeup thus avoid the race condition. BUG=b:187801363 BRANCH=dedede TEST=flash the image to the device. Run following command to check the bits[7:4] is 0x0: iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: stanley.wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I9328e758ed92389e44b25ff4daf6ec19b37ae7d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Ben Kao <ben.kao@intel.corp-partner.google.com>
2021-07-31soc/amd/common/block/gpio_banks: use unsigned int for gevent parameterFelix Held
A valid GEVENT number is never negative. The local variable in set_single_gpio still needs to be a signed integer, since the return value of get_gpio_gevent being -1 indicates that the GPIO can't generate a GEVENT. The check for that makes the function return before calling program_smi of program_sci, so the parameter of those functions can be changed to unsigned. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6ce23ceed1585589932824b8cab2a138328672a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56705 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-31soc/amd/common/block/gpio_banks/gpio: add missing newlineFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I87595aea45bb3852a70c7322eae5a94abecb76a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56704 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-31soc/amd/common/block/gpio_banks/gpio: add comment in check_gpiosFelix Held
Each bit in the GPIO wake status index registers is set to 1 when at least one of 4 corresponding GPIO pins has its wake status register set. Added the comment since the gpio_base + i * 4 in the next line looked as if it calculates some absolute register value which is not what the code does or should be doing. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2fc8e9c5bd7c1b011f364b05d0cfdeb0df88ada6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56703 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-31soc/amd/common/block/gpio_banks/gpio: use size_t where neededFelix Held
Since the parameter the variable gets compared with is size_t type, use size_t as type for that variable too. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If82a948bf71079d456616f4438f4b754e0d7262d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56702 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-30soc/amd/common/block/include/gpio_banks: use gpio_t for gpio numbersFelix Held
With the addition of the remote GPIO support, the GPIO number won't fit into 8 bit any more, so use the gpio_t type instead which is an uint32_t typedef. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3de93fd3a2f2af3c1e3b335fef84019c56482051 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56693 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-30soc/amd/common/block/gpio_banks/gpio: factor out set_gpio_muxFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I75f1e45ead4a5f04cba1eecb220ef027a8bfd09e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56678 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-30soc/amd/common/block/include/acpimmio_map: drop unused GPIO bank definesFelix Held
The offsets of all GPIOs in the up to four regular banks are all calculated relatively to ACPIMMIO_GPIO0_BANK, so we can just drop the unused defines for ACPIMMIO_GPIO1_BANK and ACPIMMIO_GPIO2_BANK. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I832ffdca479c1f07219a23b4a7f9be69322dfe03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56675 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-30soc/amd/common/block/include/acpimmio_map: add GPIO bank 3 to tableFelix Held
GPIO bank 3 isn't used in coreboot, but the existence is documented in both the Picasso PPR #55570 Rev 3.16 and Cezanne PPR #56569 Rev 3.01 and for those two SoCs all 4 banks are covered by the corresponding Memory32Fixed region in the DSDT. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id444a97a398d7e3abfd1f5c4a32e762ee6ff68f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56674 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-30vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2265_01Ronak Kanabar
The headers added are generated as per FSP v2265_01. Previous FSP version was v2237_00. Changes Include: - Add Irms UPD in FspsUpd.h - Adjust Reserved UPD Offset in FspsUpd.h - Few UPDs description update in FspmUpd.h BUG=b:194032028 BRANCH=None TEST=Build and boot brya Change-Id: I49b1187d9dcedade47951274db49b7bdc437679f Cq-Depend:chrome-internal:4004482 Cq-Depend:chrome-internal:4003608 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56511 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-30mb/google/brya/variants/primus: Disable PCIe6Malik_Hsu
WWAN (fibocom L850-GL) works in USB mode, so turn off PCIe 6. BUG=b:194861116 Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: Ie04a5bb2af9ce11f57339f460a7f880bfc14b688 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-29mb/google/dedede/var/cappy2: Add I2C devicesSunwei Li
Add tp and audio devices support in devicetree. BUG=b:193099842 BRANCH=dedede TEST=i2c devices function is OK Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com> Change-Id: I995e93b5a4c4294d6f6b97c48d14fabf48004d92 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56513 Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29vc/intel/fsp/fsp2_0/alderlake: Update MemInfoHob.h for new FSPEric Lai
Sync the MemInfoHob.h with current FSP code. BUG=b:190339677 TEST=dmidecode -t 17 can show the memory information. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I80d1252b1f12b164d4f6d3a01221507cdfbe4d08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-07-29mb/google/brya: add BASEBOARD_DIR to support different baseboardZhuohao Lee
In order to support different baseboard configuration, we add the BASEBOARD_DIR to switch the directory. The expected structure looks like: mb ..|_ google .........|_ brya .............. |_ variants .....................|_ baseboard ..............................|_ brya ....................................|_ gpio.c ....................................|_ memory.c ....................................|_ devicetree ..............................|_ brask ....................................|_ gpio.c ....................................|_ memory.c ....................................|_ devicetree ......................|_ brya_variant1 ......................|_ brya_variant2 ......................|_ ... ......................|_ brask_variant1 ......................|_ brask_variant2 ......................|_ ... ...............|_ <all mb common code> BUG=b:191472401 BRANCH=None TEST=build pass Change-Id: Ic99e42dbbd27fa3e1f6cb3a1b5daee1c8c7b1083 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-07-29mb/google/dedede: Configure VCCIOSEL for EN_SPKR GPIO PadKarthikeyan Ramasubramanian
Realtek speaker amplifiers under auto mode operation have Absolute Max Rating (AMR) at 1.98 V. Hence probe the firmware config for speaker amplifier and program the VCCIOSEL accordingly. BUG=b:194120188 TEST=Build and boot to OS in Storo. Ensure that the VCCIO selection is configured as expected and probing the GPIO reads the configured voltage. Change-Id: Ibd3bc90bd0bbc9a35922b29e3d1e106321bc7a06 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56616 Reviewed-by: Evan Green <evgreen@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29mb/siemens/mc_ehl1: Disable LTR for all PCIe root portsWerner Zeh
Latency Tolerance Reporting is yet another PCIe power management feature which can have a bad influence on realtime performance. Disable this feature for all PCIe root ports. Change-Id: I38023e095ca55efd2178ad944f651fee1f1c34cd Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-07-29mb/siemens/mc_ehl1: Disable L1 substates for PCIe root portsWerner Zeh
L1 substates of a PCIe link are meant to save some power when the link is not active but have the drawback that the PCIe latency is increased as PLLs are switched on and off as needed. In order to get a better realtime performance, disable all substates for every PCIe root port. Change-Id: Ic5bc8410709d0f0094810bc11a7723e88c30e397 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 00:43:09 +0000