summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2022-02-03mb/google/brya: Add SPD configs for nivviks and nereidReka Norman
Add a mem_parts_used.txt for each of nivviks and nereid, containing the memory parts used in their pre-proto builds. Generate Makefile.inc and dram_id.generated.txt using part_id_gen. nivviks: Micron MT62F1G32D4DR-031 WT:B nereid: Samsung K3LKBKB0BM-MGCP BUG=b:197479026 TEST=Build nivviks and nereid. Use cbfstool to check that coreboot.rom contains an spd.bin. Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Ia3e5ee22199371980d3c1bf85e95e067d3c73e67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-03mb/google/brya: Fill in ec.h for nissa baseboardReka Norman
BUG=b:197479026 TEST=abuild -a -x -c max -p none -t google/brya -b nivviks abuild -a -x -c max -p none -t google/brya -b nereid Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I322a94569d8a63e8c0da68a8feb394ade4ce7999 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-03mb/google/brya: Add memory config for nissaReka Norman
Fill in the memory config based on the the schematic and doc #573387. BUG=b:197479026 TEST=abuild -a -x -c max -p none -t google/brya -b nivviks abuild -a -x -c max -p none -t google/brya -b nereid Change-Id: I6958c7b74851879dbea41d181ef8f1282bf0101d Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-03mb/google/brya: Fill in gpio.h for nissa baseboardReka Norman
BUG=b:197479026 TEST=abuild -a -x -c max -p none -t google/brya -b nivviks abuild -a -x -c max -p none -t google/brya -b nereid Change-Id: I7ec4b9368e0a63c0c0c9a92c8367a89d57f10d51 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-03mb/google/brya: Add Kconfig for SLP_S0_GATEReka Norman
Nissa doesn't have a SLP_S0_GATE signal, so we shouldn't generate the related ACPI code. Therefore, move this behind a Kconfig which is currently selected by the brya and brask baseboards. BUG=b:197479026 TEST=Build brya0, check that there's no change to the generated dsdt.asl Change-Id: I5a73c6794f6d3977cbff47aeff571154e41944cc Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-03mb/google/brya: Add GPIO table for nissaReka Norman
Fill in the nissa baseboard GPIO table based on the nivviks P0 and nereid P0 schematics. Also, add an override GPIO table for each of nivviks and nereid. The differences between nivviks and nereid are: - WFC: nivviks has a MIPI WFC and nereid has a USB WFC, so the MIPI-related pins are overriden to NC on nereid. - The DMIC pins and speaker I2S pins were swapped after nivviks P0. The baseboard reflects the new configuration, which will be used in nivviks P1 onwards, nereid, and future variants. For now, nivviks overrides the pins to the old configuration. Once nivviks P1 is released, this will need to be updated to handle both. BUG=b:197479026 TEST=abuild -a -x -c max -p none -t google/brya -b nivviks abuild -a -x -c max -p none -t google/brya -b nereid Change-Id: Ic923fd22abcaf7da0c607f66705a6e16c14cf8f2 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-03mb/siemens/mc_ehl2: Disable PCIe RPsMario Scheithauer
With latest hardware revision only PCIe RP2 and RP7 are used on this mainboard. Change-Id: I7702c2b9058dde1c819cb1df8a68fd602f5997da Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-02-03mb/siemens/mc_ehl2: Disable SATAMario Scheithauer
With latest hardware revision SATA interface is no longer used on this mainboard. The mainboard is still in development and not yet released and for this reason there may still be adjustments. Change-Id: Icbf088ce4c907e207f6f5d11b8bf5556fe2c90d6 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-02-03soc/intel/cannonlake: Forbid FSP from disabling HECI1Subrata Banik
The functionality of disabling HECI1 device has been moved from the FSP to coreboot (using `DISABLE_HECI1_AT_PRE_BOOT` config), hence, always set the `Heci1Disabled` UPD to `0`. BUG=none TEST=Boot to OS, verify HECI1 is disabled on hatch system using coreboot when mainboard selects DISABLE_HECI1_AT_PRE_BOOT config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia8908c080ca9991e7a71e795ccb8fc76d99514f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-02-03cpu/x86/smm: Retype variablesArthur Heymans
Change-Id: I85750282ab274f52bc176a1ac151ef2f9e0dd15d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-02-02mb/google/guybrush: Enable PSP port 80sRaul E Rangel
Let's re-enable PSP post codes when running PSP verstage. The original reason we disabled POST codes was that it was causing problems during eSPI init in bootblock. Since we now init eSPI in PSP verstage, it's safe to re-enable them. We can now see post codes during S0i3 enter and exit. This will help when debugging resume or suspend hangs. Port 80 writes on suspend: ef000020 ef00ed00 ef00ed01 ef000021 <--new Port 80 writes on resume: 05 eea80025 eea90000 eea90100 eea90200 eea50000 eeae0000 eeae0004 eeaf0000 eeb00000 eec00000 eec00100 eec10000 eec40000 eec40500 eec40200 eefc0000 eefc0100 eec50000 ea00e0fc ea00abc1 ea00e60b ea00e60c ea00abe1 ea00abe2 ea00abe4 ea00abe5 ea00abeb ea00abec ea00abed ea00abee ea00abef ea00e10f ea00e098 ea00e099 ea00abf0 ea00abf2 ea00e10e ea00e60c ea00e101 ea00e090 ea00e091 ea00e098 ea00e099 ea00e098 ea00e099 ea00e100 ea00e60c ea00e0b0 ea00e0b4 ea00e0b7 ea00e60c ea00e0c2 ea00e0c4 ea00e0d3 ea00e60c ea00e10d ea00e0c1 ea00e10c ea00e60c ea00e0c4 e000 eec60000 eec20000 eec20800 b40000 eeb50000 eefc0000 eefc0300 ee070000 eed90000 eed90700 eeda0600 eedd0000 eecb0000 eecf0000 eecf0200 eee30000 eee30900 eee40000 ef000025 BUG=b:215425753 TEST=Boot/suspend/resume guybrush and verify post codes are printed Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ie759f66be2b8ffac19145491a227752d4762a5b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-02soc/amd/cezanne: Rename PSP_POSTCODES_ON_ESPI to PSP_INIT_ESPIRaul E Rangel
This flag only controls eSPI init in the PSP Stage 2 Boot Loader. It doesn't control if port 80s are written. This flag also doesn't currently control LPC init. The PSP is currently hard coded to remove any LPC init. BUG=b:215425753 TEST=build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Idf3f0dcc216df2fd15b016f9458a208b7e15c720 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61534 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-02soc/amd/cezanne,vc/cezanne: Implement svc_write_postcodeRaul E Rangel
This will allow verstage to write post codes. BUG=b:215425753 TEST=Boot guybrush and verify PSP post codes are printed 22-01-31 15:12:03.214 (S3->S0) 22-01-31 15:12:03.214 03 04 0f 0e f0 f1 f2 01 10 a0 a2 <--new Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I6ceee8fcb094f462de99c07aef8e96425d9c3270 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61522 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-02drivers/intel/fsp2_0/include/fsp: fix fsp_headerJulian Schroeder
This patch aligns fsp_header with the Intel specification 2.0 and 2.3. The main impetus for this change is to make the fsp_info_header fully accessible in soc/vendor code. Here items such as image_revision can be checked. TEST=verify image revision output in the coreboot serial log. compare to FSP version shown in serial debug output. verify Google Guybrush machine boots into OS. Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com> Change-Id: Ibf50f16b5e9793d946a95970fcdabc4c07289646 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-02drivers/i2c/designware/dw_i2c: use cb_err for dw_i2c_gen_speed_configFelix Held
Using enum cb_err as return type instead of int improves the readability of the code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8d96e5f72a8b3552ab39c1d298bafcc224bf9e55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61512 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-02mb/prodrive/hermes: Add VT-x control via EEPROMAngel Pons
Introduce a new field in the board settings EEPROM region to control whether VT-x is to be enabled. Change-Id: If65c58dd6e5069dba1675ad875c7ac89e704350e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
2022-02-02soc/intel/cannonlake: Add `disable_vmx` devtree optionAngel Pons
This option isn't meant to be assigned statically through devicetrees, but at runtime according to some config mechanism. It works in conjunction with the existing Kconfig option. Change-Id: Ia760be61466bc6a0ec187746e6e32537029512b4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
2022-02-02cpu/intel/common: Add `set_feature_ctrl_vmx_arg()`Angel Pons
Allow deciding whether to enable VMX through a function parameter. Used in a follow-up. Change-Id: I4f932de53207cd4e24cb4c67d20c60f708bfaa89 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
2022-02-02mb/google/brya/var/vell: Enable SaGvGaggery Tsai
This patch enables SaGv since somehow it was accidently removed by commit a52b9c3. BUG=b:208719081 TEST=FW_NAME=vell emerge-brya coreboot Fixes:a52b9c3 ("mb/google/brya: Move gpio_pm settings for brya variants to baseboards") Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Change-Id: Ideae3dbd9746590db104d93afadbd8d574298b83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-02soc/intel/alderlake: Use PMC IPC to disable HECI1Subrata Banik
This patch allows common CSE block to disable HECI1 device using PMC IPC command `0xA9`. Select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC config for Alder Lake to disable HECI1 device using PMC IPC. Additionally, remove dead code that deals with HECI1 disabling using in SMM as HECI1 disabling using PMC IPC is simpler solution. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I11a677173fd6fb38f7c09594a653aeea0df1332c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-02-02soc/intel/tigerlake: Use PMC IPC to disable HECI1Subrata Banik
This patch allows common CSE block to disable HECI1 device using PMC IPC command `0xA9`. Select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC config for Tiger Lake to disable HECI1 device using PMC IPC. Additionally, remove dead code that deals with HECI1 disabling using in SMM as HECI1 disabling using PMC IPC is simpler solution. BUG=none TEST=None Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Id5f1e3f622f65cd0f892c0dc541625bfd50d038e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-02soc/intel/jasperlake: Use SBI msg to disable HECI1Subrata Banik
Select HECI_DISABLE_USING_SMM config for Jasper Lake to disable HECI1 device using the SBI msg in SMM. BUG=none TEST=None Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3e8568750ec941fc8b8e7407bad027f7175953c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-02soc/intel/cannonlake: Use SBI msg to disable HECI1Subrata Banik
Select HECI_DISABLE_USING_SMM config for Cannon Lake to disable HECI1 device using the SBI msg in SMM. BUG=none TEST=None Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6882b619506d1bf4131f68c2c9a32ef4f7d6f6d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-02soc/intel/apollolake: Use PCR write to disable HECI1Subrata Banik
Set the SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR config for Apollo Lake to disable HECI1 device using PCR writes. BUG=none TEST=None Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8df9544296f0bea095c5415805a596cb5b36885e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-02-02soc/intel/skylake: Use PCR write to disable HECI1Subrata Banik
Set the SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR config for Skylake to disable HECI1 device using PCR writes. BUG=none TEST=None Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib6bfa7c48660a6df8d0944de675a4f30fe248d1b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-02-02soc/intel/elkhartlake: Use SBI msg to disable HECI1Subrata Banik
Select HECI_DISABLE_USING_SMM config for Elkhart Lake to disable HECI1 device using the SBI msg in SMM. BUG=none TEST=None Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4ef7ff7aa234ce411092d70bcb2c9141609be90e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-02-02soc/intel/common/cse: Rework heci_disable functionSubrata Banik
This patch provides the possible options for SoC users to choose the applicable interface to make HECI1 function disable at pre-boot. `SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_SBI` config is used for disabling heci1 using non-posted sideband write (inside SMM) after FSP-S sets the postboot_sai attribute. Applicable from CNL PCH onwards. `SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PMC_IPC` config is used for disabling heci1 using PMC IPC command `0xA9`. Applicable from TGL PCH onwards. `SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PCR` config is used for disabling heci1 using private configuration register (PCR) write. Applicable for SoC platform prior to CNL PCH. Additionally, add PID_CSME0 macro for SKL, Xeon_SP and APL to fix the compilation failure. Finally, rename heci_disable() function to heci1_disable() to make it more meaningful. BUG=none TEST=Able to build and boot brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7e0bab0004013b999ec1e054310763427d7b9348 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-02-02soc/intel/common/cse: Make cse_disable_mei_devices a public functionSubrata Banik
This patch export cse_disable_mei_devices() function instead of marking it static. Other IA common code may need to get access to this function for making `heci1` device disable. BUG=none TEST=Able to build and boot brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib2a1eb2fdc9d4724bd287b82be4238893c967046 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-02-02mb/google/brya: Remove `mb_gpio_lock_config()` override functionSubrata Banik
This patch removes `lockable_brya_gpios` lists and `mb_gpio_lock_config` override function from brya baseboard directory as the variant GPIO pad configuration table is now capable of locking GPIO PADs. BUG=b:208827718 TEST=Able to built and boot brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ifc7354f2ae3817459b5494d572c603eba48ec66a Reviewed-on: https://review.coreboot.org/c/coreboot/+/61503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-02-02mb/google/brya: Lock FPMCU pins in brask and brya baseboardsSubrata Banik
This applies a configuration lock to the FPMCU SPI and IRQ GPIOs for all brya and brask variants. BUG=b:208827718 TEST=cat /sys/kernel/debug/pinctrl/INTC1055\:00/pins suggests `FPMCU_*` (F11-F13 and F15-F16) are locked. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1d0b8a5aed6ea54bcfaa267cae5ca78595396ce5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-02-02mb/google/brya: Lock PCH WP pin in brask and brya baseboardsSubrata Banik
This applies a configuration lock to the PCH write protect GPIO for all brya and brask variants. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia125c513c09ecbb1047100e72f8540369646988e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-02-02mb/google/brya: Lock TPM IRQ pin in brask and brya baseboardsSubrata Banik
This applies a configuration lock to the TPM IRQ pins for all brya and brask variants. BUG=b:208827718 TEST=cat /sys/kernel/debug/pinctrl/INTC1055\:00/pins suggests GSC_PCH_INT_ODL is locked. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Icfc251152278c59f9a94b84fcd8c6d36c26bff62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-02-02mb/google/brya: Lock TPM pin in brask and brya baseboardsSubrata Banik
This applies a configuration lock to the TPM I2C and IRQ GPIO for all brya and brask variants. BUG=b:208827718 TEST=cat /sys/kernel/debug/pinctrl/INTC1055\:00/pins suggests I2C_TPM_SDL and I2C_TPM__SDA GPIO PINs are locked. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4f2a7014faeecd4701ea35ec77ef0e1692516b9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/61499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-01psp_verstage: report developer mode to PSPKangheui Won
Add platform_report_mode function which report current developer mode status to the PSP. L1 widevine app in the PSP will use this information to select key box. BUG=b:211058864 TEST=build and boot guybrush TEST=build picasso chrome os boards Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I04b5fcfa338b485b36f1b946203f32823385c0b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-01psp_verstage: add new svc for cezanneKangheui Won
Add svc_set_platform_bootmode svc to cezanne. PSP will use this information to select proper widevine keybox. BUG=b:211058864 TEST=build guybrush Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I6bcc9e49a2b73d486cfecd7b240bf989cad94630 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-01cpu/x86/smm: Add SMM_LEGACY_ASEGKyösti Mälkki
Followup will allow use of PARALLEL_MP with SMM_ASEG so some guards need to be adjusted. Change-Id: If032ce2be4749559db0d46ab5ae422afa7666785 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-01cpu/x86/lapic: Drop SMM_SERIALIZED_INITIALIZATIONKyösti Mälkki
It was only evaluated on LEGACY_SMP_INIT path while model_106cx has used PARALLEL_MP for a long time. Change-Id: I90ce838f1041d55a7c77ca80e563e413ef3ff88d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-01soc/samsung/exynos5420: Remove unuseful 'return' in void functionElyes HAOUAS
Change-Id: I6c093e8326733a079ab3c41dfd2c77fe1883a9d4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2022-02-01soc/nvidia/tegra124/sor.c: Remove unuseful 'return' in void functionElyes HAOUAS
Change-Id: I8539eb9028f3141dfbeb926a1e19e3ad94be3edf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2022-02-01soc/nvidia/tegra210/sor.c: Remove unuseful 'return' in void functionElyes HAOUAS
Change-Id: Ifaaf8a240436758a83216037994493255935f158 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2022-02-01soc/rockchip/rk3399/display.c: Remove unuseful 'return' in void functionElyes HAOUAS
Change-Id: I8b5537bb6d0cb934aadb0eba8ba4f51dd53026c2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2022-02-01soc/qualcomm/ipq40xx/spi.c: Remove unuseful 'return' in void functionElyes HAOUAS
Change-Id: I0ca7cbbf6c4884b58b4ec8a8e3cbc77f118a42f2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2022-02-01soc/intel/xeon_sp/acpi.c: Remove unuseful 'return' in void functionElyes HAOUAS
Change-Id: Ib964939468ebb8cd0a537d514060ee5b8b13e320 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2022-02-01sb/amd/cimx/sb800/fan.c: Remove unuseful 'return' in void functionElyes HAOUAS
Change-Id: I458ff53bb9ae3a6c1003ee857b61fb350152cc86 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2022-02-01drivers/spi/spiconsole.c: Remove unuseful 'return' in void functionElyes HAOUAS
Change-Id: Ie5c83f16146517d0aa37cd1975de725f57323094 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2022-02-01ec/quanta/ene_kb3940q/ec.c: Remove unuseful 'return' in void functionElyes HAOUAS
Change-Id: Ifb5f848912fca4e86b6eab16a74733571a4ba26d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2022-02-01drivers/net/ne2k.c: Remove unuseful 'return' in void functionElyes HAOUAS
Change-Id: I2313dc209eb9035f1026a1f37ef8146c57c60986 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2022-02-01soc/samsung/exynos5250: Add missing 'void' in function definitionElyes HAOUAS
Change-Id: I59203253ba9e66e4db3ff5dcae347b68d1203f21 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2022-02-01drivers/i2c/designware/dw_i2c: limit scope of dw_i2c_transferFelix Held
Outside of the designware I2C driver the generic platform_i2c_transfer function should be used instead, so don't make dw_i2c_transfer available outside of this file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib8b6a08b6aa2cd63adc2ef69b828661fa0ed154a Reviewed-on: https://review.coreboot.org/c/coreboot/+/61514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-01drivers/i2c/designware/dw_i2c: return enum cb_err from dw_i2c_transferFelix Held
Using enum cb_err as return type instead of int improves the readability of the code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic1812c4d8d2b4d9ad331a787bd302a4f0707c1fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/61513 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-01drivers/i2c/designware/dw_i2c: return enum cb_err from dw_i2c_initFelix Held
Using enum cb_err as return type instead of int improves the readability of the code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I55e6d93ca141b687871ceaa763bbbbe966c4b4a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-02-01drivers/i2c/designware/dw_i2c: use enum cb_err for static functionsFelix Held
Using enum cb_err as return type instead of int improves the readability of the code. This commit only changes the return value of the static functions in this file keeping the external interface identical. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I80300e0b24591fc660c3134139b9257e002cdbbb Reviewed-on: https://review.coreboot.org/c/coreboot/+/61510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-01drivers/i2c/designware/dw_i2c.h: include types.h instead of stdint.hFelix Held
size_t is defined in stddef.h and not stdint.h, so include types.h to get both. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3782d3a949b72d1530ebd8078c46bc695f76dc4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-01drivers/i2c/designware/dw_i2c: add missing types.h includeFelix Held
This will provide the definitions for size_t, uint32_t and uintptr_t. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icda8d458565bf981545d720d612cbdace04bedd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-01soc/intel/common: Add the Primary to Sideband bridge libraryJohn Zhao
New platforms have additional Primary to Sideband bridge besides the PCH P2SB. This change puts the common functions into the P2SB library. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I63f58584e8c3bfe42cdd81912e1e5140337c2d55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-01mb/google/brya: Use PAD config macro to add lock supportMeera Ravindranath
Use PAD config macro to add lock support for all the gpios used in CB:58352 CB:58353. BUG=b:211573253 TEST=Boot to OS, issue warm reboot and see no issue with any IP enumeration Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I558bab39f935ab31a89541c6498a73af70cbf9ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/60320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-01mb/siemens/{mc_apl1,...,mc_apl6}: Disable SATA ALPM supportMario Scheithauer
Aggressive Link Power Management are no longer supported on these mainboards and must therefore be disabled. This feature can have a negative impact on the real-time behavior of the systems. TEST: - Boot into system software on mc_apl1 Change-Id: I8b08381743018790a20273ea1f61e5b0a56e6015 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-02-01soc/intel/appololake: Allow to configure SATA ALPM via devicetreeMario Scheithauer
Add a devicetree option to disable SATA Aggressive Link Power Management. ALPM is a method of saving power. The corresponding FSP-S UPD parameter is enabled by default. It may be that this feature is unwanted, for example for a real-time system. Therefore, allow to disable ALPM using the devicetree. Change-Id: Ica8920a87ebebe83f5d8cb4d6c8c0a6105e183e4 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-02-01mb/google/dedede/var/galtic: Generate SPD ID for Samsung K4U6E3S4AA-MGCRFrankChu
Add supported memory parts in the mem_list_variant.txt and generate the SPD ID for the parts. The memory parts being added are: 1. Samsung K4U6E3S4AA-MGCR BUG=b:214460184 TEST=emerge-dedede coreboot Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Ief75fcb7a8f1c25feaf05b1535a9528a351b23b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-01mb/google/dedede/var/galtic: Decrease core display clock to 172.8 MHzFrankChu
Galtic has a rare stability issue. The symptom is display black screen while switching to secure mode, normally it will occurred at the last step of factory side and it'll follow by some specific SOCs. Slowing the initial core display clock frequency down to 172.8 MHz as per Intel recommend for short term solution for Gal series. The CdClock=0xff is set in dedede baseboard, and we overwrite it as 0x0 (172.8 MHz) for Galtic. BUG=b:206557434 BRANCH=dedede TEST=Build firmware and verify on fail DUTs. Check the DUTs can boot up in secure mode well. Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Ic059ab306f80a6d01f4b0a380a3b767d3245478d Reviewed-on: https://review.coreboot.org/c/coreboot/+/61103 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-01soc/intel/alderlake: Add PMC register base for ADL-NUsha P
Add PCR_PSF3_TO_SHDW_PMC_REG_BASE for Alderlake-N.This value is updated from the FSP code. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I7c788e149744bfae2c5260c996b16fc1ce2070c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61148 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-01soc/intel/alderlake: Select SOC_INTEL_COMMON_BLOCK_SCS for Alder Lake NKrishna Prasad Bhat
Alder Lake N has eMMC storage device. Select SOC_INTEL_COMMON_BLOCK_SCS Kconfig for Alder Lake N. Change-Id: I577ffdc80ef09471309c827551a347d4397a33d1 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-01soc/intel/alderlake: Add eMMC PCR Port ID for Alder Lake NKrishna Prasad Bhat
Alder Lake N has eMMC storage device. Add PCR Port ID for it. Reference: Alder Lake N platform EDS Doc# 645548. Change-Id: I6dc494d1748e66b8b4058954f127ec226863e8af Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-01soc/intel/alderlake: Add GPP_I GPIO group for Alder Lake N SOCKrishna Prasad Bhat
Add definitions for GPP_I GPIO group pins on Alder Lake N SOC and GPIO IRQ routing information. GPP_I GPIO group belongs to GPIO community 1. Hence GPIO community 1 in Alder Lake N contains GPP_S, GPP_I, GPP_H, GPP_D GPIO groups. GPIO groups 1-6 in Doc# 645550 Chapter 36 corresponds to GPIO communities 5-0 respectively. BUG=b:213535859 Change-Id: Ia71a399c03cb7d098a381bd9439d448e8a620761 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61106 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-31nb/intel/gm45/raminit.c: Fix indent for 'if' statementElyes HAOUAS
Change-Id: I316ae56321da1183caefeac3163b8909d1a554b1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-31superio/smsc/lpc47n207/early_serial.c: Fix indent for 'if' statementElyes HAOUAS
Change-Id: I0342e25747458239c1ad8c0f70f91f700ae8325d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-31sb/intel/i82801dx: Add call i8259_setup()Kyösti Mälkki
Observed with aopen/dxplplusu that without SeaBIOS (using GRUB2 payload) Linux kernel panics. < [ 0.000000] Using NULL legacy PIC < [ 0.000000] NR_IRQS: 2304, nr_irqs: 1024, preallocated irqs: 0 ... < [ 0.000000] unexpected #NM exception: ffff [#1] SMP PTI versus > [ 0.000000] NR_IRQS: 2304, nr_irqs: 1024, preallocated irqs: 16 ... > [ 0.004000] Enabling APIC mode: Flat. Using 3 I/O APICs > [ 0.008000] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=0 pin2=0 > [ 0.028000] tsc: Fast TSC calibration using PIT > [ 0.032000] tsc: Detected 3198.436 MHz processor Change-Id: I1beb93a8fd04697f259aefddfd369aa79e3359b7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-01-31mb/**/Kconfig: Properly override `DISABLE_HECI1_AT_PRE_BOOT`Angel Pons
Don't unconditionally override `DISABLE_HECI1_AT_PRE_BOOT`. Change-Id: I7d447e73f672877c76eecea1eb8b8f41f89ce686 Fixes: commit a0d9ad322fe603d4d4cbccda9c7edcfbf0b13409 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61478 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-31mb/**/Kconfig: Properly override `IGNORE_IASL_MISSING_DEPENDENCY`Angel Pons
Don't unconditionally override `IGNORE_IASL_MISSING_DEPENDENCY`. Change-Id: I02081d0f04be4af9cd765aa3b29295af40f9ca99 Fixes: commit 28fa297901ffd158631cfc9f562f38119eff628e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-01-31mb/google/brya/variant/agah: Update memory settingsBora Guvendik
Based on the agah schematic, add memory settings. BUG=b:215662929 TEST=none Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ib45241d708d025ca75ed06e2bcf3997558723a62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-31soc/intel/adl: Update devicetree based on remapping for TBT PCIeMAULIK V VAGHELA
ADL has 4 TBT root ports which are PCIe compliant. TBT uses PCIe coalescing logic where in case root port 0 is disabled, other enabled root port is remapped to port 0. coreboot handles this remapping scenarios for PCH and CPU PCIe root ports and not for TBT root ports. This patch uses the same function used for PCIe remapping to update devicetree based on coalescing and SoC needs to pass correct function number and number of slots. BUG=b:210933428 BRANCH=None TEST=Check if TBT remapping happens correctly and ACPI tables are generated correctly. Change-Id: Ied16191d6af41f8e2b31baee80cb475e7d557010 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-31intel/common/block/pcie: Add NULL/count check in pcie_rp_update_devtreeMAULIK V VAGHELA
pcie_rp_update_devicetree function takes pcie_rp_group strcuture as an argument and SoC code passes the parameter in this structure. This pointer can be NULL and common code may try to dereference this NULL pointer. Also, group might have no data and SoC may pass this by indicating group count as zero (For example, for CPU or TBT root ports). These checks will prevent function from executing redundant code and returning early from the call as it's not required. BUG=b:210933428 BRANCH=None TEST=check if function returns early for group count 0 and there is no issue while booting board in case group count = 0. Change-Id: I132319bb05fdef1590c18302fc64cc76e15bea6d Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-31mb/google/brya: Create crota variantTerry Chen
Create the crota variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:215443524 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_CROTA Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: Ic8f1a0bde286d5d014dfdf87c2a417ca6ff8b3a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-31mb/amd/majolica: Add variant to disable HDMIZheng Bao
For one specific type of APU, it doesn't have HDMI. When we detect this APU, we need to explicitly disable HDMI in DDI settings, otherwise the system would freeze. Please refer src/mainboard/google/guybrush/variants/dewatt/variant.c Change-Id: I8d7637467d2f16377d3c3064cdb0934d1658fdf7 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-31mb/google/guybrush/guybrush: Add variant to disable HDMIZheng Bao
For one specific type of APU, it doesn't have HDMI. When we detect this APU, we need to explicitly disable HDMI in DDI settings, otherwise the system would freeze. Please refer src/mainboard/google/guybrush/variants/dewatt/variant.c BUG=b:215432928 Change-Id: I93fca8cf9870533da1bcca5fa28ff22085e65beb Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-31soc/amd/sabrina: Add PRE_X86_CBMEM_CONSOLE_SIZEFelix Held
Commit 86302a806c5cc9b575424305e761753710417692 (soc/amd/{common, cezanne,picasso}: Add PRE_X86_CBMEM_CONSOLE_SIZE) added this Kconfig option before the initial commit that added soc/amd/sabrina as copy of soc/amd/cezanne landed in the tree, so port the change forward to Sabrina. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2e8df5e7b7f1ac0af772e8c565f616a68b28e29e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-31soc/intel/alderlake: Add Alder Lake P IGD device IDsKane Chen
This patch adds additional IGD device IDs as per document 638514. BUG=b:216420554 TEST=coreboot is able to probe the IGD device during PCI enumeration. Change-Id: I0cafe92581c454da5e4aeafd7ad52f0e65370b11 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61441 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-30soc/intel/elkhartlake: Drop stale eNEM TODO commentSubrata Banik
This patch drops stale TODO comment about enabling eNEM on EHL. eNEM is non-POR on the elkhartlake product. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I47fd755dec2324e05e6349e51e15abcf26967604 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-29soc/mediatek/mt8186: Add register protect control for MT6366Rex-BC Chen
Some registers of PMIC init settings are protected, so we failed to set the correct value for init_setting. We disable protection before setting PMIC init setting and enable it afterward. BUG=b:216263707 TEST=PMIC setting value is set correctly. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I94d73d9c8a137444988e65c3709d29a3a4c03c5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61390 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-28sc7280: Add Modem region to avoid modem cleanup in Secboot rebootT Michael Turney
Modem uses different memory regions based on LTE/WiFi. This adds correct carve-out to prevent region being disturbed. BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board Signed-off-by: T Michael Turney <quic_mturney@quicinc.com> Change-Id: I56bfb210606b08893ff71dd1b6679f1ec102ec95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-01-28mb/google/brya/var/redrix: Enable MKBP wakeDaisuke Nojiri
To timely update stylus charging status (b:206012072), PCHG device events have been moved to MKBP. This patch registers the MKPB host event as a wake-up signal to match the change. EC filters other EC_MKBP_EVENT_* events (chromium:3413180). BUG=b:205675485,b:206012072 Cq-Depend: chromium:3413180 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: Ie4536b2c0ccc37f92dfa940c5a5712340a32c82c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-28lib/spd_cache.c: Drop comparison to {true, false}Elyes HAOUAS
Change-Id: I0ef8c0159c99606aad537fd5e14d3c74e32651d8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-28soc/intel/xeon_sp/nb_acpi.c: Drop comparison to trueElyes HAOUAS
Change-Id: Ib9670ee22e36dd988a75b2f8dc565534927b6107 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-01-28mb/purism/librem_skl: disable HECI PCI deviceMatt DeVillier
As all librem_skl devices ship with the ME disabled via HAP bit and ME firmware "neutralized" via me_cleaner, the HECI1 PCI device should be marked off/disabled to ensure that heci_reset() is not called at the end of heci_init(), as this causes a 15s timeout delay when booting (introduced in commit cb2fd20 [soc/intel/common: Add HECI Reset flow in the CSE driver]). Change-Id: Ib6bfcfd97e32bb9cf5be33535d77eea8227a8f9f Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-28mb/google/herobrine: Add senor support QUP FW for I2C and SPIRavi Kumar Bokka
Add senor board to QUP FW load for: APPS I2C, ESIM SPI & fingerprint SPI. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board. Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: I6fdd09bb437547e6d12eb60c4b2917d2a3074618 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-01-28sc7280: enable bl31 and SDI feature supportRavi Kumar Bokka
BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: I61c695fb4fef3ae36ffc5a263236b9d40c299dc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-01-28mb/acer: Add Acer Aspire VN7-572GBenjamin Doron
Add initial support for Acer Aspire VN7-572G (Skylake-U). Also note that there are two similar boards, Aspire VN7-792G and Aspire VN7-592G; both are Skylake-H. These are not supported (yet). Do not flash images intended for Aspire VN7-572G on those boards: the GPIOs and HSIO routing will be different and may risk damage to the hardware. Working: - Payload - TianoCore (custom fork of MrChromebox's UefiPayloadPkg; edk2-202102) - OS - Fedora 35 (kernel 5.14.15) - Windows 10 20H1 (bugs present: battery paging fixed; abandoning testing) - Both DIMM slots - eDP and HDMI display (VBT partially matches vendor's configuration) - with FSP GOP - with IntelGopDriver (in payload: TianoCore) - with libgfxinit - Audio - Speakers and headphone jack - Internal microphone - HDMI audio - Devices - PCIe and SATA (unable to test M.2 SATA) - Discrete graphics, Ethernet and WiFi - USB ports (unable to test type-C, touchscreen and fingerprint reader) - Includes internal devices (Bluetooth, SD card reader and webcam) - TPM - Keyboard and touchpad - Optimus (see CB:28380, CB:40625 and CB:40628) - ACPI functionality - S3 suspend and resume - EC support - Internal flashing with flashrom - CMOS settings In progress: - EC SMM functionality Not working: - vboot (breaks boot): See CB:58249 Notes: - `tpm2_pcrallocate` to enable SHA256 PCR bank Not implemented: - WMI Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2022-01-28IASL: Ignore IASL's "Missing dependency" warningElyes HAOUAS
IASL compiler check for usage of _CRS, _DIS, _PRS, and _SRS objects: 1) If _PRS is present, must have _CRS and _SRS 2) If _SRS is present, must have _PRS (_PRS requires _CRS and _SRS) 3) If _DIS is present, must have _SRS (_SRS requires _PRS, _PRS requires _CRS and _SRS) 4) If _SRS is present, probably should have a _DIS (Remark only) IASL will issue a warning for each missing dependency. Ignore this warnings for existing ASL code and issue a message when the build is complete. Change-Id: I28b437194f08232727623009372327fec15215dd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2022-01-28soc/intel/common/gpio: Skip GPIO PAD locking in recovery modeSubrata Banik
The recovery mode is meant to provide fixes for the platform deformity hence, skip locking the GPIO PAD configuration to provide the same flexibility to the platform owner while booting in recovery mode. BUG=b:211950520 TEST=Able to build and boot the brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0f0a3cfb2be7f2a5485679f6a3d8cb4fb407fcf4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-28mb/google/zork/var/shuboz: Add SPD ID for MT40A512M16TB-062E:RKane Chen
Add supported memory parts in "mem_parts_used.txt" and generate the SPD ID 0x04 for the parts. Shuboz memory table as follow: value Vendor Part number 0000 MICRON MT40A512M16TB-062E:J 0001 HYNIX H5AN8G6NCJR-XNC 0010 MICRON MT40A1G16KD-062E:E 0011 SAMSUNG K4AAG165WA-BCWE 0100 MICRON MT40A512M16TB-062E:R BUG=b:216571906 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Ib0100456457adabed6fd6615e0873de2cf9acb98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61373 Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-28soc/intel: Abstract the common block API for TCSS registers accessJohn Zhao
The existing TCSS registers access is through the REGBAR. There will be future platforms which access the TCSS registers through the Sideband interface. This change abstracts the common block API for TCSS access. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I3e2696b117af24412d73b257f470efc40caa5022 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-28src/{drivers,soc}: Fix some code indentsElyes HAOUAS
Change-Id: I55682de4a1bc74f170e2044de35b0d8d53ef51ff Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-01-28soc/intel/common/cse: skip heci_init() if HECI1 is disabledMatt DeVillier
If the HECI1 PCI device is disabled, either via devicetree or other method (HAP, me_cleaner), then we don't want/need to program a BAR, set the PCI config, or call heci_reset(), as the latter will result in a 15s timeout delay when booting. Test: build/boot Purism Librem 13v2, verify heci_reset() timeout delay is no longer present. Change-Id: I0babe417173d10e37327538dc9e7aae980225367 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-28mb/google/brya: Remove EC_GOOGLE_CHROMEEC_ACPI_MEMMAP KconfigTim Wawrzynczak
The EC_GOOGLE_CHROMEEC_ACPI_MEMMAP is intended for Chrome microchip ECs only, which have different requirements as to the amount of memory mapped space they can claim. The brya family of boards does not use any microchip ECs, therefore remove this Kconfig. BUG=b:214460174 TEST=boot brya4es to kernel, no EC errors seen in cbmem log, EC software sync still works. Change-Id: I6e9858f29d079140ec43341de90f222b03986edb Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-28mb/google/dedede/var/drawcia: Change power sequencing of Camera and VCMVarshit B Pandya
Drawcia's MIPI camera sensor and VCM both share the same reset GPIO from the PCH. The current power sequence does not take this into account, and this leads to an unbalanced ref count of the reset GPIO, which can cause one or the other of the devices to reset unexpectedly. This patch corrects that by explicitly sequencing the reset GPIO for both devices, which the builtin refcounting of this driver will automatically handle. BUG=b:214665783 TEST=Build, boot to OS and check VCM once camera stream off Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: Ib676fd1f43dbd9cf75e4aff01baab4a4bb4e2a89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-28driver/intel/mipi_camera: Increase max power ops count to 6Varshit B Pandya
Current max count for camera power ops is 5 which is not sufficient. If we increase the ops by 1 in current variants the compiler will not throw error for intel mipi camera driver. Hence increase current max count for camera power ops to 6 from 5. BUG=b:214665783 TEST=Build and boot to OS Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I4f4c090f2275616816dfc697f27520cd1cbc1a80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61146 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-28soc/intel/alderlake: Enable CPPCv3Sridahr Siricilla
The patch defines the following helper functions: get_cpu_scaling_factor(): Returns scaling factors of big and small core. cpu_is_nominal_freq_supported(): Returns true if CPU supports Nominal Frequency, otherwise false. cpu_is_nominal_freq_supported(): Check CPU supports nominal frequency or not. The patch also enables CPPCv3 support for Intel Alder Lake which is based on hybrid core architecture. TEST=Verified Nominal Frequency and Nominal Performance are getting updated for ADL-P small and big cores correctly. Signed-off-by: Sridahr Siricilla <sridhar.siricilla@intel.com> Change-Id: I963690a4fadad322095d202bcc08c92dcd845360 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-28soc/intel/common: Implement ACPI CPPCv3 package to support hybrid coreSridhar Siricilla
The patch implements ACPI CPPCv3 package. It implements and updates the following methods: generate_cppc_entries(): Updates method to support CPPCv3 package acpi_get_cpu_nominal_freq(): Calculates CPU's nominal frequency acpi_get_cpu_nomi_perf(): Calculates nominal performance for big and small cores. acpigen_write_CPPC_hybrid_method(): It generates ACPI code to implement _CPC method. acpigen_cppc_update_nominal_freq_perf(): It updates CPPC3 package if cpu supports Nominal Frequency. It generates ACPI code which sets Nominal Frequency and updates Nominal Performance. It uses below calculation to update the Nominal Frequency and Nominal Performance: Nominal Frequency = Max non-turbo ratio * cpu_bus_frequency Nominal Performance = Max non-turn ratio * cpu scaling factor CPU scaling factor varies in the hybrid core environment. So, the generated ACPI code updates Nominal Performance based on the CPU's scaling factor. TEST=Verified CPPCv3 package is getting created in the SSDT table. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Signed-off-by: ravindr1 <ravindra@intel.com> Change-Id: Icd5ea9e70bebd1e66d3cea2bcf8a6678e5cc95ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/59359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-01-28ec/google/chromeec: Consider custom_pld when checking USB port numberWon Chung
Currently only PLD group is used to check USB port number. In the future, we want to use custom PLD fields, so custom PLD should also be considered when checking USB port number. BUG=b:216376040 TEST=emerge-brya coreboot & SSDT dump in Brya test device Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Id8076a2a952de61a6f38fbdecd76e991487bf696 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-27soc/amd/sabrina/chipset.cb: update USB portsFelix Held
The corresponding mainboard design guide was used as a reference here. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie61af7dab35b560d2eec1ea62058f3a4dad5cb0f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-25 11:44:30 +0000