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2022-10-27cpu/x86/mp_init: adjust timeout for final SIPIJonathan Zhang
Adjust timeout for final SIPI to satisfy some to-be-launched server processors. Add a spew print to display how long it takes for the APs to be ready. This is intended to facilitate only troubleshooting and trend analysis. Change-Id: Id958f18bdcb34d76df8aa443161123252524328e Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68262 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-27mb/lenovo/haswell: Enable VBOOT_VBNV_FLASHYu-Ping Wu
To deprecate VBOOT_VBNV_CMOS [1], replace VBOOT_VBNV_CMOS with VBOOT_VBNV_FLASH for Haswell. Currently BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is selected for CPU_INTEL_HASWELL (see [2]). However, there seems to be no particular reason on those platforms. Flashconsole works on Broadwell, at least, and it writes to flash as early as bootblock. Therefore, remove BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES, so that VBOOT_VBNV_FLASH can be enabled. [1] https://issuetracker.google.com/issues/235293589 [2] commit 6c2568f4f58b9a1b209c9af36d7f980fde784f08 (CB:45740) drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config BUG=b:235293589 TEST=./util/abuild/abuild -t LENOVO_THINKPAD_T440P -a (with VBOOT) Change-Id: If1430ffd6115a0bc151cbe0632cda7fc5f6c26a6 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-10-27soc/intel/alderlake: Select X86_INIT_NEED_1_SIPI Kconfig for RPLSubrata Banik
This patch helps to save 10.200ms of booting time without any issue seen during MP Init. All cores are out from reset and alive. Additionally, no performance degradation is observed while running benchmarks. Refer to Intel Technical White Paper number:751003 for more details. BUG=b:211770003 TEST=Able to boot to ChromeOS with all cores are enabled. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1886bc5e60c2f6bc1e2f9d3c8d9c11799d2b53c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-10-27Revert "soc/intel/systemagent.c: Fix memory type reporting"Arthur Heymans
This reverts commit 9c2f3cc9d9b3b3b7cfe1e62a70ea3061ca6c15ac. This broke the smihandler for no clear reason on some platforms. Change-Id: I72da99c019241b627ce8b543937364a53a5fe97b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-10-27mb/siemens/mc_apl2: Enable early POST through NC_FPGAJan Samek
Enable early POST code output for this mainboard, using the NC FPGA device on PCIe. This requires the parent PCI bridge to be initialized early. BUG=none TEST=boot on siemens/mc_apl2 and observe whether the POST codes coming from before FSP-M init are visible Change-Id: Ice5fe26e11d0513e6bb0a20f1d8f0483d7b3dc6a Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-10-27mb/google/brya/gaelin: Change DDR4 from interleave to non-interleaveRaymond Chung
The brask DDR4 is set to interleave, due to the limited number of gaelin PCB layers and the traces need to be smooth, we will use non-interleave for gaelin DDR4. BUG=b:255399229, b:249000573 BRANCH=firmware-brya-14505.B TEST=Build "emerge-brask coreboot" and pass MRC memory training Change-Id: I34413343e3f7c283f49fbbdd277d9da39c09f9f8 Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-10-27soc/intel/{adl,cmn}: Add/Remove LTR disqualification for UFSMeera Ravindranath
a) Add LTR disqualification in D3 to ensure PMC ignores LTR from UFS IP as it is infinite. b) Remove LTR disqualification in _PS0 to ensure PMC stops ignoring LTR from UFS IP during D3 exit. c) Add Kconfig (SOC_INTEL_UFS_LTR_DISQUALIFY) check to apply this LTR WA. BUG=b:252975357 TEST=build and boot nirwen and see no issues in PLT runs Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I88772b0b7dde1fca0130472a38628e72dfd6c26c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-10-27soc/intel/{adl, cmn}: Allow config to select the OCP workaroundSubrata Banik
This patch introduces a config option for SoC code to choose the applicable SoC workaround. For now, we have introduced `SOC_INTEL_UFS_OCP_TIMER_DISABLE` to apply UFS OCP timeout disable workaround. At present ADL SoC only selects so, and in future MTL and others should check with Intel prior selecting this kconfig. It's the placeholder to add more workaround in required going forward. BUG=none TEST=Able to build and boot Google/Brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia2364d2de9725256dfa2269f2feb3d892c52086a Reviewed-on: https://review.coreboot.org/c/coreboot/+/68309 Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-10-26mb/google/guybrush,skyrim,zork: rework FCH IRQ mapping table generationFelix Held
This ports the changes to the way the fch_pic_routing and fch_apic_routing arrays get populated from Mandolin to Guybrush, Skyrim and Zork. This is a preparation to move the init_tables implementation to the common AMD SoC code in a later patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie550238dfa0d4c7cebe849966d40fa0b1984a0f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-26mb/amd/bilby,birman,chausie,majolica: rework FCH IRQ mapping generationFelix Held
This ports the changes to the way the fch_pic_routing and fch_apic_routing arrays get populated from Mandolin to Bilby, Birman, Chausie and Majolica. This is a preparation to move the init_tables implementation to the common AMD SoC code in a later patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia957056b60dafbc52a9809a4563a348ad7443376 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-26mb/amd/mandolin: handle invalid intr_index values in init_tablesFelix Held
Make sure that the intr_index is valid to avoid out-of-bounds writes to the fch_pic_routing and fch_apic_routing arrays. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I45ab115f3814b212243c4f6cf706daf77b6ff3b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-26mb/amd/mandolin: introduce mb_get_fch_irq_mappingFelix Held
Introduce mb_get_fch_irq_mapping to access the FCH IRQ routing mapping information and use it in init_tables to get the mapping instead of directly accessing the array's contents. This is a preparation to move the init_tables implementation to the common AMD SoC code in a later patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9c39ea9de5ebbf70d2c5a87bfdfe270796548c5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-26mb/amd,google: unify fch_irq_routing struct instance nameFelix Held
Use the same fch_irq_map name in all mainboards using the Picasso, Cezanne, Mendocino and Morgana instead of using a mainboard-specific name. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I035cffb9c6c8afd6bd115831e8eed4a395e2a7fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/68846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-26mb/google/guybrush,skyrim: add missing string.h includeFelix Held
string.h defines the memset function. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I286557d6ad83990bc101eaa930bde04345859c0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/68845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-26mb/amd/bilby,mandolin: add missing string.h includeFelix Held
string.h defines the memset function. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I242a0382e7020681b6c3a25f75a2a91cbccbe815 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-26soc/amd/mendocino: Enable GPP clk req disabling for disabled devicesRobert Zieba
Enable GPP clk req disabling for disabled PCIe devices. If a clk req line is enabled for a PCIe device that is not actually present and enabled then the L1SS could get confused and cause issues with suspending the SoC. BUG=b:250009974 TEST=Ran on skyrim proto device, verified that clk reqs are set appropriately Change-Id: I6c840f2fa3f9358f58c0386134d23511ff880248 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68139 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-26soc/amd/cezanne: Update GPP clk req code to use ARRAY_SIZERobert Zieba
Currently the GPP clk req configuration code assumes that the size of the config array is `GPP_CLK_OUTPUT_COUNT`. This commit changes that code to use the `ARRAY_SIZE` macro instead. BRANCH=guybrush BUG=b:250009974 TEST=Ran on nipperkin device, verified that clk req settings are correct. Change-Id: I3ff555843c6f5aa38acd8300e0dc2da4e33fb4b7 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-26soc/amd/cezanne: Factor out common GPP clk req codeRobert Zieba
Factor out the `gpp_dxio_update_clk_req_config` function as it will be useful for other AMD SoCs. BUG=b:250009974 TEST=Ran on nipperkin device, verified clk req settings match enabled devices Change-Id: I9a4c72d8e980993c76a1b128f17b65b0db972a03 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-26soc/amd/common/include: introduce and use FCH_IRQ_ROUTING_ENTRIESFelix Held
Instead of using magic constants for the fch_pic_routing and fch_apic_routing array sizes, define FCH_IRQ_ROUTING_ENTRIES in the common code headers and use this definition. This also allows to drop the static assert for the array sizes. In the Stoneyridge mainboard code the equivalent arrays are named mainboard_picr_data and mainboard_intr_data; also use FCH_IRQ_ROUTING_ENTRIES as fixed array size there. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2d7ee46bd013ce413189398a144e46ceac0c2a10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68818 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26mb/amd,google: move fch_irq_routing struct definition to soc/amdFelix Held
Define the fch_irq_routing struct once in a common header file instead of in every mainboard's code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I11d9000b6ed7529e4afd7f6e8a7332c390da6dab Reviewed-on: https://review.coreboot.org/c/coreboot/+/68817 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26mb/google/skyrim: Enable CBFS VerificationKarthikeyan Ramasubramanian
Enable RO verification by GSC and CBFS verification. BUG=b:227809919 TEST=Build and boot to OS in Skyrim with CBFS verification enabled using x86 verstage and PSP verstage. Change-Id: Idd22a521a913705af0d2aca17acd1aa069a77f29 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-26cbfs_verification: Remove dependency on VBOOT_STARTS_BEFORE_BOOTBLOCKKarthikeyan Ramasubramanian
CBFS verification on boards where VBOOT starts before bootblock eg. PSP verstage has been accommodated by keeping metadata hash outside the bootblock. Hence the dependency can be removed. BUG=b:227809919 TEST=Build and boot to OS in skyrim with CBFS verification enabled using both x86 verstage and PSP verstage. Change-Id: I0a3254728a51a8ee7d7782afcea15ea06d93da7d Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66947 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-26soc/amd/common/psp_verstage: Pass SRAM buffer to Crypto EngineKarthikeyan Ramasubramanian
Crypto engine prefers the buffer from SRAM. CBFS verification may pass the mapped address of a CBFS file from SPI flash. This causes PSP crypto engine to return invalid address. Hence if the buffer is from SRAM, pass it directly to crypto engine. Else copy into a temporary buffer before passing it to crypto engine. BUG=b:b:227809919 TEST=Build and boot to OS in skyrim with CBFS verification enabled using both x86 verstage and PSP verstage. Change-Id: Ie9bc9e786f302e7938969c8093d5405b5a85b711 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-26src/drivers: Clean up includesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ia40678019b2a54deb246dbfbf33ec37a8c3839e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-26src/device: Clean up includesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Idd78271f2158bdc29ce9ac8d81f46ad8cbe84c5e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-26cpu/x86: Clean up includesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I01c6651079333686cb0eb68e89e56d7907868124 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-26cpu/intel: Clean up includesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ie760711916c49d275ca49d94b9597fd24b5e7628 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-26src/commonlib: Clean up includesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ieba5a5291209e50dc8b3816efb25bb5b2515fa6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/68201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-26arch/x86: Clean up includesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Id2db229dec2ed44333faaa8c53f3a2f9d66d52e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-26soc/amd/mendocino: Add GSVCD rangeKarthikeyan Ramasubramanian
Add region/range of SPI ROM to be verified by Google Security Chip (GSC). BUG=b:227809919 TEST=Build and boot to OS in Skyrim with CBFS verification enabled. Change-Id: If8a766d9a7ef26f94e3ab002a9384ba9d444dd1f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-26soc/amd/mendocino: Update build rules for PSP BIOS imageKarthikeyan Ramasubramanian
Do not compress PSP BIOS image when CBFS verification is enabled. Otherwise when a file is added to CBFS, cbfstool is not able to find the metadata hash anchor magic in the compressed PSP BIOS image. BUG=b:227809919 TEST=Build and boot to OS in Skyrim with CBFS verification enabled for both x86 and PSP verstage. Change-Id: Iaed888b81d14ede77132ff48abcfbeb138c01ce4 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-26soc/amd/mendocino: Reserve more space for metadataKarthikeyan Ramasubramanian
With CBFS verification enabled, CBFS file header + file name + metadata consumes more than 64 bytes. Hence reserve additional space aligned to the next 64 bytes. BUG=b:227809919 TEST=Build and boot to OS in Skyrim with CBFS verification enabled. Change-Id: I2b7346e2150835443425179048415f3b27d89d89 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66944 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26soc/amd: Add amdfw.rom in coreboot.preKarthikeyan Ramasubramanian
This change ensures that amdfw.rom binary containing metadata hash anchor is added before any file is added to CBFS. This will allow to verify all the CBFS files that are not excluded from verification. BUG=b:227809919 TEST=Build and boot to OS in Skyrim with CBFS verification enabled using x86 and PSP verstages. Change-Id: Id4d1a2d8b145cbbbf2da27aa73b296c9c8a65209 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-26util/cbfstool: Check for metadata hash in verstageKarthikeyan Ramasubramanian
Metadata Hash is usually present inside the first segment of BIOS. On board where vboot starts in bootblock, it is present in bootblock. On boards where vboot starts before bootblock, it is present in file containing verstage. Update cbfstool to check for metadata hash in file containing verstage besides bootblock. Add a new CBFS file type for the concerned file and exclude it from CBFS verification. BUG=b:227809919 TEST=Build and boot to OS in Skyrim with CBFS verification enabled using x86 and PSP verstages. Change-Id: Ib4dfba6a9cdbda0ef367b812f671c90e5f90caf8 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66942 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26soc/amd: Add an optional unsigned section in PSP verstageKarthikeyan Ramasubramanian
To enable RO CBFS verification in AMD platforms with PSP verstage, metadata hash for RO CBFS is kept as part of verstage. This means any updates to RO CBFS, before WP is enabled, requires updating the metadata hash in the verstage. Hence keep the metadata hash outside the signed range of PSP verstage. This means the metadata hash gets loaded as part of loading PSP verstage while still being excluded from the verification of PSP verstage. This change keeps the metadata hash outside the PSP footer data. This will help to keep it outside the signed range of PSP verstage & aligned to 64 bytes. BUG=b:227809919 TEST=Build and boot to OS in Skyrim with CBFS verification enabled with both x86 and PSP verstage. Change-Id: I308223be8fbca1c0bec8c2e1c86ed65d9f91b966 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68135 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26lib/metadata_hash: Include metadata_hash in verstageKarthikeyan Ramasubramanian
On boards where vboot starts before bootblock, build metadata_hash in verstage. This will allow to enable CBFS verification for such platforms. BUG=b:227809919 TEST=Build and boot to OS in Skyrim with CBFS verification enabled using x86 verstage and PSP verstage. Change-Id: I4269069b66ed66c7b1a47fdef2fd0a8054b2e6a1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68134 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26util/amdfwtool: Add build rules for amdfwreadKarthikeyan Ramasubramanian
Add build rules to build amdfwread tool. Also mark this as a dependency either while building tools or amdfw.rom. BUG=None TEST=Build and boot to OS in Skyrim with CBFS verification enabled. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I3fee4e4c77f62bb2840270b3eaaa58b894780d75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66939 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26coreboot_tables: Drop uart PCI addrArthur Heymans
Only edk2 used this to fill in a different struct but even there the entries go unused, so removing this struct element from coreboot has no side effects. Change-Id: Iadd2678c4e01d30471eac43017392d256adda341 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-26mb/google/brya/var/kano: select SOC_INTEL_RAPTORLAKEDavid Wu
Select SOC_INTEL_RAPTORLAKE to force coreboot to use the RPL FSP headers for FSP as kano is using a converged firmware image. BUG=b:253337338 BRANCH=firmware-brya-14505.B TEST=Cherry-pick Cq-Depends, then "FW_NAME=kano emerge-brya coreboot-private-files-baseboard-brya coreboot chromeos-bootimage", disable hardware write protect and software write protect, flash and boot kano in end-of-manufacturing mode to kernel. Cq-Depend: chrome-internal:5046060, chromium:3967356 Change-Id: I75da3af530e0eafdc684f19ea0f6674f6dc10f01 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-10-26mb/prodrive/atlas: Disable S3Maximilian Brune
The Atlas board has currently the problem that suspending the System causes the System to freeze. Therefore disable S3, until the cause is figured out and fixed. Change-Id: I5b28787df9b01683fcd4a1de8267840a80bb4fe6 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68591 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26mb/google/rex: Move `DRIVERS_INTEL_USB4_RETIMER` configSubrata Banik
This patch moves DRIVERS_INTEL_USB4_RETIMER config from Meteor Lake SoC to Rex mainboard to maintain the symmetry with previous generation ChromeOS devices (Brya and Volteer). BUG=none TEST=Able to build and boot to Google/Rex with USB4 functionality remaining intact. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I38360f6f1f2fcb4b0315de93c68f00d77e63003c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-10-26cpu/x86/Kconfig: Enable LAPIC remap mitigation on likely affect NBArthur Heymans
Pre-sandy bridge hardware is likely affected by the sinkhole vulnerability. Intel sandy bridge and newer has hardware mitigations against this attack according to https://github.com/xoreaxeaxeax/sinkhole. Change-Id: I52cb20e0edac62475597b31696f38d0ffc6080de Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-25soc/amd: Add framework for Glinda SoCMartin Roth
This adds the initial framework for the Glinda SoC, based on what's been done for Morgana already. I believe that there's more that can be made common, but that work will continue as both platforms are developed. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I43d0fdb711c441dc410a14f6bb04b808abefe920 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-25soc/intel/alderlake: Add Raptor Lake device IDsLawrence Chang
Add system agent ID for RPL QDF# Q271 TEST=Tested by ODM and "MCH: device id a71b (rev 01) is Unknown" msg is gone Signed-off-by: Lawrence Chang <lawrence.chang@intel.corp-partner.google.com> Change-Id: I6fd51d9915aa59d012c73abc2477531643655e54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kane Chen <kane.chen@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-10-25mb/google/skyrim/var/frostflow: Update devicetree settingFrank Wu
Update devicetree based on the schematic_20221014. BUG=b:253506651, b:251367588 BRANCH=None TEST=FW_NAME=frostflow emerge-skyrim coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Ia03962b0e01394ddcd4971cbe0172ef5bd913e15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68482 Reviewed-by: Chao Gui <chaogui@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
2022-10-25mb/google/kahlee/liara/devicetree: move Raydium touchscreen to baseboardFelix Held
Move the Raydium touchscreen to the baseboard devicetree. Since only the liara variant uses a level IRQ as I2C devices are supposed to, all other board variants still override this to use an edge IRQ which were added as a workaround to make the touchscreen work on the other devices. Right now it's unclear to me if that edge IRQ workaround was only needed temporarily and can now be removed, so I'll keep it as it was for now. If this turns out to be no longer needed on the other variants, the overrides can be dropped in the future. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic621c1a5856e9e280a25b0668010a1ee5bbb61e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68770 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-10-25console: Add an SoC-specific post-code callMartin Roth
Add a post-code call that SoCs can hook to output or save in any way that is specific to that SoC. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I0369e4362840d7506d301105d8e1e2fd865919f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-10-25soc/intel/common: Clean up includesElyes Haouas
Change-Id: I0081fcf3c842d8772a7045f8dc5754a2e6c039b8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-25soc/intel/tigerlake: Clean up includesElyes Haouas
Change-Id: I9c75e900d05d16de830c750f074df84bb17f64dc Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2022-10-25ec/google/wilco/superio: Fix PS2K under WindowsMatt DeVillier
PS2K device needs to be under PCI0, not LPCB, for Windows to recognize it. Same change was made to ChromeEC previously. Test: Boot Win11 on Drallion, verify built-in keyboard functional. Change-Id: I12019592dfa1d869ba57c1ff6c25ac6bdeb7a300 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68463 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-10-25soc/intel/xeon_sp: Add functions to store/restore uart state in smmTim Chu
When CONFIG_DEBUG_SMI is enabled SMM handler performs console hardware initialization that may interfere with OS. Here we store the state before console initialization and restore state before SMM exit. Tested=On not public yet system, after exiting smm, uart console can still work well. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: Ifa5042c24f0e3217a75971d9e6067b1d1f56a484 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-10-25src/drivers/uart: Add definition of FIFO enabled in IIRTim Chu
Interrupt Identification Register (IIR) is a I/O read-access register. Add definition of FIFO enabled for this register so that we can check whether FIFO is enabled or not. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I12e8566822693004418cf83cae466dc3e2d612c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68566 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-25soc/intel/elkhartlake: Fix incorrect divider for MDIO clockWerner Zeh
After some measurements it turned out that Elkhart Lake uses a higher CSR clock internally from which the MDIO clock is derived. In order to stay compliant with the specification, the MDIO clock needs to be lower than 2.5 MHz. Therefore, the divider needs to be 102 and not 62. This patch changes the define to match the new divider value and uses this new define at the appropriate place. Test=Measure the MDIO clock rate on mc_ehl2 which results in 2 MHz. Change-Id: Idf498c3547530dfa395f54488ef244e787062e34 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2022-10-25mb/siemens/mc_ehl1: Disable L1 prefetcherWerner Zeh
The highly real time driven application executed on mc_ehl1 has shown that the L1 prefetcher on Elkhart Lake is too aggressive which in the end leads to an increased number of cache misses. Disabling the L1 prefetcher boosts up the performance (in some cases by more than 10 %) in this specific use case. Change-Id: Id09a7f8f812707cd05bd5e3b530e5c3ad8067b16 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68668 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2022-10-25soc/intel/eklhartlake: Provide an option to disable the L1 prefetcherWerner Zeh
Depending on the real workload that is executed on the system the L1 prefetcher might be too aggressive and will populate the L1 cache ahead with data that is not really needed. In the end, this will result in a higher cache miss rate thus slowing down the real application. This patch provides a devicetree option to disable the L1 prefetcher if needed. This can be requested on mainboard level if needed. Change-Id: I3fc8fb79c42c298a20928ae4912ee23916463038 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68667 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-25soc/mediatek/mt8188: replace SPDX identifiers to GPL-2.0-only OR MITRex-BC Chen
For MT8188, the SPDX identifiers are all GPL-2.0-only OR MIT, so replace "GPL-2.0-only" with "GPL-2.0-only OR MIT". Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I5ef6c488b7ef937f6e298670ea75d306b9fe7491 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68759 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-25mb/google/geralt: Configure firmware display for eDP panelBo-Chen Chen
Add eDP panel power-on sequences and initialize the display in the ramstage. eDP panel in MT8188 EVB: "IVO R140NWF5 RH". Panel spec name: R140NWF5 RH Product Specification Firmware display eDP panel logs: configure_display: Starting display initialization SINK DPCD version: 0x11 SINK SUPPORT SSC! Extracted contents: header: 00 ff ff ff ff ff ff 00 serial number: 26 cf 7d 05 00 00 00 00 00 1e version: 01 04 basic params: 95 1f 11 78 0a chroma info: 76 90 94 55 54 90 27 21 50 54 established: 00 00 00 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a extensions: 00 checksum: fb Manufacturer: IVO Model 57d Serial Number 0 Made week 0 of 2020 EDID version: 1.4 BUG=b:244208960 TEST=see firmware display using eDP panel in MT8188 EVB. Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I67e0699c976c6f85e69d40d77154420c983b715e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68490 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-10-25soc/mediatek/mt8188: Update mtcmos settings for display and audioBo-Chen Chen
- For display, only vdosys0_pwr_con and edp_tx_pwr_con settings are required. - For audio, it requires powering on adsp_ao_pwr_con, adsp_infra_pwr_con and audio_pwr_con. - Add new power domain data `ext_buck_iso_bits` for buck isolation control. BUG=b:244208960 TEST=access display registers successfully. Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I7f00bda0cc5c7f8dea55a564a0ff10ae601115b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-10-25soc/mediatek/mt8188: Add eDP support for firmware displayBo-Chen Chen
MT8188 supports eDP as internal display interface. BUG=b:244208960 TEST=emerge-geralt coreboot. Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I6441a36557b097e041bc081b907eb60b56c9fbe6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2022-10-25soc/mediatek/mt8188: Add ddp driver to support eDP outputNathan Lu
Add DDP (display data path) driver that supports overlay, read/write DMA, etc. The output goes to display interface DP_INTF0 directly. Add ddp gclast and output_clamp settings to MT8188 to support multi-layer display. BUG=b:244208960 TEST=emerge-geralt coreboot. Signed-off-by: Nathan Lu <nathan.lu@mediatek.com> Change-Id: Icc0a878c609818fedd298c141bb39469fd2f6388 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68487 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-25soc/mediatek/mt8188: Rename SPM registerBo-Chen Chen
The SPM register at offset 0x0 is often named as poweron_config_set in previous MediaTek SoCs. To use common driver, we rename it from poweron_config_en to poweron_config_set. BUG=none TEST=emerge-geralt coreboot. Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I31dbf09d668844d3ee74790c657a2ab076e8cdf0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68486 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-25soc/mediatek: Add support for input 1P mode of dp_intfRex-BC Chen
MT8195 supports 2P mode and MT8188 supports 1P mode. A new struct member `input_mode` is added to `struct mtk_dpintf` for differentiation. We also move SoC-specific data `dpintf_data` to soc folder. BUG=b:244208960 TEST=emerge-cherry coreboot. Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I6d138b0ff75e005518bc8fcce06df20924b2a6ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/68485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2022-10-25soc/mediatek: Move DP drivers to commonBo-Chen Chen
DP drivers can be shared for both MT8195 and MT8188, so move them to common folder. BUG=b:244208960 TEST=emerge-cherry coreboot. Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ic80c03aa6b13e6c9c39fd63b5c1c1cbdbe93a7c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-10-24mb/clevo/tgl-u: Avoid indirect includesElyes Haouas
Change-Id: I51ab987420e592ac2f841c2d7761c0adcc43124e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-10-24mb/google/kahlee: always detect ELAN touchpadFelix Held
Always detecting the presence of the ELAN touchpad doesn't affect the functionality, but allows dropping the override for all variants that have multiple touchpad options. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id5d14eedd5d95dd0990ae56775daed9284c03717 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-10-24mb/google/kahlee: use override devicetrees for variantsFelix Held
This helps with deduplicating the identical parts of the variants' devicetrees. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie050c4624327b904e8cb0959b40421339e43f825 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-10-24arch/x86: x86_64 implies SSE2 supportPatrick Rudolph
Enable SSE2 (and SSE) when compiling for x86_64. Compilers often assume SSE2 is present and enabled when targeting x86_64. This fixes: - lzma decompression code is compiled with the -Ofast flag - 'everything' when compiling with clang. This mostly affects qemu targets, which did not have this flag selected yet. TESTED on qemu. Change-Id: I3cdc584c97016e15513df663a54a7bdb549a73e4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44869 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-24mb/Kconfig: Add a prompt string for MAINBOARD_PART_NUMBERSam McNally
For some nissa variants, there are build configurations that need to use different blobs, but otherwise are identical. Currently, they use the same choice of board config and configure blob paths appropriately. This avoids duplication within the Kconfig file, but the resulting firmware images can be difficult to distinguish, since they report the same FRID. Add a prompt string for MAINBOARD_PART_NUMBER so it can be overridden and round-tripped through make oldconfig, allowing customisation of the reported FRID and other MAINBOARD_PART_NUMBER-derived values with minimal overhead. BUG=b:253966060 BRANCH=None TEST=CL:3960290 MAINBOARD_PART_NUMBER configs apply successfully Signed-off-by: Sam McNally <sammc@chromium.org> Change-Id: I3497d7fa1c04c8fa2592025c771d9dbc65632e6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-10-23soc/amd/mendocino: Add STB Spill-to-DRAM enumMartin Roth
This is the enum value to initialize the Smart Trace Buffer's Spill-to-DRAM feature. More information on how this is used is available in the STB Linux kernel driver. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Iab2e5fb121902959ddd0e7c8cca930a327b69291 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-10-22soc/amd/morgana/mca: Update for morganaFred Reitberger
Update the MCA bank names for morgana per PPR #57396, rev 1.52 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: If0082bd5362bdead3f9dc693d1e338e8cda224f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-22mb/google/brask/var/kuldax: Revise PsysPL2 to 150W for Pentium CPUDavid Wu
Pentium CPU will use 150W adaptor, this change revises PsysPL2 to 150W based on fw_config. BUG=b:253542746 TEST=Check CPU PsysPL2=150W in AP log with Pentium CPU. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I63b2a9d79454b20b60ba1317a8eebb3c10eff9d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-10-22mb/google/brya: Enable SaGv for brask variantsDerek Huang
SaGv is enabled for all brya variants, so it should be harmless to enable it for brask variants to save some power. BUG=254374912 TEST=Build and boot to Chrome OS Signed-off-by: Derek Huang <derekhuang@google.com> Change-Id: Ib5d1e39b3f901606e2f1449e4ed40d53696562ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/68646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-10-22mb/google/skyrim/var/baseboard: Update gpio setting for touchscreen IRQFrank Wu
The touchscreen IRQ has been configured as LEVEL_LOW in skyrim projects. Therefore, update the gpio.c to be consistent with the configuration. BUG=b:253506651, b:251367588 BRANCH=None TEST=FW_NAME=frostflow emerge-skyrim coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Iccfe5b01f10899c43151762e4730a05990afa602 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chao Gui <chaogui@google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-10-22payloads/edk2: Disable the CPU Timer Lib unless supportedSean Rhodes
For recent X86 CPUs, the 0x15 CPUID instruction will return Time Stamp Counter Frequence. For CPUs that do not support this instruction, EDK2 must include a different library which is the reason why this must be configured at build time. If this is enabled, and the CPU doesn't support 0x15, it will fail to boot. If is not enabled, and the CPU does support 0x15, it will still boot but without support for the leaf. Consequently, disabled it by default. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4f0f43ce50c4f6f7eb03063fff34d015468f6daa Reviewed-on: https://review.coreboot.org/c/coreboot/+/65950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-22soc/intel/systemagent: Rewrite using new resource APIArthur Heymans
Working with resources in KB is tedious and the base_k / size_k variable naming was simply wrong in one case. Change-Id: Ic5df054e714d06c9003752ed49dc704554e7b904 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68406 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-22soc/intel/systemagent.c: Fix memory type reportingArthur Heymans
TOLUD stands for top of lower usable dram. Memory between cbmem_top and TOLUD, even if stolen for another device/purpose can still be marked WB cacheable. This will result in a cleaner MTRR setup. Change-Id: Ic3d6f589c60e44a3dce9122d206397cac968647f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68405 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-22mb/siemens/mc_ehl: Add FIVR config to devicetree for all variantsWerner Zeh
Add a config for FIVR in devicetree for both, mc_ehl1 and mc_ehl2 variants in order to provide the real delay value for the VCC supply rail. This delay is needed to enable proper switching between different VCC levels based on current system state. Change-Id: Ibccb8ea1b42ccd2ff0a37cbd9651528a2a55ebd6 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-22arch/x86/include/arch: fix assembly clobber for 64bitMatei Dibu
the "x86 PIC code ebx" workaround done previously by commit 689e31d18b0f ("Make cpuid functions usable when compiled with PIC") does not work for x86_64 (the upper dword of rbx is set to 0) the GCC bug that needed the workaround was fixed in version 5 (see GCC bug 54232) Change-Id: Iff1dd72c7423a3b385a000457bcd065cf7ed6b95 Signed-off-by: Matei Dibu <matdibu@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66345 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-22mb/siemens/mc_apl*: Enable early PCI bridge before FSP-MAngel Pons
Apollo Lake seems to start with PCIe root ports unusable/uninitialized before FspMemoryInit() is called and FSP-M properly initializes these root ports. However, we need the root ports accessible before FspMemoryInit() in certain cases, such as emitting POST codes through a PCIe device. For the initialization to happen properly, certain register writes specified in Apollo Lake IAFW BIOS spec, vol. 2 (#559811), chapter 3.3.1 have to be done. BUG=none TEST=Boot on siemens/mc_apl2 with NC_FPGA_POST_CODE enabled and check that the POST codes are emitted before FspMemoryInit(). Change-Id: If782bfdd5f499dd47c085a0a16b4b15832bc040e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68223 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-22soc/intel/alderlake_n: Enable FIVR VCCST ICCMax ControlV Sowmya
Enable the VCCST ICCMax Control for the ADL-N display flicker issue. Please refer the Doc with ID 742988 for more details. BUG=b:248249033 TEST=Verified that the display flicker issue is fixed. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I10709ee8653563b397e8408e8e24ef8e656b02e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68252 Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-10-22nb/intel/i945/raminit: Use 'bool' for do_resetElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I692b86bba28853186185846f63dad1dcbfce1eea Reviewed-on: https://review.coreboot.org/c/coreboot/+/68217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-22nb/intel/i945/raminit: Use 'bool' for clkcfg_bit7Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ia87fbbeb9ecb57ee2f4879404cbae5403de9bfc7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-22smbios.h: Add High Bandwidth Memory Generation 3Elyes Haouas
Add HBM3 according to SMBIOS 3.6.0: https://web.archive.org/web/20221012222420/https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.6.0.pdf Change-Id: Id8473e8c4b5006b53b5ff9de7825d15595f2a616 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65356 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-22nb/intel/i945/raminit: Use 'size_t' for banksize[]Elyes Haouas
Change-Id: I4fb845bb4145d47aea39d7e5493d854d00e289aa Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-22vc/amd/fsp: Get rid of last "sabrina" referenceMartin Roth
We still had a lingering reference to the old sabrina codename in the vendorcode directory. Searching through the code now, the only places the sabrina codename is seen is in the release notes, as is proper. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I41762880b45a85ce7cd4210b8ce623076d874c06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-22soc/amd/*/i2c.h: Make definition more accurateFred Reitberger
Make GPIO_I2C_MASK macro more accurate by using the GPIO_I2Cx_SCL definitions instead of BIT(x). Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I13fc376552068a64768fe1cf9f1c09cca1768aed Reviewed-on: https://review.coreboot.org/c/coreboot/+/68682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-22mb/google/nissa: Disable SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRYReka Norman
On nissa, the pre-x86 time is not part of the 1s firmware boot time target. Including the pre-x86 timestamps causes confusion since the boot time appears to be greater than 1s, so disable the Kconfig on nissa. We're not doing any analysis or optimisation of the pre-x86 time on nissa anyway, this work will start from MTL onwards. Also, the Kconfig is already disabled on the brya firmware branch, so this will result in the same behaviour as brya. Before: Total Time: 1,205,840 After: Total Time: 995,300 BUG=b:239769532 TEST=Boot nivviks, check "1st timestamp" is the first timestamp. Change-Id: I885071c9e0ff9c8fac9444b382567d38a19c3c15 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68553 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-22mb/lenovo/*/mainboard.c: Clean up includesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I406f21c0c05e6af357e45e718422be94c6fd5408 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-10-22mb/google/kahlee: Fix audio ACPI inclusionMatt DeVillier
Not all kahlee variants use the RT5682 audio codec, so split the baseboard audio ACPI into two parts and only include the asl for the codec(s) actually needed for a given variant. TEST=build/boot aleena, liara variants and verify no ACPI present for RT5682 codec (which is not present on the boards). Change-Id: Icb7df4f8e51495ad3cb40113cd00810fd27dcd00 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-22vc/intel/fsp: Update ADL N FSP headers from v3301.00 to v3343.04Shaik Shahina
Update generated FSP headers for Alder Lake N from v3301.00 to v3343.04. Changes include: - FspsUpd.h: 1. Add PchFivrVccstIccMaxControl UPD BUG=b:254374913 BRANCH=None TEST=Build using "emerge-nissa intel-adlnfsp" and boot Nissa. Change-Id: I20b13d3dff2951e6ec3aa754c8954989a3b4e176 Signed-off-by: Shaik Shahina <shahina.shaik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68424 Reviewed-by: Reka Norman <rekanorman@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21mb/google/skyrim: Enable genesyslogic gl9755 for frostflowFrank Wu
Enable DRIVERS_GENESYSLOGIC_GL9755 support for frostflow BUG=b:253506651, b:251367588 BRANCH=None TEST=FW_NAME=frostflow emerge-skyrim coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I1db598c68687ed17fd9baa3567ab8fdd3e4fb6a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-10-21soc/amd/*/smi.h: Use BIT() for clarityFred Reitberger
Use the BIT() macro for single-bit constants. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I490f0093d55813260fcdb7303a94accfa90e75e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-21soc/amd/*/uart: cleanup includesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I59ab9c2eaa65d974d418123e87e9afe65b1168cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/68633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-21mb/gigabyte/ga-h61m-series: Add GA-H61M-DS2Angel Pons
Built from a mixture of autoport output, other variants, schematics and expert guesswork. I don't have this board, but the code has been tested by someone else and boots successfully (first try) with TianoCore. It's reasonable to assume most things work, as this board is very similar to the already-supported variants. Change-Id: I3d8df483e5573f77782b7d18b1410b391bfe387d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61541 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21arch/x86/include: Split msr access into separate fileMartin Roth
To allow testing of code that uses msr calls, separate the actual calls into a separate header file, This allows the tests to emulate the msr access without replacing the rest of the msr.h definitions. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I102709fec346f18040baf9f2ce6e6d7eb094682d Reviewed-on: https://review.coreboot.org/c/coreboot/+/67917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-21mb/lenovo/t{410,60}/dock.h: Fix header guardsElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I7b279cf2c69f62b47ef497edd372034f148fff03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-21soc/mediatek: Unify PLL function namesRex-BC Chen
For consistency with the PLL function naming: - Rename edp_mux_set_sel() to mt_pll_edp_mux_set_sel(). - Rename mux_set_sel() to pll_mux_set_sel(). BUG=none TEST=build pass. BRANCH=corsola Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ifc7b14bf0db5a5461037e2fbf41756d1542ca945 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68622 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21mb/google/corsola: Initialize MT6315 for MT8186TSen Chu
Initialize MT6315 for powering on big cores on MT8186T. BUG=b:249436110 TEST=build pass. BRANCH=corsola Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com> Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ib1d71d4f1689ba1e7ea5f798503ef11eff423fff Reviewed-on: https://review.coreboot.org/c/coreboot/+/68621 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21soc/mediatek/mt8186: Add support for PMIC MT6315Sen Chu
On MT8186T, the big cores are powered on by MT6315 via PMIF. This patch adds the following changes. - Add MT6315 settings. - Configure PMIC PMIF for MT6315. BUG=b:249436110 TEST=build pass. BRANCH=corsola Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com> Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Id01931e564b0b5002b8d6b9d13d4f32cdf0ae708 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68620 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21soc/mediatek: Move SPMI interface configuration to SoC folderSen Chu
The SPMI interface configuration is SoC-dependent. - MT8192 and MT8195 are the same. - MT8186 does not need to implement this. - MT8188 is different from MT8195, and we will submit another patch to fix this. BUG=b:249436110 TEST=build pass. BRANCH=corsola Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com> Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I4cf508a0690995a7fe7b7316269d07cb7a799191 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68619 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-22 01:31:14 +0000