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2012-11-14Sandybridge: Set PEG clock gatingMarc Jones
If the PEI System Agent doesn't run PCIe initialization, the PEG clock gating will not be setup. Add the PEG clock gating when pei_data->pcie_init is 0. Change-Id: I7e31bcebd11feb4807aa29b528adf09fb013c3ce Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1827 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14Add PCIe init and NMode flag to PEI data structureStefan Reinauer
The IvyBridge reference code does some slow and extensive PCIe init that we do not need on Link. Hence, add a flag to disable/enable running that init code from coreboot. NMode was used during bringup. We'll switch the setting back to auto, to let MRC decide the right thing. Change-Id: Ia989bb9ea079aadfeb41dc3029b7c2c623e84760 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1826 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14Add ddr3lv_support flag to pei_data structureDuncan Laurie
This will enable DDR3 1.35V support for memory training in the reference code. It requires the board to be setup for 1.35V with whatever board-specific GPIOs are available. Change-Id: I14e4686c20f9610f90678e6e3bece8ba80d8621a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1825 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14pei_data.h: Fix commentMarc Jones
I added a comment to the pei_data.h to remind users about how the OC pins are mapped. Change-Id: I4d74eb69fc78816a69e61260c2c9b2b3e58cafec Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1824 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14Provide MRC with a console printing callback functionVadim Bendebury
Let memory initialization code use the coreboot romstage console. This simplifies the code and makes sure that all output is available in /sys/firmware/log. The pei_data structure is modified to allow passing the console output function pointer. Romstage console_tx_byte() is used for this purpose. Change-Id: I722cfcb9ff0cf527c12cb6cac09d77ef17b588e0 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1823 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13Add spinlock to serialize Intel microcode updatesStefan Reinauer
Updating microcode on several threads in a core at once can be harmful. Hence add a spinlock to make sure that does not happen. Change-Id: I0c9526b6194202ae7ab5c66361fe04ce137372cc Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1778 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13cros: Inform U-Boot via fake gpio when VGA Option ROM is loadedBill Richardson
This prepares the way for vboot to inform coreboot when it needs the VGA Option ROM loaded. Coreboot can't always know when it's needed (with keyboard-based dev-mode, coreboot can't tell if we're in dev-mode or not). By the time we get to U-Boot, it's too late, so we need two extra bits - one for vboot to tell coreboot to load the Option ROM and another for coreboot to let vboot know it's been done. This change sets up the communication, but doesn't act on it just yet. Even with this CL we always load the VGA Option ROM, so there's nothing to test. There should be no user-visible change. Change-Id: Ic4e9673a3707b6605064f4879bb3e74d4412322f Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: http://review.coreboot.org/1822 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13Export optionrom status on Stumpy/LumpyVadim Bendebury
ChromeOS' top of the tree u-boot expects coreboot to export information about option ROM status (started/not started). Stumpy and Lumpy were left behind and are not exporting this information. This CL fixes the problem. Change-Id: Id90035bd76ab177e4fc269efc2b74f15f641c77d Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1713 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13Make EmeraldLake2 work againDuncan Laurie
Fix GPIO exporting for new Vboot for oprom-matters GPIO and to make the power button static. Change-Id: Ic042c428a1d43512228c686121fa057d876606e1 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1761 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13Clean up stack checking codeStefan Reinauer
Several small improvements of the stack checking code: - move the CPU0 stack check right before jumping to the payload and out of hardwaremain (that file is too crowded anyways) - fix prototype in lib.h - print size of used stack - use checkstack function both on CPU0 and CPU1-x - print amount of stack used per core Signed-off-by: Stefan Reinauer <reinauer@google.com> Test: Boot coreboot on Link, see the following output: ... CPU1: stack: 00156000 - 00157000, lowest used address 00156c68, stack used: 920 bytes CPU2: stack: 00155000 - 00156000, lowest used address 00155c68, stack used: 920 bytes CPU3: stack: 00154000 - 00155000, lowest used address 00154c68, stack used: 920 bytes ... Jumping to boot code at 1110008 CPU0: stack: 00157000 - 00158000, lowest used address 00157af8, stack used: 1288 bytes Change-Id: I7b83eeee0186559a0a62daa12e3f7782990fd2df Reviewed-on: http://review.coreboot.org/1787 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13Add method for delaying adding of timestampsStefan Reinauer
In hardwaremain() we can't add timestamps before we actually reinitialized the cbmem area. Hence we kept the timestamps in an array and added them later. This is ugly and intrusive and helped hiding a bug that prevented any timestamps to be logged in hardwaremain() when coming out of an S3 resume. The problem is solved by moving the logic to keep a few timestamps around into the timestamp code. This also gets rid of a lot of ugly ifdefs in hardwaremain.c Change-Id: I945fc4c77e990f620c18cbd054ccd87e746706ef Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1785 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13Add Kconfig option to lock/unlock ME firmware during buildStefan Reinauer
For reasons of security and testing we want to be able to enable/disable ME section locking through a config option. Change-Id: I341c577cdae86be62c0e3d32bbd6b3333c004a5f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1798 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13clean up lapic_cpu_init.cStefan Reinauer
- drop changelog and add license header instead - 80+ character fixes - make stacks array static because it's not used externally - rename copy_secondary_start_to_1m_below() Change-Id: I8b461bea21ee0ddd85ea3a3a923d1e15167f54f0 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1821 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13Pass the CPU index as a parameter to startup.Ronald G. Minnich
This addition is in support of future multicore support in coreboot. It also will allow us to remove some asssembly code. The CPU "index" -- i.e., its order in the sequence in which cores are brought up, NOT its APIC id -- is passed into the secondary start. We modify the function to specify regparm(0). We also take this opportunity to do some cleanup: indexes become unsigned ints, not unsigned longs, for example. Build and boot on a multicore system, with pcserial enabled. Capture the output. Observe that the messages Initializing CPU #0 Initializing CPU #1 Initializing CPU #2 Initializing CPU #3 appear exactly as they do prior to this change. Change-Id: I5854d8d957c414f75fdd63fb017d2249330f955d Signed-off-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/1820 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-11-13Fix CONFIG_MAX_CPU set to 1 CPU build problemStefan Reinauer
There are some function dependancies that didn't work when MAX_CPU was set to 1 and the build would fail. Change-Id: I033a42056f7b48a40316e03772ed89ad9cb013fe Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1819 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-11-13Support better tracking of AP stack usage.Ronald G. Minnich
This change allows us to figure out how much of the AP stacks we are using, as well as to catch any case of an AP overrunning its stack. Also, the stack is poisoned, which is a good way to catch programming errors -- code should never count on auto variables being zerod. The stack bases are recorded in a new array, stacks. At the end, when all APs are initialized, the stacks are walked and the lowest level of the stack that is reached is printed. Build and boot and look for output like this: CPU1: stack allocated from 00148000 to 00148ff4:\ lowest stack address was 00148c4c CPU2: stack allocated from 00147000 to 00147ff4:\ lowest stack address was 00147c4c CPU3: stack allocated from 00146000 to 00146ff4:\ lowest stack address was 00146c4c Note that we used only about 1K of stack, even though in this case we allocated 4K (and in the main branch, we allocate 32K!) Change-Id: I99b7b9086848496feb3ecd207f64203fa69fadf5 Signed-off-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/1818 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-11-13SandyBridge/IvyBridge: Add IFD and ME firmware automaticallyStefan Reinauer
Right now coreboot's build process produces images that are not booting on actual hardware because they are smaller than the actual flash device and also don't have an IFD nor an ME firmware in them. In order to produce bootable images, you needed a wrapper script / extra step until now. With this change, the resulting coreboot.rom is actually bootable. Change-Id: I82714069fb004d4badc41698747a704bd9fed4da Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1771 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12vboot: Add option to skip TPM resume on S3 resumeStefan Reinauer
Change-Id: Ie4a98cc8af0dbcf09c7ace79668949ace5938c12 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1752 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12mmio pci config: Remove register constraintsAaron Durbin
The currently encoded register constraints fails compilation for SMM code or any code that compiles with -fPIC. The reason is that the ebx register is used for GOT base register. I don't believe the comment eluding to register constraints for AMD processors still applies. Therefore remove mmio_conf.h, and use the mmio methods in io.h. Change-Id: I391e5c2088ebc760b3a6ed6c37b65bbecab40a5c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/1801 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12cbfstool: Rework to use getopt style parametersStefan Reinauer
- Adding more and more optional and non-optional parameters bloated cbfstool and made the code hard to read with a lot of parsing in the actual cbfs handling functions. This change switches over to use getopt style options for everything but command and cbfs file name. - This allows us to simplify the coreboot Makefiles a bit - Also, add guards to include files - Fix some 80+ character lines - Add more detailed error reporting - Free memory we're allocating Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Ia9137942deb8d26bbb30068e6de72466afe9b0a7 Reviewed-on: http://review.coreboot.org/1800 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12Initial IGD OpRegion implementationStefan Reinauer
Change-Id: I9e57c5792409830895a1147799acab95d910a336 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1757 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12romcc_io: add pci_or_configX functions.Aaron Durbin
Some of the modules use their own rolled pci_or_configX functions. Therefore, make them first class so everyone can use them without copying them. Change-Id: I9a4d3364c832548dbfe18139c27cce2d60c3316d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/1797 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12x86/Makefile.inc: Test if the strings are equal by single equal signZheng Bao
Double equal sign like "test a == b" works. It really does, except NetBSD. But I haven't found any clue in the manual for the command test about "==". Change-Id: I37254cfeb688fd1092f2e549d24f8eb270f02fd8 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1817 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-11-12If cmos is invalid, always set the rtc date and timeStefan Reinauer
If cmos is invalid for any reason, always set the date and time before marking RTC valid. Change-Id: Ib9d154802f75221d58bf28ba9c813f2529904596 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1790 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12Remove duplicate defines from mc146818rtc.cMarc Jones
Remove the duplicate #defines and use what is set in mc146818rtc.h. Change-Id: Ic471e03c68b591d19c0646fdbea78374af11c8b8 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1789 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12Avoid using hardcoded values in MRC cache codeVadim Bendebury
The MRC cache code, as implemented, in some cases uses configuration settings for MRC cache region, and in some cases - the values read from FMAP. These do not necessarily match, the code should use FMAP across the board. This change also refactors mrccache.c to limit number of iterations through the cache area and number of fmap area searches. Change-Id: Idb9cb70ead4baa3601aa244afc326d5be0d06446 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1788 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12ivybridge: Catch unknown CPU revisionsStefan Reinauer
Adding an entry for 0x306a0 will make sure that all CPUs with CPUIDs 0x306aX will execute the driver (analog to Sandybridge behavior) Change-Id: I0353f3a48ecfd41274fdf6ee302c7d34482f1b5b Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1783 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12Store timestamps before resuming from suspendStefan Reinauer
in the resume case, timestamps were collected in RAM stage but not stored in CBMEM. This leads to only a single time stamp covering 200ms being available for all of ram stage. Change-Id: Ibf0bb92caf5e032c12fe4e1b9b84b3624d499511 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1781 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12Reduce default stack size to 4KStefan Reinauer
coreboot uses about 2K of stack on the BSP, and about 1K of stack on the APs. No reason to use an overdimensonal stack of 32k per core/thread. Change-Id: I734c240b992d40e1e35db3df5437c36da0a755cf Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1780 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12Add dependency for CONFIG_AP_IN_SIPI_WAITStefan Reinauer
Change-Id: Ia20c138dae1fc1382abe74303e1117472c513d1d Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1779 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12SPI: Add early romstage SPI driver using hardware sequencingDuncan Laurie
This is a basic romstage driver that can be used for the MRC cache code on systems where we do not have the MRC cache stored in a flash region that is memory mapped. It uses the hardware sequencing interface to avoid having to know anything about the flash chip itself. BUG=chrome-os-partner:15031 BRANCH=stout TEST=manual: this was tested with debug code added to romstage that attempted to read the MRC cache at offset 0x3e0000. SPI READ offset=003e0000 size=64 buffer=ff7fba00 SPI ADDR 0x003e0000 SPI HSFC 0x3f00 SPI READ: 0=4443524d SPI READ: 1=00000bb0 SPI READ: 2=00008e24 SPI READ: 3=00000000 SPI READ: 4=001c8bbb SPI READ: 5=0c206466 SPI READ: 6=0a043220 SPI READ: 7=000058b4 SPI READ: 8=00000000 SPI READ: 9=00000000 SPI READ: 10=00100000 SPI READ: 11=00100005 SPI READ: 12=20202025 SPI READ: 13=000e0001 SPI READ: 14=00000000 SPI READ: 15=00000000 Change-Id: I5f78f53111f912ff5dda52bbf90fdc1824b82681 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1777 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12ELOG: Support for non-memory mapped flashDuncan Laurie
If the event log is stored in flash that is not memory mapped then it must use the SPI controller to read from the flash device instead of relying on memory accesses. In addition a new CBMEM ID is added to keep an resident copy of the ELOG around if needed. The use of CBMEM for this is guarded by a new CONFIG_ELOG_CBMEM config option. This CBMEM buffer is created and filled late in the process when the SMBIOS table is being created because CBMEM is not functional when ELOG is first initialized. The downside to using CBMEM is that events added via the SMI handler at runtime are not reflected in the CBMEM copy because I don't want to let the SMM handler write to memory outside the TSEG region. In reality the only time we add runtime events is at kernel shutdown so the impact is limited. Test: 1) Test with CONFIG_ELOG_CBMEM enabled to ensure the event log is operational and SMBIOS points to address in CBMEM. The test should involve at least on reboot to ensure that the kernel is able to write events as well. > mosys -l smbios info log | grep ^address address | 0xacedd000 > mosys eventlog list 0 | 2012-10-10 14:02:46 | Log area cleared | 4096 1 | 2012-10-10 14:02:46 | System boot | 478 2 | 2012-10-10 14:02:46 | System Reset 3 | 2012-10-10 14:03:33 | Kernel Event | Clean Shutdown 4 | 2012-10-10 14:03:34 | System boot | 479 5 | 2012-10-10 14:03:34 | System Reset 2) Test with CONFIG_ELOG_CBMEM disabled to ensure the event log is operational and SMBIOS points to memory mapped flash. The test should involve at least on reboot to ensure that the kernel is able to write events as well. > mosys -l smbios info log | grep ^address address | 0xffbf0000 > mosys eventlog list 0 | 2012-10-10 14:33:17 | Log area cleared | 4096 1 | 2012-10-10 14:33:18 | System boot | 480 2 | 2012-10-10 14:33:18 | System Reset 3 | 2012-10-10 14:33:35 | Kernel Event | Clean Shutdown 4 | 2012-10-10 14:33:36 | System boot | 481 5 | 2012-10-10 14:33:36 | System Reset Change-Id: I87755d5291ce209c1e647792227c433dc966615d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1776 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12SPI: Fix and enable Fast Read supportDuncan Laurie
- Fix handling of 5-byte Fast Read command in the ICH SPI driver. This fix is ported from the U-boot driver. - Allow CONFIG_SPI_FLASH_NO_FAST_READ to be overridden by defining a name for the bool in Kconfig and removing the forced select in southbridge config - Fix use of CONFIG_SPI_FLASH_NO_FAST_READ in SPI drivers to use #if instead of #ifdef - Relocate flash functions in SMM so they are usable. This really only needs to happen for read function pointer since it uses a global function rather than a static one from the chip, but it is good to ensure the rest are set up correctly as well. Change-Id: Ic1bb0764cb111f96dd8a389d83b39fe8f5e72fbd Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1775 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12Fix gcc-4.7 building problem.Han Shen
Applied function attribute to function definition to avoid 'conflicting type' warning. Function declaration is in src/include/cpu.h void secondary_cpu_init(unsigned int cpu_index)__attribute__((regparm(0))); But function definition in lapic_cpu_init.c is missing the "__attribute__" part. Change-Id: Idb7cd00fda5a2d486893f9866920929c685d266e Signed-off-by: Han Shen <shenhan@google.com> Reviewed-on: http://review.coreboot.org/1784 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-11-12Add bd82x6x mainboards ASPM overrides.Marc Jones
The Intel PCH can override the ASPM settings via the MPC2 register. Add a chip override for F0-F7. Mainboards may implement this as needed. This also fixes the final PM setup being done too early. It was being done prior to the PCIe ASPM setup, which happens in the bridge scan. Change-Id: Idf2d2374899873fc6b1a2b00abdb683ea9f5bd6b Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1796 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-12SPI: Configure Software Sequence SPI Freq to match descriptorDuncan Laurie
Right now the SPI bus is getting set to 20mhz for transactions initiated with the software sequence interface. In order to be able to do reasonable fastread/write/erase we can bump this up to a higher value at boot before it gets locked at 20mhz. To do this read out the speed set in the SPI descriptor for hardware sequencing and apply it to software sequencing. Change-Id: I79aa2fe7f30f734785d61955ed81329fc654f4a4 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/1773 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-12SPI: Add Fast Read to the OPMENU for locked down SPIDuncan Laurie
The chips we are using do not use BE52 (block erase 0x52) so we can use that opcode menu location to enable fast read. Change-Id: I18f3e0e5e462b052358654faa0c82103b23a9f61 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/1772 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-12oprom: Ensure that mode information is valid before putting it in the tables.Gabe Black
At least when CONFIG_CHROMEOS is turned on, it's possible for CONFIG_FRAMEBUFFER_KEEP_VESA_MODE to be set but for there not to be any valid information to put into the framebuffer coreboot table. That means that what's put in there is junk, probably all zeroes from the uninitialized global variable the mode information is stored in (mode_info). When a payload uses libpayload and turns on the coreboot framebuffer console, that console will attempt to scroll at some point and decrease the cursor's y coordinate until it is less than the number of rows claimed by the console. The number of rows is computed by taking the vertical resolution of the framebuffer and dividing it by the height of the font. Because the mode information was all zeroes, the coreboot table info is all zeroes, and that means that the number of rows the console claims is zero. You can't get the unsigned y coordinate of the cursor to be less than zero, so libpayload gets stuck in an infinite loop. The solution this change implements is to add a new function, vbe_mode_info_valid, which simply returns whether or not mode_info has anything in it. If not, the framebuffer coreboot table is not created, and libpayload doesn't get stuck. Change-Id: I08f3ec628e4453f0cfe9e15c4d8dfd40327f91c9 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/1758 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-12Define post codes for OS boot and resumeDuncan Laurie
And move the pre-hardwaremain post code to 0x79 so it comes before hardwaremain at 0x80. Emit these codes from ACPI OS resume vector as well as the finalize step in bd82x6x southbridge. Change-Id: I7f258998a2f6549016e99b67bc21f7c59d2bcf9e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1702 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-12Pass correct sleep type to mainboard sleep handlerStefan Reinauer
The sleep type is 5 for S3 and 7 for S5. Change-Id: I7ffdb3d27b6994ac4a12a343caf4d7abb82fe6ca Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1760 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-12ACPI: Zero pstate/cstate control values in FADTDuncan Laurie
If these values are non-zero then the kernel will issue an SMI for each core (cstate) and package (pstate). Since we don't do anything with these SMI callbacks we can avoid taking the extra SMIs at boot time by zeroing these fields. Change-Id: I3bc5fe0a9f45141d46884cb77ecdfaeaa45d2439 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1769 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-12Initialize the VMX MSRMarc Jones
The VMX MSR may come up with random values and needs to be initialized to zero. This was done incorrectly in finalize_smm. It must be done on a per core basis in the general CPU init. This touches all Sandybridge and Ivybridge configs. Change-Id: I015352d0f8e2ebe55ac0a5e9c5bbff83bd2ff86b Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1794 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-12Revert "Remove code that enables/disables VMX in coreboot on chromebooks."Marc Jones
The MSR for VMX can start with a random value and needs to be cleared by coreboot. I am reverting this change, as it handles almost everything and doing a follow-on change to fix the improper clearing of the MSR. Change-Id: Ibad7a27b03f199241c52c1ebdd2b6d4e81a18a4e Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1793 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-12sandybridge: Correct reporting of cores and threadsStefan Reinauer
The reporting of cores and threads in the system was a bit ambiguous. This patch makes it clearer. Change-Id: Ia05838a53f696fbaf78a1762fc6f4bf348d4ff0e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1786 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-09Make coreboot use the offset parameter in cbfstool createStefan Reinauer
On Sandybridge and Ivybridge systems the firmware image has to store a lot more than just coreboot, including: - a firmware descriptor - Intel Management Engine firmware - MRC cache information This option allows to limit the size of the CBFS portion in the firmware image. Change-Id: Ib87fd16fff2a6811cf898d611c966b90c939c50f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1770 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-09Prevent inclusion of tsc.h when not neededVadim Bendebury
src/include/timestamp.h is an interface describing timestamp storage in coreboot. Exporting this interface is complicated by inclusion of tsc.h which is needed only for the API and is not used in structure definitions. Including this dependency only when needed fixes the problem. Change-Id: Ie6b1460b1dab0f5b5781cb5a9fa89a1a52aa9f17 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1753 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-09PCH: Add register descriptions used by IGD OpRegionStefan Reinauer
These bits are used by the IGD OpRegion code Change-Id: I89a11fc5021d51e0c1675ba56f6a3bc3b79bb8aa Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1751 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-09Add IGD Opregion variables to NVSStefan Reinauer
In order to support Intel's IGD Opregion standard, we need an additional set of flags shared between firmware, ACPI, SMM, and the graphics driver. Change-Id: I1a9b8dff5e5ee8d501b6672bc3bcca39ea65572e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1750 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-09Make register/value lists constStefan Reinauer
These can be stored in the code segment, since it's never changed. Change-Id: I8b3827838e08e6cc30678aad36c39249fbca0c38 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1749 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-09Get rid of hard coded strings in ACPI tablesStefan Reinauer
(cosmetical) Change-Id: I3e01d8fbf2d71abcfcbe47efedd2184566c91df7 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1748 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-09Add Gigadevice SPI rom supportMartin Roth
Add support for GigaDevice SPI ROMS. The GD25Q64B device has been tested, the other rom devices added to the file have not. Change-Id: If35676ca6b90329f15667ebb32efa0d1a159ae91 Signed-off-by: Martin Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/1747 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-09ELOG: Add EC events to elog headerDuncan Laurie
These events were initially for Chrome EC but they can be applied to any EC. Change-Id: I0eba9dbe8bde506e7f9ce18c7793399d40e6ab3b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1746 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-09SPI: re-init SMM SPI driver after lockdownDuncan Laurie
If the driver is initialized before the lockdown then it will fail to work after the lockdown bit is set. Change-Id: Idc05d33d8d726bf29cb3c9b1b4604522bd64170a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1745 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-09Change flashmap base to reflect new FMAP in U-bootDuncan Laurie
The RO_FMAP base moved from 0x5f0000 to 0x610000. Also update Kconfig default and add a descripton so the default can be changed by boards. Change-Id: I0caad0ce6e6f19750dbbf042a5a489b558f62b96 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1705 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-09mc146818rtc: Remove the hyphen to build on NetBSD and DarwinZheng Bao
http://netbsd.gw.com/cgi-bin/man-cgi?date++NetBSD-current The NetBSD manual tells us the date in NetBSD doesn't take any flags to enable or disable padding in the format. By default, date pads numeric fields with zeroes. This will convert the number to octal one. So add "0x" to convert it to BCD directly. Change-Id: Icd44312acf01b8232f1da1fbaa70630d09007b40 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1804 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-11-09mc146818rtc: Update the Day of Week in CMOS in the right way.Zheng Bao
The range of weekday in CMOS is 01-07, while the Sunday is 1, and Saturday is 7. The comand date in coreutils defines %u day of week (1..7); 1 is Monday %w day of week (0..6); 0 is Sunday There are 1 day offset for each week day. So we use "%w" and plus 1 before we update the weekday in CMOS. Change-Id: I3fab4e95f04924ff0ba10a7012b57da1d3f0d1a5 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1802 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-11-08mainboard/roda/rk886ex: Disable CHECK_SLFRCS_ON_RESUMENico Huber
This makes resume from S3 work again. The check is new and fails on other boards, too. Change-Id: I0ada569e4ba649b9ac82768b0888e16104c621e8 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1809 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-08Log unexpected post code from the previous bootDuncan Laurie
Read out the post code from the previous boot and log it if the code is not one of the expected values. Test: 1) interrupt the boot of the system, this is easiest with warm reset button when servo is attached 2) check the event log with mosys 65 | 2012-09-09 12:32:11 | Last post code in previous boot | 0x9d Change-Id: Id418f4c0cf005a3e97b8c63de67cb9a09bc57384 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1744 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-08Add support for storing POST codes in CMOSDuncan Laurie
This will use 3 bytes of CMOS to keep track of the POST code for the current boot while also leaving a record of the previous boot. The active bank is switched early in the bootblock. Test: 1) clear cmos 2) reboot 3) use "mosys nvram dump" to verify that the first byte contains 0x80 and the second byte contains 0xF8 4) powerd_suspend and then resume 5) use "mosys nvram dump" to verify that the first byte contains 0x81 and the second byte contains 0xFD Change-Id: I1ee6bb2dac053018f3042ab5a0b26c435dbfd151 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1743 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-08x86 memcpy: Copy 4 bytes at onceStefan Reinauer
This is a slight improvement over the rep movsb loop Change-Id: Id71d9bfe5330b154a5c62fac85ce3955ae89b057 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1742 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-08RTC: Don't clear pending interrupt in resume pathDuncan Laurie
The linux kernel relies on the RTC reporting pending interrupts if the RTC alarm was used to wake the system. If we clear these flags here then the rtc-cmos driver in the kernel will think that no interrupts are pending and will not re-start the timerqueue to handle the alarm timerqueue node. This flag doesn't exist in SMM but the rtc code is compiled there. Since rtc_init() is not called by SMM it is guarded with an ifdef. I performed several thousand suspend/resume cycles without seeing an issue where hwclock was unable to read from /dev/rtc. There still is a potential kernel issue where the timerqueue can stall but this makes that much less likely to happen on resume. Change-Id: I5a343da4ce5c4c8ec4783b4e503869ccfa5077f0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1741 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-08smi: make tseg_relocate check pointer offsetDuncan Laurie
In case tseg_relocate() is called again on a pointer we should not relocate it again. Change-Id: Ida1f9c20dc94b448c773b14d8864afe585369119 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1740 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-08elog: add extended management engine eventDuncan Laurie
We are seeing ME disabled and ME error events on some devices and this extended info can help with debug. Also fix a potential issue where if the log does manage to get completely full it will never try to shrink it because the only call to shrink the log happens after a successful event write. Add a check at elog init time to shrink the log size. Change-Id: Ib81dc231f6a004b341900374e6c07962cc292031 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1739 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-08spi: fix erase in SMM while SPIBAR is lockedDuncan Laurie
The handling of write enable was not entirely correct, the opcode needs to be skipped when the controller is locked down. Addresses were not getting set properly for erase commands which seemed to mostly work when the previous command had set an address. Tested by adding events to the event log at runtime on a freslhy flashed device (with locked down SPI controller) until the log log shrink happens to ensure it does not hang: hexdump -C elog.event.kernel_clean 00000000 01 00 00 00 ad de 00 00 00 00 for x in $(seq 1 232); do cat elog.event.kernel_clean > /sys/firmware/gsmi/append_to_eventlog done mosys eventlog list | tail -6 154 | 2012-09-01 13:54:43 | Kernel Event | Clean Shutdown 155 | 2012-09-01 13:54:43 | Kernel Event | Clean Shutdown 156 | 2012-09-01 13:54:43 | Kernel Event | Clean Shutdown 157 | 2012-09-01 13:54:43 | Kernel Event | Clean Shutdown 158 | 2012-09-01 13:54:43 | Log area cleared | 1030 159 | 2012-09-01 13:54:43 | Kernel Event | Clean Shutdown Change-Id: I3a50dae54422a9ff37daefce3632f8bcbe4eb89f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1717 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-08Make option rom init more verboseStefan Reinauer
When bringing up VGA by running the option rom it's sometimes useful to get more information about the mode that gets set, or the reason why the mode could not be set or a picture could not be displayed. Also prefix the output from VBE mode setting with VBE: Copying VGA ROM Image from fff0fd78 to 0xc0000, 0x10000 bytes Real mode stub @00000600: 867 bytes Calling Option ROM... int15_handler: INT15 function 5fac! ... Option ROM returned. VBE: Getting information about VESA mode 4161 VBE: resolution: 1280x1024@16 VBE: framebuffer: d0000000 VBE: Setting VESA mode 4161 VGA Option ROM has been loaded Change-Id: I2be11f095dc62ed3c99e0d4272ad9d6521608a44 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1714 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-08ELOG: Find flash base in FMAP if possibleDuncan Laurie
Now that we have FMAP support in coreboot use it to find the offset in flash for ELOG to use. If coreboot has elog configured with a smaller size then use that over the FMAP size. This is because I set aside a 16KB region in the FMAP but we only use 4KB of it to keep the impact to boot/resume speed to a minimum. FMAP: Found "FMAP" version 1.0 at ffe10000. FMAP: base = 0 size = 800000 #areas = 32 FMAP: area RW_ELOG found FMAP: offset: 3f0000 FMAP: size: 16384 bytes FMAP: No valid base address, using 0xff800000 ELOG: base=0x003f0000 base_ptr=0xffbf0000 ELOG: MEM @0x00190ad8 FLASH @0xffbf0000 ELOG: areas are 4096 bytes, full threshold 3072, shrink size 1024 Change-Id: I3d826812c0f259d61f41b42797c58dd179f9f1c8 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1706 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-07ELOG: Don't disable SPI controller lockdownDuncan Laurie
Now that WREN prefix is handled properly ELOG is able to write when the SPI controller is locked down. To test, ensure that runtime SPI write via ELOG is successful by checking the event log for a kernel shutdown reason code: 5 | 2012-08-27 11:09:48 | Kernel Event | Clean Shutdown 6 | 2012-08-27 11:09:50 | System boot | 26 7 | 2012-08-27 11:09:50 | System Reset Change-Id: If6d0dced7cb0f5ca7038b3d758f31b856826d30b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1712 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-11-07SPI: opmenu special case for WREN as atomic prefixDuncan Laurie
The code that attempts to use the opmenu needs to have a special case for write enable now that it is handled as an atomic prefix and not as a standalone opcode. To test, ensure that runtime SPI write via ELOG is successful by checking the event log for a kernel shutdown reason code: 5 | 2012-08-27 11:09:48 | Kernel Event | Clean Shutdown 6 | 2012-08-27 11:09:50 | System boot | 26 7 | 2012-08-27 11:09:50 | System Reset Change-Id: I527638ef3e2a5ab100192c5be6e6b3b40916295a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1710 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-11-07RTC: Write build date in BCD when clearing RTC CMOSDuncan Laurie
Check the RTC on boot after RTC battery failure and ensure that the reported build date matches what is reported: > grep ^rtc /proc/driver/rtc rtc_time : 01:00:21 rtc_date : 2012-08-16 Change-Id: If23f436796754c68ae6244ef7633ff4fa0a93603 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1709 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-11-07SMI: Change order of SMI_EN and PM1_EN initDuncan Laurie
This appears to fix an infrequent resume hang on Ivybridge. Tested on 2 devices with 15k suspend/resume cycles each Change-Id: I53618bc7966824413f1720a2be3cbd2550e29473 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1704 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-11-07EC: Prepare to read and log last post code from previous bootDuncan Laurie
(elog portion, support in EC code pending) - Use a new EC command to read the last post code from the previous boot - If the post code is not well-known final boot or resume code then log it Change-Id: Id6249e9a182243eb87c777edd56f48de72125e77 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1703 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-11-07SandyBridge/IvyBridge: Use flash map to find MRC cacheStefan Reinauer
Until now, the MRC cache position and size was hard coded in Kconfig. However, on ChromeOS devices, it should be determined by reading the FMAP. This patch provides a minimalistic FMAP parser (libflashmap was too complex and OS centered) to allow reading the in-ROM flash map and look for sections. This will also be needed on some partner devices where coreboot will have to find the VPD in order to set up the device's mac address correctly. The MRC cache implementation demonstrates how to use the FMAP parser. Change-Id: I34964b72587443a6ca4f27407d778af8728565f8 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1701 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-11-07Add missing newline in error messageStefan Reinauer
This is purely cosmetic. All error messages in the Sandybridge raminit code printed a newline at the end. Change-Id: I880d291928291d487039850a2a3d53a1101124ba Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1699 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-11-07rtc: add explicit dependency on build.hVincent Palatin
build.h is generated at build time, with highly parallel builds, we might try to compile the rtc driver too early. Change-Id: I9a2681484d58b67ed3061669fbdf52ac5ad14dab Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: http://review.coreboot.org/1698 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-11-07rtc: erase CMOS memory after power failureVincent Palatin
When a power failure happens on the RTC rail, the CMOS memory (including the RTC registers) is filled with garbage. So, we erase the full first bank (112 bytes) and we reset the RTC date to the build date. To test, disconnect the CMOS battery to produce an RTC power failure, then boot the machine and observe the RTC date is the build date using "cat /sys/class/rtc/rtc0/date" Change-Id: I684bb3ad5079f96825555d4ed84dc0f7914e9884 Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: http://review.coreboot.org/1697 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-11-07AMD G34 CPU: change lapic_id in northbridge.c to accommodate G34 CPUSiyuan Wang
Each G34 socket has two node. Previous lapic algorithm is written for the CPU which has one node per socket. I test the code on h8qgi with 4 family 15 CPUs(8 cores per CPU). The topology is: socket 0 --> Node 0, Node 1 socket 2 --> Node 2, Node 3 socket 1 --> Node 4, Node 5 socket 3 --> Node 6, Node 7 Each node has 4 cores. I change the code according to this topology. Change-Id: I45f242e0dfc61bd9b18afc952d7a0ad6a0fc3855 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/1659 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-07CMOS: Move MRC seed offset into upper bankDuncan Laurie
This will allow the lower bank to be cleared without impacting the ability to suspend/resume. Change-Id: Iaec3c9e7e40c334053c814eaddd1f614df245a73 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1696 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-11-07rtc: force mc146818 register D to a correct valueVincent Palatin
On Panther Point PCH (and maybe cougar point), when some of the register D reserved bits are set, the RTC starts misbehaving (e.g. incrementing the year byte every second). There are probably undocumented features implemented behind those bits. Let's reset register D to a known state to ensure we get the expected RTC behavior. Change-Id: I7e2c2a2c6130a974bccb3d760b41eaa579a58b67 Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: http://review.coreboot.org/1695 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-11-07Fix CONFIG_ use in i8254.cStefan Reinauer
We always define CONFIG_ variables, even if they're not set. Hence, remove the check whether CONFIG_UDELAY_TIMER2 is defined Change-Id: Iefdf2389941f2cc63ae4f13ac6b213da4c96b201 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1694 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-11-07Add POST code for "All devices initialized"Stefan Reinauer
Right now we only had a post code for "All devices enabled" which was emitted at the wrong time (after the device initialize stage rather than the device enable stage) Change-Id: Iee82bff020de844c7095703f8d6521953003032c Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1693 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-11-07Move global variable check to MakefileStefan Reinauer
Our linker script for romstage checks for global variables and makes the build fail if there are any (on non-AMD systems). This is great, but having the build fail without any indication which variables are global is not very useful. Moving the check to the Makefile allows us to let the linking stage succeed and reveil which variable names end up in the data and bss sections of the binary. To test, add "int foo;" as the first line in src/mainboard/samsung/lumpy/romstage.c and build coreboot for Lumpy. See the build break the following way: LINK cbfs/fallback/romstage_null.debug Forbidden global variables in romstage: 00006a84 B foo Change-Id: I3c8780888f46a6577ffd36bcea317997b4f84f6f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1692 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-07Leave power control registers unlockedSameer Nanda
To allow easy experimentation with thermals, leave power control registers unlocked. Change-Id: Ia53065f3f220c2faed58e7d53e60c3f169ae58ec Signed-off-by: Sameer Nanda <snanda@chromium.org> Reviewed-on: http://review.coreboot.org/1688 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-07Fix whitespace issue with help message in Kconfig fileDave Frodin
Every line of text after a 'help' label in a Kconfig file must have the same whitespace preceding it, otherwise it's no longer considered help text. Change-Id: I97093bee72b295b315d78d4c26d7186bf1017fda Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/1687 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-11-07AMD rd890 late.c: Don't enable PCIe ports after PCIe init.Siyuan Wang
PCIE devices are detected and initialized by the AMD PCIe init functions, which is in cimx rd890. The parameters are read from devicetree.cb before PCIe init. Now, all bridges and devices are trained on the device 0.0 enable. After PCIe init, the PCIe ports with devices are on and the PCIe ports without devices are off. so resources may be allocated correctly during the rest of the PCI scan. But if the devicetree was being used to enable/disable devices after initialization, the problems would arise. Take a look at the serial log: do_pci_scan_bridge for PCI: 00:02.0 PCI: pci_scan_bus for bus 01 PCI: pci_scan_bus returning with max=001 do_pci_scan_bridge returns max 1 do_pci_scan_bridge for PCI: 00:03.0 PCI: pci_scan_bus for bus 02 PCI: pci_scan_bus returning with max=002 do_pci_scan_bridge returns max 2 do_pci_scan_bridge for PCI: 00:04.0 PCI: pci_scan_bus for bus 03 PCI: pci_scan_bus returning with max=003 do_pci_scan_bridge returns max 3 PCI bridge 02.0, 03.0 and 04.0 are not inserted devices, but these bridges are still scanned. This is not correct. Change-Id: I87dac5f062c6926081970ed0c5f26a7e3f447395 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/1640 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-07AMD agesa family15: PCI domain should scan bus from 0x18.0Siyuan Wang
There are four mainboards using agesa family15 code: Supermicro h8scm and h8qgi, Tyan s8226 and AMD dinar. All of these boards' PCI domain starts from 0x18.0. Take h8scm as an example, PCI devices from 0.0 to 0x14.5 is under 0x18.0. Now, the PCI domain's scan bus function stats from 0.0. This would result to the PCI devices be scanned twice. Because when the function run to device 18.0, it would scan from 0.0 again. This issue would result to 2 problems: 1) PCI device may be assigned two different PCI address. If this happenned on VGA device, coreboot maybe not load vga bios correctly. 2) coreboot initializes rd890's IO APIC twice. So this patch scans from 0x18.0 and could resolve the problems above. Change-Id: I90fbdf695413fd24c7a5e3e9b426dc7ca6e128b1 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/1639 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-06acpi: Add support for DMAR tables (Intel IOMMU support)Patrick Georgi
Adds lowlevel handling of DMAR tables for use by mainboards' ACPI code. Not much automagic (yet). Change-Id: Ia86e950dfcc5b9994202ec0e2f6d9a2912c74ad8 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1654 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-06Drop redundant CHIP_NAME in mainboard.cKyösti Mälkki
Compose the name from Kconfig strings instead. As the field is for debug print use only, a minor change in the output should do no harm. The strings no longer include word "Mainboard". Change-Id: Ifd24f408271eb5a5d1a08a317512ef00cb537ee2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1635 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-06smsc/lpc47n227: Make early_serial usablePatrick Georgi
This is the smallest possible change to make early_serial.c compile when included from romstage.c. early_serial could be reworked to be built as separate unit (romstage-y), but that should be done for all SuperIOs, not some individual outlier. Change-Id: I90ee66b43c9677b86b1b5d6fcc8febfbe58d80dd Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1686 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-06cpu/intel/model_1067x: Add proper c-state/p-state/thermal supportNico Huber
Change-Id: I853454e8f5617fb7af5dddd7288bdeeacc7b1b8e Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1663 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-06intel/socket_BGA956: enable speedstep, CAR, MMX, SSEPatrick Georgi
All of these capabilities exist on all CPUs supported on this socket. Change-Id: I54f34e48e34bb6ab5b9954ab7ece8c2c3a1a8e67 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1664 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-06Add name field for deviceKyösti Mälkki
The constant field "name" in chip_operations is common to multiple different devices within a chip and cannot reflect the actual device as found on the platform. The intention is that a driver sets dev->name as part of the device enumeration sequence with the detected hardware type and revision. The field is for debug print use only. Change-Id: Ib7bf90ba3c618ad0cb715d80d6a937ceaae0adcf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1634 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-05Overhaul speedstep codeNico Huber
This adds proper support for turbo and super-low-frequency modes. Calculation of the p-states has been rewritten and moved into an extra file speedstep.c so it can be used for non-acpi stuff like EMTTM table generation. It has been tested with a Core2Duo T9400 (Penryn) and a Core Duo T2300 (Yonah) processor. Change-Id: I5f7104fc921ba67d85794254f11d486b6688ecec Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1658 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-05Fix some indentation flaws and break very long linesNico Huber
Change-Id: I3efef6bc8f519382ffdd92eb10b4bcd1a4361ba9 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1657 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-02remove enable_cache() of 3 mainboardsSiyuan Wang
Because enable cache is added at the end of disable_cache_as_ram, ( http://review.coreboot.org/#/c/1662/2/src/cpu/amd/agesa/cache_as_ram.inc ) enable_cache() should be removed. The 3 mainboards are: amd parmer, amd thatcher and tyan s8226 Change-Id: If870ca07d2e97b9e860a2e2315f551251c7a4ed2 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/1669 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-11-02Persimmon: disable the unconnected Full-Speed USB portDave Frodin
Change-Id: Ia3824059a38412896ed2be0c8714018b2291c9f8 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/1660 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-02AMD agesa: add enable cache at the end of disable_cache_as_ramSiyuan Wang
add this code according to src/include/cpu/x86/cache.h ,line 92, functin enable_cache() Change-Id: Ida96a98397eeed98dd61ca979e8c5a33bf00f9e5 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/1662 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-02Correct FSB reading in speedstep ACPINico Huber
We parsed the MSR the wrong way, and didn't support some valid values. Change-Id: Ia42e3de05dd76b6830aaa310ec82031d36def3a0 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1656 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-02Fix some issues with new "reference" toolchainStefan Reinauer
Unfortunately the reference tool chain was updated without ever even testing it on an abuild run. This broke a number of ports. This change gets coreboot at least compiling again for all supported systems. Change-Id: I92c7cbc834de6d792fdab86b75df339e2874c52e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1670 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-11-01Merge cpu/intel/acpi.h into cpu/intel/speedstep.hNico Huber
We had only some MSR definitions in there, which are used in speedstep related code. I think speedstep.h is the better and less confusing place for these. Change-Id: I1eddea72c1e2d3b2f651468b08b3c6f88b713149 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1655 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-10-30Add support for socket LGA775Stefan Tauner
Change-Id: Ia7ef3a4cbc3638a9c9a48b297e392e4e655b6e6b Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: http://review.coreboot.org/1581 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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