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2021-03-25mb/google/dedede/var/cret: Enable touchscreenDtrain Hsu
Add ELAN and Weida touchscreen into devicetree for cret. BUG=b:180547621 BRANCH=dedede TEST=Build the cret board. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Icdb7aabe4a9ecd7b5a057c4644799aa537adb6ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/51737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-25mb/google/dedede/var/cret: Configure I2C ports and touchpadDtrain Hsu
1. Support Elan touchpad. 2. Support JYT touchpad. 3. Follow schematic to disable I2C1 and I2C3. BUG=b:183454249, b:180547781 BRANCH=dedede TEST=Build the cret board. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I8c150c3f65d0e057d5ba1b07ec1c20886f02ef6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51726 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-25mb/google/dedede/var/cret: Generate SPD ID for supported partsDtrain Hsu
Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: 1. H9HCNNNBKMMLXR-NEE 2. MT53E512M32D2NP-046 WT:F 3. K4U6E3S4AA-MGCR BUG=b:183057749 BRANCH=dedede TEST=Build the cret board. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Iacfdd9a27f126ba4b97d1a6493bcc09bb31454a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51619 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-25mb/google/dedede/var/cret: Configure USB port settingsDtrain Hsu
Follow schematic to modify USB port settings. USB2 [0]: USB Type C Port 0 USB2 [1]: None USB2 [2]: USB Type A Port 0 USB2 [3]: LTE USB2 [4]: None USB2 [5]: Camera UFC USB2 [6]: Camera WFC USB2 [7]: Integrated Bluetooth USB3 [0]: USB Type C Port 0 (M/B side) USB3 [1]: None USB3 [2]: USB Type A Port 0 (M/B side) USB3 [3]: LTE BUG=b:182973703 BRANCH=dedede TEST=Build the coreboot image. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I80447d6ac3422f858a9022f550b4f42353819405 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-25mb/google/dedede/var/cret: Configure GPIODtrain Hsu
Follow schematic to modify some GPIO pins. GPP_C12 - NC Pin, UP_20K GPP_C18 - NC Pin GPP_C19 - NC Pin GPP_C22 - NC Pin, UP_20K GPP_D12 - NC Pin GPP_D14 - NC Pin GPP_D15 - NC Pin GPP_D19 - NC Pin GPP_D20 - NC Pin GPP_E0 - NC Pin GPP_E2 - NC Pin GPP_H1 - NC Pin GPP_H6 - NC Pin GPP_H7 - NC Pin GPP_G0 - NC Pin GPP_G1 - NC Pin GPP_G2 - NC Pin GPP_G3 - NC Pin GPP_G4 - NC Pin GPP_G5 - NC Pin, UP_20K GPP_G6 - NC Pin GPP_G7 - NC Pin BUG=b:183078393 BRANCH=dedede TEST=Build the cret board. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Id966884f3e36303b636fa13ef9baecccae87604a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-25soc/amd/common/block/gpio_defs: Wake from either S0i3 or S3Karthikeyan Ramasubramanian
Add a helper bit mask to enable wake from either S0i3 or S3. BUG=None TEST=Build the Guyrbush mainboard. Change-Id: I934abad78135260081a61aee4c496b362e483de1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-24mb/purism/librem_mini: Drop superfluous devices from devicetreeMatt DeVillier
The 'device pci 00.0 on end' entries are not necessary for socketed devices unless a chip driver needs to be bound to a device, so remove them from the devicetree. Also remove the `drivers/wifi/generic` chip driver as it was not necessary either. Change-Id: Id5f2e34d98b236f9cfac9f0afd8a8017e349603f Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-24mb/google/guybrush: Temporary fix to set eSPI muxMathew King
This change allows guybrush EC communication while other patches in the SOC code are worked on. BUG=b:183149183 TEST=Boot guybrush with EC comunication Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I56fb64d4c065cf0665025346218cc66d77dacb52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51665 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-24mb/google/guybrush: disable KBRSTENKangheui Won
GPIO129 is muxed with KBRST, so setting GPIO129 to low causes reset when KBRSTEN is set to 1. Since reset value of KBRSTEN is 1 we need a logic to clear it. BUG=b:183340503 TEST=build Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I194e8432a14d6105f6bcf12111647f5aad4e2de2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-24mb/google/volteer/variants/drobit: Modify touchpad power sequenceWayne3 Wang
Modify power sequence of touchpad to meet the definition in the spec. BUG=b:178353432 BRANCH=firmware-volteer-13672.B TEST=build test firmware and verified by EE team. Change-Id: I8b8e383223d017223c36044efdf21738fe26d2ea Signed-off-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51514 Reviewed-by: Hao Chou <hao_chou@pegatron.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-24sb/intel/common: Use new acpigen_write_PRT_*_entry functionsTim Wawrzynczak
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I9f573b9bd40260ab963c5a4a965a6ac483af91ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/51158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-24acpi: Add acpigen_write_PRT* helpers for generating _PRT entriesTim Wawrzynczak
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ia666bd0e5db40d7873532dc22bc89be9854b903a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-24cpu/x86/smm: Fix SMM start address passingMarc Jones
This fixes an issue introduced in commit ad0116c0327f575f0af184a2f4861848a49a0e2a cpu/x86/smm_loaderv2: Remove unused variables It removed one variable that was needed to set the SMM start address that is used to set the SMM stack location. Change-Id: Iddf9f204db54f0d97a90bb423b65db2f7625217f Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51721 Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-24device/azalia_device.c: Program beep verbsPatrick Rudolph
Change-Id: I11b362d5e586194501de5dbd11f9c934a9d53940 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-03-24device/azalia_device.c: Introduce AZALIA_MAX_CODECSAngel Pons
Add the AZALIA_MAX_CODECS Kconfig option and use it. Change-Id: Ibb10c2f2992257bc261e6cb35f11cc4b2d956054 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-03-24device/azalia_device.c: Correct STATESTS access widthAngel Pons
The HD Audio spec states that the STATESTS register is 16 bits wide. Change-Id: If7859ed33e58d907a91c4ac8675892e37998cf41 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-03-24device/azalia_device.c: Unify `wait_for_valid` timeoutsAngel Pons
The timeout is never reached when the codec is functioning properly. Using a small timeout value can result in spurious errors with some codecs, e.g. a codec that is slow to respond but operates correctly. When a codec is non-operative, the timeout is only reached once per verb table, thus the impact on booting time is relatively small. So, use a reasonably long enough timeout to cover all possible cases. Remove the unconditional 25 µs delay and increase the timeout delay. The new value of 1 ms is the maximum of all existing implementations. Currently, the only boards using this code are AMD reference boards: - AMD Bilby - AMD Mandolin - AMD Padmelon Change-Id: Ia5e4829d404dcecdb9e7a377e896a319cb38531a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-24mb/emulation/qemu-q35: Fix format specifier for a `size_t`Benjamin Doron
Fix compilation on GCC 10.2.1 Change-Id: I47d29ef065f57f171f429bb6a368bc86e31acee9 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-24mb/system76/gaze15: Add System76 Gazelle 15Tim Crawford
Tested with TianoCore payload (UefiPayloadPkg). Working: - PS/2 keyboard, touchpad - Both DIMM slots - Both NVMe ports - SATA port - All USB ports - Webcam - Ethernet - Integrated graphics using Intel GOP driver - Internal microphone - Internal speakers - S3 suspend/resume - Flashing with flashrom - Booting to Ubuntu Linux 20.10 and Windows 10 Not working: - Discrete/Hybrid graphics This requires a new driver to work correctly, which will be added and enabled later. Change-Id: I10667fa26ac7c4b8eb67da11f3e963062bd0db47 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47822 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-24mb/intel/adlrvp: Enable CnviBtAudioOffloadUsha P
This change enables CnviBtAudioOffload. FSP is invoked to configure BT over USB and BT I2S pins for cAVS connection. BUG=None TEST=Verified BT offload working on ADL RVP Signed-off-by: Usha P <usha.p@intel.corp-partner.google.com> Change-Id: I1185a6c2295bae7d469be4da86502506adbeb8cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/51032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-03-24soc/mediatek: Use MRC cache API for asuradaYu-Ping Wu
Use the MRC cache API for asurada, and sync dramc_param.h with dram blob (CL:*3674585). With this change, the checksum, originally stored in flash, is replaced with a hash in TPM. In addition, in recovery boot, full calibration will always ne performed, and the cached calibration data will be cleared from flash. This change increases ROMSTAGE size from 236K to 264K. Most of the increase is caused by TPM-related functions. Add new API mtk_dram_init() to emi.h, so that 'dramc_parameter' can be moved to soc folder. With this CL, there is no significant change in boot time. Normal AP reboot time (fast calibration) is consistently 0.98s as before, so this change should not affect the result of platform_BootPerf. BUG=b:170687062 TEST=emerge-asurada coreboot TEST=Hayato boots with both full and fast calibration BRANCH=none Cq-Depend: chrome-internal:3674585, chrome-internal:3704751 Change-Id: Ief942048ce530433a57e8205d3a68ad56235b427 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-03-24soc/mediatek/mt8192: Enlarge ROMSTAGE to 272KYu-Ping Wu
Enlarge ROMSTAGE from 256K to 272K for the upcoming change of MRC cache (CB:51620). To have more compact space usage, reduce BOOTBLOCK size from 64K to 60K (only 44K needed), and move starting address of DRAM blob (DRAM_INIT_CODE) to 0x210000 (64K-aligned). BUG=b:170687062 TEST=emerge-asurada coreboot TEST=Hayato boots BRANCH=asurada Cq-Depend: chrome-internal:3704751 Change-Id: I7aaf9faf048e0adcb3a7d856d40891762c9a6604 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-03-23mb/google/octopus: Wake up AP on AC plug and unplugDerek Basehore
This patch makes all Octopus variants resume from S0ix/S3 on AC plug and unplug. Change-Id: Iab054d77368bf2047b6d523188b8c401a7643aaa Signed-off-by: Derek Basehore <dbasehore@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-23vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2081_02Ronak Kanabar
The headers added are generated as per FSP v2081_02. Previous FSP version was v2081_02. Changes Include: - Adjust UPD Offset in FspmUpd.h and FspsUpd.h - Add UPDs in Fsps.h and Fspm.h BUG=b:180918805 BRANCH=None TEST=Build and boot ADLRVP Change-Id: I69611de8286a570c59a6b4a44b9164384e9be81f Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51632 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-23soc/amd/cezanne: select HAVE_EM100_SUPPORTFelix Held
This makes the EM100 option visible in Kconfig that makes sure that the SPI settings that coreboot applies are valid for the EM100 that has some limitations on the maximum SPI frequency and possibly on the supported SPI modes. For the PSP SPI settings, the mainboard still might need to provide EM100-specific settings for EFS_SPI_READ_MODE, EFS_SPI_SPEED and EFS_SPI_MICRON_FLAG. Haven't checked if those PSP settings are correctly integrated for Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5dec9ce69628ca3623b5009d47f4b3dc020a3dad Reviewed-on: https://review.coreboot.org/c/coreboot/+/51711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-23soc/amd/common/block/gpio_defs: Support wake and debounce configurationKarthikeyan Ramasubramanian
Add a pad configuration macro to support configuring both wake and debounce. This support is required by Pen Detect GPIO. BUG=b:180539900 TEST=Build Guybrush mainboard. Change-Id: I3343a4e80fd5aa3047d76ff9f91ea57c3763bbca Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-23nb/intel/haswell: Limit mainboard USB config array lengthsAngel Pons
There are at most 14 USB2 ports and 6 USB3 ports on LynxPoint-H, and there are at most 10 USB2 ports and 4 USB3 ports on LynxPoint-LP. Limit the array lengths accordingly to cause build errors on invalid configs. Change-Id: Ieda7a1320d78dbbcb651f1715a87cd1d202a79f2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51451 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-23haswell boards: Use zero length for disabled USB portsAngel Pons
For disabled USB ports, the length setting does not matter. In future commits, disabled USB ports will end up with length field set to zero. Change-Id: I7613e1b0c89c0b58eca790ca14fcd1633c8a93af Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2021-03-23nb/intel/haswell: Use unshifted SPD addresses in mainboardsAngel Pons
It's common to use the raw, unshifted I2C address in coreboot. Adapt mainboards accordingly and perform the shift in MRC glue code. Tested on Asrock B85M Pro4, still boots and still resumes from S3. Change-Id: I4e4978772744ea27f4c5a88def60a8ded66520e1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51458 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-23nb/intel/haswell: Confine `pei_data` uses to raminit.cAngel Pons
Reorganize romstage.c to resemble sandybridge, and move everything that needs `pei_data` into raminit.c function `perform_raminit`. Barring USB settings, coreboot code no longer depends on pei_data.h definitions. It still depends on MRC, though. For now. Tested on Asrock B85M Pro4, still boots and still resumes from S3. Change-Id: I433f88db5fe7a7533ab6837015647ec31fb45e88 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51449 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-23mb/google/kukui: Add a new config 'Makomo'Sunway
A new board introduced to Kukui family. BUG=None TEST=make # select Makomo BRANCH=kukui Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com> Change-Id: I42b84e2c0926e755ba210fc8baac19f8ed2c4e57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51565 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-23mb/google/volteer/variants/delbin: Disable PmcUsb2PhySusPgEnableRavi Sarawadi
eDP panel flicker during system idle state is observed. Disabling USB2 SUS well power gating can remove flicker symptom. Please refer to doc#634894 for more details. BUG=b:182323059 BRANCH=None TEST=Boot and confirm no display flicker. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: Icadf9c494fab82b219317c3ca3b04f633b543083 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2021-03-22mb/google/volteer/variants/eldrid: Include SPD for H4AAG165WB-BCWENick Vaccaro
Add SPD support to eldrid for DDR4 memory part H4AAG165WB-BCWE. Eldrid should use DRAM_ID strap ID 4 (0100) on SKUs populated with H4AAG165WB-BCWE DDR4 memory parts. BUG=b:181732562 TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds successfully. Change-Id: I38cfe3eb26b00563ce17df3a3ac2a0a846f2ae00 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51667 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22mb/google/dedede: Create cret variantIan Feng
Create the cret variant of the waddledoo reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:181325655 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_CRET Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I700201cf81b25c6776df3ec9fc843cd9bd8c88c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-03-22soc/amd/common/block/psp/psp: update psp_status_nobase error messageFelix Held
When the soc_get_mbox_address functions returns 0 after not being able to find an initialized PSP base address MSR or in case of Stoneyridge the PSP's BAR3, the code will print an error string. This string needs to reference both PSP_ADDR_MSR and PSP BAR3 and not only the latter one, since in Picasso and Cezanne only the former one is present. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I32a1e87e2a7d89c7b53f47c987e7bf0556154cf7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-22mb/google/volteer/variants/copano: Configure specific DPTF parametershao_chou
Configure board specific DPTF parameters for copano BUG=b:176961219 BRANCH=firmware-volteer-13672.B TEST=build and verify by thermal team Change-Id: Ibce67f81503b84b58798bc198947e61907276ad3 Signed-off-by: Hao Chou <hao_chou@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51561 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22soc/intel/tigerlake: Add #include guards to soc/early_tcss.hTim Wawrzynczak
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I8a630655731b3ee30ef8377296878cce7b8c2201 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51648 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22{lynxpoint/broadwell}: Set Azalia HDCFG.BCLD bitAngel Pons
Lock down several HD Audio registers by setting the HDCFG.BCLD bit. Tested on Asrock B85M Pro4, the GCAP register becomes read-only. Change-Id: Id6208289a68baaedc4aad51cc0c5355f996a1b00 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-03-22{lynxpoint,broadwell}/hda_verb.c: Drop effect-free writeAngel Pons
This bit is hardwired to 1 (Intel High Definition Audio mode). Change-Id: I3683497c5e2446f1d8319037583890b5d0a8a95c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-03-22soc/intel/broadwell: Use Lynx Point hda_verb.cAngel Pons
This allows dropping the SOC_INTEL_COMMON selection. Pull in the options selected by SOC_INTEL_COMMON into Broadwell Kconfig as they still apply. Change-Id: I0dd7de5358667240b0b3c1a550ba373a2a5af7d1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-03-22sb/intel/lynxpoint/hda_verb.c: Add missing codec detect stepsAngel Pons
Lynx Point reference code version 1.9.1 and soc/intel/common/hda_verb.c perform these steps. Add them to Lynx Point as well. With this change, Lynx Point and soc/intel/common hda_verb.c files are now identical. Change-Id: I2fc592f73697a43bd5a3315ac80c77ff9f00da9b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-03-22soc/intel/common/hda_verb.c: Fix up comment styleAngel Pons
Change-Id: I31c541fb197aca33ef64d2972a32924b61fd015c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-03-22purism/librem_14: add on-board LAN deviceMichael Niewöhner
On-board devices should be present in the devicetree, so that `.on_mainboard` field of `struct device` is `1`. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I3678514482724377bcdfcbdc7f2c5b312a48b2c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-03-22mb/asus/p2b: Refactor southbridge ACPI stuffKeith Hui
Move (remaining) southbridge ACPI stuff into one file under sb/intel/i82371eb, that is simply included from the board's \_SB scope. Change-Id: Ibed49a800dec19534761e5ab22a6cbb1e6bd4a5d Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-22util: Add DDR4 generic SPD for H4AAG165WB-BCWENick Vaccaro
Add SPD support for DDR4 memory part H4AAG165WB-BCWE. BUG=b:181732562 TEST=none Change-Id: I923fcbd08875a2a581fba4b1db00a4d1c1bb11cf Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51666 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22lynxpoint/broadwell: Rename LP GPIO config globalAngel Pons
Do not use the same name as the non-LP GPIO config. This allows checking at build-time that a mainboard uses the correct GPIO config format. Without this commit, there are no build-time errors when using the wrong format of GPIO config, but there would be undefined behavior at runtime. Tested by trying to build asrock/b85m_pro4 and hp/folio_9480m after toggling the `INTEL_LYNXPOINT_LP` Kconfig option (and trimming down the USB config arrays for asrock/b85m_pro4). In both cases, building failed because the necessary GPIO config global is not defined, as expected. Change-Id: Ib06507ef8179da22bdb27593daf972e788051f3a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51661 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22mb/google/zork: Enable SSFC as upper 32 bit of fw_configFrank Wu
To append SSFC to top 32 bits of fw_config. BUG=b:177971830 BRANCH=firmware-zork-13434.B TEST=Build coreboot and get the value of SSFC. Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Iab1596f1cc8fbbf45e6a9269351bf422a43f3583 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51655 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22mb/google/brya: Enable S0ixSugnan Prabhu S
This change enables S0ix for brya platform. BUG=b:181843816 TEST=Built image and booted to kernel. Change-Id: Idc6f7fce9779ef4458375becebf5dc65b228abeb Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51526 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22device/azalia_device.c: Switch to stopwatchPatrick Rudolph
Use timer.h helpers instead of open-coding timeout handling in polling loops. The 25-microsecond delay in `wait_for_valid` looks odd, and may be removed in subsequent commits. For now, preserve existing behavior. Change-Id: Id1227c6812618597c37408a7bf53bcbcae97374a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50789 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22mb/google/dedede/var/storo: Add USB Port ConfigurationZanxi Chen
Add USB Port configuration into devicetree for storo BUG=b:177389444 BRANCH=dedede TEST=built firmware and verified USB3.0 function is OK Change-Id: I1527c7178ffac9b2322eb65aab6e2086d949e47c Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-22acpi/acpigen.h: Add more intuitive AML package closing functionsJakub Czapiga
Until now every AML package had to be closed using acpigen_pop_len(). This commit introduces set of package closing functions corresponding with their opening function names. For example acpigen_write_if() opens if-statement package, acpigen_write_if_end() closes it. Now acpigen_write_else() closes previously opened acpigen_write_if(), so acpigen_pop_len() is not required before it. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Icfdc3804cd93bde049cd11dec98758b3a639eafd Reviewed-on: https://review.coreboot.org/c/coreboot/+/50910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-22mb/google/zork: Move max98357a out of baseboardEric Lai
Not all of dalboz variants support the this amp. Thus, move out of baseboard. BUG=b:182815488 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: If708574f5fb18dd3b4f2ef978529a16a40d5dc0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-hsuan Hsu <yuhsuan@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-03-22mb/google/guybrush: Enable AP <-> H1 communicationKarthikeyan Ramasubramanian
Configure H1 I2C and Interrupt GPIOs during the early initialization. Add devicetree configuration for H1 device and enable the required config items. BUG=b:180528902 TEST=Build Guybrush mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I040a5e6101bab0c7425d7b6cc6fbed3b479a5a44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-22mb/google/guybrush: Add initial I2C configurationKarthikeyan Ramasubramanian
Add I2C peripheral reset configuration required during early init. Enabled I2C generic and HID drivers. I2C GPIOs are configured as required in CB:50091. BUG=b:180531661 TEST=Build guybrush mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I67690fbd25639879a730260aaca4cddb5e47bbc7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-22soc/amd/cezanne: Initialize I2CZheng Bao
Add I2C initialization in romstage and ramstage. TEST=To test the I2C connection on Majolica, which doesn't have SPD connection, call the function below after i2c_soc_init is called. i2c_read_bytes(2, 0x4d, addr, data, 1);/* Read out 1 byte one time */ It can get the register values of TMP432B. Or /* Override EC port in ec.h */ #define EC_DATA 0x662 #define EC_SC 0x666 ec_write(0xA9, 0x40); i2c_read_bytes(1, 0x10, addr, data, 2);/* Read out 2 bytes one time */ It can get the register values of CM32181A3OP(ALS). Change-Id: I3a2a1494b44b68e8d8204fba0c90e769e0256e6f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51029 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22soc/amd/cezanne: Get I2C specific code for cezanneZheng Bao
Add macros, settings and callbacks to support I2C for cezanne. Change-Id: Ic480681d4b7c6fb8591e729090e4faeb5fccf800 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-22trivial: Fix the tab and rearrange the linesZheng Bao
Change-Id: I1ded9fcec9594977b9b9c8d3c105f9998c0ee2bc Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51656 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22mb/amd/majolica: Set IOMUX to enable I2C2 & I2C3Zheng Bao
Change-Id: I142c06c150214d58acc04b8c6b3b027fff0256db Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2021-03-22soc/amd/common/block/i2c: Move SoC agnostic parts into commonKarthikeyan Ramasubramanian
The logic behind I2C bus initialization, I2C MMIO base address getter and setter, I2C bus ACPI name resolution are identical for all the AMD SoCs. Hence moving all the SoC agnotic parts of the driver into the common driver and just configure the SoC specific parts into individual I2C drivers. BUG=None TEST=Build Dalboz and Grunt. Boot to OS in Dalboz. Ensure that the I2C peripherals are detected as earlier in Dalboz. Verify some I2C peripheral functionality like trackpad and touchscreen. Change-Id: Ic9c99ec769d7d8ad7e1e566fdf42a5206657183d Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Suggested-by: Kyosti Malkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51509 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22soc/amd/common: Introduce I2C driver common to all AMD SoCsKarthikeyan Ramasubramanian
I2C driver is replicated in each generation of AMD SoCs. Introduce a common I2C driver that can be used across all the AMD SoCs. To begin with, peripheral reset functionality is moved into this common driver. SoC specific I2C driver passes the SCL pin configuration in order for the common driver to reset the peripherals. More functionality can be moved here in subsequent changes. Also sb_reset_i2c_slaves() is renamed as sb_reset_i2c_peripherals() as an effort towards using inclusive language. BUG=None TEST=Build Dalboz and Grunt. Boot to OS in Dalboz. Ensure that the I2C peripherals are detected as earlier in Dalboz. localhost ~ # i2cdetect -y 0 Warning: Can't use SMBus Quick Write command, will skip some addresses 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 10: 20: 30: -- -- -- -- -- -- -- -- 40: 50: 50 51 -- -- -- -- -- -- 58 59 -- -- -- -- -- -- 60: 70: localhost ~ # i2cdetect -y 1 Warning: Can't use SMBus Quick Write command, will skip some addresses 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 10: 20: 30: -- -- -- -- -- -- -- -- 40: 50: UU -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60: 70: Change-Id: I9f735dcfe8375abdc88ff06e8c4f8a6b741bc085 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Suggested-by: Kyosti Malkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-22soc/mediatek/mt8192: devapc: Add SCP domain settingTinghan Shen
Configure SCP domain from 0 to 3 and lock it to prevent changing it unexpectedly. BUG=b:163300760 TEST=emerge-asurada coreboot BRANCH=asurada Change-Id: Idccb001f0cf58492f7f1655203106470637b9b82 Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-03-20soc/intel/xeon_sp/cpx: Set PCU locksMarc Jones
Set the PCU locks as indicated by the BWG. Lock the following: P_STATE_LIMITS PACKAGE_RAPL_LIMIT SAPMCTL DRAM_PLANE_POWER_LIMIT CONFIG_TDP_CONTROL Change-Id: I5f44d83e2dd8411358a83b5641ddb4c370eb4e84 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51505 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-20soc/intel/xeon_sp/: Fix SMI_LOCK settingMarc Jones
Move the SMI_LOCK to post SMM setup. Also, use the correct access method for SMI_LOCK. GEN_PMCON_A is in PCI config space and not in MMIO space on this PCH. Change-Id: Ibbb183ef61ca7330198c1243ecfc2d4df51e652b Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51452 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-20mainboard/: Register chipset_lockdown on xeon_sp mainboardsMarc Jones
Set chipset_lockdown in devicetree for recommended security settings. Change-Id: Ie27450dd32463243b1456932a1d39d40afa81da1 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51388 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-20soc/intel: Drop unused `GPIO_NUM_GROUPS` macroAngel Pons
This macro is unused and its value is often wrong. Drop it. Change-Id: Id3cfaa4d2eef49eddc02833efbe14e0c5c816263 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51662 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-20mb/purism/librem_cnl: Add new board/variant Librem 14Matt DeVillier
Add support for the CometLake-U based Librem 14 laptop. Change-Id: I24a2a92091cc272638ecaf8ea23a896cab8a7153 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51549 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-20google/trogdor: Add new variant MarzipanKevin Chiu
This patch adds a new variant called Marzipan that is identical to Lazor for now. BUG=b:182181519,b:182018606 BRANCH=master TEST=make Change-Id: I92b667c63b0a06255d1e9511d7486293d8b4426a Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-03-20mb/google/trogdor: Add support for SPI_FLASH_GIGADEVICExuxinxiong
Add support SPI_FLASH_GIGADEVICE for some project. BUG=b:182246432 BRANCH=trogdor TEST=emerge-strongbad and test with power on. Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com> Change-Id: I6ab948909f4e17b4b992be6d699646f7a62bef7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-03-19mb/lenovo/x200: Fix boot-time docking stateKevin Keijzer
The X200 would undock itself when waking up from S3, requiring a physical reconnection before the dock would work again. Similar to 4611ad8, this reintroduces h8_mb_init() for the X200. A hook function h8_mb_init() will be called at the end of h8_enable(), in place of the ancient h8_mainboard_init_dock(). This should fix the regression the X201 and T410 also suffered from for the X200. Change-Id: Icb6dd145e56b90e0e04133810c5e9ac7b641ad68 Signed-off-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51123 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19mb/scaleway/tagada: Don't change FIAMUX when Security Override is setJulien Viard de Galbert
This will not enable M.2 SATA drive if the ME config was lost (For instance after flashing a full flash factory image) This is required so that the system can boot without FIA MUX error during flash update procedure. Change-Id: I55a8bcdc30bc67af2d3e9ccb8844eac599727108 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/25443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19security/intel/cbnt: Make CBNT compatible with CMOS option tableArthur Heymans
Make sure the bytes in RTC cmos used by CBNT don't collide with the option table. This depends on what is set up in the BPM, Boot Policy Manifest. When the BPM is provided as a binary the Kconfig needs to be adapted accordingly. A later patch will use this when generating the BPM. Change-Id: I246ada8a64ad5f831705a4293d87ab7adc5ef3aa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-03-19cpu/x86/mp_init.c: Drop unnecessary preprocessor usageArthur Heymans
Change-Id: If67bcbf0c8ffbd041e2e4cab8496f4634de26552 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19cpu/x86/mp_init.c: Don't overwrite the global variable per CPUArthur Heymans
Global variables are located in .bss and not on the CPU stack. Overwriting them a per CPU case is bound to cause race conditions. In this case it is even just plainly wrong. Note: This variable is set up in the get_smm_info() function. Change-Id: Iaef26fa996f7e30b6e4c4941683026b8a29a5fd1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19cpu/x86/smm_module_loaderv2.c: Remove noop stack size checkArthur Heymans
The argument provided to the function was always the same as the one computed inside the function so drop the argument. Change-Id: I14abf400dce1bd9b03e401b6619a0500a650fa0e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19cpu/x86/mp_init: Allow stub sizes larger than the save state sizeArthur Heymans
The permanent handler module argument 'save_state_size' now holds the meaning of the real save state size which is then substracted from the CPUs save state 'top' to get the save state base. TESTED with qemu Q35 on x86_64 where the stub size exceeds the AMD64 save state size. Change-Id: I55d7611a17b6d0a39aee1c56318539232a9bb781 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19cpu/x86/smm_loaderv2: Remove unused variablesArthur Heymans
Remove variables that are either constants or are just assigned but not used. Change-Id: I5d291a3464f30fc5d9f4b7233bde575010275973 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19cpu/x86/smm/smm_module_loaderv2.c: Constify setup_stub()Arthur Heymans
Change-Id: I6648d0710bc0ba71cfbaaf4db7a8c1f33bbc9b35 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19cpu/x86/smm_module_hander: Set up a save state mapArthur Heymans
With the smm_module_loaderv2 the save state map is not linear so copy a map from ramstage into the smihandler. TESTED on QEMU q35: Both SMMLOADER V1 and V2 handle save states properly. Change-Id: I31c57b59559ad4ee98500d83969424e5345881ee Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50769 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19cpu/x86/smm_loaderv2: Fix when only 1 CPU is presentArthur Heymans
Move out smm_create_map as this was not run if concurrent_save_states is 1. The cpus struct array is used in the smm_get_cpu_smbase() callback so it is necessary to create this. TEST: run qemu/q35 with -smp 1 (or no -smp argument) Change-Id: I07a98bbc9ff6dce548171ee6cd0c303db94087aa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50783 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19cpu/x86/smm_stub.S: Drop smm_runtime from the stubArthur Heymans
The parameters that the permanent handler requires are pushed directly to the permanent handlers relocatable module params. The paremeters that the relocation handler requires are not passed on via arguments but are copied inside the ramstage. This is ok as the relocation handler calls into ramstage. Change-Id: Ice311d05e2eb0e95122312511d83683d7f0dee58 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-03-19cpu/x86/smm.h: Remove smm runtime pointer from smm_loader_paramsArthur Heymans
struct smm_loader_params is a struct that is passed around in the ramstage code to set up either the relocation handler or the permanent handler. At the moment no parameters in the stub 'smm_runtime' are referenced so it can be dropped. The purpose is to drop the smm_runtime struct from the stub as it is already located in the permanent handler. Change-Id: I09c1b649b5991f55b5ccf57f22e4a3ad4c9e4f03 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19cpu/x86/mp_init.c: Copy the stub parameter start32_offset into ramstageArthur Heymans
Keep a copy of start32_offset into ramstage to avoid needing to pass arguments, calling from assembly. Doing this in C code is better than assembly. Change-Id: Iac04358e377026f45293bbee03e30d792df407fd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50765 Reviewed-by: Eugene Myers <cedarhouse1@comcast.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19cpu/x86/smm_module_handler: Add relocatable module paramsArthur Heymans
Instead of passing on parameters from the stub to the permanent handler, add them directly to the permanent handler. The parameters in the stub will be removed in a later patch. Change-Id: Ib3bde78dd9e0c02dd1d86e03665fa9c65e3d07eb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19cpu/intel/fit: Reserve the FIT pointer using a .c fileArthur Heymans
No need to do this assembly anymore. Change-Id: I69b42c31e495530fe96030a5a25209775f9d4dca Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-03-19cpu/intel/fit: Add the FIT table as a separate CBFS fileArthur Heymans
With CBnT a digest needs to be made of the IBB, Initial BootBlock, in this case the bootblock. After that a pointer to the BPM, Boot Policy Manifest, containing the IBB digest needs to be added to the FIT table. If the fit table is inside the IBB, updating it with a pointer to the BPM, would make the digest invalid. The proper solution is to move the FIT table out of the bootblock. The FIT table itself does not need to be covered by the digest as it just contains pointers to structures that can by verified by the hardware itself, such as microcode and ACMs (Authenticated Code Modules). Change-Id: I352e11d5f7717147a877be16a87e9ae35ae14856 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50926 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19soc/amd/picasso/soc_util.c: Fix typo in macro nameAngel Pons
Change-Id: I3225fa4e53a75c2bf6fe0dcea85db57efe489482 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51615 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19mb/google/volteer/var/elemi: Config GPP_B7/GPP_B8 as NCWisley Chen
elemi does not use the GPP_B7/GPP_B8, so config to NC. Currently, there is no functional impact. BUG=b:182981460 TEST=emerge-volteer coreboot, boot into OS, and suspend/resume successfully. Change-Id: I7b491fd595b0e77e6dcce08e3172dbe592f63c37 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-03-19soc/intel/tgl: Add configurable value for PmcUsb2PhySusPgEnableDerek Huang
PmcUsb2PhySusPgEnable is enabled by default. Expose devicetree parameter to disable Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com> Change-Id: Ibd54a10c57d39bb8762b705ef0d6ff4cd47f0d89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-03-19mb/purism/librem_cnl: drop MAX_CPUS from KconfigMatt DeVillier
No need to restrict this further than the platform default, and will be problematic with the addition of the upcoming 6C/12T Librem 14 board. Change-Id: I1913992ec12578e1ad3bf6bf679d1a35a46d7370 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19mb/{clevo/cml-u,system76/lemp9}: Clarify `gen2_dec` useAngel Pons
This I/O range is for a PM channel on the EC, not the PCH PMC. Change-Id: I64422e537c1edcd0673cf87f16139fb117b10e75 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51604 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19nb/intel/haswell: Consolidate memory-down SPD handlingAngel Pons
Mainboards do not need to know about `pei_data` to tell northbridge code where to find the SPD data. Adjust `mb_get_spd_map` to take a pointer to a struct instead of an array, and update all the mainboards accordingly. Currently, the only board with memory-down in the tree is google/slippy. Mainboard code now obtains the SPD index in `mb_get_spd_map` and adjusts the channel population accordingly. Then, northbridge code reads the SPD file and uses the index that was read in `mb_get_spd_map`, and copies it to channel 0 slot 0 unconditionally. MRC only uses the first position of the `spd_data` array, and ignores the other positions. In coreboot code, `setup_sdram_meminfo` uses the data of each SPD index, so `copy_spd` has to account for this. Tested on Asrock B85M Pro4, still boots and still resumes from S3. Change-Id: Ibaed5c6de9853db6abd08f53bbfda8800d207c3e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51448 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19mb/google/slippy: Correct memory-down SPD handlingAngel Pons
MRC only uses the SPD data for the first index, and ignores the rest. Moreover, index 1 corresponds to the second DIMM on the first channel, which does not exist on ULT (only one DIMM per channel is supported). Copy the SPD to the first DIMM on channel 1 instead. Adjust northbridge code to retrieve the serial number from the correct SPD data block. Tested on Google Wolf, both channels are still correctly detected. Change-Id: Ic60ff75043e6b96a59baa9e5ebffb712a100a934 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-18mb/google/brya: Implement SLP_S0_GATE signalTim Wawrzynczak
The SLP_S0_GATE# signal is used in conjunction with the PCH's SLP_S0# to provide an indication to the rest of the platform when the system is entering its software-initiated low-power state (i.e. S0ix). This lets the platform distinguish between opportunistic S0ix entry and the runtime suspend mechanism. BUG=b:180401723 TEST=abuild Change-Id: I7fe2e3707465778baf56283617a8485a94f2dbca Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50881 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18vc/google/chromeos/acpi: Add type to OIPG declarationRaul E Rangel
OIPG is a Package. Define the type so it doesn't default to UnknwonObj. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I068ed4ae95967aa884506c4971ee2e2dba7b5e4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51537 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18mb/amd/majolica: Generate OIPG PackageRaul E Rangel
This fixes the unknown reference errors for OIPG. Since Majolica doesn't actually have any of the GPIOs ChromeOS uses, we leave the arrays empty. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifeae84e0ccab187a4e7131cd6ea9e1336d79df67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51536 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18mb/google/guybrush: Add eSPI GPIO back to init tableMathew King
GPIOs should be configured in ramstage even if they are configured in an earlier stage. BUG=b:180721208 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I9896db41dbe2812856357510bc4420482e73ab3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51547 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18mb/google/guybrush: Configure UART0 gpio in early stageMathew King
BUG=b:180721208 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I8aa54acf1fa9295b27c33a0066432665e6e3755c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-03-18soc/amd/common: Make fch_spi_config_modes staticMathew King
It is currently only used in this translation unit. Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Ib779a38306fb45320f3e4eb71f63630023d59906 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51535 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18mb/ocp/deltalake: Initialize VPD 'coreboot_uart_io' with default value 1Johnny Lin
In case the VPD variable cannot be read. Change-Id: I79fae6f4b4aad91a4040387ca6ddee8dfcc34d90 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51559 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18mb/google/mancomb: Configure eSPI GPIOs in early stageEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ifa51705b3b5aab16f9cd2c11084220aafacd2774 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-20 16:26:10 +0000