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Wow, this one is disliked by clang for the empty for() loop, but
looking at the file just makes my eyes bleed a little bit. I remember
the circumstances under which we let this code go in. It was supposed
to save contributions from a vendor, but that never worked out.
Just to keep the little chunks down, here's an indent run and some of
the cruft removed that doesn't actually contribute to functionality in
any way.
Change-Id: Ie82166ca82f09c4b66decfde5ad194a2d70b0708
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Fix CID 1376472 detected by coverity. Zero extend the capacity instead
of sign extending it.
TEST=Build and run on reef
Change-Id: I6aac422fb1dacb75e0cc44a94ff1f467ce9f529e
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/20392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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Add a SMM_TSEG_SIZE symbol that can be used in top of memory
calculations.
Change-Id: I26f3b06f85f0cf5613656c1d5df55bd9ea4bbbbc
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19750
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove IDE from the Stoney Ridge source. This APU doesn't have
an IDE controller. The support was left over from pi/hudson.
BUG=chrome-os-partner:62580062
Change-Id: I7316c113a7464089ccfbea6b6cf69787940b9e97
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Remove the pcie.c file. Historically PCIe lanes have been
available from the Gfx and/or the FCH. The integrated FCH in
this APU has no PCIe available.
BUG=chrome-os-partner:62580062
Change-Id: Ie89383dadfaa57c5a6d185e74551ae50ac8d9778
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The Stoney Ridge does not contain this bridge like some of the older
Hudson FCHs. Remove this support from the source.
This moves the Stoney Ridge IRQ setup to the southbridge file, hudson.c.
BUG=chrome-os-partner:62580062
Change-Id: I8f974ba76b8c20f4335dd8872eaf4b8172188ee2
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Correct the majority of reported errors and mark most of the
remaining ones as todo. Some of the lines requiring a >80
break are indented too much currently.
Changes to agesawrapper.c cause the build to change, so this
file is also left as-is. Make hex values consistently lower-case.
BUG=chrome-os-partner:622407746
Change-Id: I0464f0cafac4ee67edc95d377dcf7aab9a90c66b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Correct the majority of reported errors and mark most of the
remaining ones as todo. (Some of the lines requiring a >80
break are indented too much currently.) Some of the alignment
in hudson.h still causes checkpatch errors, but this is
intentionally left as-is.
Also make other misc. changes, e.g. consistency in lower-case
for hex values, using defined values, etc.
These changes were confirmed to cause no changes in a Gardenia
build. No other improvements were made, e.g. changing to helper
functions, or converting functions like __outbyte().
BUG=chrome-os-partner:622407746
Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Update Psi2Threshold, IccMax, AcLoadline, DcLoadline
VR config settings as per board design.
BUG=b:62063434
BRANCH=none
TEST=Build and boot soraka.
Change-Id: I254bbb88b82ddf278f0ec71bc98873df1d5e0d27
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Signed-off-by: G Naveen <naveen.g@intel.com>
Reviewed-on: https://review.coreboot.org/20309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Soraka uses MPS2949 IMVP8 controller and does not need the VR
workaroud similar to Eve.
BUG=None
TEST=Build & boot on soraka. Ensure IMVP8 controller goes to low power
mode in S3 and S0ix by measuring power.
Change-Id: Ib98bb709ecc9e362a5cef437e7319e41f398a73b
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Reviewed-on: https://review.coreboot.org/20255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Code checked manually
Change-Id: Idf86546ddda4fa2b4b96f0b703c03af9931c757d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Correct the checkpatch errors reported in the asl files and
make other stylistic modifications.
These changes were confirmed to cause no changes in a Gardenia
build.
BUG=chrome-os-partner:622407746
Change-Id: Id8b2620d161062c444e493325d83bb158705b76b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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This requires to also unify the calling convention for
AGESA functions from
AGESA_STATUS (*agesa_func)(UINT32 Func, UINT32 Data, VOID *ConfigPtr)
to
AGESA_STATUS (*agesa_func)(UINT32 Func, UINTN Data, VOID *ConfigPtr)
On systems running 32bit x86 code this will not make a difference as
UINTN is uintptr_t which is 32bit on these machines.
Change-Id: I095ec2273c18a9fda11712654e290ebc41b27bd9
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Return CB_SUCCESS and CB_ERR instead of some integer.
Preparation to merge intel/soc and intel/nb opregion implementations.
Change-Id: Ib99fcfe347b98736979fc82ab3de48bfc6fc7dcd
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.
Change-Id: Id5bc8b75b1fa372f31982b8636f1efa4975b61a5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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... even though the author of the code probably wished he was
working on a (much faster) broadwell system instead. Let's fix
the header guard to reflect the right SOC.
Noteworthy: clang detected that this was wrong.
Change-Id: I74c217c0471800f40c31a9ac38ba5396f82cd724
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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It's pretty obvious that the author did not want to use a logical
and (&&) here but an arithmetical and (&)
Change-Id: Ic1bece86986906b76308bbb46235c22418e27990
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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dual_node is never used in that function. And it is never set
correctly either, because the register f3xe8 is never actually
read either. Just remove the whole useless construct.
Change-Id: If316da89bceae6b162f20e4b632276db2d9ef423
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The warning -Wstack-usage= doesn't seem to exist on clang, so trying
to disable it makes the compiler unhappy about non-existent pragmas.
Catching this on gcc is good enough, so let's disable it for the clang
case
Change-Id: Ia3716a83ba41743ac1dbe73e70abd170de30d7ab
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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src/vendorcode/amd/agesa/f15/Include/OptionMemoryInstall.h:3688:7: error:
suggest braces around initialization of subobject
Change-Id: Id086a64205dfffa2d1324993f4164508b57b6993
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Ibff31a9960a23f03facbb09e76d6a5d6fbfb5e94
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I8b02596b116c0b164e83e7b02449c547224a50a6
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/20330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: Ia76c391e04e1e11bd110764902b91ef4ed5e8490
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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If SSE instructions are enabled in the build assume the SMM
modules are compiled with SSE instructions. As such enable
the SSE instructions in SMM mode by setting up the cr4 register.
In addition, provide a place to save and restore the SSE state
in both the relocation handler and permanent handler.
Change-Id: Ifa16876b57544919fde88fba5b8f18e4ca286841
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20244
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fill in acpi_name to return proper ACPI names.
To be used with SSDT generators.
The ACPI names have to match those already used in ASL code.
By providing the ACPI name it can be retrieved by the
acpi_device_name() method and doesn't need to be hardcoded in
SSDT generators any more.
HDEF is defined in sb/intel/bd82x6x/acpi/audio.asl.
LPCB is defined in sb/intel/bd82x6x/acpi/lpc.asl.
RP0* is defined in sb/intel/bd82x6x/acpi/pcie.asl.
SATA is defined in sb/intel/bd82x6x/acpi/sata.asl.
SBUS is defined in sb/intel/bd82x6x/acpi/smbus.asl.
EHC? is defined in sb/intel/bd82x6x/acpi/usb.asl.
XHC is defined in sb/intel/bd82x6x/acpi/usb.asl.
Change-Id: I08611b11c694ee5034bca11cb321915d5c73c2f6
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Fill in acpi_name to return proper ACPI names. To be used with
SSDT generators.
The ACPI names have to match those already used in ASL code.
By providing the ACPI name it can be retrieved by the
acpi_device_name() method and doesn't need to be hardcoded in
SSDT generators any more.
GFX0 is used in drivers/intel/gma/acpi/pch.asl.
MCHC is used in nb/intel/sandybridge/acpi/hostbridge.asl.
Change-Id: I19526e334a9c5435fdb19419a671b86c5f6b2be9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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The ChromeEC board directories for auron and rambi have been removed
from the latest version of ChromeEC. Remove them here so the submodule
can be brought forward.
Change-Id: I763d03009f735d3f8aedbeb44788d03714c86102
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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Update the world facing camera sensor to OV13858 and also
add delay of 5ms after xshutdown rising which indicates system
ready status.
BUG=b:38326541
BRANCH=none
TEST=Build and boot soraka. Dump and verify that the generated DSDT table
has the required entries. Verified that sensor probe is successfull.
Change-Id: I0cd535e6568f104ffaa1092a13667def646df0eb
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
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Add clock frequency property into _DSD ACPI object and set it
to 19.2MHz for camera sensors. Upstream camera kernel has added
a check for clock frequency in sensor probe function and without
this property sensor probe fails.
BUG=b:38326541
BRANCH=none
TEST=Build and boot poppy. Dump and verify that the generated DSDT table
has the required entries. Verified that sensor probe is successfull.
Change-Id: I147b3c932a33ae034868f7f9b616500d24ca71e3
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20294
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
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Zero the framebuffer structure so if it is not filled in (either if
no display is present or if there is an error) then it does not
provide garbage data to the payload.
This was noticed when booting a board without a display attached as
the payload wrote to the framebuffer at a random address.
With this change the payload can properly handle the case where a
display is not attached and not corrupt memory.
Change-Id: I8114d88496cd2a4f2e7f07f377fe76f3180a7f40
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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In the D0 and D3 ACPI methods use word access to the PME status and
control register. This brings the code inline with the Intel reference
code and matches how the kernel handles access to this register.
BUG=b:35587084
BRANCH=eve
TEST=manual stress testing of D0<>D3 transition across multiple devices
Change-Id: I53f7465d6ad5da1780a5641ff52056445ebaca8b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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For the skylake/kabylake generation of PCH there is an ACPI workaround
for emmc/sd power state that involves disabling and re-enabling dynamic
clock gating after enabling power to the controller, before setting the
power state to D0.
Under certain conditions we have observed that the controller is not
powered and ready by the time the kernel attempts to read the PME
control and status register and so the system will hang while attempting
to read PCI config register 0x84.
To ensure that the controller is ready add a 2ms delay after re-enabling
dynamic clock gating and before setting the power state to D0.
This issue has been observed on eMMC, but the same workaround exists for
the SD card interface so the same delay is added there.
BUG=b:35587084
BRANCH=eve
TEST=manual stress testing of D0<>D3 transition across many devices
shows no hard hang after 2 days.
Change-Id: If0f0323cf5437c54c907c332937b5de9dda2d8f6
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: Ifc6a0638c03fa5f3e1007a844e56dfa6f4c71d7e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Most of these functions go unused most of the time, but in order
to not keep several copies around, let's make sure we are using
the same file everywhere first.
Change-Id: Ie121e67f3663410fd2860b7d619e8a679c57caba
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Code checked manually
Change-Id: I91ababb3bf7aa1ab0f71bb005c4685e81bb4d92f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Correct all checkpatch errors but leave two errors in place
that are caused by AMD typing.
Change-Id: I9daa374da76ff991de72d16bad0e8b586aa95525
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Switch Garnenia mainboard to single soc/ directory structure.
Change-Id: I095804d603bcccf324d3244965081a9dccba62ae
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Copy northbridge files from northbridge/amd/pi/00670F00
to soc/amd/stoneyridge and soc/amd/common.
Changes:
- update chip_ops and device_ops
- remove multi-node support
- clean up Kconfig and Makefile
Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Copy cpu/amd/pi/00670F00 to soc/amd/stoneyridge and
soc/amd/common. This is the second patch in the process of
converting Stoney Ridge to soc/.
Changes:
- update Kconfig and Makefiles
- update vendorcode/amd for new soc/ path
Change-Id: I8b6b1991372c2c6a02709777a73615a86e78ac26
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This
is the first of a series of patches to migrate Stoney Ridge
support from cpu, northbridge, and southbridge to soc/
Changes:
- add soc/amd/stoneyridge and soc/amd/common
- remove all other Husdon versions
- update include paths, etc
- clean up Kconfig and Makefile
- create chip.c to contain chip_ops
Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
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This patch updates the coreboot DDR Settings to match the configuration
used by ARM-Trusted-Firmware.
Change-Id: I34bc2950a9708ac89a5637bf682551e03d993fcc
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-on: https://review.coreboot.org/20304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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As per latest BWG, ucode reloading should be done at the end
of Mp Init, i.e., after PRMRR and other features are enabled.
No reloading specifically after SMM Relocation is required.
As, in the Common CPU MP Init code, we are already doing a
uCode load at the end of MP Init Feature Programming, hence,
the uCode loading after SMM relocation can be removed.
Change-Id: Ib1957c5fe5a8c83bb20b978a9841670b0c3e8846
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch uses the common CPU Mp Init code.
BUG=none
BRANCH=none
TEST=Build and boot poppy
Change-Id: Ieb2f8ae25a31e86e9251fe97859678745fe610f5
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
|
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This patch contains State Machine callbacks init_cpus()
and post_cpu_init().
Also, it has the SOC call for CPU feature programming.
Change-Id: I5b20d413c85bf7ec6ed89b4cdf1770c33507236b
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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It does not work to enable the LPC range in the function
mainboard_init() because the LPC bus driver closes the range during PCI
enumeration again. For this reason, enabling decoding of the address
range for COM 3 will be done at a later point in time -
mainboard_final().
Change-Id: I452bca4e430b1ea75e4a327591da84500491fe84
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/20295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
With enabled XDCI support we are not able to use USB port 0 over XHCI
driver. For this reason, we disable XDCI into devicetree.cb.
Change-Id: I1ed721d9ffd44a920a6f1f16855d5b7ceb1b17c5
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/20296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
Code checked manually
Change-Id: I92f0b5d47c60c259171c4db90fb5003f4eb8580b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Code checked manually
Change-Id: I5a9596328c028d570303e9390c0133b19b97d683
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
|
|
With the do while loop, it can be avoided do use an infinite loop with a
break condition inside.
Change-Id: I030f6782ad618b55112a2f0bac8dda08b497a9f1
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/20269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
This fixes improper dram frequency being displayed in sandy bridge
native raminit.
Change-Id: I1fe4e4331f45ce1c21113c039b8433252326293d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
|
On boards that are able to take two DIMMs per channel the
command rate should be 2T. It is possible to use 1T with
load reduced "1T" DIMMs, but it's not clear how to detect
those DIMMs. Raminit might fail for those who do not have
such DIMMS installed.
Hardcode command rate of 2T to make sure raminit works on
dual DIMM per channel boards (currently only desktop boards).
The command rate of 1T is still tested if only 1 DIMM per
channel is present.
Will decrease performance on quad slot mainboards, if two DIMMs
are installed in one channel and previously 1T have been selected.
Tested on ASRock B75 Pro3-M.
Change-Id: I029d01092fd0e11390cebcd94ca6f23bf0ee2cab
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Maybe we could go on, but cbmem_add() failing is a very bad sign.
Should fix coverity CID 1376384 (Null pointer dereferences
(NULL_RETURNS)).
Change-Id: I330cee6db3540c6a9c408d56da43105de5d075f7
Found-by: Coverity Scan #1376384
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20280
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
|
|
Fix up for 1b5eda0 (arch/x86/smbios: Fix undefined behavior) which
introduced the variable `tmp` and used it out of scope. Should fix
coverity CID 1376385 (Memory - illegal accesses (RETURN_LOCAL)).
Change-Id: I8d4f664fc54faf6beb432b939dda4ddf93cf5d3e
Found-by: Coverity Scan #1376385
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
|
|
Bifferboard was the only board that used this chip, and it has now
been removed. Removing the chip as well. If there is desire to
continue work on the board, it can be found in the 4.6 branch.
Change-Id: I33a1e713cdfea47abce71b79f0a9c93562c96d12
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
This board can't be found to be tested, and compiles romstage with
romcc. If desired, it can be continued in the 4.6 branch.
Change-Id: I4826c277bbb444c2f0573729d76cd492ade95b4c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Use full text GPLv2 header.
Change-Id: I937aed725ebf0d2e12c52ac4d94794830fbd764d
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
|
rdrand64() is not clang friendly. Actually it looks like the
function is incorrect on 32bit x86 for all compilers including
gcc, but gcc won't care because the function is never called on
x86:
src/arch/x86/rdrand.c:51:15: error: invalid output size for constraint '=a'
: "=a" (*rand), "=qm" (carry));
^
1 error generated.
Guard the code correctly if ENV_X86_64 is not set.
Change-Id: Ia565897f5e4caaaccfcb02cf1245b150272dff68
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
|
|
Use the existing macros for CR0 to set the flags in the
SIPI vector code.
Change-Id: Iad231b7611b613512fd000a7013175e91542ac10
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Use the existing macros for CR0 to set the flags in the
SMM stub.
Change-Id: I0f02fd6b0c14cee35ec33be2cac51057d18b82c0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20242
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
For sizes and dimensions use size_t. For pointer casts
use uintptr_t. Also, use the ALIGN_UP macro instead of
open coding the operation.
Change-Id: Id28968e60e51f46662c37249277454998afd5c0d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20241
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
The vboot code tries reading rollback protection indices from the TPM,
and if the attempt to read returns TPM_E_BADINDEX, it decides that the
TPM has not yet been initialized for the Chromebook use, and needs to
be taken through the factory initialization sequence.
TPM_E_BADINDEX is an internal representation of the TPM error 0x28b,
generated on attempts to read a non existing NVMEM space.
If the space exists, but has never been written the TPM returns error
0x14a. This condition (the space exists but not written) could happen
if the previous factory initialization attempt was interrupted right
after the space was created.
Let's map this error to the same internal representation
(TPM_E_BADINDEX) so that the Chrome OS device could recover when this
condition occurs.
BRANCH=reef, gru
BUG=b:37443842
TEST=verified that the Pyro device stuck in TPM error state recovered
when this patch was applied.
Change-Id: I6ff976c839efcd23ae26cef3ee428e7ae02e68f8
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/20299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
SMI code is very similar across Intel platforms. Move this code to
common/block/smi to allow it to be shared between platforms instead
of duplicating the code for each platform. smihandler.h has already
been made common so all it will contain is name changes and a move
to the common block location. Due to moving smihandler code, APL
changes are bundled here to show this change.
Change-Id: I599358f23d5de7564ef1ca414bccd54cebab5a4c
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/19392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Add SPI driver code for the legacy SPI flash controller. Enable erase
and write support allowing coreboot to save non-volatile data into
the SPI flash.
TEST=Build and run on Galileo Gen2.
Change-Id: I8f38c955d7c42a1e58728c728d0cecc36556de5c
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/20231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
resources
This patch controls the camera devices power through ACPI power resource.
* Add Opregions for PMIC,
* TI_PMIC_POWER_OPREGION
* TI_PMIC_VR_VAL_OPREGION
* TI_PMIC_CLK_OPREGION
* TI_PMIC_CLK_FREQ_OPREGION
* Add power resources for sensors and VCM,
* OVTH for CAM0
* OVFI for CAM1
* VCMP for VCM
* Implement _ON and _OFF methods for sensor and VCM module's power on
and power off sequences.
BUG=b:38326541
BRANCH=none
TEST=Build and boot poppy. Dump and verify that the generated DSDT table
has the required entries.
Change-Id: I87cd0508ed5ed922211a51f43ee96b6f44cf673d
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/20054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Bind the camera sensor and CIO2 devices through the ports and endpoints
configuration available in _DSD ACPI object.
* Port represents an interface in a device.
* Endpoint represents a connection to that interface.
BUG=b:38326541
BRANCH=none
TEST=Build and boot poppy. Dump and verify that the generated DSDT table
has the required entries.
Change-Id: I6d822165bb9a0cd6f7d4cdcb36333887953110a3
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Enable RT8168_GET_MAC_FROM_VPD in fizz Kconfig.
BUG=b:62090148, b:35775024
BRANCH=None
TEST=Boot to kernel. Insert mac address into VPD
vpd -s ethernet_mac=<address>
reboot the system.
Ensure we have ip address and corresponding mac
address with ifconfig.
Ensure ethernet controller shows up with lspci.
Change-Id: I00f63dcb56a2c9a4600c8461bc94e06ec5ab2d81
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/20232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
If RT8168_GET_MAC_FROM_VPD selected, use r8168
driver with some slight mods to check the VPD
for a mac address. Otherwise, check for mac
address in cbfs. Use default mac address if
cannot find one.
BUG=b:62090148, b:35775024
BRANCH=None
TEST=Boot to kernel. Insert mac address into VPD
vpd -s ethernet_mac=<address>
reboot the system.
Ensure we have ip address and corresponding mac
address with ifconfig.
Ensure ethernet controller shows up with lspci.
Change-Id: I7ff29de2c4c3635dc786686cc071c68d51b0f975
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/20008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
By default disabled. Will need to add
FIZZ_USE_SPI_TPM config to enable.
BUG=b:62456589, b:35775024
BRANCH=None
TEST=Reboot and ensure that TPM works in verstage
CQ-DEPEND=CL:530184
Change-Id: I14ce73a1c3745c996b79c4d4758ca744e63a46b4
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/20134
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:62456589, b:35775024
BRANCH=None
TEST=Reboot and ensure verstage doesn't have any TPM errors
CQ-DEPEND=CL:530185
Change-Id: Icfde0f62bd058d960fcb0c6fc67f9d8f6b9462f5
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/20133
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Fixes report found by undefined behavior sanitizer. Dereferencing a
pointer that's not aligned to the size of access is undefined behavior.
The report triggered for smbios_cpu_vendor(). Also fixes the same issue
in smbios_processor_name() found by inspection.
Change-Id: I1b7d08655edce729e107a5b6e61ee509ebde33b6
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
|
|
Change memcpy()s and memset()s to endian.h wrappers for consistency
and safety. Add zero_n() wrapper to safely clear memory.
Change-Id: If155d82608c81992f05eae4d2223de6f506e98c5
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Add missing includes to build mmc.c.
TEST=Build and run on Galileo Gen2
Change-Id: I0dea597272e5ece97843704a159aa546a8d77ff0
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/20271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
This patch adds mipi_camera.asl,
* Add TPS68470 PMIC related ACPI objects.
* Add OV cameras related ACPI objects.
* Add Dongwoon AF DAC related ACPI objects.
* SSDB: Sensor specific database for camera sensor.
* CAMD: ACPI object to specify the camera device type.
BUG=b:38326541
BRANCH=none
TEST=Build and boot poppy. Dump and verify that the generated DSDT table
has the required entries.
Change-Id: If32a2a8313488d2f50aad3feaa79e17b1d06c80f
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/19621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Remove MIPI camera related register entries from devicetree.cb.
BUG=b:38326541
BRANCH=none
TEST=Build and boot poppy and soraka.
Change-Id: Ic6a6a98d4c8ed6cba760eae5fd87bc2a3f15d7d2
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/19619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
These delays, adding up to 600 ms, don’t seem to be needed, so remove
them.
TESTED on d510mo, boots fine without.
Change-Id: If089d6677fe95b086eeb00540acfbb66fa2e1c47
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Damien Zammit <damien@zamaudio.com>
|
|
Fixes 2 reports found by undefined behavior sanitizer. Dereferencing
pointers that are not aligned to the size of access is undefiend
behavior.
Change-Id: Iaa3845308171c307f1ddc7937286aacbd00e3a10
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Use define for SSA base address.
Move EM64T area to 0x7c00 and add reserved area of size 0x100,
as there's no indication that the address 0x7d00 exists on any
platform.
No functional change.
Change-Id: I38c405c8977f5dd571e0da3a44fcad4738b696b2
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Disable TPM when VBOOT_MOCK_SECDATA is enabled.
BUG=None
BRANCH=None
TEST= Build image using USE="mocktpm" emerge-poppy coreboot depthcharge
vboot_reference chromeos-bootimage . Verify boot is successful with mock
tpm.
Change-Id: Iee527ed17cffb7d25d9089e48a194d99ac8c3cd1
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/20158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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RAMD_ID_1 moves to PAD_DSI_TE and RAM_ID_2 moves to PAD_RDP1_A on Rowan.
BUG=chrome-os-partner:62672
BRANCH=none
TEST=emerge-rowan coreboot
Change-Id: Iae44934d8d669d696b83f9d3e3450a0e408fe062
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Gerrit-Rebase-Ignore-CLs-Before: https://chromium-review.googlesource.com/539234
Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/388068
Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/453778
Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/454921
Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/455118
Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/479613
Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/487023
Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/498587
Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/506785
Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/520572
Original-Commit-Id: 4da19b3c00578f96ec933cff9ad0c9988a4c4a30
Original-Change-Id: I64fd29de607a0b360d355fd3724e3a649adc658b
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/448397
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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The differential signal of DQS needs to keep low
level before gate training. RPULL will connect
4Kn from PADP to VSS and a 4Kn from PADN to
VDDQ to ensure it. But if it has PHY side ODT
connected at this time, it will change the DQS
signal level. So it needs to disable PHY side ODT
when doing gate training.
BRANCH=None
BUG=None
TEST=boot from bob
Change-Id: I56ace8375067aa0bb54d558bc28172b431b92ca5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: cb024042c7297a6b17c41cf650990cd342b1376f
Original-Change-Id: I33cf743c3793a2765a21e5121ce7351410b9e19d
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/448278
Original-Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Original-Tested-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-on: https://review.coreboot.org/18582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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The previous implementation was using a for loop. By it's
very definition the last statement in the for loop declaration
is done at the end of the loop. Therefore, if the conditional for
breaking out of the for loop because of a timeout would always
see a value of 0 for the number of APs accepted. Correct this
by changing to a while loop with an explicit timeout condition
at the end of the loop.
Change-Id: I503953c46c2a65f7e264ed49c94c0a46d6c41c57
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch uses common SCS library to setup
sd card.
Change-Id: I06898e30a9b39f169b35f581a3ee09238f0f40c4
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/20217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
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This patch uses common SCS library to setup
sd card.
Change-Id: Iafbba04d7a498b9a321e8efee4abf07820d17330
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/19632
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
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Create Intel Common SCS code. This code currently only contains
the code for SD card SSDT generation. More code will get added up
in the subsequent phases.
Change-Id: I82f034ced64e1eaef41a7806133361d73b5009d3
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/19631
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
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Use verb table values from AMI firmware, consolidate NID
definitions using azalia macros. Fixes headphone jack detection
and microphone.
Change-Id: Ia31be6efc7afe921ad91b400f66694d951f0a260
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Initialize the audio codec without depending on DSP binary blobs.
The hda_verb.c was copied from the intel/kblrvp rvp7 variant, and the
hda_verb.h file was copied from the purism/librem13.
The IoBufferOwnership FSP option in devicetree has to be 0 for the azalia
driver to work.
Change-Id: Ifa36ac0839daedfa59c497057da0ace04d401f2a
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Some NVMe devices (Intel 600p series for example) seem to lock up
in D3 drive power state (L1.2 PCIe power state).
Disabling L1 substates fixes it.
Change-Id: I00a327dc91d443beb565fe4e72aaf816e40a007c
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/19900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: I88e376d61c4aba5030a0be7c8bdfe7b57881a197
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/20169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Enable libgfxinit.
Tested on Lenovo T430:
* LVDS
* VGA
* DP (using DP->HDMI adapter)
All three ports are working. The LVDS port is garbled under linux
when VGA or DP is connected, likely due to missing VBT.
Change-Id: I665661e93724072d1e8412cfcc0e818f824c8cb0
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Use a GNVS variable to store the trackpad interrupt, in order to
support both SNB and IVB variants from a single build.
Change-Id: I53df35fff41f52a7d142aea9b1b590c65195bcfd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add a GNVS variable to store trackpad IRQ for google/parrot, so
that both SNB and IVB variants can be built with the same config
Change-Id: I232da4077e3400b8ef2520dc33fd770c731b7ec3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Existing value was copied from librem13 v1 board, use value
obtained from AMI firmware.
TEST: Observe Windows boots correctly, function keys work
under both Windows and Linux.
Change-Id: I0ea6cc4602ce1047cb803acc65cbca1af1f480b0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Populate a memory_info struct with PEI and SPD data,
in order to inject the CBMEM_INFO table necessary to
populate a type17 SMBIOS table.
On Broadwell, this is done by the MRC binary, but the older
Haswell MRC binary doesn't populate the pei_data struct with
all the info needed, so we have to pull it from the SPD.
Some values are hardcoded based on platform specifications.
Change-Id: Iea837d23f2c9c1c943e0db28cf81b265f054e9d1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Add default values for MAINBOARD_VERSION and CBFS_SIZE.
Change-Id: Ib6461cef78f3fea448baf1ada456e3c8335f1543
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
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- remove unused I2C, serialIO defs
- set PL2 override, VR mailbox cmd based on SKL-U ref board,
as values copied from google/chell are for SKL-Y
Change-Id: I3a138c28d0322df6cb41ec1a845ae31602cb69a7
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Update devicetree USB config based on board spec.
Leave OC pins set to skip since the info is unavailable.
Change-Id: I2a4fe17ed7edacbbbaf56969f9d2801b45a20da9
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Don't allow the user to set PCIe configspace base address.
Don't allow the user to set the DCACHE size and base.
Change-Id: I7a42cc5f6098214364624bcfa3cbd93b4903ee84
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Change-Id: Ic1656311ecc670dc0436995f0ec8199d270da4d1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Change-Id: I8b2794f56f39492589a08e5676cb33eec89a976e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20179
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Change-Id: I254549057552be93611afa8ca52d22be220fe3dc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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