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2019-10-31cpu/x86: make set_msr_bit publicly availableMichael Niewöhner
Haswell and model_2065 implement a static set_msr_bit helper which should be publicly available instead. Move it to cpu/x86. Change-Id: I68b314c917f15fc6e5351de1c539d5a3ae646df8 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36338 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-31mb/asrock/h110m: configure SuperIO Deep SleepMaxim Polyakov
Change-Id: I10766ffda67bdc830ab01436ebd0578c79f1ec70 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-31soc/intel/icelake: adapt FSP GOP param to match the other FSP2.0 platformsMichael Niewöhner
Set the FSP parameter PeiGraphicsPeimInit according to RUN_FSP_GOP to enable or skip GOP. Change-Id: I5993e64631f86ff0f9ae069e10b89df8bc4cd085 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-31soc/mediatek/mt8183: Disable DRAM DVFS in recovery modeYu-Ping Wu
Currently full calibration with DVFS (which implies tripling memory training time for multiple frequencies) will be run in recovery mode, which takes up to 30 seconds with serial console enabled. However, in recovery mode the system should be running only the recovery programs with minimal services. DVFS should be not needed. In order to improve stability and system boot time, we want to disable DVFS training in recovery mode. BRANCH=kukui BUG=b:142358843 TEST=emerge-kukui coreboot Change-Id: I4f1b1b020eba9bfce21655169bcb31b98d54b010 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36456 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-31soc/intel/icelake: Enable caching on SPI memory-mapped boot device ↵Subrata Banik
unconditionally Icelake platform doesn't support booting from any other media (like eMMC on APL/GLK platform) than only booting from SPI device and on IA platform SPI is memory mapped hence enabling temporarily cacheing on memory-mapped spi boot media. Also removed inclusion of unused header in cpu.c file TEST=Able to build and boot ICL DE board. Change-Id: I46d9ec054c4804ca756f2101085a55e91b5cc6f0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36431 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30sb/intel/common: Make linking pmbase.c conditionalArthur Heymans
Change-Id: I6a7cd96699dbeb42a53bf1d25db1bcf93e416e0f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33200 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30sb/intel/common/Makefile: Use 'all' class to link files in all stagesArthur Heymans
This links the reset function, the common pmbase functions and the spi driver in all stages. The RTC code is not included in SMM as it is unused there. Change-Id: I65926046d941df3121c7483d69c0b4f7003d783e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-30mb/google/hatch/variants/helios: Modify DPTF parametersKane Chen
Modify DPTF parameters. Modify TDP PL1 values to 15. Remove TCHG Level 3 - 0.5A. BUG=b:131272830 BRANCH=none TEST=emerge-hatch coreboot chromeos-bootimage Signed-off-by: YenLu Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I0e5c079856a167b1c2ef52e446d055404e565858 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35794 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30src/southbridge: change "unsigned" to "unsigned int"Martin Roth
Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Iee2056a50a1201626fa29194afdbfc1f11094420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36333 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30Program loading: Handoff cbmem_top via calling argumentsArthur Heymans
There are a lot of different implementations to pass information from romstage to ramstage. These could all be unified by passing this information via cbmem. Often however these methods exist for that very purpose. This solves this by passing cbmem_top via the programs arguments. Change-Id: Id2031f7bb81ce65fc318313c270eb1fbae3b2114 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36272 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30arch/x86/boot.c: Pass arguments when running programsArthur Heymans
Payloads can use coreboot tables passed on via arguments instead of via a pointer in lower memory. Stages can make use of the argument to pass on information. Change-Id: Ie0f44e9e1992221e02c49d0492cdd2a3d9013560 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36143 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30soc/intel/apollolake: set FSP param to enable or skip GOPMichael Niewöhner
Set the FSP parameter PeiGraphicsPeimInit according to RUN_FSP_GOP to enable or skip GOP. Change-Id: I3546371dd18120e3fbd1179a79b2bdc0a7436726 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-30soc/intel/cannonlake: set FSP param to enable or skip GOPMichael Niewöhner
Set the FSP parameter PeiGraphicsPeimInit according to RUN_FSP_GOP to enable or skip GOP. Change-Id: I7f7b2c688e46534046dc0976458c4c96614100b0 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-30soc/intel/common: move common memmap functionality from skl,icl,cnl,aplMichael Niewöhner
This moves common memmap functionality from skl,icl,cnl,apl to the common tree. Change-Id: I45ddfabeac806ad5ff62da97ec1409c6bb9e89ac Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36410 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30arch/x86/Makefile.inc: Use the 'all' target to add common sourcesArthur Heymans
Change-Id: Ibbd418656c32f56be2b00481068e8499421b147c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-30hatch: refactor gpio table into baseboard, allow empty SPDsPaul Fagerburg
Each variant needed to define variant_early_gpio_table(), even if it didn't need to make any changes. Added a __weak version of the function into baseboard/gpio.c. Certain upcoming Hatch variants will not use SPD files. Allow SPD_SOURCES in spd/Makefile.inc to be empty. BUG=None BRANCH=None TEST=Build coreboot and see that it builds without error Change-Id: Ie946cfd7c071824168faa38fd53bd338a5a451e1 Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36068 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30mainboard: Add Lenovo ThinkPad T440pIru Cai
The code is based on autoport. This port is tested on a T440p without a dGPU and can boot Arch Linux from SATA disk with SeaBIOS payload. The tested components and issues are in the documentation. Change-Id: I56a6b94197789a83731d8b349b8ba6814bf57ca2 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34359 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30commonlib/helpers: Add alloca() macroTim Wawrzynczak
If there is no alloca() macro defined, then define it as __builtin_alloca(), as most compilers support that as an intrinsic instead, if no alloca.h is included. Change-Id: I8730d57ce7c2f323b52e7a5720c598fb7af16b44 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36387 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-29arch/x86/*.S: use defines instead of hardcoded valuesPatrick Rudolph
As preparation for x86_64 clean the assembly code and introduce arch/ram_segs.h similar to existing arch/rom_segs.h. Replace open coded segment values with the defines from the new header. Change-Id: Ib006cd4df59951335506b8153e9347450ec3403e Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36321 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-29soc/skylake/vr_config: print mch_id in hexMaxim Polyakov
Change-Id: I89e2bccf3fb99b20dde38745fc124d5dc95feb78 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-29ec/google/chromeec: Clean up ec.[ch]Tim Wawrzynczak
Change all uN integral types to uintN_t. Make the names of host command params/responses consistent. Use static struct initialization to ensure all fields are initialized. BUG=none BRANCH=none TEST=compiles Change-Id: Ibe1e29e88975c85eea215adedc5f5e483243e0d6 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Joel Kitching <kitching@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-29nb/intel/{nehalem,x4x}: Remove unused 'include <pc80/vga_io.h>'Elyes HAOUAS
Change-Id: If9c743335ab09038c9e22d1f4d3b7411585b2c8c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-29purism/librem_skl: add libgfxinit supportMatt DeVillier
Panel settings taken from KBL FSP sample vbt.bin Test: build/boot librem13v2/15v3 with libgfxinit init, verify both LFB and text modes functional Change-Id: I9582065603417e53704244e95dde51a59f709664 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-10-28src/soc/intel: skl,cnl,icl: remove unneeded check in cbmem_top()Michael Niewöhner
As stated in CB:36334 cbmem_top() should not be called before memory is initialized. Therefore drop the check to see if MRC finished. Change-Id: I964a20a5e9aa69fdb75413c36a17d34b7ba00098 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36386 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-28soc/intel/broadwell_de: Implement smbios_cpu_get_maximum_freq_mhz()Andrey Petrov
Determine maximum speed by looking at either turbo flex limit or uncore ratio limit. Signed-off-by: Andrey Petrov <anpetrov@fb.com> Change-Id: I0f3a64a40cb1d28d8eb9380c2071ec748e345b88 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-10-28arch/x86: Populate more fields in SMBIOS type 4Andrey Petrov
If CPUID leaf 0x16 is available (Skylake and later) use it to obtain current and maximum speed. Otherwise call weak function that can be provided elsewhere (cpu/soc/mainboard). Also, populate "core enabled" with the same value as "core count". TEST=tested on OCP Monolake with dmidecode -t processor Change-Id: Ie5d88dacae6623dfa0ceb3ca1bb5eeff2adda103 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-10-28arch/x86: Move max cpuid leaf function into arch/x86Andrey Petrov
This cpuid function (0) is same across Intel and AMD so having it in arch/x86 seems like a good idea. Change-Id: I38f1c40bceac38ed6428f74b08bf60b971644f5a Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-10-28nb/intel/gm45: Add C_ENVIRONMENT_BOOTBLOCK supportArthur Heymans
The i82801ix_early_init is now called both in the bootblock and romstage. The rationale behind setting this up twice is to ensure bootblock-romstage compatibility in the future if for instance VBOOT is used. This moves the console init to the bootblock. The romstage now runs uncached. Adding a prog_run hooks to set up an MTRR to cache the romstage will be done in a followup patch. The default size of 64KiB is not modified for the bootblock as trying to fit both EHCI and SPI flash debugging needs a more space and 64KiB is the next power of 2 size that fits it. TESTED on Thinkpad X200. Change-Id: I8f59736cb54377973215f35e35d2cbcd1d82c374 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-28cpu/intel/car: Correctly cache the bootblock with C_ENVIRONMENT_BOOTBLOCKArthur Heymans
With CONFIG_C_ENVIRONMENT_BOOTBLOCK it makes more sense to rely on the size of the bootblock over CONFIG_XIP_ROM_SIZE. To make this work, only powers of 2 are allowed as bootblock size. Change-Id: Ic8104ca9c51e4d2eccdb277e4c2111d2da662f3e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-28soc/mediatek/mt8183: Pass MR values as function argumentsYu-Ping Wu
To make data flow more explicit, global variables 'MR01Value' and 'MR13Value' are replaced with local variables, which are passed as function arguments. BRANCH=kukui BUG=none TEST=1. emerge-kukui coreboot 2. Fast calibration succeeded Change-Id: Id21483092c86c3ae7dbb1173a2b943defe41a379 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-28src/cpu: Use 'include <stdlib.h>' when appropriateElyes HAOUAS
Also: add some missing includes spotted by Jenkins. Including <types.h>, is supposed to provide stdint and stddef. Change-Id: I7bd999b59d1c0bdfa5999bf5805576f94c9a2390 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-28src/southbridge: Use 'include <stdlib.h>' when appropriateElyes HAOUAS
Also, including <types.h>, is supposed to provide stdint and stddef. Change-Id: I7e1a3483aae0e3f0a7bc2eb2c1862ae7a325fd9c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-28src: Remove unused '#include <cpu/cpu.h>'Elyes HAOUAS
Change-Id: Ibcb1cafe36c255b4c5bd0a4faeedb95e91048709 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-28mb/lenovo/x200: Correct device tree override logicBill XIE
If a device node should be enabled on some variants, but disabled on others, it had better be declared as disabled (rather than absent) in base device tree (rather than override tree for the variant disabling it), and enabled in override tree for the variant needing it, so that it does not need to be declared once more when adding another variant with such node disabled. Change-Id: I4b28360905ae38149ace9ac5d21cd6d5045b7584 Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-28lib/cbfs: Don't load XIP stages from bootblockArthur Heymans
This should improve boot times as it skips unnecessary read and writes. Change-Id: I8cf36613903783e741b2e3bfeeee5bc29ab26d5b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-28mb/google/sarien/arcada: Add support for Cirque TouchpadKarthikeyan Ramasubramanian
Add Cirque Touchpad devicetree configuration to export relevant ACPI objects to the kernel. BUG=b:141259109 BRANCH=sarien TEST=Boot to ChromeOS. Ensure that relevant ACPI objects are exported in the SSDT. Change-Id: I91dcb27b86c6a2bed5579f1f6c1102871d55b315 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-10-28lib/prog_loaders.c: Add prog_locate_hook()Frans Hendriks
There is no posibility to prevent loading images from cbfs at this stage For security features prog_locate_hook() is added. This hook can be used to prevent loading the image. BUG=N/A TEST=Created verified binary and verify logging on Facebook FBG-1701 Change-Id: I12207fc8f2e9ca45d048cf8c8d9c057f53e5c2c7 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-27mb/google/poppy/variant/nocturne: don't invert GPP_D17Nick Vaccaro
This change removes an inversion of GPP_D17 that caused the device to get stuck in a reboot loop because the kernel was crashing within the first couple seconds of kernel boot. BUG=b:142515200 BRANCH=none TEST=Flash and boot nocturne, verify boot is stable and that device doesn't reboot after jumping into kernel, and that it passes the 'tast -verbose run <ip> hardware.SensorRing' test. Change-Id: Ia1408ef6ea92f6b31a9f3eee8720954af3a7c382 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35967 Reviewed-by: Yicheng Li <yichengli@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-27Dragonair: Add sku23Wisley Chen
BUG=b:142987639 TEST=emerge-hatch coreboot Change-Id: I0ff1a81d0579d0b328a48bc7d4f867592ec63e8b Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philip Chen <philipchen@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-10-27mb/supermicro/x11-lga1151: use the new Kconfig to hide GOPMichael Niewöhner
The board does not have any graphics port connected to the SoC. Hence, use the new Kconfig to hide GOP initialization. Change-Id: Ia88e062bea243369da27b94608f89f0808257688 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-27device: add Kconfig option to hide GOP initialization optionMichael Niewöhner
There are mainboards that do not have any graphics ports connected to the SoC. It would be senseless to initialize the iGD, thus add a new mainboard Kconfig to hide the GOP option. Change-Id: Ica3b3a7a0c8120c95412369a24d8d669fb59fded Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-27src/soc: change "unsigned" to "unsigned int"Martin Roth
Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I9c1228d3f9e7a12fe30c48e3b1f143520fed875c Reviewed-on: https://review.coreboot.org/c/coreboot/+/36332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-27src/mainboard: change "unsigned" to "unsigned int"Martin Roth
Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I46d131f76ec930d2ef0f74e6eaabae067df10754 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-27src/[arch-lib]: change "unsigned" to "unsigned int"Martin Roth
Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ibb7b48a7a144421aff29acbb7ac30968ae5fe5ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/36329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-27mb/supermicro/h8scm_fam10: Use 'Device()' instead of 'Processor()'Elyes HAOUAS
Processor() operator is deprecated, use Device() instead. Found-by: ACPICA 20191018 Change-Id: I9f6c025a548e60a91d8064b0aeaf4d8530d78305 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27mb/amd/serengeti_cheetah_fam10: Use 'Device()' instead of 'Processor()'Elyes HAOUAS
Processor() operator is deprecated, use Device() instead. Change-Id: I1650df927aa6d4a1282ed50b2bcbb63d5bd04347 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27mb/msi/ms7721: Use 'Device()' instead of 'Processor()'Elyes HAOUAS
Processor() operator is deprecated, use Device() instead. Change-Id: Ib70b349742fb636e25f1369d54641997e57a2045 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27mb/lippert: Use 'Device()' instead of 'Processor()'Elyes HAOUAS
Processor() operator is deprecated, use Device() instead. Change-Id: I5761b093b43aa7d97a6b84730a4009a5d163550d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27mb/jetway: Use 'Device()' instead of 'Processor()'Elyes HAOUAS
Processor() operator is deprecated, use Device() instead. Change-Id: Ib454fc76db0b45332326772b8d1f295429107133 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27src/[northbridge,security]: change "unsigned" to "unsigned int"Martin Roth
Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: If6b5930f78c3da6dcefaa7b6202cd0424a24525b Reviewed-on: https://review.coreboot.org/c/coreboot/+/36331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-27mb/iei: Use 'Device()' instead of 'Processor()'Elyes HAOUAS
Processor() operator is deprecated, use Device() instead. Change-Id: I547be16285787ee3578f855111ca177be047ced2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27mb/gigabyte: Use 'Device()' instead of 'Processor()'Elyes HAOUAS
Processor() operator is deprecated, use Device() instead. Change-Id: Ia27308ba17c6b5c836ada6278f7d26631e09c022 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27mb/avalue: Use 'Device()' instead of 'Processor()'Elyes HAOUAS
Processor() operator is deprecated, use Device() instead. Change-Id: I303023a16f8c913c965995794cb627bb9591560b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27mb/asus: Use 'Device()' instead of 'Processor()'Elyes HAOUAS
Processor() keyword is deprecated, use Device() instead. Change-Id: I162304bdef6562fd660c01fb8fc67037ebe8cfa5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27mb/advansus: Use 'Device()' instead of 'Processor()'Elyes HAOUAS
Processor() Keyword is deprecated, use Device() instead. Change-Id: I805291716ab3395736d8a70a18468f247d9f4edf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27mb/amd: Use 'Device()' instead of 'Processor()'Elyes HAOUAS
Processor() operator is deprecated, use Device() instead. Change-Id: Ia1d73806b00ec38084fff3989f52227d4c216e65 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27cpu/amd/*/*/acpi/: Use 'Device()' instead of 'Processor()'Elyes HAOUAS
Processor() operator is deprecated, use Device() instead. Found-by: ACPICA 20191018 Change-Id: I4541372a98f05d3e915c74bc28f41309754014e4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36258 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-27mb/(ich7): Use macro instead of magic numberElyes HAOUAS
Change-Id: Ida291ed9f3a509e9b96a5c254433db6f8028bfb2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27src/{device,drivers}: Use 'include <stdlib.h>' when appropriateElyes HAOUAS
Also, including <types.h>, is supposed to provide stdint and stddef. Change-Id: I99918a5a77e759bc7d4192d2c3fd6ad493c70248 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27src: Use 'include <boot/coreboot_tables.h>' when appropriateElyes HAOUAS
Change-Id: I3d90e46ed391ce323436750c866a0afc3879e2e6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36359 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-27cbmem.h: Align comment with the reality of implementationsArthur Heymans
cbmem_top() should simply not be called before memory is initialed, in order for the implementation to return something meaningful. Change-Id: I8fe32844af290626a0f91279143fda4d3442680f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Michael Niewöhner
2019-10-26drivers/intel/fsp2_0: move die() calls to the functionsMichael Niewöhner
Since there are no calls where we wouldn't die(), move die() calls into the fsp_find_* functions. Change-Id: I750a225999688137421bbc560d9d1f5fdf68fd01 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-26soc/intel: common,skl,cnl,icl: drop reserved mmio memory size calculationMichael Niewöhner
Remove the calculation of the Reserved Intel MMIO Memory size from systemagent and memmap, since it is not needed. The size is used in SA to calculate the space between cbmem_top and TSEG without DPR and Chipset Reserved Memory. Since this will always be equal to 0, the reservation will be skipped and TSEG, DPR and Chipset Reserved Memory will get reserved alltogether. By reading the code and pratical testing we figured out that: - TSEG - DPR - reserved - top_of_memory == 0 - TSEG - DPR - reserved == top_of_memory This means the whole block will never reserve anything because it is always 0. Hence the code can be removed for simplification. Tested successfully on X11SSM-F Change-Id: I0cc730551eb3a79c78a971b40056de8d029f4b82 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-26soc,mb/intel: clean up remaining FSP2.0 socs/boardsMichael Niewöhner
Remove CONFIG_...FSP2.0 based if-switches from FSP2.0-only socs/boards Change-Id: Iae92dc2e2328b14c78ac686aaf326bd68430933b Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36279 Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-26soc/intel/skylake: move/rename files after drop of FSP 1.1Michael Niewöhner
Follow-up commit where only files are moved and paths adapted to make review of the previous commit easier. Change-Id: Iff1acbd286c2ba8e6613e866d4e2f893562e8973 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35868 Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-26drivers/intel/fsp1_1: remove orphaned functionalityMichael Niewöhner
Remove orphaned functionality from the FSP1.1 driver that only has been used by skylake, which is now FSP2.0-only. Change-Id: I732f2d6846788d5c03647c6fb620e45b3b66de5f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36266 Reviewed-by: Michael Niewöhner Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-26soc/intel/skylake: drop support for FSP 1.1Michael Niewöhner
This drops support for FSP 1.1 in soc/intel/skylake, after all boards have been migrated to FSP 2.0, which is backwards compatible. Any moving of files happens in a follow-up commit to make review easier. Change-Id: I0dd2eab0edfda0545ff94c3908b8574d5ad830bd Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35813 Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-26mb/intel/saddlebrook: Enable serial port on SIOPraveen Hodagatta Pranesh
Enable saddlebrook board Serial port on SuperIO by selecting DRIVERS_UART_8250IO. TEST=Build, Boot saddlebrook board and verified serial logs. Change-Id: Ic7b3416f281bfd91416c987c5a720ffac0c89d45 Signed-off-by: Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner
2019-10-26mb/intel/saddlebrook: migrate to FSP 2.0Michael Niewöhner
This patch is part of the patch series to drop support for FSP 1.1 in soc/intel/skylake. The following modifications have been done to migrate the board(s) from FSP 1.1 to FSP 2.0: - remove deprecated devicetree VR_RING domain (only 4 domains in FSP 2.0) TODO: - testing Change-Id: I7481f3413de6780df01d9b769bd4f16d439f087c Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35923 Reviewed-by: Michael Niewöhner Reviewed-by: Wim Vervoorn Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25trogdor: Provide initial mainboard supportT Michael Turney
Change-Id: Ic2f0944b92dcad7048a0c38720d2ef3c855ef007 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-10-25mb/lenovo/{t60,r60}: Add ThinkPad R60 support as variant boardMaccraft
- This port should be Reclaim Your Freedom compliant (not certified yet). - Untested on boards with external Radeon graphics adapter. - Some columns on the left-most side of display are completely black on 1400x1050 IPS display[1]. Display works fine on Linux. I don't know why it appears like that. So far it has been observed only with native graphics initialization. - Only GRUB2 and SeaBIOS payloads tested for now. - 2504 docking station USB doesn't work under Linux. Can detect pendrive in GRUB2 payload. - Sometimes it takes 20s of "pretending it's powered off" to run coreboot code. Issue is payload agnostic. Probably caused by missing one capacitor on my unit. [1] https://imgur.com/a/0wpMGsm Change-Id: Ibd9208a5eafd228f8eedbc8fb4f4eb9ed1932a14 Signed-off-by: Maciej Matuszczyk <maccraft123mc@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-25soc/intel: Drop wrong _ADR objectsElyes HAOUAS
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID object or an _ADR object, but should not contain both." Change-Id: I09fce1298794f30c1db699438204ac32ee9cb27d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36296 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25src/mainboard: Drop wrong _ADR objectsElyes HAOUAS
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID object or an _ADR object, but should not contain both." Change-Id: I50cafce0aaf465ee95562ccff6c8f63fb22096c0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-25ec/{compal,google,quanta}: Drop wrong _ADR objectsElyes HAOUAS
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID object or an _ADR object, but should not contain both." Change-Id: If3ee38f3eaa8e6d1c1b0393d0ba289f708e0ae5e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36293 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25mb/lenovo/x201/smihandler: Remove mainboard_io_trap_handler functionPeter Lemenkov
An io_trap_handler on this board is unused in SMM. Change-Id: Ie922f8f1a10495ae887221735c96807261508041 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-25mb/*/*/smihandler: Remove bogus mainboard_io_trap_handlerPeter Lemenkov
These mainboard_io_trap_handler functions do nothing compared to a weak mainboard_io_trap_handler in src/cpu/x86/smm/. Change-Id: I73ebcc6c3f604a075a946503d51881ccc6820dac Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-25mb/lenovo/{t60,x201,x60}/smihandler: Remove SMM reinitializationPeter Lemenkov
Remove SMM reinitialization since it's already done in src/ec/lenovo/h8. Untested on a real hardware. See also commit 8953d4a1 with Change-Id I33fd829a7e34aefa8f76ca6020cc8e802f7aab17 ("mb/lenovo/*/smihandler: Get rid of mainboard_io_trap_handler"). Change-Id: Icc582527db15f3a31cdee8948bc5a190240fdc84 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-25mb/*/*/smihandler: Remove bogus SMM initPeter Lemenkov
I does nothing on these boards. It's just a call a local noop function which only prints a debug-level message. Change-Id: Id3fb2e9074db72d9025b95f7d4918417dd488b9e Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-25arch/acpi.h: Convert MADT APIC type names to all capsHimanshu Sahdev
Convert names to all capital in enum acpi_apic_types. Use of these names in corresponding type assign for I/O APIC Structure. Change-Id: Iab2f6d8f645677734df753f8bf59fde4205ce714 Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36197 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25arch/acpi.h: Use the aforementioned typedef acpi_table_headerHimanshu Sahdev
Use already declared typedef and modify the usage accordingly. Change-Id: Icf12ab9059be444fbe252b26e70214b1ef062c72 Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36194 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25mb/google/{glados,dragonegg}: Configure GPIOs in mainboard chip->init()Furquan Shaikh
mainboard_silicon_init_params() is supposed to be used for only overriding any FSP params as per mainboard configuration. GPIOs should be configured by mainboard as part of its chip init(). This ensures proper ordering w.r.t. any common operations that the SoC code might want to perform e.g. snapshot ITSS polarities. This change moves the configuration of GPIOs from mainboard_silicon_init_params() to mainboard chip->init(). Change-Id: I5d10c01c5b9d5f8ed02274d51dcf9c2a17269685 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36270 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25mb/google/{drallion,sarien}: Configure GPIOs in mainboard chip->init()Furquan Shaikh
mainboard_silicon_init_params() is supposed to be used for only overriding any FSP params as per mainboard configuration. GPIOs should be configured by mainboard as part of its chip init(). This ensures proper ordering w.r.t. any common operations that the SoC code might want to perform e.g. snapshot ITSS polarities. This change moves the configuration of GPIOs from mainboard_silicon_init_params() to mainboard chip->init(). Change-Id: I5cd89c6e24b6a4b0c20fd476915f3781a0d46e0d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36269 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25mb/google/{poppy,eve,fizz}: Configure GPIOs in mainboard chip->init()Furquan Shaikh
mainboard_silicon_init_params() is supposed to be used for only overriding any FSP params as per mainboard configuration. GPIOs should be configured by mainboard as part of its chip init(). This ensures proper ordering w.r.t. any common operations that the SoC code might want to perform e.g. snapshot ITSS polarities. This change moves the configuration of GPIOs from mainboard_silicon_init_params() to mainboard chip->init(). Change-Id: Ied0201b954894acd3503801e7739b91a2cc9b4a8 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36268 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25mb/google/hatch: Configure GPIOs in mainboard chip->init()Furquan Shaikh
mainboard_silicon_init_params() is supposed to be used for only overriding any FSP params as per mainboard configuration. GPIOs should be configured by mainboard as part of its chip init(). This ensures proper ordering w.r.t. any common operations that the SoC code might want to perform e.g. snapshot ITSS polarities. This change moves the configuration of GPIOs from mainboard_silicon_init_params() to mainboard chip->init(). Additionally, this change moves mainboard_ec_init() to mainboard dev->init(). TEST=Verified that GPIOs are configured properly and hatch boots to OS. Change-Id: Ia509471a3678c60454cd4f14625f151860d9b9d2 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36267 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25mb/google/hatch: Set DSM parameters for HeliosCheng-Yi Chiang
Set VPD keys for DSM parameters in overridetree.cb for Helios. RT1011 driver will load values from VPD and set them to device property. BUG=b:140397934 BRANCH=none TEST=On Helios, with patch series, check realtek,r0_calib and realtek,temperature_calib are available to rt1011 codec driver. Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org> Change-Id: Ic72fd57becf93e70a1a716dbb76633509f2fd5c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-10-25mb/google/hatch: Fix speaker mapping for HeliosCheng-Yi Chiang
The correct mapping for speakers to their names should be: uid 0: Woofer Left uid 1: Woofer Right uid 2: Tweeter Left uid 3: Tweeter Right Also, fix the name to be 4-character. BUG=b:140397934, b:143192767 BRANCH=none TEST=On Helios, with patch series, check realtek,r0_calib and realtek,temperature_calib are available to rt1011 codec driver. And the speaker mapping is correct. Change-Id: I353fb9ad0ca8ec85431eb2b59be748b4887278cf Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36256 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25src/vendorcode/intel: Update Comet Lake FSP headers as per FSP v1394Ronak Kanabar
"EnforceEDebugMode" UPD added in FSP_S_TEST_CONFIG Change-Id: I1583d8583db20b29505e5a7ae4084013334c87c2 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35852 Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24mb/google/hatch/var/akemi: Update DPTF thermal sensor for AkemiPeichao Wang
Add thermal sensor: TSR2 to ACPI table, monitor CPU temperature BUG=b:143046086 TEST=FW_NAME="akemi" emerge-hatch coreboot chromeos-ec chromeos-bootimage Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: Id150c5c3cb6d07407fd20417237457b5722e6f2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/36052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Philip Chen <philipchen@google.com>
2019-10-24soc/amd/picasso: Remove duplicate AMD_PUBKEY_FILE from KconfigJustin Frodsham
BUG=b:143229128 Change-Id: I03aa12b16979dc07869b0d33daedcde4fe84bc27 Signed-off-by: Justin Frodsham <justin.frodsham@amd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36281 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24src/include/console: Get rid of unused deprecated POST codesElyes HAOUAS
Change-Id: Id577b7c1421e9ffc3f51e90fcc9330c8f3be9a56 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36215 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-24mb/google/octopus: Override VBT selection for Dorp/Vortininja/VorticonTony Huang
Add enum for Vorticon sku. Vortininja/Vorticon will load vbt_vortininja.bin Dorp will load vbt_dorp.bin BUG=b:143197918 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage check i915_drrs_status shows DRRS supported NO when SKU-ID sets to Dorp/Vortininja/Vorticon. Change-Id: I67d7a8ab62a1838b0a0a05f532d8b067ece686d9 Cq-Depend: chrome-internal:2026287 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-10-24mb/google/{butterfly,link,parrot}: Drop wrong _ADR objectsElyes HAOUAS
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID object or an _ADR object, but should not contain both." Found-by: ACPICA 20191018 Change-Id: I8bcdfa7a4dc33c3e3866d3135249a602379b9615 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36265 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24src/ec/quanta: Drop wrong _ADR objectsElyes HAOUAS
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID object or an _ADR object, but should not contain both." Found-by: ACPICA 20191018 Change-Id: Iaa35790a38c36091a228007d739b970cb66a3e1c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36264 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24(acpi) superio.asl: Drop wrong _ADR objectsElyes HAOUAS
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID object or an _ADR object, but should not contain both." Found-by: ACPICA 20191018 Change-Id: Ic0bcaa37ac017ab61e1fb4e78d3c7dfbbcc0899d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-10-24ec/google/chromeec/acpi: Drop wrong _ADR objectElyes HAOUAS
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID object or an _ADR object, but should not contain both." Change-Id: Ieb54664a6528ce67634991f64a5f3c411822cdf4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36260 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24soc/intel/apollolake/acpi: Drop wrong _ADR objects for gpioElyes HAOUAS
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID object or an _ADR object, but should not contain both." Found-by: ACPICA 20191018 Change-Id: I9f55cc033b5672917520b139444bc614462c4a05 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-10-24soc/mediatek/mt8183: Add udelay after setting voltagesYu-Ping Wu
The SOC DRAM team suggested to delay at least 1us after setting new voltage in PMIC wrapper so the new value can be effective. BRANCH=kukui BUG=b:142358843 TEST=emerge-kukui coreboot Change-Id: I19d236769c3c0c87513ea4a0a3f64b83e3a844c2 Signed-off-by: Yu-Ping Wu <yupingso@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36254 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24mb/ocp/monolake: Configure IPMI BMC FRB2 watchdog timer via VPD variablesJohnny Lin
Add VPD variables for enabling/disabling FRB2 watchdog timer and setting the timer countdown value. By default it would start the timer and trigger hard reset when it's expired. The timer is expected to be stopped later by payload or OS. Right now the timer is started after FSP-M. Ideally it should be before FSP-M (to detect memory training error). Tested on OCP Mono Lake. Change-Id: I82b244d08380a0461c92662e025d8b95b3133e23 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-24drivers/ipmi: Add IPMI BMC FRB2 watchdog timer supportJohnny Lin
Add a function for initializing and starting FRB2 timer with the provided countdown and action values, and a stop function for stopping the timer. Tested on OCP Monolake. Change-Id: Ic91905e5f01b962473b6b3a9616266d2d95b1d6b Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-24mb/siemens/{mc_apl1, mc_bdx1}: Remove offsets from flashmap filesWerner Zeh
As fmaptool can now handle the offset computation for every mentioned region in the fmap file on its own there is no need to provide the offset in the fmd file anymore. This patch clears this out so that the files are way more readable now. Change-Id: I1dc841604fdb662e08cb6690ff4bf6dd311e01d8 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-26 18:28:34 +0000