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2019-08-11arch/x86: Enable POSTCAR_CONSOLE by defaultKyösti Mälkki
Almost all platforms force it on. Make it enabled by default but under user control to optionally disable it. Change-Id: I6b0f19c8bfd6ffed93023d57a1d28ca6acc06835 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-11vendorcode/eltan/security/lib: Add missing vb2ex_printf()Frans Hendriks
Build error on missing vb2ex_printf() in bootblock stage Add the file vboot_logic.c which contains the missing vb2ex_printf(). BUG=N/A TEST=Boot Linux 4.20 and verify logging on Facebook FBG-1701 Change-Id: I3f649f3faf1e812d592e4981bc75698e2cad1cc8 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
2019-08-11kohaku: add TEMP_SENSOR_3 and TEMP_SENSOR_4 to DPTFPaul Fagerburg
The Kohaku V24 schematic adds two additional temperature sensors to the EC. Add these to the DPTF tables. Cq-Depend: chromium:1742914 BRANCH=none BUG=b:138578073 TEST=Rebuild EC and BIOS, look for new thermal sensors in kernel. 1. Build EC ``cd ~/trunk/src/platform/ec`` ``make -j BOARD=kohaku`` 2. Program EC ``./util/flash_ec --board=kohaku`` 3. Reboot device 4. Rebuild BIOS ``cd ~/trunk/src/third_party/coreboot`` ``FEATURES="noclean" FW_NAME=kohaku emerge-hatch chromeos-ec depthcharge vboot_reference libpayload coreboot-private-files intel-cmlfsp coreboot-private-files-hatch coreboot chromeos-bootimage`` 5. Use flashrom to program the BIOS 6. Reboot device 7. Log into the root console (ctrl-alt-F2 or servo) 8. Example thermal sensor information ``grep . /sys/class/thermal/t*/type`` Look for "TSR0" through "TSR3" in the output. Change-Id: Ib8f38beae6392855927ce1249c229d7a114c72b2 Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34765 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-11mb/google/hatch: Fix Kohaku pen GPIO configurationTim Wawrzynczak
Oops, I missed this in the last CL. The pin needs to be configured as owned by GPIO, so that the kernel driver can bind it with an IRQ. BUG=b:139165490 TEST=Ensure kernel nastygram about inability to claim the IRQ is gone Change-Id: I26c08d75d8b4e3b834db6e90868239899605fa5b Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-10include, lib: Add <inttypes.h> printf macrosJacob Garber
In general, third party code (such as vboot) doesn't know what the underlying types are for the integers in <stdint.h>, so these macros are useful for portably printing them. Of these definitions, coreboot so far has only used PRIu64 (in one place), which isn't needed anymore since we know what the underlying type of a u64 is. Change-Id: I9e3a300f9b1c38e4831b030ff8af3fed2fa60f14 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-08-10mb/facebook/fbg1701: Select SOC_INTEL_COMMON_BLOCK_HDA_VERBFrans Hendriks
HDA is not configured. Enable SOC_INTEL_COMMON_BLOCK_HDA_VERB to configure the HDA using cim_verb_data[] table. BUG=N/A TEST=Boot Embedded Linux 4.20 on Facebook FBG-1701 Change-Id: I9bb542091ad200833894431f5b840f48dd388173 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34655 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-10mb/google/octopus: Add G2touch touchscreen supportWisley Chen
Add G2touch touchscreen support for Dorp/Vortinija/Vorticon. BUG=b:139110164 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage, and check touchscreen by evtest. Change-Id: Ia42757c881ec78b1c676ac984507732717af94a9 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-08-10src: Include <stdint.h> instead of <inttypes.h>Jacob Garber
The <inttypes.h> header currently does nothing but include the definitions from <stdint.h>, so let's #include that directly instead. Change-Id: I9d83ad37d0d7300a093001596ce3f0b3830c5701 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-08-10string: implement strspn, strcspn, atolYuji Sasaki
Change-Id: Id8fa880357124b620bde8884949bd8ffff7d0762 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-09soc/amd/picasso: Update i2c supportMarshall Dawson
Change the stoneyridge definitions into picasso. The named 0 and 1 buses are controlled by the PSP and not directly accessible by host firmware. I2C4 operates only in slave mode so is not added to to the bus clear-after-reset sequence. The I2C controller is fundamentally the same as on Stoney Ridge so the ability to clear a potentially jammed bus is still required. Program Picasso's new pad control registers in the MISC AcpiMmio space according to the recommended settings. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ibbc5504ebc36654e28c79fe3ae17cc0d9255118f Reviewed-on: https://review.coreboot.org/c/coreboot/+/33763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-09soc/amd/picasso: Update CPU supportMarshall Dawson
Change the Stoney Ridge ID to Picasso. Rename family 15h. Get the number of cores/threads from CPUID as all D18 registers are new. Change-Id: I44c45db637897f6caf320032c9f79a3a1ab4d6c9 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-09soc/amd/picasso: Reduce 48M out configurationMarshall Dawson
Picasso has only a single 48M output. Simplify the setup function. Note that while the feature is similar to older products, the register definition and Enable bit has changed. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Iebaf5219fdcd3145a4faf906f656a7fbdc7e0c36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-09soc/amd/picasso: Remove IOAPIC2Marshall Dawson
Remove the Family 15h device. It's not in Family 17h documentation and isn't detectable with HDT. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ifa9c06f78f39a3ec3b555d4ecc542172cd44a0b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33990 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-09soc/amd/picasso: Update SMI sourcesMarshall Dawson
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I42bb0edb6fa2c6fa92829ef5d3623483aa448a5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/33771 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-09soc/amd/picasso: Update machine check supportMarshall Dawson
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Iae48a0c3fb2abf2aa3fb78af8d50431c8533f76f Reviewed-on: https://review.coreboot.org/c/coreboot/+/33769 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-09src/amd/picasso: Update reset codeMarshall Dawson
Remove the scratch register indicators. Per AMD, AGESA no longer uses these. Use a new IO register to determine whether a warm reset should occur. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I0ff7935004b3d1ac5204d3ef575cfa98116a57fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/33989 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-09soc/amd/common: Add new GPIO 8K pull-up definitionMarshall Dawson
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: If24bed8b3f10d945b9988445025409c8420dd07a Reviewed-on: https://review.coreboot.org/c/coreboot/+/33762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-09src/soc/amd/picasso: Update GPIO configurationMarshall Dawson
Make the definitions match Picasso's definitions. Add/remove pins that differ from stoneyridge, update GEVENTs for the FCH mapping. Change-Id: I59f958151f27ed4ca0eb1a87ade6102eec1e5061 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-09src/vendorcode/intel: Update Cometlake FSP headers as per FSP v1263Aamir Bohra
Change-Id: Ia29769f1fc9947d9e37de2534c9486d21a4c9eae Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-09google/drallion: Fix build issue due to recent mergeKyösti Mälkki
One case slipped past the review and rebase of 733c28fa42 (soc/intel/{cnl,icl}: Use new power-failure-state API). Change-Id: Id01df30d10e202e9672bf5be799a84f4f202fe24 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34812 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-09cpu/x86/smm: Drop SMI handler address from structKyösti Mälkki
Change-Id: Ib925b11ba269e0f3a9a0a7550705bf2a6794c5b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-08-09amd/stoneyridge,picasso: Open TSEG earlierKyösti Mälkki
Don't make assumptions about which subregion will be accessed first. Change-Id: I558fa4acc5068014b3748be6fc1bc34999054c0a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34775 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-09soc/intel/common: Set power-failure-state via option tableNico Huber
Allow get_option() to override the Kconfig choice. Change-Id: Ie91b502a38d1a40a3dea3711b017b7a5b7edd2db Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-09soc/intel: Drop pmc_soc_restore_power_failure()Nico Huber
Get rid of this function and its dangerous, weak implementation. Instead, call pmc_set_power_failure_state() directly from the SMI handler. Change-Id: I0718afc5db66447c93289643f9097a4257b10934 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-09soc/intel/apl: Implement power-failure-state APINico Huber
Needed some Makefile changes to be able to compile for SMM. Change-Id: Ibf218b90088a45349c54f4b881e895bb852e88bb Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-09soc/intel/{cnl,icl}: Use new power-failure-state APINico Huber
pmc_soc_restore_power_failure() is only called from SMM, so add `pmc.c` to the `smm` class. Once all platforms moved to the new API, it can be implemented in a central place, avoiding the weak- function trap. Change-Id: Ib13eac00002232d4377f683ad92b04a0907529f3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34726 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-09soc/intel/skylake: Use new power-failure-state APINico Huber
Also move pmc_soc_restore_power_failure() which was guarded twice to not be included in SMM, where the only call lives. Once all platforms moved to the new API, it can be implemented in a central place, avoi- ding the weak-function trap. Change-Id: Ie72753764ecd876e6cb999fa0074d1114ae5efcf Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34725 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-09soc/intel/common: Implement power-failure-state handlingNico Huber
This is a consolidation of the respective feature in `soc/intel/*lake/`, including additional support for MAINBOARD_POWER_STATE_PREVIOUS. For the latter, firmware has to keep track of the `previous` state. The feature was already advertised in Kconfig long ago, but not implemented. SoC code has to call pmc_set_power_failure_state() at least once during boot and needs to implement pmc_soc_set_afterg3_en() for the actual register write. Change-Id: Ic6970a79d9b95373c2855f4c92232d2aa05963bb Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-09soc/mediatek/mt8183: Add display controller driverYongqiang Niu
The MT8183 SOC has a DISP (display controller) that supports overlay, read/write DMA, ... etc. The output of DISP goes to display interface DSI, DPI or DBI directly. Reference: MT8183 Application Processor Functional Spec, 6.1 Display Controller BUG=b:80501386,b:117254947 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Ic4aecc58d081f14f5d136b9ff8e813e6f40f78eb Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-09soc/mediatek/mt8173: Refactor display driver to share common partsHung-Te Lin
Move those will be shared by other MTK SOCs (for example, MT8183) to common/ddp.c. BUG=b:80501386,b:117254947 BRANCH=none TEST=Boots correctly on Oak Change-Id: Ie5709ab6e263caa21fdf7e799dc2ee884ffaf800 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-09soc/mediatek/mt8173: Remove dual DSI modeHung-Te Lin
The 'dual DSI mode' was never used by any real boards running coreboot and is introducing lots of complexity when it comes to refactoring. In order to create a common display stack for MTK SOCs, we want to first drop dual DSI mode so 8173 and 8183 DSI/DDP implementation will be more similar to each other. BUG=b:80501386,b:117254947 TEST=emerge-oak coreboot Change-Id: I357c30cc687803ca8045d0b055dec2e22eef4291 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34693 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-09mb/google/sarien/variants/sarien: Set PCH Thermal Trip point to 77 degree CSumeet Pawnikar
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal Shutdown when S0ix is enabled. BUG=None BRANCH=None TEST=Verified Thermal Device (B0: D20: F2) TSPM offset 0x1c [LTT (8:0)] value is 0xFE on Sarien. Change-Id: Ibc336be0523ff4e65a818474907faf20fc417ff4 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-09mb/google/sarien/variants/arcada: Set PCH Thermal Trip point to 77 degree CSumeet Pawnikar
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal shutdown when S0ix is enabled. BUG=None BRANCH=None TEST=Verified Thermal Device(B0: D18: F0) TSPM offset 0x1c [LTT (8:0)] value is 0xFE on Arcada. Change-Id: I1915b974b10638b0f6ab97c6fb9b7a58d2cabc59 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-09soc/nvidia/tegra210: Fix potential NULL pointer dereferenceTim Wawrzynczak
Recent Coverity scan indicated potential NULL deference; if either spi->dma_in or spi->dma_out are NULL, the fifo_error() check could dereference a NULL pointer. Also fixed what appears to be a logic bug for the spi->dma_out case, where it was using the todo (count) from spi->dma_in. Found-by: Coverity CID 1241838, 1241854 Change-Id: Icd1412f0956c0a4a75266d1873d5e9848aceee32 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34787 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-09cpu/x86 mp_init: Add option for AMD INIT SIPI sequenceMarshall Dawson
The common code adheres to the Intel requirement of bringing up the cores with INIT SIPI SIPI. This sequence is tolerated on some AMD AMD CPUs but fails on others. Add a way to skip the second SIPI. TEST=Mock up on grunt and verify no errors BUG=b:138919564 Change-Id: I201869003ddc7d04d332cd5734ac6d63979d89e0 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34759 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-09mb/google/hatch: Refactor override_early_gpio_tableTim Wawrzynczak
There was the potential for misuse of the override early GPIO table, because if the override early GPIO table did not have a corresponding entry in the base table, it would not get overridden, and there was no way to know except manual inspection (this has already happened here), so now all hatch mainboards are required to explicitly list out all of their required early GPIOs. TEST=booted several hatch boards, verified that they can communicate with TPM and successfully train memory Change-Id: I0552b08a284fd6fb41a09fef431a0d006b0cf0bd Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-08-09soc/intel/common/gspi: Use GSPI bus id to map to the controllerKarthikeyan Ramasubramanian
Currently SPI bus id is used to map to the controller in order to set the controller state. In certain platforms SPI bus id might not be exactly the same as GSPI bus id. For example, in Intel platforms SPI bus id 0 maps to fast spi i.e. SPI going to the flash and SPI bus id 1 .. n map to GSPI bus id 0 .. n-1. Hence using SPI bus id leads to mapping to the GSPI controller that is not enabled. Use the GSPI id bus so that the right controller is set to active state. This fixes the regression introduced by CB:34449 BUG=b:135941367 TEST=Boot to ChromeOS. Change-Id: I792ab1fa6529f5317218896ad05321f8f17cedcd Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-08-08arch/riscv: Enable FIT supportJonathan Neuschäfer
Tested on qemu-riscv. Depends on OpenSBI integration and proper memory detection in qemu. Boots into Linux until initrd should be loaded. Tested on SiFive/unleashed: Boots into Linux until earlycon terminates. Change-Id: I5ebc6cc2cc9e328f36d70fba13555386bb8c29d6 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30292 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-08vboot: fix conditional using vboot_setup_tpm return valueJoel Kitching
vboot_setup_tpm returns (TPM_SUCCESS == 0) on success. In this case, call antirollback_read_space_firmware. This regression was introduced in CB:34510. BUG=b:139101213 TEST=make clean && make test-abuild BRANCH=none Change-Id: Ifdea1d85167a50a1ada5afe9b107408e3a2e0d6f Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34790 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-08soc/intel/{APL, BSW, SKL}: Remove unused CPU_ADDR_BITS kconfigSubrata Banik
This patch removes CONFIG_CPU_ADDR_BITS kconfig from soc/intel/<soc>/Kconfig as not getting used anymore. Change-Id: Ie7fa386c9c0aae19da1fbd09407494d9812247a4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34768 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-08cpu/x86/mtrr: Replace CONFIG_CPU_ADDR_BITS with cpu_phys_address_size()Subrata Banik
This patch helps to generate correct MTRR mask value while using set_var_mtrr(). example: set_var_mtrr(1, 0x99000000, 16*MiB, WP) without CL : 0x0000000099000005: PHYBASE2: Address = 0x0000000099000000, WP 0x0000000fff000800: PHYMASK2: Length = 0x0000007001000000, Valid with CL : 0x0000000099000005: PHYBASE1: Address = 0x0000000099000000, WP 0x0000007fff000800: PHYMASK1: Length = 0x0000000001000000, Valid Change-Id: Ie3185dd8d4af73ec0605e19e9aa4223f2c2ad462 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34753 Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-08soc/intel: Fix SMRAM base MSRKyösti Mälkki
Previous setting was correct but assumed SMI handler is always located at the beginning of TSEG. Break the assumption. Change-Id: I5da1a36fc95f76fa3225498bbac41b2dd4d1dfec Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34730 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-08arch/x86: Handle smm_subregion() failureKyösti Mälkki
The callers don't necessarily check return value of function. Make sure the parameters are not left uninitialised in that case. Change-Id: Ic02db2d35b2ec88506320e7df609940de4aef005 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34708 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-08arch/x86: Change smm_subregion() prototypeKyösti Mälkki
Do this to avoid some amount of explicit typecasting that would be required otherwise. Change-Id: I5bc2c3c1dd579f7c6c3d3354c0691e4ba3c778e1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-08arch/x86: Move TSEG_STAGE_CACHE implementationKyösti Mälkki
This is declared weak so that platforms that do not have smm_subregion() can provide their own implementation. Change-Id: Ide815b45cbc21a295b8e58434644e82920e84e31 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-08lib/stage_cache: Refactor Kconfig optionsKyösti Mälkki
Add explicit CBMEM_STAGE_CACHE option. Rename CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM to TSEG_STAGE_CACHE. Platforms with SMM_TSEG=y always need to implement stage_cache_external_region(). It is allowed to return with a region of size 0 to effectively disable the cache. There are no provisions in Kconfig to degrade from TSEG_STAGE_CACHE to CBMEM_STAGE_CACHE. As a security measure CBMEM_STAGE_CACHE default is changed to disabled. AGESA platforms without TSEG will experience slower S3 resume speed unless they explicitly select the option. Change-Id: Ibbdc701ea85b5a3208ca4e98c428b05b6d4e5340 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-08vendorcode/eltan/security: Use config VENDORCODE_ELTAN_XXXFrans Hendriks
To avoid confusion use VENDORCODE_ELTAN_VBOOT and VENDORCODE_ELTAN_MBOOT config values. Include verfied_boot and mboot subdirectories as CPPFLAGS when measured boot or verified boot is enabled. This allows to generate binary with measured boot enabled only. BUG=N/A TEST=Boot Linux 4.20 and verify logging on Facebook FBG-1701 Change-Id: Iaaf3c8cacbc8d2be7387264ca9c973e583871f0a Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33442 Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-08drivers/ipmi: Add option to wait for BMCPatrick Rudolph
The BMC on Supermicro X11SSH takes 34 seconds to start the IPMI KCS, but the default timeout of the IPMI KCS code is just 100 msec. Add a configurable timeout option to wait for the BMC to become ready. As it only should boot very long after power on reset, it's not a problem on reset or warm boot. Tested on Supermicro X11SSH. The IPMI driver doesn't fail with a time-out any more. Change-Id: I22c6885eae6fd7c778ac37b18f95b8775e9064e3 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-08-08tpm/tspi: include vb2_sha for vb2_get_hash_algorithm_nameJoel Kitching
BUG=b:124141368 TEST=make clean && make test-abuild BRANCH=none Change-Id: I2e04c16e309d765353f152203a44e90d997394d1 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-08lib/edid: Add suport for display rotationNicolas Boichat
Sometimes the display native orientation does not match the device default orientation. We add a parameter to be passed to libpayload, which can then do the rotation. BUG=b:132049716 TEST=Boot krane, see that FW screen is orientation properly. Change-Id: I5e1d94b973a3f615b73eebe0ca1202ba03731844 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-08fsp_baytrail/fsp_broadwell_de: Sort entries in Makefile.inchcl-coreboot
Change-Id: I12e6ec4aec7dcadcbb886c3fc4c3b9126a0a835c Signed-off-by: Sourabh Kashyap <sourabhka@hcl.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-08-08mainboard/emulation/qemu-aarch64: Add new board for ARMv8Asami Doi
This CL adds a new board, QEMU/AArch64, for ARMv8. The machine supported is virt which is a QEMU 2.8 ARM virtual machine. The default CPU of qemu-system-aarch64 is Cortex-a15, so you need to specify a 64-bit cpu via a flag. To execute: $ qemu-system-aarch64 -M virt,secure=on,virtualization=on \ -cpu cortex-a53 -bios build/coreboot.rom -m 8192M -nographic Change-Id: Id7c0831b1ecf08785b4ec8139d809bad9b3e1eec Signed-off-by: Asami Doi <d0iasm.pub@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-07soc/amd/picasso: Set HAVE_BOOTBLOCK=nKyösti Mälkki
Change-Id: Iaf370e04adb04eb81555a57e81812ebe3339971d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-08-07mb/google/hatch: Kohaku: Re-setup dual-routing of EMR_GARAGE_DETTim Wawrzynczak
The pinctrl driver in the linux kernel automatically turns off SCI routing for all GPIOs exported via ACPI, so this patch sets up dual-routing of the EMR_GARAGE_DET signal so that one can be used for IRQs and one for the SCI wake. Change-Id: Iadeb4502c5a98a72ba651bdcad626609656c196f Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34780 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-07mb/google/hatch: Kohaku: Add touchscreen controller to device treeTim Wawrzynczak
The touchscreen controller was never added to the device tree, and the next board rev will have this IC connected. Set it up in the device tree with conservative power resource timings from the datasheet. BUG=b:138869702 BRANCH=none TEST=compiles; current board rev does not have touch IC Change-Id: I759fb32f31c8eee0e6bd664c6a82308354ef5d08 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-07mb/google/kohaku: Enable stylus pen deviceSeunghwan Kim
Enabling stylus pen device and pen_eject event. - Adding enable_gpio for power sequencing - Configuring GPP_H4 and GPP_H5 as native function - Adding PENH device node for pen ejection event BUG=b:137326841 BRANCH=none TEST=Verified pen input operation and pen_eject event (pop-up and wake from s0ix on pen ejection) Change-Id: Ic252a1f90c0fc6cb9b1e426d75a8b503824681f3 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-08-07intel/braswell: Drop config IED_REGION_SIZEKyösti Mälkki
Platform does not set up IED. Change-Id: Ied72888c6406b59332bc3d68eccb50bf1eab3419 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-07soc/amd: Rename smm_region_info() to smm_region()Kyösti Mälkki
Change-Id: I361fb0e02fd0bd92bb1e13fe84c898a1ac85aa40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34703 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-07intel/apollolake: Replace smm_region_info() with smm_region()Kyösti Mälkki
Implementation remains the same. Change-Id: I8483bb8e5bba66b4854597f58ddcfe59aac17ae0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-07cpu/x86/smm: Promote smm_subregion()Kyösti Mälkki
No need to limit these declarations to FSP. Both PARALLEL_MP_INIT smm_relocate() and TSEG_STAGE_CACHE can be built on top of this. Change-Id: I7b0b9b8c8bee03aabe251c50c47dc42f6596e169 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-07northbridge/intel: Rename ram_calc.c to memmap.cKyösti Mälkki
Use a name consistent with the more recent soc/intel. Change-Id: Ie69583f28f384eb49517203e1c3867f27e6272de Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-07intel/fsp_rangeley: Rename raminit.c to memmap.cKyösti Mälkki
Use a name consistent with the more recent soc/intel. Change-Id: I704d7cb637e4e12039ade99f57e10af794c8be97 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: David Guckian
2019-08-07intel/icelake,skylake,cannonlake: Drop unused parameterKyösti Mälkki
Change-Id: I0900c3b893d72063cc8df5d8ac370cf9d54df17a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-07soc/intel: Obsolete mmap_region_granularity()Kyösti Mälkki
Change-Id: I471598d3ce61b70e35adba3bd983f5d823ba3816 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-07opencellular/rotundu: Disable HAVE_ACPI_RESUME supportKyösti Mälkki
FSP1.0 has low memory corruptions below CONFIG_RAMTOP on S3 resume path, as romstage ram stack will be utilised before there is a chance to make the necessary backup to CBMEM. Previously done for intel/minnowmax in commit b6fc727. Change-Id: I2e128079b180f9978e8519b190648d516aaee0dc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34673 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-07intel/nehalem,sandybridge: Move stage_cache support functionKyösti Mälkki
Let garbage-collection take care of stage_cache_external_region() if it is no needed and move implementation to a suitable file already building for needed stages. Remove aliasing CONFIG_RESERVED_SMM_SIZE as RESERVED_SMM_SIZE and (unused) aliasing of CONFIG_IED_REGION_SIZE as IED_SIZE. Change-Id: Idf00ba3180d8c3bc974dd3c5ca5f98a6c08bf34d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34672 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-07mb/google/octopus: Add custom SAR value for VortininjaWisley Chen
Vortininja needs different SAR values than meep. Use sku-id to load SAR values. BUG=b:138261454 BRANCH=octopus TEST=build and verified SAR values by sku id Change-Id: I7b3ab51e1d6cada4faaba1b9d72bd9eacf6b04dd Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-08-07mediatek/mt8183: Add I2C driver codeQii Wang
This patch implements i2c driver for MT8183. BUG=b:80501386 BRANCH=none TEST=Boot correctly on kukui. Change-Id: I0a4d78b494819f45951f78e5a618021000cf3463 Signed-off-by: Qii Wang <qii.wang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30976 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-06lib: Throw an error when ramdisk is present but initrd.size is 0Asami Doi
It fails if you call extract() when ramdisk is present but initrd size is 0. This CL adds if-statement to throw an error when initrd size is 0. Change-Id: I85aa33d2c2846b6b3a58df834dda18c47433257d Signed-off-by: Asami Doi <d0iasm.pub@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-06src/mainboard/up/squared: Add Support for iTPMChristian Walter
Add support for the integrated TPM in Kconfig and update device tree. Change-Id: I3a51545c493674aeed9aef72db24f77315d033ce Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-08-06arch/x86/acpi.c: Change TPM2 ACPI Table to support CRBChristian Walter
Change the TPM2 ACPI Table to support CRB Interface when selected. Change-Id: Ide3af348fd4676f2d04e1d0b9ad83f9124e09dcc Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-08-06drivers/crb: Add support for PTTChristian Walter
When we use Intel Platform Trust Technologies, we need to verify that the enable bit is set before we use the integrated TPM. Change-Id: I3b262a5d5253648fb96fb1fd9ba3995f92755bb1 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-06security/vboot: Add Support for Intel PTTChristian Walter
Add support for Intel PTT. For supporting Intel PTT we need to disable read and write access to the TPM NVRAM during the bootblock. TPM NVRAM will only be available once the DRAM is initialized. To circumvent this, we mock secdata if HAVE_INTEL_PTT is set. The underlying problem is, that the iTPM only supports a stripped down instruction set while the Intel ME is not fully booted up. Details can be found in Intel document number 571993 - Paragraph 2.10. Change-Id: I08c9a839f53f96506be5fb68f7c1ed5bf6692505 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-06tegra210: Increase size of verstage due to overflowChristian Walter
When imlpementing changes in VBOOT, within the build process, tegra210 overflows into the romstage. Reduce the size of romstage from 104 to 100 and increase the size from verstage from 66 to 70. Change-Id: Ie00498838a644a6f92881db85833dd0a94b87f53 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34640 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-06soc/*: Report mp_init errorsPatrick Rudolph
* Increase log level from ERR to CRITICAL in run_ap_work(). * Print or return errors if mp_run_on_all_cpus() failed. Tested on Supermicro X11SSH-TF. Change-Id: I740505e3b6a46ebb3311d0e6b9669e7f929f9ab9 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-05mb/google/helios: Set SPKR_PA_EN PIN high for boot beepSubrata Banik
This patch makes SPKR_PA_EN PIN output and high for boot beep to work in pre-os environment. BUG=b:135104721 BRANCH=NONE TEST=Boot Beep is working with required ALC1011 depthcharge code changes. Change-Id: I012462f93e9e2bcafe5f18ce7d04e3fcd1db9ffa Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com>
2019-08-05mb/google/octopus: Add EMRight digitizer supportWisley Chen
The device Vortininja uses the variant meep, and supports WACOM/EMRIGHT digitizer. BUG=b:138276179 BRANCH=octopus TEST=verified that WACOM/EMRIGHT digitizer can works. Change-Id: I2bed4edb0261953f122f1d9ccca1fe4fa9406b33 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-08-05mb/google/drallion: Add new mainboardThejaswani Putta
Drallion is a new mainboard using Intel Comet Lake SOC. As a starting point, I took mainboard/sarien as the reference code and modified WHL to Comet Lake. BUG=b:138098572 Test=compiles Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com> Change-Id: I541952a4ef337e7277a85f02d25979f12ec075c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34497 Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-05soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOCAamir Bohra
This implementation adds support to provide list of LPSS controllers for a canonlake and icelake platforms. It implements strong function of get_soc_lpss_controllers defined under intel common block lpss driver. Change-Id: I36c87e2324caf8ed3e4bb3e3dc6f5d4edf3e8d46 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-08-05soc/intel/common/lpss: Add function to check for a LPSS controllerAamir Bohra
Add an API to check if device is a LPSS controller. This API can be used for IRQ assignments for LPSS PCI controllers, since the LPSS controllers have a requirement of unique IRQ assignments and do not share same IRQ# with other LPSS controllers. SOC code is reponsible to provide list of the LPSS controllers supported and needs to implement soc_lpss_controllers_list API, in case it needs to use this common implementation. Change-Id: I3f5bb268fc581280bb1b87b6b175a0299a24a44a Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34137 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-05mb/google/sarien: Increase Wacom touchscreen reset delay to 120 msCasper Chang
Increase reset delay to 120ms of touchscreen to meet wacom touchscreen T4 specification and resolve re-bind hid over i2c driver failed after touchscreen firmware auto update. BUG=b:132211627 TEST=Stress touchscreen firmware auto update 200 times and not found re-bind driver failed. Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I488660aefdc6df27077efc7fec2f3b99adbaef9f Reviewed-on: https://review.coreboot.org/c/coreboot/+/34665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mike Hsieh <mike_hsieh@wistron.corp-partner.google.com> Reviewed-by: Nick Crews <ncrews@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-08-05soc/intel/cnl/graphics: Hook up libgfxinitNico Huber
Change-Id: Ic038adad6cf76867cd4a8626d4c49e17018389fd Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-05drivers/intel/gma: Export Read_EDID() to CNico Huber
Change-Id: Icf802904c569e621ca3b3105b6107936776c5cee Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31458 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-05drivers/xpowers/axp209: Remove codeArthur Heymans
This code was only used by allwinner CPUs which is removed at this point. Change-Id: I31a2a502bffdc605cc31127723ed769b8665c314 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33170 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-05cpu/allwinner: Remove supportArthur Heymans
The Allwinner code was never completed and lacks a driver to load romstage from the bootblock. Change-Id: If2bae9e28a6e1ed6bfe0e9cb022ca410918cc4db Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33133 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-05mb/cubietech/cubieboard: Remove boardArthur Heymans
The Allwinner code was never completed and lacks a driver to load romstage from the bootblock. Change-Id: I12e9d7213ce61ab757e9317a63299d5d82e69acb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33132 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-05drivers/intel/gma: Enable Kabylake+ libgfxinit supportNico Huber
Kaby, Coffee and Whiskey Lake are all supported by the same code path in libgfxinit. TEST=Played Tint on clevo/kbl-u(n130bu). Change-Id: Ic911bda3dd62c4d37a1b74a87fb51adc6c9d6ad4 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31464 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-05soc/sifive/fu540: Add opensbi supportPatrick Rudolph
Tested on SiFive/unleashed: Boots into Linux until earlycon terminates. Change-Id: I35abacc16f244b95f9fd1947d1a5ea10c4dee097 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34142 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-04soc/intel/common/block/uart: Update the UART PCI device referenceAamir Bohra
This implementation revises the UART PCI device reference in common UART driver. The SOC functions have been aligned to provide the UART PCI device reference using pcidev_path_on_root. The uart_get_device() return type is changed, and files in which it gets used are updated. Change-Id: Ie0fe5991f3b0b9c596c3de9472e98e4091d7dd87 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-08-04drivers/fsp1_1/raminit: fix use of mrc_hobMatt DeVillier
Commit 509f469 [drivers/fsp1_1/raminit.c: Always check FSP HOBs] inadvertently made use of the mrc_hob conditional on CONFIG_DISPLAY_HOBS, when there is no relation between the two, leading to MRC cache data being corrupted. On some devices this caused RAM training to be redone, on others it resulted in a bricked device. Fix this by removing the condition on CONFIG_DISPLAY_HOBS. Test: boot google/{cyan,edgar}, observe third boot and onward do not brick device, properly use mrc_hob via cbmem console and timestamps. Change-Id: I01f6d1d6dfd10297b30de638301c5e0b6545da9c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34685 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-03intel/i945,gm45,pineview,x4x: Fix stage cache locationKyösti Mälkki
The cache is at the end of TSEG. As SMM_RESERVED_SIZE was half of TSEG size, offseting from the start gave same position. Change-Id: I2d5df90b40ff7cd9fde3cbe3cc5090aac74825f7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-03intel/i945,gm45,pineview,x4x: Move stage cache support functionKyösti Mälkki
Let garbage-collection take care of stage_cache_external_region() when it is not needed and move implementation to a suitable file already building for needed stages. Change-Id: Ic32adcc62c7ee21bf38e2e4e5ece00524871b091 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-03intel/baytrail,broadwell: Move stage cache support functionKyösti Mälkki
Let garbage-collection take care of stage_cache_external_region() when it is not needed and move implementation to a suitable file already building for needed stages. Change-Id: Ia6adcc0c8bf6d4abc095ac669aaae876b33ed0f3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34669 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-03intel/haswell: Move stage_cache support functionKyösti Mälkki
Let garbage-collection take care of stage_cache_external_region() if it is no needed and move implementation to a suitable file already building for needed stages. Remove aliasing CONFIG_RESERVED_SMM_SIZE as RESERVED_SMM_SIZE. Change-Id: Ie6fcc40fba14575e8ee058f45a1a359a05f00aca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-03mb/google/hatch/variants/helios: Adjust all I2C CLK and I2C0 SDA hold timeFrank_Chu
After adjustment Touch Pad CLK: 383.4 KHz Touch Screen CLK: 381.6 KHz Audio codec CLK: 386.0 KHz TouchPad SDA hold time: 0.325ns BUG=b:137722634 BRANCH=none TEST=emerge-hatch coreboot chromeos-bootimage Signed-off-by: Frank_Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I27dec2f3e00eb6618cc429aff3dae7a5d937d638 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-08-03mb/google/octopus: Add custom SAR values for droid/blorbSheng-Liang Pan
droid/blorb needs to use different SAR values than bobba. Use sku-id to load the SAR values. BUG=b:138091179 BRANCH=octopus TEST=build and verify SAR load by sku-id Change-Id: I71b5d69ffbba82018a682202df73b604332dd9e7 Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34542 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-03smbios: Make SMBIOS type 3 enclosure type settable at runtimeMathew King
smbios.h had already declared smbios_mainboard_enclosure_type so this change defines it. It can be overridden in a mainboard so the enclosure type can be set at runtime. We have a mainboard that will be used in different enclosures and we are planning on using a single BIOS image for all of the enclosures so it will need to be set dynamically based on sku. BUG=b:138745917 TEST=Built arcada firmware and verified via dmidecode that enclosure type is correctly set to "Convertible", then temporarily added a smbios_mainboard_enclosure_type to arcadas board file returning 0x20 and verified with dmidecode that the enclosure type is "Detachable" Change-Id: Iba6e582640989f5cb7e6613813e7b033760a977c Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-03mb/emulation/qemu-riscv: Add opensbi supportPatrick Rudolph
Tested on qemu-riscv: Boots into Linux until initrd should be loaded. Change-Id: I4aa307c91d37703ad16643e7f8eb7925dede71a8 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-08-03riscv: add support for OpenSBIXiang Wang
Call OpenSBI in M-Mode and use it to set up SBI and to lockdown the platform. It will also jump to the specified payload when done. This behaviour is similar to BL31 on aarch31. The payload is 41KiB in size on qemu. Tested on qemu-riscv: Required to boot a kernel as OpenSBI's instruction emulation feature is required on that virtual machine. Tested on SiFive/unleashed: The earlycon is working. No console after regular serial driver should take over, which might be related to kernel config. Change-Id: I2a178595bd2aa2e1f114cbc69e8eadd46955b54d Signed-off-by: Xiang Wang <merle@hardenedlinux.org> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-08-03mb/google/hatch: Enable PmTimerDisabled config to reduce S0ix power usageSubrata Banik
BRANCH=none BUG=b:138152075 TEST=Build for cometlake board with the PmTimerDisabled policy in devicetree set to 1. With PmTimerDisabled = 0 >> iotools mmio_read8 0xfe0018fc 0x00 With PmTimerDisabled = 1 >> iotools mmio_read8 0xfe0018fc 0x02 Bit 1: ACPI Timer Disable (ACPI_TIM_DIS): This bit determines whether the ACPI Timer is enabled to run. - 0: ACPI Timer is enabled - 1: ACPI Timer is disabled Change-Id: I83f49505a804c99d7978e5d541ea9fe8ead9b88f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-03 07:17:44 +0000