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2018-10-18tpm/tspi: clean up tpm_setup function flowJoel Kitching
Introduce two helper functions for more readable code. Use epilogue function instead of goto for error handling. BUG=None TEST=None Change-Id: Ibea44880683a301e82ee2ba049003c36fcb44eba Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/29026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-18cpu/x86/smm: Fix non-local header treated as localElyes HAOUAS
Change-Id: I15dfe0332fd87db61d692a94bf1fd5d00dfb83d4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-10-18src/{sb/intel,mb/google/auron}: Don't use device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: I564319506870f75eab58cce535d4e3535a64a993 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-10-18ec/google/chromeec: Use common MEC interfaceDuncan Laurie
Switch to using the common MEC interface instead of the Chrome EC specific code. Tested on a Chell chromebook that has a MEC based Chrome EC to ensure that the EC interface is still functional. Change-Id: Idf26e62c2843993c2df2ab8ef157b263a71a97c9 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-18ec/google/common: Add a common MEC interfaceDuncan Laurie
In order to re-use the MEC interface code in the Chrome EC driver move it to a common directory within the ec/google directory. The Chrome EC driver itself is changed to use this interface in the next commit, and future commits will introduce a new EC that also uses this interface. Change-Id: I13516b5e4c4c49f53bb998366284a26703142e2a Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-18mediatek/mt8183: Add EMI init for DDR driver initHuayang Duan
Add EMI config to initialize memory. BRANCH=none TEST=Boots correctly on Kukui, and inits DRAM successfully with related patches. Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: I945181aa1c901fe78ec1f4478a928c600c1b1dea Reviewed-on: https://review.coreboot.org/28835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-10-18mediatek/mt8183: Add register definitions of DRAM controllerTristan Shieh
Add register definitions of DRAM controller. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I8b51486deab856a783b87f0b2812a991d4111020 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/28668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-10-18mb: Fix non-local header treated as localElyes HAOUAS
Change-Id: Ib39305effdb00e032ca07e6d0e0d84cdf3dcf916 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-18mb: Replace MSR addresses with macrosElyes HAOUAS
Change-Id: I020431ba8eb61f5ce256088b919c049985331d64 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-18cpu/amd: Use common AMD's MSRElyes HAOUAS
Phase 1. Due to the size of the effort, this CL is broken into several phases. Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-18console: Set default loglevel to 8 (SPEW) for CONFIG_CHROMEOSJulius Werner
CB:26053 changed coreboot's default loglevel from SPEW to DEBUG. This may be the most reasonable choice for most users that are mostly interested in the UART console. However, on Chrome OS devices the UART is disabled for production configurations anyway, and instead they rely heavily on the CBMEM console for remote debugging and bug reports. For these kinds of cases more info is almost always better, and you can't easily reproduce a remotely filed bug if you notice that you need some info that is only provided by BIOS_SPEW. On the other hand, the cost of logging extra info to the CBMEM console is pretty negligible. Therefore, let's bump the loglevel for CONFIG_CHROMEOS in particular back up to the maximum. (Unfortunately, it seems that you can't 'select' a choice option from another option, so this has to go in the console/Kconfig file.) Change-Id: I50724e3f7f8f57fdbc5846f21babc71798b21b65 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/29144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-18soc/amd/stoneyridge: Replace double defined MISC MMIO reg. 0x40Richard Spiegel
Register 0x40 of miscellaneous MMIO is double defined, with different names, which makes it confusing. Eliminate MISC_MISC_CLK_CNTL_1, and move its only bit definition to MISC_CLK_CNTL1 (which is correctly placed among MMIO registers. BUG=b:117818431 TEST=Build grunt. Change-Id: I5ca5045498b8a81943282e0d6ecfbaecbd600d19 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-10-18soc/amd/stoneyridge: Remove double defined SPI100_SPEED_CONFIGRichard Spiegel
SPI100_SPEED_CONFIG is double defined. Bits and shift definitions on the first definition are unused. Remove first definition and its associated bits and shifts. BUG=b:117818430 TEST=Build grunt. Change-Id: I8175b9a2f379b47475a71f93096f682bc56d051c Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-18soc/amd/stoneyridge: Remove double definition for wideioRichard Spiegel
WIDEIO_RANGE_ERROR and TOTAL_WIDEIO_PORTS are defined twice. Remove the definitions within MMIO definitions, as wideio is not related to MMIO. BUG=b:117814228 TEST=Build grunt. Change-Id: I370a5b387b908fe7a840eb7579d45c1a6a9ca615 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-10-18soc/amd/stoneyridge: Remove DEV_D18F4 definitionRichard Spiegel
The definition DEV_D18F4 is only used once, in file tsc_freq.c, and is the same as SOC_PM_DEV. Remove the definition, and replace its use in tsc_freq.c with SOC_PM_DEV. BUG=b:117754424 TEST=Build and boot grunt. Change-Id: I9eeeaa084e5b16280713b8b833b4faa78d277586 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-10-18soc/amd/stoneyridge: Remove double defined GPIO MMIO basesRichard Spiegel
GPIO control a mux base addresses are defined within MMIO definitions and again bellow as GPIO specific base addresses. Eliminate those outside MMIO bases. Rename them to something indicating that they are both MMIO and related to GPIO. BUG=b:117754420 TEST=Build grunt. Change-Id: I53f7cf17d6267e6f8daa650b5f864bab688dc3f0 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29156 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-18amd/stoneyridge/include/soc: Re-arrange NB IOAPIC definitionsRichard Spiegel
There's no indication that they are accessed through D0F0. Add a D0F0 header and move IOAPIC definitions under it. The registers defined to be accessed through index/data pair should be indented relative to the index/data pair definition. BUG=b:117754786 TEST=Build grunt. Change-Id: If4fb6514bb13f1c944d0e1756d8d9de1f08c99f3 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29155 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-18soc/amd/stoneyridge/smi.c: Prefer using '"%s...", __func__'Richard Spiegel
In function smm_setup_structures(), the function name is used in a print string. Use __func__ instead. BUG=b:117642170 TEST=Build grunt. Change-Id: Icac5ea997289ef75fb246a09715cbca4442a57f4 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29154 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-18soc/amd/stoneyridge/southbridge.c: Change comparison orderRichard Spiegel
Comparison should place the constant on the right side. Southbridge.c has 6 instances where the opposite happens. Reverse the order of six comparisons to eliminate checkpatch warnings: WARNING: Comparisons should place the constant on the right side of the test BUG=b:117656929 TEST=Build grunt. Change-Id: I94f17b81f845fa94599f93c0be1144ffcb8e4165 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29153 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-18soc/amd/stoneyridge: Remove "else" after a returnRichard Spiegel
File smbus_spd.c has 2 instances of if()/else where the if tests for an error condition and returns just before the "else" statement. These "else" statements are not needed. BUG=b:117648025 TEST=Build and boot grunt. Change-Id: Ie8298773ae455dbb1125420ec65df24f3c65eb44 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29152 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-18drivers/intel/fsp*: Use newly added post codes for memory param prepFurquan Shaikh
This change replaces use of post codes 0x34 and 0x36 in fsp drivers to instead use POST_MEM_PREINIT_PREP_{START,END} to make it easy to search from where these post codes are generated during boot flow. Additionally, it adds POST_MEM_PREINIT_PREP_END to fsp2_0 memory_init to make it consistent with fsp1_1 memory init. Change-Id: I307ada1679f212c424e9f7ad2c9d254e24f41fd3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-18console/post_codes: Add post codes for memory param prep callbackFurquan Shaikh
This change adds two new post codes to indicate start and end of memory param preparation in callbacks to SoC/mainboard code: 1. 0x34: Start of memory preparation 2. 0x36: End of memory preparation These post codes are already used in coreboot. This change just ensures that the codes are defined in post_codes.h for easy lookup. These post codes are useful if SoC/mainboard decides to do a reset of the platform before returning back to memory initialization. Change-Id: I065518caedb7943d960a8a5c8708823b8eb3246d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-18intel/common/block: Fix issue found by klockworkJohn Zhao
src/soc/intel/common/block/pmc/pmclib.c Function acpi_get_sleep_type: Pointer ps checked for NULL may be dereferenced. BRANCH=None TEST=Built & booted Yorp board. Change-Id: I15fe39fd9f930be56d03c2ffe62fb6f17249d4b5 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/29149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-18mb/lenovo/*/romstage: Use macros instead of magic numbersPeter Lemenkov
Apparently coreboot still uses magic numbers instead of macros in some Lenovo mainboards. Let's use macros instead. Also removed FDD from l520 romstage (original value, 0x3c0c, means that FDD_LPC_EN was also enabled). Change-Id: I6468e3357f8eed434f8527a852e134380f486d9a Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/28976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-10-18soc/intel/skylake: Prevent disabling of TCONaresh G Solanki
In Skylake/Kabylake, if ACPI PM timer is disabled then TCO also gets disabled & vice versa. FSP default config for EnableTcoTimer is disabled, this caused ACPI PM timer & TCO to be disabled by FSP even when config PmTimerDisable = 0. Thus update FSPS UPD EnableTcoTimer in accordance to devicetree config PmTimerDisable. BUG=None TEST= Build for Soraka with PmTimerDisable=0 & check if TCO caused reboot after running shell command: cat >> /dev/watchdog0 Change-Id: Ia146761036c9dbaef3c02c9a7122ae3dcdef7bdd Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/29108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2018-10-18mb/lenovo/z61t: Add VBT-filePeter Lemenkov
This file was extracted directly from the vendor's firmware ver. 2.27. Change-Id: Ic2d2b259f3b535a791c9dcfdf962c03a0bab87a2 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-10-17soc/intel/cannonlake: Add CNP PCH-H gpio pin definitionspraveen hodagatta pranesh
- CNL PCH-H has 12 GPIO groups which are grouped under 5 gpio communities. - Add gpio pin definitions for CNP-H and related changes. - Add gpio device name, host software ownership reg offset for CNP-H. BUG: none TEST: build and flash, boot to windows and yocto os on both CFL RVP8 & RVP11 and verify power management, IO device functionalities work fine. Change-Id: I496ec059de125b97c646581bbd3b8bfe6ffa641e Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/28890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-17soc/intel/cannonlake: Add new cannon lake PCH-H supportpraveen hodagatta pranesh
Cannon lake PCH-H is added to support coffee lake RVP11 and coffee lake RVP8 platforms. - Add new device IDs for LPC, PCIE, PMC, I2C, UART, SMBUS, XHCI, P2SB, SRAM, AUDIO, CSE0, XDCI, SD, MCH and graphics device. - Add new device IDs to intel common code respectively. - Add CPU, LPC, GD, MCH entry to report_platform.c to identify RVP11 & RVP8. - CNL PCH-H supports 24 pcie root ports and 4 I2C controllers, hence chip.c is modified accordingly. - Add board type UserBd UPD to BOARD_TYPE_DESKTOP for both RVP11 & RVP8. BUG=None TEST=successfully boot both CFL RVP11 & RVP8, verified all the enabled devices are enumerated and cross checked devices ids in serial logs and UEFI shell. Change-Id: I4b6af88d467382250aecb4102878b1c5af92ccd4 Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/28718 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-17mb/intel/coffeelake_rvp: Add support for new coffee lake RVP8praveen hodagatta pranesh
- Add new mainboard variant coffee lake RVP8, which is CRB for coffee lake-s processor, support U-DIMM DDR4 memory module. - Modify cfl_h devicetree to enable IO devices, configure PCIE root port clock source, usb over current pin as per board schematics. - Select cannonlake PCH-H chipset config for both cfl_h & cfl_s. - Add GPIO table as per board schematics. BUG= None TEST= Build and flash, confirm boot into yocoto & windows OS on both cfl RVP11 & RVP8 platform. verified PCI, USB, ethernet, SATA, display, power functionalities. Change-Id: Iabd32eb43ee8e6b1a3993ba4e083a80c62485b14 Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/29066 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-17mb/lenovo/*/acpi: Store the requested state wake state for bluetooth and WWANPatrick Rudolph
L520 and T420 should also use it - platforms are very similar to t420s and t530. Z61t is based on T60/X60, X131e is based on X230 so commit with Change-Id I13c08b8c6b1bf0f3deb25a464b26880d8469c005 should be applied as well. All four platforms are using ec/lenovo/h8 embedded controller. Change-Id: Ib177f024871e82979dd430da86f1551aef14d446 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-17google/kukui: Configure USBTristan Shieh
Set up USB host controller. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Iec98f3dc1bbf3dda3d28dbefad15339d48608c7e Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/28788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-10-17mediatek/mt8183: Add USB supportJumin Li
This patch implements SoC-specific defines of mt8183 and links the common code to support USB. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I1224cf24f92b07f3c1814f1cbfef96aafa5a992b Signed-off-by: Jumin Li <jumin.li@mediatek.com> Reviewed-on: https://review.coreboot.org/28787 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Joel Kitching <kitching@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-17mediatek: Refactor USB code among similar SoCsTristan Shieh
Refactor USB code which will be reused among similar SoCs. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: I06fefb4149a489be991e13ddf624082d11e31765 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/28786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-17vboot: do not extend PCRs on resume from S3Joel Kitching
BUG=b:114018226,chromium:873099 TEST=compile coreboot Change-Id: I6840c45604535089fa8410f03c69702bec91218f Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/28750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-17tpm/tpm_setup: fail on invalid result from tlcl_resumeJoel Kitching
BUG=b:114018226 TEST=compile coreboot Change-Id: I8f5df2b0119d35e4000fe62bf1bba6ca07f925f3 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/28748 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-17soc/cavium/cn81xx: Drop dead do_soft_reset() implementationNico Huber
Change-Id: I85f357739220f16497f65df1bb317d9d6eb54d9f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-10-17arch/x86/exception: Improve the readability of a commentJonathan Neuschäfer
Add punctuation and fix a typo. Change-Id: Ic61c665f7e2daefb50b478a1710ea66c8a88235a Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-10-17mb/lenovo/t530: Fix double indentation in Kconfig.nameJonathan Neuschäfer
There is no need to indent these lines with two tabs. Change-Id: I2164f4e3ea48db8dc5242a55b0452782dae19a4b Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-10-17mb/*/*: Clean up FADT checksum assignmentJonathan Neuschäfer
The assignment of header->checksum was in some cases done twice, or unnecessarily split into two lines. Change-Id: Ib0c0890d7589e6a24b11e9bda10e6969c7d73c56 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-10-17mb/google/poppy/variants/nocturne: Disable pull-down of GPP_E9/E10Roy Mingi Park
While these pins were set to a pull-down 20KOhm, NPCX EC consumes ~2.1mW higher power. Becasue there was leakage current on both GPIO67 and GPIO70 from NPCX EC. With the external pull-up 10KOhm for USB_OC0#/USB2_OC1#, this wasn't enough to prevent leakage current. BUG=b:117139495 TEST=Check nxpc EC power to see power improvement Change-Id: I685d876461c263f07ca4c8f8046635cb7087279c Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-on: https://review.coreboot.org/29007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-17drivers/intel/fsp2_0: Add new config option to support FSP CARpraveen hodagatta pranesh
CPU_MICROCODE_CBFS_LEN and CPU_MICROCODE_CBFS_LOC configs pass the CPU microcode length and base address in CBFS to FSPT binary as init parameters. Add new config FSP_T_XIP in Kconfig, which is selected by platform config. If FSP_T_XIP is selected, then relocate FSPT binary while adding it in CBFS so that it can be executed in place. BUG= None TEST= Build for both CFL RVP11 & RVP8 and verified for successfull CAR setup. Change-Id: Ic46e0bb9ee13c38ff322979119c4813653c61029 Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/28985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-17mb/google/poppy/variants/nocturne: Tune DPTF settings for CPUSumeet R Pawnikar
Update CPU passive temperature threshold value from 70C to 80C, to avoid early throttling for spiky workloads. Also, change CPU throttling interval from 1 sec to 5 sec for CPU temperature. BUG=b:116400298 BRANCH=None TEST=Manual performance testing on nocturne. Change-Id: Ic5031a4aa16f750237565f4e4928e78834b1d686 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/29044 Reviewed-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-16mb/*/*/Makefile.inc: Remove acpi_tables.c from MakefilesPeter Lemenkov
It always included if ACPI is supported since commit 822bc65 with Change-Id I372dbd03101030c904dab153552a1291f3b63518 ("ACPI: Remove CONFIG_GENERATE_ACPI_TABLES"). Change-Id: If17a6f43e368ccf850031b349714fa1ec4d02c1d Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/28954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-10-15mb/google/poppy/variants/nami: Disable rear camera/DMIC for SyndraAmanda Huang
Since there are two cameras on Nami and only one camera on Syndra. We need to disable rear camera/DMIC on all Syndra sku. BUG=b:112876867 Change-Id: I92fb43ec84387c268ffdb6d0d34a5e5b13bcf50a Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-15mb/lenovo/*/smihandler: Remove some unused includesPeter Lemenkov
Tried to build all affected mainboards - still compiles fine. Change-Id: I385cac1a75cee13453b831bd75b3ecc7a6d229fa Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-15mb/lenovo/*/dsdt: Remove HAVE_LCD_SCREENPeter Lemenkov
This define is no longer used by anyone. It was removed everywhere else with commit with Change-Id I556769e5e28b83e7465e3db689e26c8c0ab44757. It seems that these two files were simply mislooked. So let's remove it. Change-Id: Ifbb62441e16e97c0cae0713968844e296619a880 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-15mb/asus/p5q_pro: Add mainboardArthur Heymans
This mainboard is quite similar to the p5qc. The main differences being a second PEG slot, the IDE slot and being DDR2 only. The following was tested: - both PEG slots populated (coreboot sets legacy VGA decoding on the GPU in the black slot) - USB - Ethernet NIC - PS2 Keyboard - COM1 - S3 resume Change-Id: I49a4bca4256e2a905aff3252eca76387c81152c1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/29102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-10-15drivers/net/atl1e: Add driverArthur Heymans
A shortcoming of this driver is that if multiple devices with the same PCI ID are present and don't have an eeprom, they would all get the same macadress set. The r8168 driver deals with such cases so it should be easy to implement if needed. Change-Id: I5c32df00e25453c350a45e7f1ee6834b89c4289f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-10-15mb/asus/p5qc: Add mainboardArthur Heymans
SeaBIOS does not seem to like the Marvel IDE controller, so disabled SeaBIOS support for ATA. It works fine in Linux afterwards. Working: - SATA on southbridge port - SATA on marvel IDE controller ports (only in Linux) - USB - COM1 - PS2 Keyboard - DDR2 DIMMs - PCIe x16 PEG port - PCI port - NIC (needs a driver to set macaddress) - S3 resume Not working: - SeaBIOS with ATA support (long timeout marvel controller so disabled) - DDR3 fails because the proper clock signal does not get enabled. Even when fixing this it fails later or during memtest, so it should be considered unsupported for now Untested: - PCIe x1 ports (expected to work) - sound (expected to work) TODO: add documentation Change-Id: I4a81940707566776bd048904ca1387fea741fece Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-10-15vc/google/chromeos/ec: remove EC hibernate in cr50 update pathAaron Durbin
More platforms are not able to hibernate under certain circumstances, such as when AC is plugged. This original path was conservatively put in to prevent potential damage when cr50-update-caused asynchronous resets occur. Julius' compelling argument that async resets from recovery mode requests should have enough coverage of the design over the course of project development. Remove the hibernate path and assume all is well going forward. Change-Id: I37121e75ff4e6abcb41d8534a1eccf0788ce2ea2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/29076 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-15nb/intel/x4x: Fix P45 CAPID max frequencyArthur Heymans
It looks like on the ASUS P5QC has 0 in this CAPID field while still supporting TCK_666MHZ. Change-Id: Id1a94d91434dbe782fcc56dad56fcaee4e78463b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/29101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-10-15sb/intel/i82801jx: Use macros for LPC_ENArthur Heymans
Change-Id: I4a9a9366c85206fa460519a26f48b3aada5bc7c3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/29100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-10-15nb/intel/x4x: Program read training results to all ranksArthur Heymans
While during the read training itself only the settings for rank 0 are used for all ranks, the controller does use the separate settings for each rank later on. It is unknown which register is responsible for this. The signals are probably not generated separately and therefore need to have the same settings for all ranks. Therefore program the results for all ranks instead of for all populated ranks. TESTED: Fixes DG43GT not booting with only the second DIMM slot of a channel populated. Change-Id: I7965a068ef4779847e62e966154764370c91302a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-10-14soc/amd/stoneyridge: Define PM USB Enable registerMarshall Dawson
Make #define definitions for PMxEF and replace the hardcoded values. Note that this doesn't change the current functionality of the source. The existing code has been propogated from the sb//hudson port, which seems to attempt to enable 100% of all OHCI and EHCI controllers that may be present in the system. Change-Id: I6018b0062730de19e3283a010144dfedc2b11423 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29075 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-14soc/amd/stoneyridge: Remove hudson EHCI debug controllersMarshall Dawson
Remove nonpreset controllers from the PCI device identifier function (ignoring any CONFIG_USBDEBUG_HCD_INDEX). The extra devices appear to be holdovers from the original sb/hudson source. TEST=Jam Makefile.inc to unconditionally build enable_usbdebug.c and verify proper BDF is returned in romstage and ramstage. Change-Id: I2e819d5e998922ad427c4a094c29a590f249a0d3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-14soc/amd/stoneyridge: Remove errant parenthesis in southbridge.hMarshall Dawson
Delete an unmatched opening parenthesis in the definition for the EHCI hub config register definition. This wasn't causing a problem unless EHCI debug was enabled. TEST=Jam Makefile.inc to unconditionally build enable_usbdebug.c and verify successful build Change-Id: I5f461d1573e416b5a8ee24329142e3c46b6a05e3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29073 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-14soc/amd/stoneyridge: Rearrange southbridge.h moreMarshall Dawson
Move the SPI base address register definition to D14F3. This was missed in: bba043 amd/stoneyridge: Rearrange southbridge.h Change-Id: Ia722339418c118bdf4b000bbf97ae4266e9b3be2 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-12drivers/intel/fsp2_0: Hook up IntelFSP repoPatrick Georgi
With https://github.com/IntelFsp/FSP/pull/4 merged, this allows using Intel's FSP repo (that we mirror) to build a complete BIOS ifd region with a simple coreboot build, automatically drawing in headers and binaries. This commit covers Apollolake, Coffeelake, Skylake, and Kabylake. Skylake is using Kabylake's FSP since its own is FSP 1.1 and Kabylake's also supports Skylake. Another candidate (given 3rdparty/fsp's content) is Denverton NS, but it requires changes to coreboot's FSP bindings to become compatible. Cannonlake, Whiskeylake require an FSP release. Change-Id: I8d838ca6555348ce877f54e95907e9fdf6b9f2e7 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/28593 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-12libpayload: arm64: Conform to new coreboot lib_helpers.h and assume EL2Julius Werner
This patch adds the new, faster architectural register accessors to libpayload that were already added to coreboot in CB:27881. It also hardcodes the assumption that coreboot payloads run at EL2, which has already been hardcoded in coreboot with CB:27880 (see rationale there). This means we can drop all the read_current/write_current stuff which added a lot of unnecessary helpers to check the current exception level. This patch breaks payloads that used read_current/write_current accessors, but it seems unlikely that many payloads deal with this stuff anyway, and it should be a trivial fix (just replace them with the respective _el2 versions). Also add accessors for a couple of more registers that are required to enable debug mode while I'm here. Change-Id: Ic9dfa48411f3805747613f03611f8a134a51cc46 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/29017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2018-10-12amd/stoneyridge: Fix PmControl register size in SMI handlerMarshall Dawson
The AMD implementation of this register is only 16 bits. Change the source accordingly. TEST=Suspend/Resume a Grunt several times Change-Id: Ib900468cc1c790fa7d57bb6faa91aee012173f7a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-12amd/stoneyridge: Rename CGPLL_CONFIG definitionsMarshall Dawson
Shorten the names in the MISC CGPLL_CONFIG, and make the formatting match the surrounding source. Change-Id: I71cf1ff6bd4bca7a25484b4da9388c17cfecc043 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-12amd/stoneyridge: Rename GppClkCntrl fieldsMarshall Dawson
Make the field names of the MISCx00 GPPClkCntrl more manageable by shortening their names. Make the definitions look more like the rest of the header file. Change-Id: I515cd664808e38851a7dbdba899df4fb9bbbcde6 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-12amd/stoneyridge: Rearrange southbridge.hMarshall Dawson
Group definitions so they're near others of the same type, e.g. PCI, AcpiMmio, etc. Change-Id: Ia6ef21431db0e758eba0ea043b54c036ec6235fe Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-12amd/stoneyridge: Remove dead GPIO definitionsMarshall Dawson
Delete definitions that are no longer used. Change-Id: I94c9c33f73c1a2d9308408e3e9ca526e876d6135 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-12amd/stoneyridge: Clarify XHCI_PM register definitionsMarshall Dawson
Change-Id: I1b44ffd7c0244b0408c3823d634a9b8d5038462f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-12amd/stoneyridge: Fix SPI_CMD_TRIGGER coding styleMarshall Dawson
Make the whitespace match surrounding lines and remove unnecessary parentheses. Change-Id: I2ed02494ba69237c38af61317e435d9575cefe1c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-12amd/stoneyridge: Convert hex definitions to lower caseMarshall Dawson
Match the rest of the soc/stoneyridge source. Change-Id: I4531e6dad0362be73499647d9fc93c168b6f163e Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-12amd/stoneyridge: Remove hudson register definitionsMarshall Dawson
Delete artifacts remaining from the original "hudson" and "yangtze" controller hub designs. Husdon devices had a configurable AcpiMmio base address, and a selection for I/O vs. MMIO decode. Modern products are fixed at 0xfed80000 in MMIO. Remove the flash control register definitions for the old generations. The manual reset register appears to not function as hudson. PMIO_DEBUG is named differently now, and not used, so remove its definition too. Change-Id: I6484bb2ca80b65318565dfee1a3368b121aea9de Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-11mb/google/poppy/var/nocturne: Provide override for ec eventinfoFurquan Shaikh
This change implements the callback to provide google_chromeec_event_info structure in nocturne variant and sets MKBP SCI based on board id. BUG=b:112366846,b:112112483,b:112111610 Change-Id: Ifcc10aefc8f450214bd64dfffaf8854ada43f323 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Enrico Granata <egranata@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-11mb/google/poppy: Allow variants to provide event info at runtimeFurquan Shaikh
This change adds a variant callback to read google_chromeec_event_info from variant at runtime to allow override of any events based on factors like board id. This callback is used in ramstage and smm to get google_chromeec_event_info structure for performing various actions like setting masks and logging wake events from EC. BUG=b:112366846,b:112112483,b:112111610 Change-Id: If89e904c92372530a0f555952f87702f068e0b03 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Enrico Granata <egranata@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-11ec/google/chromeec: Add support for querying ec board id in smm stageFurquan Shaikh
This change adds ec_boardid.c to smm stage, which is required to allow mainboards to query the ec to get board version in this stage. BUG=b:112366846,b:112112483,b:112111610 Change-Id: Iccbba96ebb94a12745a62cbfe3496f9e6f921e3d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Enrico Granata <egranata@chromium.org>
2018-10-11ec/google/chromeec: Get rid of __SMM__ guard for chromeec functionsFurquan Shaikh
There doesn't seem to be a reason why we would want to protect certain chromeec functions with __SMM__ guard. So, this change gets rid of it. If the functions remain unused, then they would be removed during linking. Change-Id: I8196406074b01fe8ea15173c55d45bb86384be1b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29006 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Enrico Granata <egranata@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-11src: Move common IA-32 MSRs to <cpu/x86/msr.h>Elyes HAOUAS
Use "cpu/x86/msr.h" for common IA-32 MSRs and correct IA-32 MSRs names. Change-Id: Ida7f2d608c55796abf9452f190a58802e498302d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28752 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-11src: Replace MSR addresses with macrosElyes HAOUAS
Change-Id: I849dd406f5ccc733d4957eaf1c774745782f531a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-10-11amd/stoneyridge: Indicate STAPM units in their nameRichard Spiegel
STAPM devicetree registers do not indicate the unit, which causes confusion. More importantly, the time was assumed to be in seconds when it's actually milliseconds. This caused early STAPM configurations to fail. BUG=b:117590953 TEST=Build grunt Change-Id: I2a7e3d43601992d1f7b02456913c763d940fe9ee Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29035 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-11mainboard/google/kahlee: Set PSPP setting to BalanceLowAkshu Agrawal
With correct stapm values audio issue is not observed with PsPPBalanceLow (Gen1 speed). BUG=b:117569918 TEST=audio playback multiple times Change-Id: Iaeae52b262b12622a6753432e3fc40bf5f0fd8e0 Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/29028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-10-11mb/google/kahlee: Set stapm parameters with time value fixedAkshu Agrawal
stapm_time passed to smu via agesa is in msec. With earlier value smu was getting stapm_time as 2.5 sec instead of 2500 sec and thus causing issue in S3, and audio in PsppBalanceLow state. BUG=b:117569918, b:117252463 TEST= 1.) audio works with PsppBalanceLow 2.) S3 cycles Change-Id: I673e7e673d042918dff47141f37bbca354f5c45c Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/29027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-10-11selfboot: remove bounce buffersRonald G. Minnich
Bounce buffers used to be used in those cases where the payload might overlap coreboot. Bounce buffers are a problem for rampayloads as they need malloc. They are also an artifact of our x86 past before we had relocatable ramstage; only x86, out of the 5 architectures we support, needs them; currently they only seem to matter on the following chipsets: src/northbridge/amd/amdfam10/Kconfig src/northbridge/amd/lx/Kconfig src/northbridge/via/vx900/Kconfig src/soc/intel/fsp_baytrail/Kconfig src/soc/intel/fsp_broadwell_de/Kconfig The first three are obsolete or at least could be changed to avoid the need to have bounce buffers. The last two should change to no longer need them. In any event they can be fixed or pegged to a release which supports them. For these five chipsets we change CONFIG_RAMBASE from 0x100000 (the value needed in 1999 for the 32-bit Linux kernel, the original ramstage) to 0xe00000 (14 Mib) which will put the non-relocatable x86 ramstage out of the way of any reasonable payload until we can get rid of it for good. 14 MiB was chosen after some discussion, but it does fit well: o Fits in the 16 MiB cacheable range coreboot sets up by default o Most small payloads are well under 14 MiB (even kernels!) o Most large payloads get loaded at 16 MiB (especially kernels!) With this change in place coreboot correctly still loads a bzImage payload. Werner reports that the 0xe00000 setting works on his broadwell systems. Change-Id: I602feb32f35e8af1d0dc4ea9f25464872c9b824c Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/28647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-11tegra124_lp0: make sure to build with compiler.h includedPatrick Georgi
Fixes builds of that binary in clean trees. Change-Id: If5a995449a74c00da836fcf22bda44ebc8197518 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/28994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-10-11commonlib/storage: Make pci sdhci code compile in romstageBora Guvendik
In romstage malloc is not available, so use CAR_GLOBAL variable instead. BUG=b:78106689 TEST=Boot to OS Change-Id: If9438d0b707c6ffaa61db80bd1d385112bc91cfc Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/25067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-11riscv: add physical memory protection (PMP) supportXiang Wang
These codes are written by me based on the privileged instruction set. I tested it by qemu/riscv-probe. Change-Id: I2e9e0c94e6518f63ade7680a3ce68bacfae219d4 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/28569 Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-11soc/intel/common/block/gpio: check for NULL using if statementBora Guvendik
Remove assert() and instead use if statement to check if comm->groups is NULL. Found-by: klockwork BUG=None TEST=Boot to OS Change-Id: I85a6bc700b52d04c61ca8f2baac62000f40cf2cb Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/28940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-11mb/google/octopus: I2C clock tuning for meepWisley Chen
Tune I2C params for I2C buses 0, 5, 6, and 7 to ensure that the frequency does not exceed 400KHz. BUG=b:117298114 TEST=emerge-octopus coreboot chromeos-bootimage and measured frequency under 400 KHz Change-Id: Id608aae7edf54a24f364606dd7952521d1d67c1a Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/29021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-11mb/cavium/cn8100_sff_evb: Only expose two UARTsPatrick Rudolph
Only two UARTs are connected to the FTDI UART USB chip. Change-Id: Id5ae7266ce44c9f64c7f7aeaf23c49122041f47a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/28986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-10soc/intel/skylake: Set PCIEXPWAK_DIS if WAKE# pin is not enabledFurquan Shaikh
This change sets PCIEXPWAK_DIS in PM1_EN register if WAKE# pin is not enabled on the platform. This is required to prevent unnecessary wakes if the WAKE# pin remains not connected on the platform. Function to set PCIEXPWAK_DIS gets called in normal boot path (BS_PAYLOAD_LOAD) as well as S3 resume path (BS_OS_RESUME). BUG=b:117284700 TEST=Verified that no spurious wakes are observed on nocturne. Change-Id: Iea93baffc9bb703c0ffedacafc6a9a9410c7ebfe Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-10-10mb/google/octopus: Drop I2C bus 0 clock frequency for Phaserpeichao.wang
Need to tune I2C bus 0 clock frequency under the 400KHz since this bus attached the Stylus EMR pen and need meet the spec. Bug=b:117297214 TEST=flash coreboot to the DUT and measure I2C bus 0 clock frequency whether under 400KHz Change-Id: I06d9d25f52d7f641d937de0d6b7df3d7a076fbf9 Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28973 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-10lib: increase part number size in memory_info/dimm_infoAaron Durbin
The dimm_info and memory_info structs are used in devices that don't strictly use DIMMs. Those platforms have the DRAM soldered down so there's no DIMM part number that encapsulates the DRAMs used in the DIMM. The full part number is desired to be exposed in the SMBIOS tables. As such extend DIMM_INFO_PART_NUMBER_SIZE to 33 to accommodate longer part numbers 'MT53B256M32D1NP-053 WT:C' is one of the longer part numbers that are desired to be maintained. BUG=b:115697578 Change-Id: I0c39dd1d1c2f0776d70d8c4d8d56719779ff82ae Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/28978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-10soc/cavium: dynamic UART initialization for cavium cn8100Jens Drenhaus
Now only those UARTs that are enabled in devicetree.cb are initialized. Tested on Opencellular Elgon. Change-Id: I145c224148f0cc078bb1c76f588f603e73121a62 Signed-off-by: Jens Drenhaus <jens.drenhaus@9elements.com> Reviewed-on: https://review.coreboot.org/28975 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-10-10mb/google/poppy/variants/nami: Add samsung_dimm_K4AAG165WB-MCRC SPDChris Zhou
Add SPD file for sdp samsung_dimm_K4AAG165WB-MCRC (ram id: 9) BUG=b:112679174 TEST=emerge-nami coreboot chromeos-bootimage Change-Id: Iac1e3ca4b009cc9be94608cd342f535fa581a5eb Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28974 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-10mb/google/kahlee/variants/*/devicetree.cb: Reset I2C slavesRichard Spiegel
Use the new I2C slave reset function and reset all slaves connected to all 4 I2C. Do this in all boards. BUG=b:114479395 TEST=Added debug code. Build and boot grunt. Examined output, confirmed GPIO pins changing as required. Removed debug code. Change-Id: Ia78ee5d5319d3c1a7daa9c56c81d435999b3a359 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28575 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-10soc/amd/stoneyridge/gpio.c: Create I2C slave reset codeRichard Spiegel
AMD's SOC do not wait for I2C transactions to complete before executing a reset. Because of this, it's possible for the reset to happen in the middle of a transaction, resulting on a slave hang. There are 2 possible solutions: If the slave has a reset pin connected to a GPIO pin, it can be used to reset the slave, else the only solution is to bang SCL 9 times. Create code that makes it easy to implement SCL bang, using a devicetree register to define which I2C SCL lines needs to be reset. BUG=b:114479395 TEST=Build and boot grunt. Look at transactions on a scope. Change-Id: I7f74b7e45c509044825355874753969f074e2382 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28574 Reviewed-by: Daniel Kurtz <djkurtz@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-10mb/google/kahlee: Add delan variantMartin Roth
BUG=b:117173908 TEST=Build delan Change-Id: If149b8c43ff16637c38d5320eb606bb72d62e953 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/28972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-10-10mb/google/fizz: Prepare sharing directory for variantsDavid Wu
Clean up Kconfig file in order to support variants for fizz. Add BOARD_GOOGLE_BASEBOARD_FIZZ that can be set by various fizz variants to use the common baseboard configs. BUG=b:117066935 BRANCH=Fizz TEST=emerge-fizz coreboot Change-Id: I9c89f1dc526a9d623e1ae4d4b52a923489b389d3 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-10mediatek/mt8183: Init PLLs for DRAMTristan Shieh
Set up DRAM related PLLs. And update post divider table to fulfill all freqency settings. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Ic197cef7d31f75ffe4e7d9e73c9cc544719943ab Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Reviewed-on: https://review.coreboot.org/28667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com>
2018-10-09soc/intel/cannonlake: Add PCIE ASL entrySubrata Banik
This patch creates _PRT entires for each PCIE root port devices. TEST=Able to see PCIE wake device in cat /proc/acpi/wake list Change-Id: I183c89c92139e15e0bfc39620710dbdc6597b351 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-09soc/intel/cannonlake: Make correct IRQ mapping for CNL SA and PCH PCI devicesSubrata Banik
This patch provides option for PCI IRQ mapping in both PIC and APIC mode. TEST=Build and Boot on CNL RVP. Change-Id: Ie26750ac9dc2ce940b0c116085c041de439075df Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-09soc/intel/common/acpi: Fix ACPI Namespace lookup failure, AE_ALREADY_EXISTS ↵Subrata Banik
issue This patch fixes below ACPI compilation issue: Found 1 external control methods, reparsing with new information Pass 1 parse of [DSDT] ACPI Error: [EPCS] Namespace lookup failure, AE_ALREADY_EXISTS (20160318/dsfield-660) ACPI Error: [EMNA] Namespace lookup failure, AE_ALREADY_EXISTS (20160318/dsfield-660) ACPI Error: [ELNG] Namespace lookup failure, AE_ALREADY_EXISTS (20160318/dsfield-660) Pass 2 parse of [DSDT] ACPI Warning: NsLookup: Type mismatch on EPCS (Integer), searching for (RegionField) (20160318/nsaccess-664) ACPI Warning: NsLookup: Type mismatch on EMNA (Integer), searching for (RegionField) (20160318/nsaccess-664) ACPI Warning: NsLookup: Type mismatch on ELNG (Integer), searching for (RegionField) (20160318/nsaccess-664) Parsing Deferred Opcodes (Methods/Buffers/Packages/Regions) TEST=Able to build sgx.asl without any ASL error. Change-Id: If4e7d4c66b6aab6c081fa272d8c2c9a1f0651ef7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-09soc/intel/common/block/pcr: Add NULL pointer check in pcr_execute_sideband_msg()Subrata Banik
This patch to fix KW issue due to msg, data and response pointers NULL check fail. Change-Id: I39324514079f240ba1683a04e579de85485299bf Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-09soc/intel/cannonlake: Disable Legacy PME for Root portsSubrata Banik
Legacy PME are enabled by default in FSP-S UPD. This policy sets PME Interrupt Enable (PIE) bit of RCTL register to trigger interrupt generation when RSTS.PS state has changed (either due to 0->1 transition or due to this bit being set with RSTS.PS already set). Due to this interrupt generation, system wakes from sleep immediately it enters. This patch overrides root port legacy pme upd policy from coreboot to ensure no false SCI is triggerd when system is in S3/S0ix state. BUG=b:113083354 BRANCH=none TEST=Able to make S3 resume using wake on wifi connect/disconnect usecase without any failure. Change-Id: I779fac711eeeed65ea379fad1cc400052d8a00eb Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-09soc/intel/cannonlake: Ensure FSP don't override ITSS IPCx registersSubrata Banik
This patch save and restore ITSS IPCx register before and after FSP-S call. Change-Id: Iea9356b4404d2fa49ea62ef7bc2c72f125054ff3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28792 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-20 14:09:16 +0000