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2013-12-07haswell: VR controller configurationAaron Durbin
Configure the VR controller. This enables the PSIx levels as well as C-state ramping. PSIx thresholds are: - PSI3: 1A. - PSI2: 5A. - PSI1: 15A. Before: 0x601 0x0000000000000100 0x603 0x0036000000262626 0x636 0x000000000000006f After: 0x601 0x4010140f00000100 0x603 0x0036000000262626 0x636 0x000000000000006f Change-Id: I6958845ac4164ebd0f1bb2d6d9be55ba63ed9344 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/60931 Reviewed-by: Sameer Nanda <snanda@chromium.org> Reviewed-on: http://review.coreboot.org/4338 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2013-12-07Add kernel-derived support functions for DDI.Ronald G. Minnich
Newer mainboards that use haswell -- and, presumably, chipsets to come -- need some support functions. Add them in the drivers/intel/gma directory. Currently, this is one file: intel_ddi.c, but more may come. Compilation of this file is controlled by INTEL_DDI, defined in the Kconfig as default n and used in the Makefile.inc Change-Id: I501ee291c0d4589925ed3e478f67106337fcad31 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/60612 Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/4337 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-07haswell: Add ACPI support for Controllable TDPDuncan Laurie
Add ACPI Methods to enable and disable power limiting with PL1. This can be used in ACPI Thermal Zone or in EC ACPI _QXX events. This commit adds new unused methods and is fully tested with the subsequent commit that makes use of these methods. Change-Id: I9d8d23bfe9cf7c756ff8ab0412e5a010826b12db Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/60546 Reviewed-on: http://review.coreboot.org/4334 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2013-12-07haswell: Misc power management setup and fixesDuncan Laurie
1) fix enable of power aware interrupt routing 2) set BIOS_RESET_CPL to 3 instead of 1 3) mirror PKG power limit values from MSR to MMIO on all SKUs 4) mirror DDR power limit values from MMIO to MSR 5) remove DMI settings that were from snb/ivb as they do not apply to haswell 1) verify power aware interrupt routing is working by looking in /proc/interrupts to see interrupts routed to both cores instead of always to core0 BEFORE: 58: 4943 0 PCI-MSI-edge ahci AFTER: 58: 4766 334 PCI-MSI-edge ahci 2) read back BIOS_RESET_CPL to verify it is == 3 localhost ~ # iotools mmio_read32 0xfed15da8 0x00000003 3) read PKG power limit from MMIO and verify it is the same as the MSR value localhost ~ # rdmsr 0 0x610 0x0000809600dc8078 localhost ~ # iotools mmio_read32 0xfed159a0 0x00dc8078 localhost ~ # iotools mmio_read32 0xfed159a4 0x00008096 4) read DDR power limit from MSR and verify it is the same as the MMIO value (note this is zero based on current MRC input) localhost ~ # rdmsr 0 0x618 0x0000000000000000 localhost ~ # iotools mmio_read32 0xfed158e0 0x00000000 localhost ~ # iotools mmio_read32 0xfed158e4 0x00000000 Change-Id: I6cc4c5b2a81304e9deaad8cffcaf604ebad60b29 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/60544 Reviewed-on: http://review.coreboot.org/4333 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2013-12-07peppy: Enable power limiting for thermal controlDuncan Laurie
Limit power to 12W at 73C and remove limit at 68C. To have the CPU consume maximum power it is necessary to stress both the CPU and the GPU. Bastion (chrome.supergiantgames.com) and/or webglsamples.googlecode.com can be useful for this. Testing this properly requires a script to report the running average power readings. The watch_power.sh script is attached to this issue in the partner tracker. 1) Run watch_power.sh continuously: localhost ~ # watch -n 0 bash -e /tmp/watch_power.sh 2) Start Bastion (or other stress apps). The power draw should be close to 15W if under enough load. 3) Watch until temperature climbs above 73C and is caught by the thermal zone 10 second poll, this can be sped up by blocking or removing the fan. 4) The ACPI thermal zone states should change to reflect that active[2] is now enabled and power consumption should drop to 12W. 5) Stop the stress apps and wait until the CPU cools off again, enable the fan again if it was removed. 6) The ACPI thermal zone state should switch back to active[3]. Change-Id: Ie6714a8543d4f06edf8513086fc9c968273bdb23 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/60545 Reviewed-on: http://review.coreboot.org/4335 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-07elog: handle ROM_SIZE differences from detected flash sizeAaron Durbin
The elog code calculates flash offsets and their equivalent addresses in the memory address space. However, it assumes the detected flash size is entirely mapped into the address space. This can lead to incorrect calculations. Add code to allow ROM_SIZE to be less than detected flash size. The underlying assumption is that the first ROM_SIZE bytes are programmed into the larger device. Change-Id: Id848f136515289b40594b7d3762e26e3e55da62f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/60501 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4332 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-07Correct file permissions.Idwer Vollering
Some files have incorrect/odd permissions, correct them: remove unnecessary +x flags. Change-Id: I784e6e599dfee88239f85bb58323aae9e40fb21c Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/4490 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-12-07src/vendorcode/amd: remove Visual Studio remnants.Idwer Vollering
Delete files that (were overlooked and) are probably needed to build with Visual Studio. Remove doxygen helper files as well. Change-Id: I6b6cece178917ad9da1081eb6b1bb9be33066a77 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/4489 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-12-06arch/x86: Do not run UPDATE-FIT if we don't include microcodeAlexandru Gagniuc
The original intention was to only run UPDATE_FIT when a microcode file was included in CBFS. This happens when either CPU_MICROCODE_CBFS_GENERATE or CPU_MICROCODE_CBFS_EXTERNAL is selected, however, the makefile checked that CPU_MICROCODE_IN_CBFS was selected instead. The end result was that on hasswell, the UPDATE-FIT step was always run, even when no microcode was included, generating a build error. Instead, introduce a new variable which tells if a microcode update is added in CBFS during the build. Change-Id: I28638912ed6f77761ef8a584f7636dc907b7a9b7 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4480 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-12-06usbdebug: Hide irrelevent options from menuconfigKyösti Mälkki
No need to show the choice of USB port or controller in case of older hardware where location for usbdebug was hardwired. Change-Id: Ia186bf2c6ed60be2834cf6fd0a1965c8bf81ed4d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4290 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-06butterfly: Fix build without ChromeOSKyösti Mälkki
Use a file in CBFS for keyboard layout and ethernet MAC instead of scanning FMAP. Change-Id: I7658c7c4e389deb20d7d8f57cce8b568efdc575d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4307 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-06qemu: fix GENERATE_ACPI_TABLES=n in fw_cfg.cGerd Hoffmann
Change-Id: Ib8dc069c9e503747c349e96a466feb42279afd08 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/4305 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-06Add in the Makefile bits for the new intel gma driverRonald G. Minnich
The Intel GMA driver is in, this CL splices in the Makefile bits. Change-Id: Icf42a537575b8cc90a679ec1fc15b09294630611 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/60346 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/4331 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-05FUI: add intel_dp driver derived from kernel functionsRonald G. Minnich
These functions are not all used yet, but do compile and are partially used in the FUI testing. They were extracted from the 3.4 kernel using coccinnelle filters. The .c files are only compiled in if CONFIG_INTEL_DP is set. Change-Id: Id95622a75aa02b496c9ea4717cb143394a8332e3 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/60245 Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4329 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-05haswell: pull in the init code for FUIRonald G. Minnich
Removed two unnecessary register sets, and did the power well a bit more correctly. Also, added a register definition include file so we can used constants instead of magic numbers. We also set registers to common initialized values that are needed for FUI, VBIOS, and kernel. This set of registers appears to be an absolute bare minimum. Since we're hoping to use FUI for all chipsets from this one forward, we unconditionally do the setting here. Signed-off-by: Ronald G. Minnich <rminnich@google.com> Change-Id: Ife3f661ba010214d92b646b336f2b06645119f17 Reviewed-on: https://gerrit.chromium.org/gerrit/59988 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/4328 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-05google/link: use the new edid functions when in FUI modeRonald G. Minnich
The new edid functions support converting the edid to an lb_framebuffer. Use them. Also, since panels seem to set bits per color instead of bits per pixel, just force the right value in the edid struct. Add helpful comment because people don't always believe we need to set the pallette. While we're at it, fix a problem that caused it to not compile. Change-Id: I645edc4e442d9b96303d9e17f175458dc7ef28b6 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/57619 Reviewed-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/4327 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-05lynxpoint: Update LPT-LP PM settingsDuncan Laurie
- updates from 1.6.0 ref code - remove the step comments as they are no longer even close - add constants for LPT revisions build and boot on Falco Check that RCBA+2300[1] is set: > mmio_read32 0xfed1e300 0x00000002 Change-Id: I8b3c5fda3f3170455699a7834239cb991603e7a8 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59821 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4326 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-05lynxpoint: enable clock gatingAaron Durbin
Implement the LynxPoint BIOS Spec for clock gating. Change-Id: Iaa84cb447bd29b0d13cdda481a1661ea40499de1 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59590 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4325 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-05lynxpoint: provide gpio_is_native()Aaron Durbin
There's a need to determine if a specific gpio pin is is set up to be a native function or not. Implement this. Change-Id: I91d57a549e0f4fddc0b1849e5f74320fc839642c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59589 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4324 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-05lynxpoint: implement additional programming stepsStefan Reinauer
The BIOS spec for LynxPoint calls out additional programming steps for the PCIe Root Ports. Implement those steps from the BIOS spec. These steps are completed before deeper PCIe probing. The "late" programming was removed as that was applicable to Cougar/Panther point where this code was originally copied, though there was some overlap. Change-Id: I64f25e4451e035d98ca6b66b0335bd280b70b074 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59558 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4323 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-05lynxpoint: disable pcie devices based on configAaron Durbin
PCIe Root Ports should be disabled based on pin ownership and the strapping configuration. Implement this logic for LynxPoint. The chip_ops->enable_dev() path is no longer used. Instead the PCIe driver handles the enabling and disabling of devices. This allows for having an empty or incomplete device tree since those "allocated" devices do not travel through the chip_ops->enable_dev() path. The coalescing was tested to be working properly, however not all configurations were tested. Change-Id: I1e8bfe5e447b72ff8a4b04b650982d8c1ae0823c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59424 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4322 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-05peppy: Disable forced dev mode.Shawn Nematbakhsh
Don't force dev mode. Allow users to enter / exit dev mode as normal. Change-Id: I168eb04a8ac102a8c4a1ca8936f78f62b001e0eb Reviewed-on: https://gerrit.chromium.org/gerrit/59492 Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-by: Dave Parker <dparker@chromium.org> Reviewed-on: http://review.coreboot.org/4321 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-05Fix Makefile to include all copies of the SPD sourcesDuncan Laurie
On some systems there may be 2GB SKU that is the same as the 4GB SKU but just one channel of memory. In that case we need to ensure that both copies of the same SPD source end up populated by ensuring that repeated entries are included by using $+ instead of $^. Alternatively we could do the check inside romstage, but it is already set to behave this way if the SPD gets populated correctly. I changed spd_index to 3 in falco romstage to force it to pretend it was a 2GB config of the same memory, then booted to ensure it was indeed limited to 2GB. memcfg channel[0] config (00780008): ECC inactive enhanced interleave mode on rank interleave on DIMMA 2048 MB width x16 single rank, selected DIMMB 0 MB width x16 single rank memcfg channel[1] config (00600000): ECC inactive enhanced interleave mode on rank interleave on DIMMA 0 MB width x8 single rank, selected DIMMB 0 MB width x8 single rank Change-Id: Ibfe5051ccda2fe69e8caff3f3c264116e3411c65 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59483 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Jay Kim <yongjaek@chromium.org> Reviewed-on: http://review.coreboot.org/4319 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-05AMD Kabini: fix issue 'S3 fails to suspend after wake up from USB keyboard'Zheng Bao
Propagated from http://review.coreboot.org/3347 http://review.coreboot.org/3374 The cause of this issue is: USB devices use bit 11(0x0b) of GP0_STS represents S3 wake up event, but this bit is not clear after wake up. So OS thinks there is a wake up signal and wake up immediately. Both amd/olivehill and asrock/imb-a180 have been validated. Change-Id: I7c26cb07bcd2e62bb792809b67314e5155c6adf6 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/4261 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-05AMD Kabini: Add ACPI sleep/wakeup calls for southbridgeZheng Bao
The AML code of PTS and WAK for southbridge are in UINT8 AlibSsdtKB[], Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h. It was integrated into SSDT even it was called by nobody. The source ASL was provided by AGESA for reference, but it has been scrubbed when it was ported to Coreboot. Without the calls, Olive Hill can not wake up if it boots Windows. Both amd/olivehill and asrock/imb-a180 have been validated. Change-Id: Ia7bba29904dbd6f33fdb08bf88bb499005ef561b Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/4260 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-05AMD IMC AGESA: Access the data in stack by correct lengthZheng Bao
The bug is hard to find. We were adding the feature of fan control. We met some strange things which could not be explained. Like, sometimes adding printk let the error disappear. Then we traced the code by hardware debug tool (HDT). It turned out the data in stack was overwritten. The values of AccessWidthxx are { AccessWidth8 = 1, AccessWidth16, AccessWidth32,} For the case of AccessWidth8, we only need to access the index/data once. But ReadECmsg and WriteECmsg did the loop twice, 1 more time than they are supposed to do. The data in stack next to "Value" would be overwritten. For all the cases, the code should be OpFlag = OpFlag & 0x7f; switch (OpFlag) { case 1: /* AccessWidth8 */ OpFlag = 0;break; case 2: /* AccessWidth16 */ OpFlag = 1;break; case 3: /* AccessWidth32 */ OpFlag = 3;break; case 4: /* AccessWidth64 */ OpFlag = 7;break; default: error; } Actually, the caller only takes AccessWidth8 as the parameter. We can ignore other cases for now. That is an AGESA bug. AMD's AGESA team own this code. They have given the response that they are going to update this in next release. I presume let them decide the proper way to fix that. Before that, I change the code as little as possible to make it run without crash. Change-Id: I566f74c242ce93f4569eedf69ca07d2fb7fb368d Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/4297 Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2013-12-05cpu: Remove BOARD_MICROCODE_CBFS_GENERATE Kconfig optionAlexandru Gagniuc
Commit * bdafcfa Add the Intel FSP 206ax CPU core support Introduced this option. This option was meant to have a board generate a CBFS file containing microcode. However, microcode generation used to be enabled by default when CPU_MICROCODE_IN_CBFS was selected. The introduction of BOARD_MICROCODE_CBFS_GENERATE killed that automatic default, which is not what we want. This option is misguided in the sense that it tends to introduce a non-default which had been intentionally a default. We now have to select two Kconfig options in order to generate microcode in CBFS, meaning one option is redundant. Change-Id: I3034833df1a9afa7d6d9d537484cb4ac89d30183 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4478 Tested-by: build bot (Jenkins)
2013-12-05intel/fsp_bd82x6x: Use correct type pointer for mainboard_smi_gpiAlexandru Gagniuc
mainboard_smi_gpi has recently been updated to take a u32 argument from a u16, but the patch introducing the fsp_bd82x6x support has been verified on a master before this change, thus resulting in a 'cast from incompatible type' error. Update the pointer to the correct size argument. Change-Id: I9d62ee43f7c8ed774898f54d29a87cf463b76e91 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4479 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-12-05qemu-armv7 CPU: Move Kconfig code into CPU directoryStefan Reinauer
Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Icae8042add5f4dd5c707369ffc4587c613d69d29 Reviewed-on: https://gerrit.chromium.org/gerrit/59324 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4315 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-12-04lenovo/x60: Drop global oprom_is_loadedKyösti Mälkki
Variable use is specific to ChromeOS. Change-Id: I5b61a038e6b08e3b2408c4d990749d45fdf2148d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4306 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-12-04lumpy: Fix build without ChromeOSKyösti Mälkki
Change-Id: I1a59405499deceed7df01a03834be72830e6578f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4291 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-04intel/cougar_canyon2: Intel CRB FSP based mainboardMarc Jones
Cougar Canyon 2 is a Ivybridge/PantherPoint reference board. This implementation uses the Intel FSP (Vist the Intel FSP website for details on FSP architecture and support). The FSP does not support s3 at this time. S3 may be added when it is available in the FSP. All other features and IO ports are functional. Booted on Ubuntu 12.04 and 13.04, Fedora 18 with SeaBIOS payload. Memtest86, FWTS, and other tests pass. Board support page will be updated on acceptance. Change-Id: I26c0b82d7ac295498376ad4c3517a9d6660d1c01 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/4018 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-12-04Update SMM for FSP systemsMarc Jones
Add the FSP northbridge and southbridge includes. Change-Id: I5c7f395dc033caa8d0bf0313382769595d77f2a5 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/4019 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-12-04Add Intel FSP bd82x6x southbridge supportMarc Jones
Add support for the bd82x6x using the Intel FSP. The FSP is different enough to warrant its own source files for now. The mrc/system agent chromebook solution does much more southbridge initialization and configuration than the FSP version. It may be combined in the future. Change-Id: Ie493945f3d321d854728d231979a0c172d2b36de Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/4017 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-12-04Add the Intel FSP 206ax CPU core supportMarc Jones
Add support for 206ax using the Intel FSP. The FSP is different enough to warrant its own source files for now. It has different CAR code, micorcode, and FSP inclusion. It may be possible to combine this code with the mrc based solution used by the chromebooks in the future. Change-Id: I5105631af34e9c3a804ace908c4205f073abb9b4 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/4016 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-04Add Intel FSP northbridge support Sandybridge and IvybridgeMarc Jones
Add support for Sandybridge and Ivybridge using the Intel FSP. The FSP is different enough to warrant its own source files. This source handle the majority of FSP interaction. "Intel® Firmware Support Package (Intel® FSP) provides key programming information for initializing Intel® silicon and can be easily integrated into a boot loader of the developer’s choice. It is easy to adopt, scalable to design, reduces time-to-market, and is economical to build." http://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html Change-Id: Ib879c6b0fbf2eb1cbf929a87f592df29ac48bcc5 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/4015 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-12-03qemu-armv7: Drop additional console_init()Stefan Reinauer
It's done in bootblock_simple.c just after returning from the mainboard specific bootblock function. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I96cab5e406132a9f7dc30d48ff99f524773a1a14 Reviewed-on: https://gerrit.chromium.org/gerrit/58473 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/4257 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-12-03ibexpeak: ensure config compatibility with bd82x6xVladimir Serbinenko
Ibexpeak shares few files with bd82x6x. In order for it to work correctly their config structures from chip.h must match, so include bd82x6x/chip.h in ibexpeak/chip.h Change-Id: Ib56b311b8af04f4e4803d1834724680f604901cd Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4277 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-03Drop obsolete CONSOLE_LOGBUFStefan Reinauer
This was used by Ron 13ys ago and was never used again ever since. Change-Id: I8ae8a570d67fa0b34b17c9e3709845687f73c724 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/59320 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/4256 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-12-03lynxpoint: Fix LPT-LP PME_B0 bit offset in ACPI _PRW objectsDuncan Laurie
LynxPoint-LP has a lot of GPEs and the "default" set has been moved to register 4 starting at bit offset 96. This means that PME_B0 bit in GPE0_EN/GPE0_STS is now bit 109 in LPT-LP but still bit 13 in LPT-H. suspend on falco and wake from usb 4 | 2013-06-19 10:49:17 | ACPI Enter | S3 5 | 2013-06-19 10:49:22 | ACPI Wake | S3 6 | 2013-06-19 10:49:22 | Wake Source | Internal PME | 0 Change-Id: I443cd4d17796888debed70c0bda27ae09accd09b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59265 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4253 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-12-03vboot: use out_flags to indicate recovery modeDuncan Laurie
In order to make the proper decision on loading the option rom or not the recovery mode setting needs to be known. Normally this is detected by asking the EC, but if recovery is requested with crossystem then the EC does not know about it. Instead we need to check the output flags from VbInit(). Change-Id: I09358e6fd979b4af6b37a13115ac34db3d98b09d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57474 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4223 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-12-03vboot: Do not pass OPROM_MATTERS flag to VbInitDuncan Laurie
Since we are using VBNV to determine if developer mode is active we do not need the messy OPROM hook magic any longer. Change-Id: I1b9effef3ef2aa84e916060d8e61ee42515a2b7c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57473 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4222 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-03slippy/falco/peppy: Fix Chrome OS GPIO export in ACPIDuncan Laurie
The OIPG package needs to have >1 member to make the chromeos_acpi kernel driver do the right automagic sysfs topology creation. Additionally an "unimplemented" GPIO should be reported as 0xFF because 0 is a valid GPIO number. verify crossystem on slippy $ sudo crossystem | grep -e recoverysw_cur -e wpsw_cur recoverysw_cur = (error) wpsw_cur = 1 Change-Id: I06dff09152bde30a3ffe58b1defe9d299155472c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57471 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4221 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-03haswell boards: Enable VIRTUAL_DEV_SWITCHDuncan Laurie
This config option was not enabled which was preventing the user from enabling developer mode from recovery mode. With this enabled we can disable the "dev mode by default" behavior and let people enable it by entering recovery mode. This will make the firmware behave like a typical chromeos device. Peppy is left in "default dev mode" until after bringup. 1) boot slippy in normal mode by default 2) enter recovery mode with servo button 3) Ctrl+D on USB keyboard to enter developer mode 4) boot slippy in developer mode Change-Id: I414c0d10dd0489e3c89798f75a2872a43297c8d8 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57350 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4220 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-02Add option to disable ChromeOSKyösti Mälkki
Those building Chromebook firmware from coreboot git might be more interested in building without ChromeOS extras. Change-Id: I2f176d059fd45bf4eb02cc0f3f1dcc353095d0ce Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3977 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-02Introduce a config whether dock is inited in romstage or notVladimir Serbinenko
Instead of depending on exact mobo configure general characteristic whether dock is configured in romstage or ramstage. X60 and T60 have superio in dock so it needs to be inited to get serial, so it should be inited in romstage. On X201 there is nothing useful that early in boot but it's needed to init more to get dock working, in particular EC init needs to be done first. Change-Id: If5072e3dec883a94cd2d5643a92f7f6c3c9feee9 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4294 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-12-02EC H8: remove dependence on IS_X201Vladimir Serbinenko
Instead define brightness up/down function and gfx device and use preprocessor magic to glue it together. Change-Id: I03074ae07b33c1546d229efc3e80606ddbee6300 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4282 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-12-02global: Fix usage of get_option() to make use of CB_CMOS_ codesAlexandru Gagniuc
Do not directly check the return value of get_option, but instead compare the returned value against a CB_CMOS_ error code, or against CB_SUCCESS. Change-Id: I2fa7761d13ebb5e9b4606076991a43f18ae370ad Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4266 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-12-02haswell: Update pei_data to match ref codeDuncan Laurie
- Add a new USB location field - Add a new "ddr_refresh_2x" field, enabled on Falco only - Fix copy+paste bug in baskingridge Checked that tREFI is halved during memory setup in the memory training log: tREFImin = 6240 << DEFAULT C(0).tREFI = 0xc30 << MODIFIED (=3120) C(0).tREFI = 0xc30 << MODIFIED (=3120) Also ensure that the SD card is detected properly again. Change-Id: Ie3a82c08df06ada9af56282b5255caefa56487f2 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57349 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4219 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-02amd/car/post_cache_as_ram: Switch stack in assembly rather than in CVladimir Serbinenko
Compiler may do loads of optimisations around stack switch and so it's allowed to break stack switch as it sees fit. Do it in assembly instead. Not tested. Change-Id: I277a62a9052e8fe9b04e7c65d149e087282ac2a2 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4286 Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-12-02ec/lenovo/h8: Add h8_build_id_and_function_spec_version()Peter Stuge
The function reads the Build ID and the supported function specification version from the running EC firmware, and stores a text representation in the provided output buffer. Change-Id: I3b647d7f315c9b4922fa9a9c5167a80f6d82e753 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/3617 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-12-02Makefile: Drop obsolete rulesKyösti Mälkki
The source files were removed with commit 3e4e3038. Change-Id: I2df9d8cce0ec1462dcba4790a6c62abade0d223c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4298 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2013-12-02falco: Update panel power sequence timingsDuncan Laurie
These are based on the datasheet and I included the timing values I used from the docs. Change-Id: Ib75b2c5e50ac09d1e4cf9dd22229bb0f0a8965a4 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58540 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4234 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-02peppy: Port updates from slippy/falco boardsDuncan Laurie
- Add HDA verb table - Add on-board device table - Add panel power sequencing values Change-Id: I1b3450c2740ec1d930f157a9b23550e1efc8668f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58197 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4233 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-02vboot: use out_flags to indicate dev modeAaron Durbin
In order to make the proper decision on loading the option rom or not the developer mode setting needs to be known. Under early firmware selection it is possible to know the state of developer mode by a flag in out flags. Use this flag when early firmware selection is being employed to determine if developer mode is enabled or not. Change-Id: I9c226d368e92ddf8f14ce4dcde00da144de2a5f3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57380 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4218 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-02lenovo/x60: Add "IBM ThinkPad Embedded Controller" SMBIOS OEM StringPeter Stuge
The Linux thinkpad_acpi.c driver looks for this string while reading information about the system it is running on. This commit does not make the module load but it is one of several things that the module looks for on a ThinkPad. Change-Id: Ia48bbd85ba4d528063695345b0f968d264573341 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/3779 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-02peppy: Add 2GB DRAM configuration.Shawn Nematbakhsh
Currently, all Peppy boards w/ '000' SPD GPIOs have 2GB DRAM. Disable the second DRAM channel based upon the GPIOs. Need to change / confirm this for upcoming builds. Change-Id: I7085ddecb80626cc0bed99ba7b174c6b80350696 Reviewed-on: https://gerrit.chromium.org/gerrit/58620 Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4238 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-02peppy: Re-enable EC software syncShawn Nematbakhsh
The EC was disabling flash commands and sysjump was not working properly. With those two fixed software sync works properly. (Taken from I63ca00d6c94854f2b395eb736ce20792da5f8de2). Change-Id: I9c7d1d1f1aaf7de33d0cec5f6daf648576ba8900 Reviewed-on: https://gerrit.chromium.org/gerrit/57289 Reviewed-by: Dave Parker <dparker@chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4212 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-02peppy: Update GPIO table + USB port map.Shawn Nematbakhsh
- Update GPIO table to match board. - Update USB port map. - Remove iSSD power sequencing code. Change-Id: Iaa8e5921ed9db6bcfd18b5a888c7f80b2c93a710 Reviewed-on: https://gerrit.chromium.org/gerrit/56869 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4211 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-02elog: Get rid of the descriptor type and some unnecessary wrappersGabe Black
There was always exactly one elog descriptor declared and initialized, but its contents were being accessed through a pointer that was passed back and forth between functions instead of being accessed directly. This made the code more verbose than it needed to be and harder to follow. To address this the descriptor type was eliminated, its contents were turned into individual global variables, and various functions were adjusted to no longer take the descriptor as an argument. Similarly, the code was more verbose and complicated than it needed to be because of several wrapper functions which wrapped a single line of code which called an underlying function with particular arguments and were only used once. This makes it harder to tell what the code is doing because the call to the real function you may already be familiar with is obscured behind a new function you've never seen before. It also adds one more text to the file as a whole while providing at best a marginal benefit. Those functions were removed and their callers now call their contents directly. Built and booted on Link. Ran mosys eventlog list. Cleared the event log and ran mosys eventlog list again. Added 2000 events and ran mosys eventlog list. Cleared the log again and ran mosys eventlog list. Change-Id: I4f5f6b9f4f508548077b7f5a92f4322db99e01ca Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/49310 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4245 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-02elog: Stream line the elog driver.Gabe Black
The elog driver's design was a bit more elaborate than it really needed to be since it no longer had to keep track of multiple copies of the log in flash and also in memory. This change streamlines it by removing unnecessary compartmentalization of some bits of code, and some variables which tracked the last entry added which were never used. Built and booted on Link. Ran mosys eventlog list. Added 2000 events to the event log and ran mosys eventlog list again. Cleared the log by echoing 1 into /sys/firmware/gsmi/clear_eventlog and ran mosys eventlog list. Change-Id: I7d4cdebf2f5b1f6bb1fc70e65eca18f71b124b18 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/49309 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4244 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-02elog: Merge elog_validate_and_fill into elog_init_descriptor.Gabe Black
elog_validate_and_fill was called in exactly one place, in elog_init_descriptor. It didn't actually do what its name implied since the data in the event log was already "filled" by elog_init_descriptor. Likewise elog_init_descriptor was delegating an important part of its own job, scanning through the list of events, to elog_validate_and_fill. Since one function was basically just a displaced part of the other which couldn't really stand on its own, this change merges them together. Built and booted on Link. Ran mosys eventlog list. Added 2000 events with the SMI handler and ran mosys eventlog list again. Change-Id: Ic899eeb18146d0f127d0dded207d37d63cbc716f Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/49308 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4243 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-02elog: Get rid of elog_reinit_descriptor.Gabe Black
This function was just a wrapper around elog_init_descriptor, and all it did was pass the current backing store location and size back in so it would be reused. Those values, which never change, are now set in elog_setup_descriptors, eliminating those parameters to init and eliminating the need for _reinit_. Built and booted on Link. Ran mosys eventlog list. Added 2000 events to the log and ran mosys eventlog list again. Change-Id: I133768aa798dfc10f32e14db95235a88666890c3 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/49307 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4242 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-02elog: Eliminate the second in memory copy of the event log.Gabe Black
The event log driver keeps two copies of the event log in memory, one to take the place of the historically memory mapped image of flash which is now read and written manually, and one originally intended to be an in memory cache of flash. Since both are now just copies in memory, there's no value in having them both and keeping them in sync. Built and booted on Link. Ran mosys eventlog list. Added 2000 events to the log and ran mosys eventlog list again. Cleared the log by echoing a 1 into /sys/firmware/gsmi/clear_eventlog and ran mosys eventlog list again. Change-Id: Ibed62a10c78884849726aa15ec795ab2914afc35 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/49306 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4241 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-02Make elog_shrink not depend on having seperate memory/flash descriptors.Gabe Black
The way elog_shrink currently works is that it completely clears the data in the flash/flash descriptor and then recreates it using the part of the log it's going to keep as stored in the memory descriptor. That scheme depends on there being to independent copies of the log. This change reworks elog_shrink so that it moves the data it wants to keep within a single descriptor and then propogates it to the other and to flash intact. This way, when one of the descriptors goes away, all we have to do is remove the code that would update it. Built and booted into ChromeOS on Link. Ran mosys eventlog list. Added 2000 events to the log and ran mosys eventlog list again. Echoed a 1 into /sys/firmware/gsmi/clear_eventlog and ran mosys eventlog list. BRANCH=None Change-Id: I50d77a4f00ea3c6b3e0ec8996dab1a3b31580205 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/49305 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4240 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-02elog: Get rid of the staging_header variable.Gabe Black
The header is at the start of the log. There's no reason to either keep a seperate pointer to it, or to keep a copy of it in some other bit of memory. Built and booted on Link and used 'mosys eventlog list' to list the contents of the log. Ran for x in $(seq 1 2000); do cat elog.event.kernel_clean > /sys/firmware/gsmi/append_to_eventlog; done And ran mosys eventlog list again to verify that the log had been shrunk correctly. Change-Id: I2afcd52c0ce5bbb662ac56f2895cdbea28d5c2ce Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/49304 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4239 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-02lynxpoint: move all pcie device handling to pcie.cAaron Durbin
Some of the pcie logic was located in pch.c as well as pcie.c. Move all pcie logic to the same pcie.c file. This is a straight cut-and-paste (no logic changes) except for a rename from pch_pcie_enable() -> pch_pcie_enable_dev(). Change-Id: I338c53039b95f255ab9ced313c51193a9d34b404 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59277 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4251 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-02lynxpoint: expose pch_disable_devfn()Aaron Durbin
The function to disable devices was formerly named pch_hide_devfn(). This routine was doing more than hiding devices. It was disabling them, i.e. turning them off. Therefore, rename it to pch_disable_devfn(). Also, allow external callers to this function. Change-Id: Id5bb319d4e67892c02a39dff49e45b2811a2f016 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59276 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4250 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-02lynxpoint: expose iobp functionsAaron Durbin
The iobp functions are useful to may of the southbridge devices as certain values need to be updated to properly initialize the devices. Therefore expose read, write, and updated iobp functions. Change-Id: Id7fdd8d0d9f022f92d6285ecd8f85a52024ec2bb Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59275 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4249 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-02Add description to MAINBOARD_VENDOR string so it can be overriddenDuncan Laurie
A quirk of the Kconfig used in coreboot is that config options cannot be overriden by local config changes unless they have a description string. 1) Add CONFIG_MAINBOARD_VENDOR="Custom" to local config 2) Build and flash coreboot 3) cat /sys/class/dmi/id/sys_vendor and look for "Custom" Change-Id: I1b5f2124cd4a22c056c025143ae5bcaafa6b03f0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59088 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4248 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-02peppy: Add an inverted input GPIO typeShawn Nematbakhsh
The wake device input pins are active low and the GPIOs need to be set as inverted when they are marked as an input so they are not spuriously logged. Also sync pin states from Falco initial commit. Reference change: I15d38dcc9b2fb4b2b0eb27da358fa3c343e22323 Change-Id: I66e136d389d53a367436d816fa84dacdc8e86bad Reviewed-on: https://gerrit.chromium.org/gerrit/58334 Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-by: Dave Parker <dparker@chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> Signed-off-by: Shawn Nematbakhsh <shawnn@google.com> Reviewed-on: http://review.coreboot.org/4247 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-02falco/slippy: Fix DMIC nid verb.Dylan Reid
Set nid 0x12 instead of nid 0x05. The DMIC is on NIC 0x12. Change-Id: Ifc883b65a50aeec6a6d3ad02fe8418f124e6241d Signed-off-by: Dylan Reid <dgreid@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58711 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Duncan Laurie <dlaurie@chromium.org> Tested-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Jay Kim <yongjaek@chromium.org> Tested-by: Jay Kim <yongjaek@chromium.org> Reviewed-on: http://review.coreboot.org/4246 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-01slippy/falco/peppy: Fix SPD GPIO initialization.Aaron Durbin
SPD GPIOs were being read prior to initialization in romstage_common. To fix, pass the copy_spd function to romstage_common, to be called at the appropriate time (after PCH init, before DRAM init). Change-Id: I2554813e56a58c8c81456f1a53cc8ce9c2030a73 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58608 Reviewed-on: http://review.coreboot.org/4237 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-01Butterfly: Force DDR refresh rate to 2x.Shawn Nematbakhsh
Due to OEM request, always set DDR refresh rate at 2x. Change-Id: I81a4f57aca6388551dca6effbd9a4ac1a97e4f5a Reviewed-on: https://gerrit.chromium.org/gerrit/50477 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4214 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-01Add DDR refresh config to pei data structure.Shawn Nematbakhsh
Allow platform customized DDR config, including forcing refresh rate to 2x. Change-Id: I311ae7ddf25142153c94a3fc3fb0a36e03f50ab2 Reviewed-on: https://gerrit.chromium.org/gerrit/50476 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4213 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-01Fix build with USE_OPTION_TABLEKyösti Mälkki
Parallelized build might try to build SMM before option_table.h is created. Remove related redundant explicit rules. Change-Id: Ida8b5c408af05adcf3210ce7bfc8a1e5959194c7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4299 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-01H8: Move EC GPE declaration to mainboardVladimir Serbinenko
Change-Id: Iefc481f09268dd15bbc3cbfa8bdd110d44383f6a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4281 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-01lynxpoint: Do not clear ACPI NVS region on resumeDuncan Laurie
There are useful values in NVS that are set at boot and runtime and they should not be cleared on resume. suspend/resume twice on slippy and ensure that the USB ports are still powered on the second suspend. Change-Id: I4bce60b02b6637f6683120ae9c4a5c64563aacf7 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56941 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4210 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-30CBMEM console: increase temporary buffer size for non-dynamic CBMEMKyösti Mälkki
Make temporary buffer allocation equal with the allocation in CBMEM and let copy_console_buffer() handle possible truncation. When not using dynamic CBMEM the CBMEM area is initialized late in the ramstage and should be able to hold almost as many characters as the CBMEM can hold. We have seen 40000 was not always enough with logging level set to spew, new default size is 0x10000. Change-Id: If4b143fdf807e28b6766b8b99db5216b767948d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4295 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-11-30cbmem console: reduce temporary buffer size for dynamic CBMEMStefan Reinauer
When using dynamic CBMEM the CBMEM area is initialized before entering ram stage, and so we need a way smaller temporary buffer for the CBMEM console during early bits of ram stage. In practice around 256 bytes are needed, but keep the buffer at 1k so we make sure we don't run out. TEST=Boot tested on pit BRANCH=none BUG=none Change-Id: I462810b7bafbcc57f8e5f9b1d1f38cfdf85fa630 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://chromium-review.googlesource.com/168575 Reviewed-by: Aaron Durbin <adurbin@chromium.org> [km: cherry-pick 7fd1bbc0 from chromium git] Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4293 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-11-30CBMEM console: Prevent buffer overrunKyösti Mälkki
Make sure memcpy target and a possible message telling log was truncated stay within the allocated region for CBMEM console. This fixes observed CBMEM corruption on platforms that do not use CBMEM console during romstage. Those platforms will need an additional fix to reset cursor position to zero on s3 resume. Change-Id: I76501ca3afc716545ca76ebca1119995126a43f8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4292 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-11-30dmp/vortex86ex: Add timeout for keyboard system flag checking.Andrew Wu
If Vortex86EX PS/2 keyboard controller system flag bit times out, reload controller firmware code and try again. Abort and die after 11 tries as this means the CPU is defect. Also inform the user by printing a message. Change-Id: I24aec4b20d85c721c01e72686f3eb1259f9334b8 Signed-off-by: Andrew Wu <arw@dmp.com.tw> Reviewed-on: http://review.coreboot.org/3988 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-11-30ibexpeak: set HAVE_USBDEBUG_OPTIONSVladimir Serbinenko
Previously, I've set this config in mobo config, yet according to Kyösti Mälkki this parameter is southbridge-specific and not mobo-specific. Change-Id: I92428aed5a69d88a371f5d7267bc54ba7530766c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4276 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-11-26lynxpoint: Add an inverted input GPIO typeDuncan Laurie
The wake device input pins are active low and the GPIOs need to be set as inverted when they are marked as an input so they are not spuriously logged. suspend/resume on slippy with trackpad wake: 8 | 2013-05-29 07:43:14 | ACPI Enter | S3 9 | 2013-05-29 07:43:18 | ACPI Wake | S3 10 | 2013-05-29 07:43:18 | Wake Source | GPIO | 12 and with power button wake: 11 | 2013-05-29 07:43:35 | ACPI Enter | S3 12 | 2013-05-29 07:43:40 | EC Event | Power Button 13 | 2013-05-29 07:43:40 | ACPI Wake | S3 14 | 2013-05-29 07:43:40 | Wake Source | Power Button | 0 Change-Id: I15d38dcc9b2fb4b2b0eb27da358fa3c343e22323 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56940 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4209 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-11-26google/parrot/smihandler.c: Use `battery_critical_logged` only with `ELOG_GSMI`Paul Menzel
Make the declaration and use of it conditional on the ELOG_GSMI Kconfig variable. Change-Id: I2ef291d2f3e7d35545014e03ba8e0045da6050e5 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3987 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-26slippy/falco: Re-enable EC software syncDuncan Laurie
The EC was disabling flash commands and sysjump was not working properly. With those two fixed software sync works properly. Google Chrome EC MKBP driver ready, id 'slippy_no_version' Clearing the recovery request. EC hash:7fea29992ef72e3e64d8ffe522aa1dfa68dcb44a2da96a4c19530ea1a0bd22c4 EC-RW hash address, size are 0xffa1cfe8, 32. Hash = 727e79934d9394184da496cebc27f7275b9d2d91079bf125d8f977a1f8aa4cde Expected hash:727e79934d9394184da496cebc27f7275b9d2d91079bf125d8f977a1f8aa4cde EC-RW firmware address, size are 0xffad000c, 57180. VbEcSoftwareSync() - expected len = 57180 Computed hash of expected image:727e79934d9394184da496cebc27f7275b9d2d91079bf125d8f977a1f8aa4cde VbEcSoftwareSync() updating EC-RW... VbEcSoftwareSync() jumping to EC-RW VbEcSoftwareSync() in RW; done Change-Id: I63ca00d6c94854f2b395eb736ce20792da5f8de2 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56821 Reviewed-on: http://review.coreboot.org/4208 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-11-26Clean up POST codes for Boot State machineDuncan Laurie
Now that there is a clearly defined boot state machine we can add some useful post codes to indicate the current point in the state machine by having it log a post code before the execution of each state. This removes the currently defined POST codes that were used by hardwaremain in favor of a new contiguous range that are defined for each boot state. The reason for this is that the existing codes are mostly used to indicate when something is done, which is confusing for actual debug because POST code debugging relies on knowing what is about to happen (to know what may be at fault) rather than what has just finished. One additonal change is added during device init step as this step often does the bulk of the work, and frequently logs POST codes itself. Therefore in order to keep better track of what device is being initialized POST_BS_DEV_INIT is logged before each device is initialized. interrupted boot with reset button and gathered the eventlog. Mosys has been extended to decode the well-known POST codes: 26 | 2013-06-10 10:32:48 | System boot | 120 27 | 2013-06-10 10:32:48 | Last post code in previous boot | 0x75 | Device Initialize 28 | 2013-06-10 10:32:48 | Extra info from previous boot | PCI | 00:16.0 29 | 2013-06-10 10:32:48 | Reset Button 30 | 2013-06-10 10:32:48 | System Reset Change-Id: Ida1e1129d274d28cbe8e49e4a01483e335a03d96 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58106 Reviewed-on: http://review.coreboot.org/4231 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-26Log device path into CMOS during probe stagesDuncan Laurie
One of the most common hangs during coreboot execution is during ramstage device init steps. Currently there are a set of (somewhat misleading) post codes during this phase which give some indication as to where execution stopped, but it provides no information on what device was actually being initialized at that point. This uses the new CMOS "extra" log banks to store the encoded device path of the device that is about to be touched by coreboot. This way if the system hangs when talking to the device there will be some indication where to investigate next. interrupted boot with reset button and gathered the eventlog after several test runs: 26 | 2013-06-10 10:32:48 | System boot | 120 27 | 2013-06-10 10:32:48 | Last post code in previous boot | 0x75 | Device Initialize 28 | 2013-06-10 10:32:48 | Extra info from previous boot | PCI | 00:16.0 29 | 2013-06-10 10:32:48 | Reset Button 30 | 2013-06-10 10:32:48 | System Reset Change-Id: I6045bd4c384358b8a4e464eb03ccad639283939c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58105 Reviewed-on: http://review.coreboot.org/4230 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-26Extend CMOS POST code logging to store extra dataDuncan Laurie
This can be used to indicate sub-state within a POST code range which can assist in debugging BIOS hangs. For example this can be used to indicate which device is about to be initialized so if the system hangs while talking to that device it can be identified. Change-Id: I2f8155155f09fe9e242ebb7204f0b5cba3a1fa1e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58104 Reviewed-on: http://review.coreboot.org/4229 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-26cmos post: Guard with spinlockDuncan Laurie
The CMOS post code storage mechanism does back-to-back CMOS reads and writes that may be interleaved during CPU bringup, leading to corruption of the log or of other parts of CMOS. Change-Id: I704813cc917a659fe034b71c2ff9eb9b80f7c949 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58102 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4227 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-11-26Extend the ELOG errors for EC fan.Marc Jones
Change-Id: Ida98f81b1ac1f6b3ba16c0b98e5c64756606fd58 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: https://gerrit.chromium.org/gerrit/48318 Reviewed-by: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4126 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-11-26qemu: minor bochs cleanupsGerd Hoffmann
Add a comment, tweak spacing a bit, addr variable doesn't need to be global any more. Change-Id: Id8d8a7babce671243351074f7ac52a5c8c264de5 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/4274 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-11-26AMD Northbridge LX: simplify get_top_of_ram()Christian Gmeiner
Get rid of not needed dependency to gliu0table. This change is needed to move get_top_of_ram() to raminit.c - as needed for EARLY_CBMEM_INIT. Boot tested on a Bachmann OT200. Change-Id: I0bfe40c366a3537775d5c1ff8e0b1f5ac94320b7 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3380 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-11-26Add function to encode device path into integerDuncan Laurie
This function will encode the device path into 3 bytes of a dword which can be saved for debug. It will be used by subsequent commit to store the current device into CMOS for debugging BIOS hangs. Change-Id: I3a5155ea53c8d280806e610a0f8998dbabe15f3c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58103 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4228 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-26falco: update verbs for ALC283Duncan Laurie
Set verbs to reflect the layout used for ALC283 in Falco, which ends up being the same as Slippy. Change-Id: I3dce4effefaa91ee5bdcbe2a8a3750ebc41376ad Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58196 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4232 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25pc80/mc146818rtc: Return an error code rather than an integerAlexandru Gagniuc
Do not return hardcoded numerical values to communicate succes/failure, but instead use an enumeration. Change-Id: I742b08796adf136dce5984b702533f91640846dd Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4265 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25include/types.h: Add generic enum for error codesAlexandru Gagniuc
The idea is that instead of: if (do_something()) do_something_else(); It is more readable to write: if (do_something() != CB_SUCCESS) handle_error(); Change-Id: I4fa5a6f2d2960cd747fda6602bdfff6aef08f8e2 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4264 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25slippy: update verbs for ALC283Dylan Reid
Set verbs to reflect the layout used for the ALC283 in slippy. install on slippy and check that headphone switch works as does external mic. Change-Id: I2d6bcda9cf8bbf49cbb6d2dbbe7f1a5adf315d8a Signed-off-by: Dylan Reid <dgreid@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57560 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4224 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25lynxpoint: Enable USB clock gating, late setup, and sleep prepDuncan Laurie
Both EHCI and XHCI controllers have additional setup steps that are not part of the PEI reference code so they need to be done later. Both controllers also have specific clock gating setup requirements that are now implemented. Additionally they both have specific requirements when entering sleep states. XHCI needs something in S3/S4/S5 and EHCI only has steps for S4/S5 entry. Change-Id: Ic62cbc8b6255455e56b72dd5d52e27a311999330 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57033 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4217 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25haswell: check for clean resetAaron Durbin
When an INIT# is delivered to the CPU the CPU starts executing from the reset vector. However, the internal state is maintained. Therefore, check for such a condition and reset the system. Issues 'apreset warm' on the EC console. INIT# is sent and CPU notices it's not a clean reset and forces one. No hangs. Change-Id: I71229e0e5015ba8c60f5989c533268604ecc1ecc Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57111 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4216 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 16:32:41 +0000