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2020-05-26soc/intel/tigerlake: Fix wrong operation region for CPU to PCH methodJohn Zhao
CPU to PCH method refers to PCH ACPI operation region which was wrongly defined as SystemMemory and PCH_PWRM_BASE_ADDRESS. Change the operation region to be SystemIO and ACPI_BASE_ADDRESS. BUG=b:156530805 TEST=Built and booted to kernel. Signed-off-by: John zhao <john.zhao@intel.com> Change-Id: Ifa291a993ec23e1e4dfad8f6cdfabc80b824d20c Reviewed-on: https://review.coreboot.org/c/coreboot/+/41537 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-05-26soc/intel/cannonlake: Add VrPowerDeliveryDesign to chip optionsChristian Walter
Intel introduced the UPD VrPowerDeliveryDesign with Cannon Lake. The BIOS needs to program VrPowerDeliverDesign configuration per platform according to the platform capabilities to avoid incorrect electrial/power parameters. This is only added for Cannon Lake. Refer to document 599797 for more details. Change-Id: I89b8dceb40fa6a9dc67b218e91bf728ff928b5a0 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41081 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26intel/cannonlake: Implement PCIe RP devicetree updateNico Huber
Some existing devicetrees were manually adapted to anticipate root-port switching. Now, their PCI-device on/off settings should just reflect the `PcieRpEnable` state and configuration happens on the PCI function that was assigned at reset. Change-Id: I4d76f38c222b74053c6a2f80b492d4660ab4db6d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-26drivers/intel/fsp2_0: Remove unused 'include <memrange.h>'Elyes HAOUAS
Change-Id: Ic3eb8fca22e73a0d485a6c1bf35c33b1fc606e4a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41488 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26mb/google/foster: Remove unused 'include <memrange.h>Elyes HAOUAS
Change-Id: Ic26d03d0e695ce0823332d4c6430186c7bfbeac1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-26src/sb: Use 'print("%s...", __func__)'Elyes HAOUAS
Change-Id: Ie0d845d3e501ed5ebeef1997944445d31768e410 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39373 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26soc/amd/picasso: Give the mainboard the ability to modify the MADT tableRaul E Rangel
By default legacy ISA IRQs use edge triggering. Depending on what devices are used the IRQ types might need to be changed. We add a setting to the device tree to allow the mainboard to configure the IRS IRQs. BUG=b:145102877 TEST=Booted trembyle and was able to use the keyboard. Change-Id: Ie95e8cc7ca835fb60bee8f10d5f28def6c2801dc Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2033493 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-26superio/ite/Makefile.inc: Add it8613eAngel Pons
This Super I/O was not being built at all. Correct that. Change-Id: Id053fa919cac7b2df6a6fc45aae5e34a0dc8c0ae Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-26AGESA f14/f15tn/f16kb: Deduplicate RAM settingsAngel Pons
On AGESA f14/f15tn, various RAM-related options were defined in an enum. However, the preprocessor mess can't compare enum values. To make AGESA build, each board redefined them as macros, shadowing the enum elements. Clean this up by replacing the enums with macros in AGESA headers, and delete the now-redundant redefinitions from all the mainboards. Note that AGESA f16kb already uses macros, but each mainboard still had commented-out definitions. Remove them as well, as they are unnecessary. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: Ie1085539013d3ae0363b1596fa48555300e45172 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41666 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26AGESA f16kb: Factor out default MTRR settingsAngel Pons
All AGESA f16kb boards use the same MTRR values. Factor them out, while still allowing a board to override them via BLDCFG. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: I236e9d45505e92027acc3ba5ff496f5e2f09b9f3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mike Banon <mikebdp2@gmail.com>
2020-05-26AGESA f15tn: Factor out default MTRR settingsAngel Pons
All AGESA f15tn boards use the same MTRR values. Factor them out, while still allowing a board to override them via BLDCFG. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: I90c95493de1bb5b8f32c06b9575fef3aa7aca031 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mike Banon <mikebdp2@gmail.com>
2020-05-26AGESA f14/f15tn/f16kb: Factor out memory settingsAngel Pons
We use the same values everywhere, so we might as well factor them out. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: Ie6f166034d5d642dff37730a8d83264fb2e019b4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2020-05-26AGESA f14/f15tn/f16kb: Factor out PCI MMIO base/sizeAngel Pons
We set BLDCFG_PCI_MMIO_BASE and BLDCFG_PCI_MMIO_SIZE to the same values everywhere, so we might as well factor them out. As we have equivalent Kconfig options in coreboot, also deprecate overriding them via BLDCFG. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: I7244c39d2c2aa02a3a9092ddae98e4ac9da89107 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mike Banon <mikebdp2@gmail.com>
2020-05-26AGESA f14: Factor out default MTRR settingsAngel Pons
All AGESA f14 boards use the same MTRR values. Factor them out, while still allowing a board to override them via BLDCFG. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: Id980e4671e51fe800188f0a84768a307c8965886 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mike Banon <mikebdp2@gmail.com>
2020-05-26AGESA f14 boards: Drop useless family definitionsAngel Pons
AGESA f14 only uses INSTALL_FAMILY_14_SUPPORT. Drop the rest. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: I2fc6ba94cde66a238da9705fc42330b9e7682800 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41593 Reviewed-by: Mike Banon <mikebdp2@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26AGESA f14 boards: Drop useless socket definitionsAngel Pons
AGESA f14 only uses INSTALL_FT1_SOCKET_SUPPORT. Drop the rest. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: I48efa7496c8101115b4735a99c8c472ac65c0523 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41592 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26AGESA f14/f15tn/f16kb: Factor out AGESA_VERSION_STRINGAngel Pons
We use the same AGESA version numbers on all but one mainboard, so we might as well factor them out. The only exception is asrock/e350m1, which has the f15tn/f16kb version number even though it actually uses AGESA f14. To preserve reproducibility, do not change it in this commit. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: I0dad2352ccda454d5545f17228d52e4ff4f23f20 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41591 Reviewed-by: Mike Banon <mikebdp2@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26AGESA f14/f15tn/f16kb: Factor out AGESA_PACKAGE_STRINGAngel Pons
We use the same value everywhere, so factor it out. Note that the field where this value ends up in was doubled in size for AGESA fam16kb, but we did not update the definition to fill in the additional space. We are not changing it in this commit so as to preserve binary reproducibility. In any case, add a FIXME explaining why this value may not be correct. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: Ied118d534ee1e9728db843944d1e042760b4f32c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mike Banon <mikebdp2@gmail.com> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2020-05-26mb/*/*/buildOpts.c: Clean up whitespaceAngel Pons
Drop multiple blank lines and use one space inside C-style comments. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: Ibe1f279dd22ae7657ea7b7766f88004dbf4dceb5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mike Banon <mikebdp2@gmail.com> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2020-05-26mb/*/*/buildOpts.c: Drop BLDCFG_IR_PIN_CONTROLAngel Pons
This does not exist anywhere in the entire coreboot tree. Drop it. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: I80320a20f4b44896e72d701a1d98786cb3a93dcc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mike Banon <mikebdp2@gmail.com> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2020-05-26mb/lenovo/t410: Set default CBFS sizePatrick Rudolph
Set the default CBFS size to cover the whole BIOS region. Change-Id: If719a9cd2897d933df53bd423e71503b832411fe Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-05-26mb/intel/jasperlake_rvp: Add world facing camera supportPandya, Varshit B
1. Configure GPIOs as per schematics 2. Add 1 Ports and 1 Endpoints 3. Add support for OTVI5675 WFC is on I2C5 with VCM support and using 2 data-lanes BUG=None BRANCH=None TEST=Build and Boot jslrvp board and able to capture image using world facing camera. Change-Id: I07ae9e3473c16bde8eb1597460e70cc478357b98 Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2020-05-26soc/intel/jasperlake: correct IRQ routing Jasper LakeRonak Kanabar
Current Interrupt setting use 2nd parameters as device function number. Correct as interrupt pin number according to _PRT package format. {Address, pin, Source, Source index} Reference: - ACPI spec 6.2.13 _PRT BUG=None BRANCH=None TEST=Build and boot JSLRVP Verify Interrupt mappings are same as PCI INTR(0x3C) register and no interrupt storm is seen Change-Id: I21462c6befea310a49eecf9ad1b5c8770eccd5bd Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41404 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26ec/lenovo/h8: Config the ec hardware ids for newer thinkpadsDa Lao
Currently coreboot is using the ec hardware id IBM0068 for all thinkpads, but for newer thinkpads the id maybe LEN0068 or LEN0268. On Windows, the Lenovo Vantage app can't get battery details when using IBM0068. This patch config this id by motherboard. The hardware IDs for the following models can be found by searching for disassembled dsdt.asl on vendor BIOS: (But this info is not easy to find online. So I only changed some of the thinkpads.) T420: https://github.com/tluck/Lenovo-T420-Clover/blob/master/EFI/CLOVER/ACPI/1600x900-EDID/DSDT.edid-2e2-hs.dsl LEN0068 T430: https://github.com/ThiagoSchetini/macosx-thinkpad-t430/blob/master/vanilla%20ACPI%20dsl's/DSDT.dsl LEN0068 T520: Confirmed by Patrick Rudolph LEN0068 W520: Confirmed by Patrick Rudolph LEN0068 T530: Confirmed by Prasun Gera LEN0068 W530: https://bugzilla.kernel.org/show_bug.cgi?id=66731 LEN0068 X230/X230T: https://github.com/tuandzung/ThinkPad-X230-macOS-10.12.x/blob/master/DSDT/DSDT.dsl LEN0068 T440p: https://github.com/doudou/t440p/blob/master/acpi/2.30/dsdt.dsl LEN0068 Signed-off-by: Da Lao <dalao@tutanota.com> Change-Id: I797080ec8ba7ce39d47fe587319f8f32d6938875 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-05-25drivers: Use SPDX identifiersJacob Garber
Convert the remaining files in src/drivers to use SPDX identifiers. int15.h and default_brightness_levels.asl did not have license headers, but they were both copied from other GPL2 files, so they should be under the GPL2 as well. ne2k.c and drm_dp_helper.h are licensed under custom BSD-like licenses that do not have an SPDX equivalent, so they are added as exceptions to the license header lint. Change-Id: I87fb1c637b8d11b0463f7c19f70b847413e14aed Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-25security/tpm: Use SPDX identifiersJacob Garber
Also adjust a few comments to follow the style guide. Change-Id: I22001320f2ce1f0db348e0f7fabc5a65b50ba53e Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-24vc/amd/fsp/picasso: add Picasso misc data HOB GUID and structFelix Held
BUG=b:153779573 Change-Id: I417ce34f2c302d61cfe94ff478f9022cae16f046 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41629 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-24soc/amd/picasso/include/cpu: add Raven1 CPUIDFelix Held
Change-Id: Iaf848a68dc50c2af1e32b996f09296aaea935459 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41628 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-23mb/asrock/b85m_pro4/gma-mainboard.ads: Use GPL-2.0-or-laterAngel Pons
Other files in the tree use such license. I first added this file. Change-Id: I338654ec022bd6f2fa4a4381a8f27d024605e79d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-05-23soc/intel/broadwell: Use SPDX identifierJacob Garber
Change-Id: Ifbab50ef42f0fe49dd3949db662b245c63522f2d Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41599 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-23soc/intel/common/block: Update SA resource length to support 64 bitSubrata Banik
This patch provides an option for accommodating 64 bit width resource request with CONFIG_PCI_SEGMENT_GROUPS = 16 refer as PCIEX BAR length 4096MB (Bus 0-4095). Change-Id: I9a8448af7e9f26c8e0176e58e4fe253a6e77b69a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40336 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-23soc/intel/{jsl,tgl}: Override PRERAM_CBMEM_CONSOLE_SIZE default valueSubrata Banik
This patch increases PRERAM_CBMEM_CONSOLE_SIZE to fix *** Pre-CBMEM romstage console overflowed, log truncated! *** issue. TEST=Verified on TGL platform. Change-Id: Iae66b6a1260a9290b35d804487b7a07242c5ebc2 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-05-22mb/lenovo/x230: add "docking_supported" to x230 overridetreeBill XIE
The X230, like its larger cousins, has a docking connector. However, it lacks the "docking_supported" flag in devicetree, so add it. Change-Id: I188045e4cf9bbb0f2d434b353b84223470c951b9 Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41510 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-22mb/lenovo/t400: Add support for ThinkLightStefan Ott
With this patch, the ThinkLight on the ThinkPad T400 can be controlled through the OS. The same change was done for the ThinkPad X200 in b45912f4: mb/lenovo/x200: Add support for ThinkLight After applying this patch, the light can be controlled like this: echo on >/proc/acpi/ibm/light echo off >/proc/acpi/ibm/light Or through sysfs at /sys/class/leds/tpacpi::thinklight Unfortunately I do not own a T400 to test this. Change-Id: I377854d6f54c5459e44626a7d7b61c513268183e Signed-off-by: Stefan Ott <stefan@ott.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2020-05-22mb/lenovo/t430s: Add support for ThinkLightStefan Ott
With this patch, the ThinkLight on the ThinkPad T430S can be controlled through the OS. The same change was done for the ThinkPad X200 in b45912f4: mb/lenovo/x200: Add support for ThinkLight After applying this patch, the light can be controlled like this: echo on >/proc/acpi/ibm/light echo off >/proc/acpi/ibm/light Or through sysfs at /sys/class/leds/tpacpi::thinklight Unfortunately I do not own a T430S to test this. Change-Id: Ifa74f5373a6305d1237e7de6da35028e68f1e99c Signed-off-by: Stefan Ott <stefan@ott.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2020-05-22mb/lenovo/t420s: Add support for ThinkLightStefan Ott
With this patch, the ThinkLight on the ThinkPad T420S can be controlled through the OS. The same change was done for the ThinkPad X200 in b45912f4: mb/lenovo/x200: Add support for ThinkLight After applying this patch, the light can be controlled like this: echo on >/proc/acpi/ibm/light echo off >/proc/acpi/ibm/light Or through sysfs at /sys/class/leds/tpacpi::thinklight Unfortunately I do not own a T420S to test this. Change-Id: I245acf81b34abccf7bcb04126275ab8b154135d5 Signed-off-by: Stefan Ott <stefan@ott.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2020-05-22mb/lenovo/t520: Add support for ThinkLightStefan Ott
With this patch, the ThinkLight on the ThinkPad T520 can be controlled through the OS. The same change was done for the ThinkPad X200 in b45912f4: mb/lenovo/x200: Add support for ThinkLight After applying this patch, the light can be controlled like this: echo on >/proc/acpi/ibm/light echo off >/proc/acpi/ibm/light Or through sysfs at /sys/class/leds/tpacpi::thinklight Unfortunately I do not own a T520 to test this. Change-Id: Iffc5dd2f23ee4896da633c18cbbf22c9e448edf1 Signed-off-by: Stefan Ott <stefan@ott.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2020-05-22mb/lenovo/t530: Add support for ThinkLightStefan Ott
With this patch, the ThinkLight on the ThinkPad T530 can be controlled through the OS. The same change was done for the ThinkPad X200 in b45912f4: mb/lenovo/x200: Add support for ThinkLight After applying this patch, the light can be controlled like this: echo on >/proc/acpi/ibm/light echo off >/proc/acpi/ibm/light Or through sysfs at /sys/class/leds/tpacpi::thinklight Unfortunately I do not own a T530 to test this. Change-Id: I94d239b65e6e8546a27f751d569681a4e68a4109 Signed-off-by: Stefan Ott <stefan@ott.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2020-05-22mb/lenovo/t430: Add support for ThinkLightStefan Ott
With this patch, the ThinkLight on the ThinkPad T430 can be controlled through the OS. The same change was done for the ThinkPad X200 in b45912f4: mb/lenovo/x200: Add support for ThinkLight After applying this patch, the light can be controlled like this: echo on >/proc/acpi/ibm/light echo off >/proc/acpi/ibm/light Or through sysfs at /sys/class/leds/tpacpi::thinklight Unfortunately I do not own a T430 to test this. Change-Id: I1fb1a9d3a84ce12ab9e3f22a699afbfd7cd1688f Signed-off-by: Stefan Ott <stefan@ott.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2020-05-22mb/pcengines/apu1/platform_cfg.h: Unset UsbRxMode to avoid platform reset issuePiotr Kleinschmidt
On PC Engines apu1 there were issues with cold reset. Platform hangs in boot path after performing reset using CF9h. CB:10549 (amd/sb800: Make UsbRxMode per-board customizable) mentions a similar issue, and added a configuration macro for it. That error is also described in AMD SB800 Family Product Errata, section 15 USB Resets Asynchronously With Port CF9h Hard Reset. This workaround simply non-execute USB configuration during boot and hence no reset via CF9h is done. TEST=perform multiple cold resets and see if platform boots Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com> Change-Id: Ie6cebcfc4b77e121ef44a25fa81377eb5e1f0644 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41627 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-22mb/lenovo/x220: Add support for ThinkLightStefan Ott
With this patch, the ThinkLight on the ThinkPad X220 can be controlled through the OS. This was initially done for the X201 in f63fbdb6: mb/lenovo/x201: Add support for ThinkLight. After applying this patch, the light can be controlled like this: echo on >/proc/acpi/ibm/light echo off >/proc/acpi/ibm/light Or through sysfs at /sys/class/leds/tpacpi::thinklight Unfortunately I do not own an X220 to test this. Change-Id: Icead793694475e2f63353690203790ab7ce7c597 Signed-off-by: Stefan Ott <stefan@ott.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40668 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-22mb/lenovo/t420: Add support for ThinkLightStefan Ott
With this patch, the ThinkLight on the ThinkPad T420 can be controlled through the OS. The same change was done for the ThinkPad X200 in b45912f4: mb/lenovo/x200: Add support for ThinkLight After applying this patch, the light can be controlled like this: echo on >/proc/acpi/ibm/light echo off >/proc/acpi/ibm/light Or through sysfs at /sys/class/leds/tpacpi::thinklight Unfortunately I do not own a T420 to test this. Change-Id: I4f9a9937a45995b72a9712919316e95bb8f82f45 Signed-off-by: Stefan Ott <stefan@ott.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-22mb/google/volteer: Add SoundWire codecs to volteer variantDuncan Laurie
Enable drivers for SoundWire codecs and define the topology in the devicetree for the volteer variant with the SoundWire daughter board connected. +------------------+ +-------------------+ | | | Headphone Codec | | Intel Tigerlake | +--->| Realtek ALC5682 | | SoundWire | | | ID 1 | | Controller | | +-------------------+ | | | | Link 0 +----+ +-------------------+ | | | Left Speaker Amp | | Link 1 +----+--->| Maxim MAX98373 | | | | | ID 3 | | Link 2 | | +-------------------+ | | | | Link 3 | | +-------------------+ | | | | Right Speaker Amp | +------------------+ +--->| Maxim MAX98373 | | ID 7 | +-------------------+ This was tested by booting the firmware and dumping the SSDT table to ensure that all SoundWire ACPI devices are created as expected with the properties that are defined in coreboot under \_SB.PCI0: HDAS - Intel Tigerlake HDA PCI device HDAS.SNDW - Intel Tigerlake SoundWire Controller HDAS.SNDW.SW01 - Realtek ALC5682 - Headphone Codec HDAS.SNDW.SW13 - Maxim MAX98373 - Left Speaker Amp HDAS.SNDW.SW17 - Maxim MAX98373 - Right Speaker Amp BUG=b:146482091 Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I7782059807416369e0e1ba0d4d7c79dcab0fcbc5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40894 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-22mb/google/volteer: Add overridetree.cb for volteer variantDuncan Laurie
Instead of only using the baseboard devicetree add a placeholder overridetree for volteer and refer to it in Kconfig. This will allow us to add the volteer specific devices here instead of at the baseboard level. BUG=b:146482091 Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I7788a5473fc2275a9791fb27e0e4018a0efcd0f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40893 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-22drivers/soundwire/alc5682: Support Realtek ALC5682 SoundWire deviceDuncan Laurie
The ALC5682 headset codec can be connected over SoundWire and be configured for mainboards to use: - Data Port 0 and Bulk Register Access is supported - Data Ports 1-4 are supported as both source and sink The data port and audio mode properties are filled out as best as possible with the datasheet as a reference. The ACPI address for the codec is calculated with the information in the codec driver combined with the devicetree.cb hierarchy where the link and unique IDs are extracted from the device path. For example this device is connected to master link ID 0 and has strap settings configuring it for unique ID 1: chip drivers/soundwire/alc5682 register "desc" = ""Headset Codec"" device generic 0.1 on end end This driver was tested with the volteer reference design by booting and disassembling the runtime SSDT to ensure that the devices have the expected address and properties. Device (SW01) { Name (_ADR, 0x000021025D568200) Name (_DDN, "Headset Codec") Name (_DSD, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "mipi-sdw-sw-interface-revision", 0x00010000 }, [...] }, ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), Package () { Package () { "mipi-sdw-port-bra-mode-0", "BRA0" }, Package () { "mipi-sdw-dp-0-subproperties", "DP0" }, Package () { "mipi-sdw-port-audio-mode-0", "MOD0" }, Package () { "mipi-sdw-dp-1-source-subproperties", "SRC1" }, Package () { "mipi-sdw-dp-1-sink-subproperties", "SNK1" }, [...] } } Name (BRA0, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "mipi-sdw-bra-mode-bus-frequency-configs", Package () { 0x000F4240, [...] } }, [...] } } Name (DP0, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "mipi-sdw-bra-flow-controlled", Zero }, [...] }, ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), Package () { Package () { "mipi-sdw-port-bra-mode-0", "BRA0" } } } Name (MOD0, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "mipi-sdw-audio-mode-bus-frequency-configs", Package () { 0x000F4240, [...] } }, [...] } } Name (SNK1, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "mipi-sdw-data-port-type", Zero }, [...] }, ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), Package () { Package () { "mipi-sdw-port-audio-mode-0", "MOD0" } } } Name (SNK1, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "mipi-sdw-data-port-type", Zero }, [...] }, ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), Package () { Package () { "mipi-sdw-port-audio-mode-0", "MOD0" } } } } BUG=b:146482091 Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I488dcd81d2e66a6f2c269ab7fa9f7ceaf2cbf003 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40891 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-22drivers/soundwire/max98373: Support MAX98373 SoundWire deviceDuncan Laurie
The MAX98373 smart speaker amp can be connected over SoundWire and be configured for mainboards to use: - Data Port 0 and Bulk Register Access is not supported - Data Port 1 is the 32bit data input for the speaker path - Data Port 3 is the 16bit data output for I/V sense ADC path The data port and audio mode properties are filled out as best as possible with the datasheet as a reference. The ACPI address for the codec is calculated with the information in the codec driver combined with the devicetree.cb hierarchy where the link and unique IDs are extracted from the device path. For example this device is connected to master link ID 1 and has strap settings configuring it for unique ID 3. chip drivers/soundwire/max98373 register "desc" = ""Left Speaker Amp"" device generic 1.3 on end end This driver was tested with the volteer reference design by booting and disassembling the runtime SSDT to ensure that the devices have the expected address and properties. Device (SW13) { Name (_ADR, 0x000123019F837300) Name (_DDN, "Left Speaker Amp") Method (_STA) { Return (0x0F) } Name (_DSD, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "mipi-sdw-sw-interface-revision", 0x00010000 }, [...] }, ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), Package () { Package () { "mipi-sdw-port-audio-mode-0", "MOD0" }, Package () { "mipi-sdw-dp-1-sink-subproperties", "SNK1" }, Package () { "mipi-sdw-dp-3-source-subproperties", "SRC3" }, } } Name (MOD0, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "mipi-sdw-audio-mode-bus-frequency-configs", Package () { 0x00753000, [...] } }, [...] } } Name (SNK1, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "mipi-sdw-data-port-type", Zero }, [...] }, ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), Package () { Package () { "mipi-sdw-port-audio-mode-0", "MOD0" } } } Name (SRC3, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "mipi-sdw-data-port-type", Zero }, [...] }, ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), Package () { Package () { "mipi-sdw-port-audio-mode-0", "MOD0" } } } } BUG=b:146482091 Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I3f8cb2779ddde98c5df739bd8a1e83a12a305c00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-22soc/intel/tigerlake: Provide SoundWire controller propertiesDuncan Laurie
The Intel Tigerlake SoundWire controller has 4 master links which are configured differently depending on the external crystal oscillator which is connected to the PCH. This function will read the PCH PMC EPOC register to determine the frequency and then fill out the master link entries with the correct table values. The frequency is also provided directly in a custom "ip-clock" property which will be added to the link descriptor and passed to the OS driver so it can know the clock rate of the master. BUG=b:146482091 Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I98b7df21210c29cd8defeff648f2c2207d629295 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-22drivers/intel/soundwire: Add Intel SoundWire controller driverDuncan Laurie
This driver provides support for Intel SoundWire controllers. It is intended to be used by multiple Intel SoCs and relies on retrieving controller/master information from the SoC itself. As such it provides a function that must be implemented by the SoC to fill out this structure. The Intel SoundWire driver in the Linux kernel expects firmware to inform it which master links are unused by adding a custom property to the link descriptor. This is done by looking for any children attached to the device that use each link and disabling the ones that are unused. Mainboards will enable this driver and define the controller in devicetree.cb in order provide the required ACPI tables, but the mainboard should not need to provide any configuration itself as that should all come from the SoC directly. This was tested with the volteer board by adding this controller and a codec to devicetree.cb and ensuring that the properties are all present, including the custom properties for the device clock and quirk mask for disabled links. Device (SNDW) { Name (_ADR, 0x40000003) Name (_CID, Package () { "PRP0001", "PNP0A05" }) Name (_DDN, "Intel SoundWire Controller") Name (_DSD, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "mipi-sdw-sw-interface-revision", 0x00010000 }, Package () { "mipi-sdw-master-count", 0x04 } }, ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), Package () { Package () { "mipi-sdw-link-0-subproperties", "LNK0" }, Package () { "mipi-sdw-link-1-subproperties", "LNK1" }, Package () { "mipi-sdw-link-2-subproperties", "LNK2" }, Package () { "mipi-sdw-link-3-subproperties", "LNK3" }, } } Name (LNK0, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "mipi-sdw-clock-stop-mode0-supported", One }, [...] Package () { "intel-sdw-ip-clock", 0x0249F000 }, Package () { "intel-quirk-mask", Zero }, } } [...] } BUG=b:146482091 Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I4b4f843a7e5ea170b070a1697c8eedc7c103e127 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-22soc/intel/tigerlake: Add definition for PMC EPOCDuncan Laurie
The PMC EPOC register indicates which external crystal oscillator is connected to the PCH. This frequency is important for determining the IP clock of internal PCH devices. Add definitions that allow this register to be read and extract the crystal frequency, and a helper function to extract and return this as the defined enum. BUG=b:146482091 Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I959fe507f3dbf93b6176b333a9e725ed09f56328 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40887 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-21mb/google/volteer: set DRAM Max Cycle Time to 15Nick Vaccaro
The DRAM Max Cycle Time (tCKmax) for Samsung's K4UBE3D4AA-MGCL DRAM part should be set to 0xF. BUG=b:157178553, b:156555863 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot a SKU4 volteer to the kernel and run "memtester 6G 100" and verify it completes successfully without error and does not crash. Change-Id: Id95b19fe261e3f57a52a43055acab99af66b14ab Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41634 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-21mb/google/volteer: fix error in generic SPDNick Vaccaro
The SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex SPD contained an incorrect SDRAM Max Cycle Time (0 instead of 0x0f). After fixing that error, I noticed that two generic SPDs could be collapsed into one, so I removed one of the duplicate generic SPDs (SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_16Row_DDP_4267.spd.hex), and changed Makefile to collapse volteer's DRAM ID 2 into ID 0. BUG=b:156126658, b:156058720 TEST=Flash and boot a ripto to kernel. Also verified that ripto can boot successfully to the kernel at 4267 MT/sec with FSP built in debug mode with RMT enabled. Change-Id: Ib52bf674ebf91854d3d078015aa640aa7ee98a6f Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41345 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-21soc/amd/common/block/gpio: add API for gpio override tablePeichao Wang
This function adds support for gpio_configure_pads_with_override which: 1. Takes as input two GPIO tables -- base config table and override config table 2. Configures each pad in base config by first checking if there is a config available for the pad in override config table. If yes, then uses the one from override config table. Else, uses the base config to configure the pad. BUG=b:153456574 TEST=Build and boot dalboz BRANCH=none Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I07bfe82827d1f7aea9fcc96574d6deab9e91d503 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2153423 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41576 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-21soc/amd/picasso/chip.c: Generate ACPI nodes for PCI Bridge A and BRaul E Rangel
This node is required so we can add child ACPI nodes. BUG=b:147042464 TEST=Boot trembyle and confirm Bus A has a firmware node $ cat /sys/bus/pci/devices/0000\:00\:08.1/firmware_node/path \_SB_.PCI0.PBRA Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I18144a69ed28a913bc9a2523d69edf84a1402e7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/41546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-21soc/amd/picasso/pci_devs: Update pci_devs.h with correct valuesFurquan Shaikh
This is a squash of the following commits. The original values were wrong, and had confusing naming. soc/amd/picasso: Get rid of *_DEVID from pci_devs.h Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: I203449499840bf0a6df8bd879fb7d2e75a16b284 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2153714 src/amd/picasso: Update PCI bridge devices Orignal-Change-Id: I1fa9d52ce113eacdc5c9ba31ab46b6428a7d6ca9 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Zork: Reorganizing ACPI and adding PCI bridge configs Signed-off-by: Pranay Shoroff <pshoroff@google.com> Original-Change-Id: I1e2095567525f302dfd0bce8e39001250523180b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2063536 soc/amd/picasso: Fix soc_acpi_name() to use devfn instead of devid Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: I2486e7e0059e0528f53d5a158c9328636563fe93 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2153712 BUG=b:147042464 TEST=Build trembyle and boot to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I91bf7f9edcddf03027f8fdcaadf4e290ece10df5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-05-21ec/google/chromeec/acpi: Add CROS EC CODEC deviceYu-Hsuan Hsu
This is currently used by trembyle. Add it in a common location so other boards can use it. BUG=b:147200751 BRANCH=none TEST=Able to get ec codec on trembyle Change-Id: Ie21cd813b0e3129f1c61d2de199532b25d3c70fa Signed-off-by: Yu-Hsuan Hsu <yuhsuan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2000271 Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org> Commit-Queue: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41575 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-21ec/google/chromeec/i2c_tunnel: Fix missing constRaul E Rangel
This was missed in the refactor. BUG=b:157140753 TEST=Built trembyle Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I150e0b8a806042ef8001805eaefbce71dc1be0e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41574 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-21nb/intel/sandybridge: Use the new IOSAV struct APIAngel Pons
Now that we have created the IOSAV API, we can put it to good use. Drop all the helper macros and replace them with struct constructs. Tested with BUILD_TIMELESS=1, ASUS P8Z77-V LX2 remains unchanged. Change-Id: Ib366e364df11c9bb240cdfbce418540ec715c634 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41003 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-21nb/intel/sandybridge: Drop unused parametersAngel Pons
We now use a static variable to handle the sequence length. Tested on Asus P8Z77-V LX2, still boots. Change-Id: Id3115c14336ea128264bd3945a99c52b9796d115 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-05-21nb/intel/sandybridge: Redefine IOSAV_SUBSEQUENCEAngel Pons
Instead of directly writing values to the IOSAV registers, use a struct and some helper functions to provide a cleaner interface for the IOSAV. Having IOSAV_SUBSEQUENCE refer to a static function is weird, but we will remove this macro in a follow-up that does not change the binary. Tested on Asus P8Z77-V LX2, still boots. Change-Id: I73f13c18a739c5586a7415966f9017c2335fdfd1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-05-21nb/intel/sandybridge: Truncate IOSAV subseq gapsAngel Pons
We set bit 15 of IOSAV_n_SUBSEQ_CTRL three times, but it is reserved. Since this bitfield is five bits wide, manually truncate the values so that bit 15 does not get set. Tested on Asus P8Z77-V LX2, still boots. Change-Id: Ib61b026b016b0d22e164f8817158ec5093f6bb9e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-05-21nb/intel/sandybridge: Replace macros with functionsAngel Pons
Turn `iosav_run_queue` and `iosav_run_once` into functions. Inlining them does not have any effect, as the resulting binary is identical. Tested on Asus P8Z77-V LX2, still boots. Change-Id: I7844814eeedad9b1d24f833a77c90902fa926bfe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-05-21nb/intel/sandybridge: Refactor IOSAV_RUN_ONCEAngel Pons
Turn it into a macro that looks like a function, and add another, more generic `iosav_run_queue` that covers all current use-cases. They will be replaced with functions in a follow-up to preserve reproducibility. Tested with BUILD_TIMELESS=1, ASUS P8Z77-V LX2 remains unchanged. Change-Id: I07b260b5fb111c1408ff75316dc0735a9e642ac9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-05-21nb/intel/sandybridge: Refactor IOSAV_SUBSEQUENCE againAngel Pons
To replace the register writes with assignments to struct fields, we would need to have the values as parameters of a single macro. So, split the raw value of `IOSAV_n_SP_CMD_CTRL_ch` in two parts. Note that the single command that sets bit 17 is likely wrong, but it will be fixed after refactoring. For now, we'll treat it as part of `ranksel`. Move the parameters of `ADDR_UPDATE` into the top-level IOSAV macro. Hopefully, this will be enough to replace the underlying implementation. Line length limits are not for review. Breaking the lines unnecessarily complicates search and replace operations, and wil be taken care of in subsequent commits. Tested with BUILD_TIMELESS=1, ASUS P8Z77-V LX2 remains unchanged. Change-Id: I404edbd5d90ddc2a6993f39f552480d1ef24e153 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-05-21vc/amd/fsp/picasso: Rename the fsp_ddi and fsp_pcie descriptorsRaul E Rangel
This change was missed when I ported over fsp_params.c. BUG=b:157140753 TEST=Boot trembyle to OS Fixes: 89e51e61781 ("soc/amd/picasso: Allow mainboard to provide pci ddi descriptors") Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Icdb6aebe5a3be7174170bdf37a1f379f02dcc5a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-05-21soc/amd/picasso: Add APOB NV back for non-S3Marshall Dawson
New information indicates the PSP expects the APOB NV region populated for all types of boot, and this is not a feature only used for S3. Switch over to using the MRC_CACHE flash region. Remove the Kconfig symbols for the APOB_NV base and size. Override the MRC_CACHE_SETTINGS_CACHE_SIZE to ensure the default maintains the minimum required size. Use the generated (or mainboard-specified) fmap.fmd file as an input for amdfwtool and properly match the flash region. Change the original naming for the APOB destination, which matched the PSP spec's field name, to PSP_APOB_DESTINATION. This should be more intuitive for a source code reader. The APOB address is the location in DRAM where the PSP puts its output block. BUG=b:147042464, b:153675914 TEST=Boot trembyle Original-Change-Id: Ia5ba8646deec2bd282df930f471738723063eef8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2080375 Original-Change-Id: I972d66f1817f86ff0b689f011c0c44c3fe7c8ef7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2053312 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I4550766ece462b65a6bfe6f1b747343e08e53fe5 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-21soc/amd/picasso/soc_util: change return type of soc_is_*Felix Held
All callers just check for zero/non-zero. Change-Id: I795763ce882d879d12c97b71e7a0b35423378c36 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-21soc/amd/picasso/include/soc_util: add include guardsFelix Held
Change-Id: I2de16eaa88baace28afa30345b7762353a48ab87 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41558 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-21soc/amd/picasso/southbridge: add missing soc/i2c.h includeFelix Held
soc/i2c.h gets included indirectly via chip.h and removing the chip.h in 73716d0e924080ea32274a265a8de04e009c3676 broke the build. chip.h got added back, but including soc/i2c.h directly fixes the underlying issue. Change-Id: Ic84f7b6b4447b7c335a51dc604daf8924851e555 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-21soc/intel/tigerlake: Make audio devices scan the busDuncan Laurie
The audio devices are currently set to enable static devices at their own level, but in order to supported nested SoundWire devices these drivers must instead use scan_static_bus. Without this change the device tree code will not look at children of these devices. After this change the audio device can have nested devices: device pci 1f.3 on chip drivers/intel/soundwire device generic 0 on end end end BUG=b:146482091 Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: Ibb716fbd9ffdc45f2c4bbe5e81f420ec2b13483c Reviewed-on: https://review.coreboot.org/c/coreboot/+/40886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-21acpi/device: Add a helper function to write SoundWire _ADRDuncan Laurie
This change adds a help function to write a SoundWire ACPI address object that conforms to the SoundWire DisCo Specification Version 1.0 The SoundWire address structure is defined in include/device/soundwire.h and provides the properties that are used to form the _ADR object. BUG=b:146482091 Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I6efbf52ce20b53f96d69efe2bf004b98dbe06552 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40885 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-21acpi/soundwire: Add functions to generate SoundWire propertiesDuncan Laurie
This change uses the previously added SoundWire definitions to provide functions that generate ACPI Device Properties for SoundWire controllers and codecs. A SoundWire controller driver should populate `struct soundwire_controller` and pass it to soundwire_gen_controller(). This will add all of the defined master links provided by the controller. A SoundWire codec driver should populate the necessary members in struct soundwire_codec and pass it to soundwire_gen_codec(). Several properties are optional and depend on whether the codec itself supports certain features and behaviors. The goal of this interface is to handle all of the properties defined in the SoundWire Discovery and Configuration Specification Version 1.0 so that controller and codec drivers do not need to all have code for writing standard properties. Both of these functions also provide a callback method for adding custom properties that are not defined by the SoundWire DisCo Specification. These properties may be required by OS drivers but are outside of the scope of the SoundWire specification itself. This code is tested with controller, codec, and mainboard implementations in subsequent commits. BUG=b:146482091 Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: Ib185eaacf3c4914087497ed65479a772c155502b Reviewed-on: https://review.coreboot.org/c/coreboot/+/40884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-21mb/lenovo/x230: Turn X230 into a variantBill XIE
Other variants would be added later. Change-Id: Ic6af14f0aa7a6f7378048f3c38d5713c18950366 Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41509 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-21Revert "mainboard/lenovo/x230: Add ThinkPad x230s as a variant"Bill XIE
This reverts commit 6b95507ec5b087658178a325bdc68570bc48bb20, in order to recommit and review it again. Change-Id: Id4ddf99200f77016a48d02a8421d080cea492aae Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41504 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20google/trogdor: Fix ram_code and sku_id strappingsJulius Werner
I'm not quite sure what happened when we first added the code for Trogdor strappings but something clearly seems to be wrong. First of all, on newer schematics the RAM_ID_1 pin is actually pin 19, not pin 91. It only used to be 91 on rev0. Whether that was an intentional change or someone just swapped the digits on accident at some point, we're not quite sure anymore, but it seems to be 19 going forward so that is what we should be programming. (ram_code wasn't used for anything on Trogdor rev0 so we don't care about adding backwards-compatibility for that.) The sku_id pins are also somewhat out of whack: first of all, a new SKU_ID_2 pin was added for rev1 that wasn't there on rev0. Second, SKU_ID_0 is not GPIO_114. In fact, it has never been GPIO_114. I have no idea how that number got there. Anyway, fix it. (Like with the ram_code, SKU IDs were also not used for rev0 so we won't make this backwards-compatible.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ia14ec74ec2f16ce2661f89d0d597a5477297ab69 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philip Chen <philipchen@google.com>
2020-05-20mb/purism/librem_skl: select GFX_GMA_IGNORE_PRESENCE_STRAPSMatt DeVillier
Some Librem 13v4's don't have the presence straps connected, leading libgfxinit to fail to init the internal display. Select GFX_GMA_IGNORE_PRESENCE_STRAPS since all SKL/KBL Librems have an internal display so there's no adverse effect. Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: Ib9d281b7d495c4f9a5c6fc5fdb8042b0fcbda745 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41417 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20drivers/intel/gma: Add override for presence strapsMatt DeVillier
A handful of boards do not properly implement the presence straps, leading libgfxinit to fail to detect an attached display. Add an override, defaulting to N, which can be set for affected boards. Add a section to the documentation detailing the option and its usage. Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: I43c61d67147878887658b23d90fb1c0b91e7a2af Reviewed-on: https://review.coreboot.org/c/coreboot/+/41416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-05-20drivers/intel/gma: License libgfxinit glue code under GPL v2Nico Huber
Change-Id: I7a78e16512369cbaada4399dbb855ade358ff046 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2020-05-20mb/google/endeavour: chrontel: fix interrupt and compat stringJeff Chase
The devicetree declares the chrontel interrupt as GpioInt so the GPIO needs to be configured as such instead of routing directly to APIC. Also update the compatible string to conform to kernel standards. BUG=b:146576073 TEST=install ch7322 driver; send commands using cec-ctl and verify that the interrupt handler is called. Change-Id: I737d951db135c53deb0f3cb956f0d0f275082251 Signed-off-by: Jeff Chase <jnchase@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-20tigerlake: enable DPTF functionality for volteerSumeet R Pawnikar
Enable DPTF functionality for volteer platform BRANCH=None BUG=b:149722146 TEST=Built and tested on volteer system Change-Id: I385fb409ccd291d97369295ff99f21c9430880f9 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41427 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20soc/intel/tigerlake: Add TCSS devices to soc_acpi_name()Duncan Laurie
Add ACPI device names for TCSS devices which were not already defined which match those declared in the DSDT at acpi/tcss.asl. Change-Id: I6a79da7dd78c73345986c12d6ffe467cd4322e05 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-20soc/mediatek/mt8183: Set CA and DQ vref range to correct valueHuayang Duan
The CA vref should alway select range[1]. But in fast calibration flow, we missed the range selection and caused the CA vref to use the range[0] value. The DQ vref should select correct range that corresponds to current frequency, that is for 1600Mbps, 2400Mbps to select range[1], for 3200Mbps and 3600Mbps to select range[0]. Refer to the 'JESD209-4 - Low Power Double Data Rate 4X(LPDDR4X).pdf', used MR12 to set Vref(CA) levels, used MR14 to set VREF(DQ) levels. MR12 range[0] values from 15.0% to 44.9%, range[1] values from 32.9% to 62.9%, MR14 range[0] and range[1] values same as MR12. BUG=b:153614919 BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: Ie7680b1bf0c29c946d18e3b27626ce6f31c4216b Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40525 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20drivers/emulation/qemu/bochs: Rewrite driverPatrick Rudolph
Support MMIO mapped BOCHS interface supported since qemu 3.0. This allows to use multiple virtual GPUs by specifying: qemu -device bochs-display -device bochs-display ... Tested on qemu. std, qxl, vmware and multiple bochs displays are working fine. Change-Id: Ib0eba4815942625ce4859946efccca500301bb65 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Himanshu Sahdev <sahdev.himan@gmail.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
2020-05-20soc/intel/tigerlake: Move pmc_soc_set_afterg3_en to pmutilTim Wawrzynczak
pmc.c was included in the SMM object, but only needed the one function, pmc_soc_set_afterg3_en. pmutil.c was already doing power management- related functionality, and was included in SMM, so moving pmc_soc_set_afterg3_en to pmutil.c allows pmc.c to be removed from the SMM build. Change-Id: I87f65fd10d35f1f75516e804501d5319b81a0383 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41407 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20soc/intel/tigerlake: Move PMC PCI resources under PMC deviceTim Wawrzynczak
Historically in coreboot, the PMC's fixed PCI resources were described by the System Agent (the MMIO resource), and eSPI/LPC (the I/O resource). This patch moves both of those to a new Intel SoC-specific function, soc_pmc_read_resources(). On TGL, this new function takes care of providing the MMIO and I/O resources for the PMC. BUG=b:156388055 TEST=verified on volteer that the resource allocator is aware of and does not touch these two resources: ("PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1") Also verify that the MEM resource is described in the coreboot table: ("BIOS-e820: [mem 0x00000000fe000000-0x00000000fe00ffff] reserved") Verified the memory range is also untouchable from Linux: ("system 00:00: [mem 0xfe000000-0xffffffff] could not be reserved") Change-Id: Ia7c6ae849aefaf549fb682416a87320907fb3fe3 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41385 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20device/pci_device: Add notion of "hidden" PCI devicesTim Wawrzynczak
On some SoCs, there are PCI devices that may get hidden from PCI enumeration by platform firmware. Because the Vendor ID reads back as 0xffffffff, it appears that there is no PCI device located at that BDF. However, because the device does exist, designers may wish to hang its PCI resources off of a real __pci_driver, as well as have it participate in ACPI table generation. This patch extends the semantics of the 'hidden' keyword in devicetree.cb. If a device now uses 'hidden' instead of 'on', then it will be assumed during PCI enumeration that the device indeed does exist, and it will not be removed as a "leftover device." This allows child devices to be enumerated correctly and also PCI resources can be designated from the {read,set}_resources callbacks. It should be noted that as of this commit, there are precisely 0 devices using 'hidden' in their devicetree.cb files, so this should be a safe thing to do. Later patches will begin moving PCI resources from random places (typically hung off of fixed SA and LPC) into the PMC device (procedure will vary per- platform). Change-Id: I16c2d3e1d1433343e63dfc16856cff69cd815e2a Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-20mb/google/volteer: Fix camera dsdt config for ov2740Daniel Kang
Link frequency and a format was not correct for volteer proto 2 ov2740 user-facing camera. The link frequency is calculated in the following way. (max frame width * max frame height * max fps * data format in bps / number of lanes / data rate) + max 35% of overhead For ov2740, (1920 * 1080 * 60 * 10 / 2 / 2) = 311Mhz. 360Mhz after adding 18% of overhead. BUG=b:148428976 BRANCH=none TEST=Build and boot volteer proto 2 board. Start a camera app and check user-facing camera functionalities. Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Change-Id: I3b51826e123dec394c1b4eb9a1c5b64b8b11459e Reviewed-on: https://review.coreboot.org/c/coreboot/+/41157 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Dossym Nurmukhanov <dossym@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20tigerlake: update processor power limits configurationSumeet R Pawnikar
Update processor power limit configuration parameters based on common code base support for Intel Tigerlake SoC based platforms. BRANCH=None BUG=None TEST=Built and tested on volteer system Change-Id: Iccd387d78bb45ca3de73f531a901d1d3f793d7bd Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39345 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20icelake: remove unused processor power limits configurationSumeet R Pawnikar
Remove unused processor power limit configuration parameter and function call based on common code base support for Intel Icelake SoC based platform. BRANCH=None BUG=None TEST=Built for icelake based dragonegg board. Change-Id: Id8923f2c176092b6f7acfbfb079587f88258dce8 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41236 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20mainboard/volteer: Update Aux settings for Port 0Brandon Breitenstein
On Volteer port 0 (MB PORT) does not have a retimer so the port needs to be configured for the SOC to handle Aux orientation flipping. This requires 2 changes setting the TcssAuxOri UPD to 1 for port 0 (Bit 0) and configuring AUXP and AUXN GPIOs to Native Function 6 so SOC can control the orientation BUG=b:145220205 BRANCH=NONE TEST=booted Volteer proto 2 and verified that the AUX channels flip when the cable is flipped Change-Id: Ic81adc24d10322cc305bf0fa4c38514468ea0942 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-05-20soc/tigerlake: Add devicetree configurability for IomTypeCPortPadCfgBrandon Breitenstein
In order for the SOC to be able to control the Aux line orientation for Type-C ports that do not have a retimer, the IomTypeCPortPadCfg UPD needs to be configurable through devicetree to correctly set the GPIO pins that the SOC should use to flip orientation. BUG=b:145220205 BRANCH=NONE TEST=booted Volteer proto 2 and verified that the AUX channels flip when the cable is flipped Change-Id: I2e48adb624c7922170eafb8dfcaed680f008936e Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40244 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20mb/google/volteer: Enable EARLY_EC_SYNCCaveh Jalali
This enables EC software sync in romstage. BUG=b:148259137 TEST=verified EC is updated in romstage using coreboot serial console logs. Change-Id: Ibb97c1d57220f7fd74131a5aee450b1ab4b1c982 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41078 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20mb/google/deltaur: Remove WLAN PCIE settingEric Lai
Deltaur uses CNVi WLAN module, this setting is not required. BUG=none TEST=WiFi is functional in OS. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Idb23e271074c8d1e111c559695d4169af5e0d3cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/41495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-20mb/google/deltaur: Add tcss.aslEric Lai
Add tcss.asl to support TCSS power management. For the detail please refer cb:39785. BUG=none TEST=Check TBT PCIe root ports: 00:07.0/00:07.1/00:07.2/00:07.3 /sys/bus/pci/devices/bus:device:func/power suspend and active time can increase. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I432f3d6643de13b08c07e47f799c0ecdfe047de6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41506 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20soc/intel/jasperlake: Add ACPI method to get GPIO PCR PIDAamir Bohra
Add method acpi method GPID to return the GPIO PCR port ID. This method is further planned to be used for GPIO power management configuration. TEST=Build waddledoo board Change-Id: Ic45b40bbe39e303cddcc82e0e848786b7311ab64 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-20soc/intel/common/acpi: Remove gpio community rangeAamir Bohra
Remove hardcoded gpio community range, since it might differ across the SOCs. Change-Id: I79c10669f6096537d466d1abd356d58a50fcb8f5 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-20driver/i2c/max98390: Fix build error related to max98390 driverSeunghwan Kim
Fix coreboot build error with adding this driver BUG=b:149443429 BRANCH=None TEST=built without errors Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: I2d76ec72ca6ae9ac54ab05f15ea92beb645acd5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/41496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-20mb/google/deltaur: Add low power idle tableEric Lai
Add low power idle table to notify EC system is entering s0ix. BUG=none TEST=Power button and keyboard backlight are off when suspending. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Icf4dffe2bd289c15854bbad914c3b34b307254ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/41494 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20superio/winbond/w83977tf: Scope UART configuration defines more locallyPatrick Georgi
By undefining the configuration after use we're sure that nobody else comes to depend on it without us noticing. Change-Id: I7c5cfd58be643d6431989fc69cf3b397920590b9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-20mb/google/hatch: Fix Puff variants rom size from 32768 -> 16384 KBEdward O'Callaghan
Originally variants make use of a 32MB chip whereas now they use a 16MB SPI flash. Allow for the coordination of dealing with the transition between phases. V.2: Leave Puff alone at the moment due to the complexity of coordination. BUG=b:153682192 BRANCH=none TEST=none Change-Id: Ic336168ea1a0055c30f718f5540209d2cf69d029 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40897 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20soc/intel/broadwell: Mask lower 20 bits of TOLUD and TOLM in systemagent.aslFurquan Shaikh
Lower 20bits of TOLUD and TOLM registers include 19 reserved bits and 1 lock bit. If lock bit is set, then systemagent.asl would end up reporting the base address of low MMIO incorrectly i.e. off by 1. This change masks the lower 20 bits of TOLUD and TOM registers when exposing it in the ACPI tables to ensure that the base address of low MMIO region is reported correctly. Change-Id: I11b3ef8deda21930998471ab6e712da4c62f5b02 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>