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2015-11-05google/chell: Fix USB port assignmentDuncan Laurie
The PCH pin names in the schematic were incorrectly labeled. BUG=chrome-os-partner:46289 BRANCH=none TEST=build and boot on chell Change-Id: I6153137b7c04d22db5b3f00f5eaf3f400f4c344c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6f362900b0635dc392c63b25a88a7723f22b467a Original-Change-Id: If6f8744f020a35a76647366b247723b03c02991a Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/310061 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12324 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-05intel/kunimitsu, google/glados: Enable Fan control supportSumeet Pawnikar
This patch enables the Fan thermal participant device in the device tree for thermal active cooling action for DPTF on SKL-U fan based kunimitsu board. This patch defines the _ART table in dptf ASL file. With active cooling policy (_ART), we can control the fan on/off and speed. BRANCH=None BUG=chrome-os-partner:46493 TEST=Built for kunimitsu board. Tested to see that the thermal devices and the participants are enumerated and can be seen in the /sys/bus/platform/devices. Also, checked the FAN type the cooling devices enumerated in the /sys/class/thermal with sysfs interface. Change-Id: I40c540dad32beefe249f025b570c347d3ad08c36 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 82ae11643ca23e65780006f3890f1d173363b8af Original-Change-Id: If44b358052a677d13c74919f09a3eb89611fccad Original-Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/307028 Original-Commit-Ready: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Original-Tested-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/12323 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-05intel/skylake: Add Fan control supportSumeet Pawnikar
This patch adds the ASL file for Fan as cooling device /participant for thermal active cooling action for DPTF on SKL-U fan based kunimitsu board. With active cooling policy (_ART), we can control the fan on/off and speed. BRANCH=None BUG=chrome-os-partner:46493 TEST=Built for kunimitsu board. Tested to see that the thermal devices and the participants are enumerated and can be seen in the /sys/bus/platform/devices. Also, checked the FAN type the cooling devices enumerated in the /sys/class/thermal with sysfs interface. Change-Id: Iacfd9152e300ec47895c29deab2c9d4361230849 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d37a089b5196f02cb95f16083c416456e96d54a4 Original-Change-Id: I8293bfe2a2bf213b69fbb4223bbfcf508a9cf0bf Original-Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/307027 Original-Commit-Ready: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Original-Tested-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/12322 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-05nvidia/tegra210: lp0_resume: clear the MC_INTSTATUS if MC_INTMASK was 0Joseph Lo
The MC/SMMU should be resumed by the kernel. And the unexpected value in the MC_INTSTATUS should be cleared before that. Or it will cause some noisy MC interrupt once we enable the IRQ in the kernel. BUG=chrome-os-partner:46796 BRANCH=none TEST=LP0 suspend/resume test and the EMEM decode/arbitration errors should not be observed on resume. Change-Id: I5b32fa58ebcb8e7db6ffc88e13cca050753f621a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 07cb719caf40b59c5519fcf212c2fb50f006812e Original-Change-Id: I4d34905c04effd54d0d0edf8809e192283db2ca3 Original-Signed-off-by: Joseph Lo <josephl@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/309248 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Original-Commit-Queue: Joseph Lo <yushun.lo@gmail.com> Original-Tested-by: Joseph Lo <yushun.lo@gmail.com> Original-(cherry picked from commit 13cbcaf441bd762af9cf00eff24eb7709db38d95) Original-Signed-off-by: Joseph Lo <josephl@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/309497 Original-Commit-Ready: Andrew Bresticker <abrestic@chromium.org> Reviewed-on: http://review.coreboot.org/12321 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-05fsp1_1: pass ROM_SIZE to FSP for cacheable RO regionAaron Durbin
As vboot verification works on regions outside of CBFS pass the entire ROM_SIZE to FSP for creating a cacheable RO region. Additionally remove the CACHE_ROM_SIZE_OVERRIDE as it doesn't work with non-power of 2 CBFS_SIZE. In practice the entire ROM should be attempted to be cached. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados w/ a 3MiB CBFS_SIZE. Change-Id: I61404c626ab2bcfd039d6eb3c01d9c13a0928446 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 92568c630c48446b1ad9d4f22056f22e0679970c Original-Change-Id: I032e4d615d2b68d3a2e597555eb1b5034a74bf0a Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/309770 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/12260 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-05skylake: Set Pkg Power clamping bit in Power Limit MSRRizwan Qureshi
Setting the Package Power clamping bits in Power Limit MSR (MSR_PKG_POWER_LIMIT 0x610) Allows going below the OS requested P or T state for the time window specified for PL1 or PL2. BRANCH=none BUG=chrome-os-partner:47041 TEST=Built and boot on kunimitsu, load the system with Aquarium WebGL, change the power limit value from default (TDP or 15W) to any lower value note that the Pkg power comes down and also the CPU frequency is lowered. Change-Id: I9c0dd90a6660214ae142418aae8b8c5f6a739896 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b0b527991c2d26da5772700a22ff101eaf9993ef Original-Change-Id: Ia59fcfe2a14cd7f8b1e1b8e967073e67eb452f42 Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/309556 Original-Tested-by: Charulatha Varadarajan <charuprasanna@gmail.com> Original-Tested-by: Charulatha Varadarajan <charulatha.varadarajan@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/12257 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-05nb/intel/sandybridge: Limit GFX workaround to Sandy BridgeNico Huber
The touched workaround for Sandy Bridge reserves two memory regions that could cause graphics corruption if mapped by the integrated graphics device. To the best of our knowledge, the workaround is not needed for Ivy Bridge revisions. Tested on kontron/ktqm77 (Ivy Bridge): Booted Linux and checked the memory regions are not reserved. Couldn't test on Sandy Bridge, due to lack of hardware. Change-Id: I4273d1d804b490cf93c23426782eb1ffaf29f7d4 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/12326 Reviewed-by: Duncan Laurie <dlaurie@google.com> Tested-by: build bot (Jenkins)
2015-11-05cpu/microcode: Remove EXTERNAL / ADDED_DURING_BUILD variablesTimothy Pearson
There has been a concerted effort to clean up coreboot's microcode handling that has included a move away from coreboot-specific microcode file collections. As a result, the ability to specify a single microcode file to be added to the image is of less utility than before. NOTE: This patch remove the built-in external microcode feature, however the user can still specify no microcode during build and manually add the correct microcode file(s) to the CBFS image after the build is complete. Change-Id: Ifea94c21e531a74953f5a0e2f489378c20ef3b5c Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11903 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-11-05mainboard: Remove last_boot NVRAM optionTimothy Pearson
The last_boot NVRAM option was deprecated and removed in commit 3bfd7cc6. Remove the last_boot option from all affected mainboards to eliminate user confusion. Change-Id: I7e201b9cf21dfe5dda156785bad078524098626d Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12316 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2015-11-05src/amd: Increase maximum blootblock execution countTimothy Pearson
Most AMD hardware requires at minimum two warm resets when booting from S5 (power off). This is uncomfortably close to the maximum bootblock execution count, and has resulted in unstable normal/fallback operation on some machines. Increase the default max bootblock execution count before fallback to 6. This translates to roughly 2 - 3 failed boots before fallback mode will engage, with an absolute worst case of pushing the reset button 5 times to engage fallback mode in the absence of a dedicated recovery jumper. Change-Id: I1911f1b77f168835b516e6a915d5b6949f47219a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12317 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-04nb/intel/sandybridge: Add ACPI DMAR tableNico Huber
Add a DMAR table to advertise IOMMU and IRQ remapping capabilities to the OS. Tested with kontron/ktqm77. Under Linux, the table is detected and interrupt remapping is enabled automatically. Change-Id: Id6ee601a0a8543ed09c6bb8d308a3a3549fc34e5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/12195 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-04nb/intel/sandybridge: Enable basic IOMMU supportNico Huber
Sandy Bridge and Ivy Bridge processors have two IOMMU units. One for the integrated graphics controller and one for all other PCI devices. Assign resources for both IOMMUs and apply some quirks. Tested with kontron/ktqm77 and a Muen based system that makes use of the IOMMUs. Not tested on Sandy Bridge, but register dumps show the same settings that are applied here. Change-Id: I43b5e20b750e7529f448acac35de173185678fd9 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/12194 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-04sb/intel/bd82x6x: Assign unique bus/dev/fn for I/O APIC + HPETsNico Huber
Assign unique bus/dev/fn values for the I/O APIC and each HPET. The values are taken from an example DMAR table. They are used as source-id for MSI requests and as completer-id for reads from the device' MMIO space [1, 2]. The former is usefull for source-id verfication during interrupt remapping. [1] Intel 6 Series Chipset and Intel C200 Series Chipset Datasheet Document-Number: 324645 [2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) Datasheet Document-Number: 326776 Change-Id: Ib46f8cfb7d966dd1cf2b026f671bc45ffcc43d25 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/12193 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-04mainboard/asus: Increase reboot count on boards with recovery jumperTimothy Pearson
On server boards with a recovery jumper, having the fallback path less sensitive to power fluctuations or BMC issues makes sense. Increase the maximum number of boot attempts before automatic fallback to 10 on these boards. Change-Id: Iabe0b0cbf332686db8e9380a8b65a1477173599c Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12320 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-11-04ACPI: Add functions for DMAR I/O-APIC and HPET entriesNico Huber
Refactor acpi_create_dmar_drhd_ds_pci() and add similar functions for I/O-APICs and MSI capable HPETs. We violate the spec [1] here, which talks about 16-bit source-ids spread over start_bus and path entries. Intel actually uses bus/dev/fn identification for those devices too, and so do we. [1] Intel Virtualization Technology for Directed I/O Architecture Specification Document-Number: D51397 Change-Id: I0fce075961762610d44b5552b71e010511871fc2 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/12192 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-04ACPI: Make DMAR flags settableNico Huber
Add a parameter to acpi_create_dmar() for the flags field and define flags given by the spec [1]. [1] Intel Virtualization Technology for Directed I/O Architecture Specification Document-Number: D51397 Change-Id: I03ae32f13bb0061bd3b9bef607db175d9b0bc5e1 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/12191 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-04Drop SuperIO smsc/fdc37m60xStefan Reinauer
All boards using this SuperIO have been removed from the tree already. Change-Id: I52847bc2fc16b27ac0de0bc7c847221b1e5cb744 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12245 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-03arch/x86/bootblock_normal: Fix failure to buildTimothy Pearson
Fix a function call in the normal path using the original function name and arguments in code that was changed in commit 3bfd7cc6 (drivers/pc80: Rework normal / fallback selector code) This commit reworked most of the fallback / normal code, however the normal code paths were not fully tested by Jenkins, so this was missed. Change-Id: Ied66334977272a13b7a7307ff4d9f34eb22040aa Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12315 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2015-11-03drivers/pc80: Rework normal / fallback selector codeTimothy Pearson
Per IRC and Gerrit discussion, the normal / fallback selector code is a rather weak spot in coreboot, and did not function correctly for certain use cases. Rework the selector to more clearly indicate proper operation, and also remove dead code. Also tentatively abandon use of RTC bit 385; a follow-up patch will remove said bit from all affected mainboards. The correct operation of the fallback code selector approximates that of a power line recloser, with a user option to attempt normal boot that can be cleared by firmware, but never set by firmware. Additionally, if cleared by user, the fallback path should always be used on the next reboot. Change-Id: I753ae9f0710c524875a85354ac2547df0c305569 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12289 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-03cpu/amd/model_fxx: Backport PowerNow! core count fix from Family 10hTimothy Pearson
The K8 PowerNow! state generator does not generate _PSS objects for nodes other than the first CPU package. This patch backports the PowerNow! core count fixes for Family 10h to the K8 CPUs. Change-Id: I7b411ab75155dfb4bf51ae04301aa16fb2ae89f3 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12286 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-03via/cx700: remove unused #definePatrick Georgi
Change-Id: I0180e0ae2aeeffcef46a97892356f1955f581efd Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/12295 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-03cbmem: add coreboot table records for each cbmem entryAaron Durbin
In order to not expose the cbmem data structures to userland that are used by coreboot internally add each of the cbmem entries to a coreboot table record. The payload ABI uses coreboot tables so this just provides a shortcut for cbmem entries which were manually added previously by doing the work on behalf of all entries. A cursor structure and associated functions are added to the imd code for walking the entries in order to be placed in the coreboot tables. Additionally a struct lb_cbmem_entry is added that lists the base address, size, and id of the cbmem entry. BUG=chrome-os-partner:43731 BRANCH=None TEST=Booted glados. View coreboot table entries with cbmem. Change-Id: I125940aa1898c3e99077ead0660eff8aa905b13b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11757 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-11-02cpu/amd: Add initial AMD Family 15h supportTimothy Pearson
TEST: Booted ASUS KGPE-D16 with single Opteron 6380 * Unbuffered DDR3 DIMMs tested and working * Suspend to RAM (S3) tested and working Change-Id: Idffd2ce36ce183fbfa087e5ba69a9148f084b45e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11966 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-02cpu/amd/family_10h-family_15h: Use correct label for break stateTimothy Pearson
Change-Id: I07e517f239807cbe76037308f0beff80c9a6f2ba Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12101 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2015-11-02cpu/amd: Move model_10xxx to family_10h-family_15hTimothy Pearson
Change-Id: I34501d3fc68b71db7781dad11d5b883868932a60 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11965 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-02northbridge/amd/amdmct/mct_ddr3: Fix S3 suspend overrunning the stack size limitTimothy Pearson
Change-Id: Id7441dacef2e46e283d1fc99d5e5fa3f20e0d097 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11959 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-02mainboard/asus/kgpe-d16: Set DDR3 memory voltage based on SPD dataTimothy Pearson
Change-Id: I21777283ce0fd3c607951204a63ff67dc656c8cc Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11956 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-02northbridge/amd/amdfam10: Set DIMM voltage based on SPD dataTimothy Pearson
Change-Id: I67a76cf0e4ebc33fbd7dd151bb68dce1fc6ba680 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11957 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-11-02amd/olivehillplus: Tidy up devicetreeKyösti Mälkki
Some comments and leftover static USB devices whose function numbers changed. Change-Id: I4d7c7499fe436588ef7e5ae030212c2638a4505f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/12263 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-02asrock/e350m1: Add ACPI S3 supportKyösti Mälkki
To store memory configuration in SPI flash currently adds some 150 ms delay in ramstage, visible in timestamps listing at 75:cbmem post. Change-Id: I1160259054b58e9a8df2a105c730e0f4140be1f5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/12215 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-02asrock/e350m1: Match super-io GPIO configuration with vendorKyösti Mälkki
Disables mouse ps2 data/clock signals, not connected in hardware. Purpose of other GPIOs is not really known, but match them with superiotool dump taken from vendor bios. Change-Id: I7b549fbd7dd3fa4cbd507d76882b60bc324a4bd0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/12214 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-02superio/nuvoton/nct5572d: Add missing logical devicesKyösti Mälkki
While the actual pins behind these devices are not exposed on the chip, the enable registers are implemented in hardware. Allow to turn these LDNs off, like the vendor bios for asrock/e350m1 does. Change-Id: I4d6d5a8de12b09095138cacbad62b2dfbbe54028 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/12213 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-11-02mainboard/asus/kfsn4-dre_k8: Fix ramstage using Family 10h structsTimothy Pearson
Several ramstage files were inadvertently using Family 10h-specfic structures, causing unstable operation. Use the K8-specific structures instead. Change-Id: I64066dfdca83557393499b77726051e25b814381 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12290 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-10-31northbridge/amd/amdfam10: Correct S3_DATA_POS type from int to hexTimothy Pearson
This resolves a Kconfig warning. Change-Id: Ic77c8bf89613c116dfdc73572709aeb354e33b2a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12287 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2015-10-31mainboard/asus/kgpe-d16: Add initial Suspend to RAM (S3) supportTimothy Pearson
Change-Id: I7da84b064287a445fd75a947e2f96ce1ae30d3de Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11954 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2015-10-31northbridge/amd/amdfam10: Update RAM speed table with DDR3 valuesTimothy Pearson
Change-Id: I8ab7b2cd9bf36d53b744a11d32dd40c750149567 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12272 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-31southbridge/amd/sb700: Remove acpi_get_sleep_type for early CBMEMTimothy Pearson
The acpi_get_sleep_type function in SB700 ramstage is only needed for boards / CPUs that require late CBMEM initialization. Providing this function in early CBMEM-compatible boards breaks building of the ACPI S3 code due to multiple definitions of acpi_get_sleep_type. Change-Id: Ieebc2640a586812e3e2bfd410987205d64147314 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12267 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-31intel/gma: Return success for Intel int15 VGA set panel type hookKonstantin Aladyshev
One of the interrupts in intel_vga_int15_handler lacks positive return status. Write correct status to avoid error messages in log. TEST=With this change `int15 call returned error` is not shown anymore on a custom board with Intel Atom CPU, i945GME northbridge and i82801gx southbridge. Change-Id: I740b2df9bd6a7d261d89bef74b924edbb64354aa Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/12255 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-31mainboard/asus/kfsn4-dre_k8: Fix broken dual CPU package supportTimothy Pearson
The existing KFSN4-DRE support hung during ramstage while initializing AP #3 if a second CPU package was installed. After analyzing the Sun Ultra 40 M2 support code it became apparent that the K8 code cannot function correctly if sequential RAM training is disabled, and that there were a few other missing calls. This patch adds the missing calls, adjust the CAR space to an appropriate level, and explicitly defines the link numbers and connections in devicetree.cb TEST: Booted ASUS KFSN4-DRE with 2x Opteron 8222 installed. Change-Id: I96178b7367b0c13de5c9d5d90d032fb0c53639c2 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12285 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-10-31arch/x86: avoid race condition on build.hPatrick Georgi
Change-Id: I15375ac1247b7cc8d80d910a767c7f3e67eb8739 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11904 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-10-31sandybridge: Disable parallel CPU initializationNico Huber
Disable the parallel CPU initialization for model_206ax, that is Sandy Bridge and Ivy Bridge processors. We never did it the way that Intel recommends and it became unreliable with the introduction of SMM_MODULES in commit a3e41c0 Migrate 206ax to SMM_MODULES. Tested by booting kontron/ktqm77 2.6k times into Linux user space. No issues so far. Change-Id: Idffc352341419f22a36bf772534a5e11e711edf1 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/12266 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-30cpu: port amd/pi to 64bitStefan Reinauer
Change-Id: I66ef081fa1a520f0199366587800783ea1ef8719 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11023 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2015-10-30Drop SuperIO nuvoton/nct6779dStefan Reinauer
All boards using this SuperIO have been removed from the tree already. Change-Id: I57eacf2a88077d0d0bffdcf44b3c2ecbd301e625 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12242 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30Drop SuperIO ite/it8661fStefan Reinauer
All boards using this SuperIO have been removed from the tree already. Change-Id: Ifca91ae44ab222371808ff1e0027a7cbd4646b0a Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12243 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30Drop SuperIO nuvoton/nct6776Stefan Reinauer
All boards using this SuperIO have been removed from the tree already. Change-Id: Ic5604c75de249b945dca58aa904edec86558d3ec Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12241 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30Drop SuperIO nsc/pc97307Stefan Reinauer
All boards using this SuperIO have been removed already. Change-Id: I667a8d15a2d16671115f62de656b1c5c6a8259b9 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12240 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30Drop SuperIO nsc/pc8374Stefan Reinauer
All boards using this SuperIO have been removed from the tree. Change-Id: I1d13ec7c5f27e82523612af7f07fca3176953600 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12239 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30Drop southbridge intel/esb6300Stefan Reinauer
All mainboards using this southbridge have been removed from the tree already. Change-Id: I4398ef1e270bd0f36c5dd1c6ec3bfec6c2c091e6 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12238 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30Drop southbridge intel/i82801cxStefan Reinauer
All boards using this southbridge have been removed from the tree already. Change-Id: I08269931d845d1f57b34174238bcce245ad77894 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12237 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30Drop northbridge/i440lxStefan Reinauer
All boards using it have been deleted a long time ago. Change-Id: Ib1c4018ab6ec27868c0e2fdbf9c91323ead076fb Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12236 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30wakeup: Switch back to 32bit mode firstStefan Reinauer
On x86_64 we need to leave long mode before we can switch to 16bit mode. Oh joy! When's my 64bit resume pointer coming? Why didn't this get caught earlier? Seems the Asrock E350M2 didn't do Suspend/Resume? Yes, I know it's Intel syntax. Will be converted to AT&T syntax as soon as the whole thing actually works.. 8) Change-Id: Ic51869cf67d842041f8842cd9964d72a024c335f Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11106 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30Drop geode_post_code.hStefan Reinauer
It's unused and empty. Change-Id: Ieb9225083cb779b7b94ca47488dad4d7beb30a94 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12235 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30smm: 64bit fixesStefan Reinauer
Change-Id: I35dab4e66514948aafa912d993fb8d42c5a520a0 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11089 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30Drop unused code from gcc-intrin.hStefan Reinauer
Change-Id: I3df66320d0bc18221f947b47e7f09533daafabad Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11108 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30AMD mainboards: Fix 64bit BiosCallOuts.cStefan Reinauer
Change-Id: I0f3297dff47dfb44da034ac6f305dcf1981b9de1 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11080 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30cpu/amd: Fix cbtypes.h to match UINTN conventionStefan Reinauer
There are some inconsistencies in AMDs APIs between the coreboot code and the vendorcode code. Unify the API. UINTN maps to uintptr_t in UEFI land. Do the same here. Also switch the other UEFI types to map to fixed size types. Change-Id: Ib46893c7cd5368eae43e9cda30eed7398867ac5b Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/10601 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30vendorcode/amd: 64bit fixesStefan Reinauer
Change-Id: I6a0752cf0c0e484e670acca97c4991b5578845fb Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11081 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30More Hudson 64bit fixesStefan Reinauer
Change-Id: I2a6cd7ad27cb6d16dfe3267ea6fb844a5e2e20c6 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11083 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30SB900 64bit fixesStefan Reinauer
Change-Id: I5ea0f9338ccdd658b5fbec72aa35b4f80d63d4f9 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11084 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30SB700: 64bit fixesStefan Reinauer
Change-Id: Ib4b643441a5b887abf73cc55930ea9b01037f6ea Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11085 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30RD890: 64bit fixesStefan Reinauer
Change-Id: I326c070398c72a877054969d3a03e6e427edc304 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11086 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30northbridge/amd/amdmct/mct_ddr3: Add initial Suspend to RAM (S3) supportTimothy Pearson
Change-Id: Ic97567851fa40295bc21cefd7537407b99d71709 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11952 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30northbridge/amd/amdfam10: Add Suspend to RAM (S3) Flash data storage areaTimothy Pearson
Change-Id: I169fafc3a61e11c3e4781190053e57bf34502d7b Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11951 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-30Hudson: Port to 64bitStefan Reinauer
Bring http://review.coreboot.org/#/c/10582/ to Hudson Change-Id: I1ba3047699c304a769215fe901dc3511bf23199d Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11022 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30Port AGESA based northbridge code to 64bitStefan Reinauer
This is extending http://review.coreboot.org/#/c/10583/ (29e6548) to the remaining AGESA northbridge drivers. Change-Id: I6fa53b36a1420e92cb4aecb0f7b4c71541a94c71 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11021 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30mainboard 64bit fixesStefan Reinauer
Change-Id: I2b4338927d56a2075c0a95f2ab981f1beaf69cc7 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11082 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30cpu/amd/model_fxx: Clear out unused / stale MTRRs in ramstageTimothy Pearson
This mirrors a similar commit made to Family 10h support in changeset 11966 file model_10xxx_init.c TEST: Booted ASS KFSN4-DRE with 1x Opteron 8222 Change-Id: I760ef27be00aed11c0ac21b9bd741189f4b05834 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12250 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-30cpu/amd/model_fxx: Enable FIDVID code on Socket F K8Timothy Pearson
The existing Kconfig option for FIDVID was permanently set to "no" due to Kconfig stopping at the first matching value set when parsing the file. This patch moves the conditional set above the unconditional set, resolving the issue. Change-Id: Ic19f68f6b17943f9133ff32a9b6538f0bf942eca Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12224 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-30cpu/amd/model_fxx: Backport APIC code and debug aids from Family 10hTimothy Pearson
Backport a handful of debugging routines and the extended APIC initialization code from Family 10h support to K8 support. Change-Id: I08cc5c8bc65635ce09a69e32940dd7edd8d3be87 TEST: Booted ASUS KFSN4-DRE with 1x Opteron 8222 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12251 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30cpu/amd/car: Honor BKDG recommendations for DisFillP in CARTimothy Pearson
The recommendation to set DisFillP during CAR initialization on K8 NPT CPUs was ignored. The consequences of this are largely unknown; fix up coreboot to follow the recommendations. Change-Id: Ide512bbc1d9aa284179628e2aa598ef5475e8eeb Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12249 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30mainboard/asus/m2n-e|msi/ms9282: Clean up FIDVID mistakesTimothy Pearson
These two mainboards contained trivial mistakes related to FIDVID that broke build when FIDVID was enabled. Change-Id: Ie7bec77f26ec37eada21308984db4a9fd7a1866f Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12226 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30southbridge/nvidia/ck804: Fix FIDVID build failure on CK804Timothy Pearson
Change-Id: I74c285ff86993898e0120170cf07f48ef4dc9612 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12225 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30cpu/amd/model_fxx: Fix invalid P-state power valuesTimothy Pearson
Change-Id: Ifdb1d1f267af289d962effe1150c7bc0a39cb5d2 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12233 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-30mainboard: Add initial K8-compatible version of the KFSN4-DRETimothy Pearson
This is a clone of the original Family 10h-compatible ASUS KFSN4-DRE board, modified for basic K8 support to allow for future K8 Socket F Opteron testing. TEST: Booted KFSN4-DRE with 1 Opteron 8222 processor KNOWN ISSUES: * Second CPU package fails to initialize AP This prevents use of a secondary CPU package * Second memory channel of at least CPU package #0 does not function (crash at CAR handoff) Change-Id: I591725babe685fa50a0d7473b17005fbd258056e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12212 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30cpu/amd/model_fxx: Add Socket F CPU ID mappingsTimothy Pearson
Change-Id: If1df7f3ae9661fae49557c07def397b36b1d38f0 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12210 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30Revert "device/pciexp_device: Tune PCIe bridges before scanning children"Kyösti Mälkki
This reverts commit 785b3eb6e8fcafb38395eec00f4f0fc0e906c7cc. The commit re-tuned the upstream link again, it does not tune secondary side. Change-Id: I9be70e95b06ceff99beba8a7c7eb6402b32fcca1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/12253 Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2015-10-29rockchip/rk3288: If we fail to read the EDID 5 times in a row, it's an errorDouglas Anderson
Previously if we tried to read the HDMI EDID several times and failed each time then we're return from hdmi_read_edid() with no error. Then we'd interpret whatever happened to be in memory at the time as an EDID--not so great. Let's actually look at the error. BRANCH=none BUG=chrome-os-partner:46256 TEST=Monitor that can't read EDID not shows that in the log Change-Id: I6e64b13ae3f8c61bf1baaa1cfc8b24987bd75cf3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 44bda7311f9ee677235e4dc8db669226518b3895 Original-Change-Id: I9089755b75118499bec37bdb96d1635f66252e65 Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/309298 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/12231 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-29mainboard/asus/kgpe-d16: Add nvram option to enable/disable IEEE 1394Timothy Pearson
Change-Id: I4f0f6c1cb1fad5b65f196dc6b443252a0ecc70a1 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11947 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-10-29commonlib/region: add xlate_region_deviceAaron Durbin
There are cases where one region_device needs to be accessed using offset/sizes from one address space that need the offset translated into a different address space for operations to take place. The xlate_region_device provides an offset that is subtracted from the incoming transaction before deferring to the backing access region. Change-Id: I41d43924bb6fbc7b4d3681877543209e1085e15c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12227 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-10-29nb/intel/sandybridge/gma: add disable functionPatrick Rudolph
Issue observed: In a multi GPU setup (IGD and PEG) the system still uses the IGD. CONFIG_ONBOARD_VGA_IS_PRIMARY has no effect on Sandy/Ivy Bridge. Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 * ATI Radeon HD4780 Problem description: The GMA is missing a disable function. Problem solution: Add a GMA disable function. Deactivate PCI device until remaining multi GPU issues are resolved. Do not claim VGA decode any more. Final testing results: The system is able to boot using the PEG device as primary VGA device. Change-Id: I52af32df41ca22f808b119f3a4099849c74068b3 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: http://review.coreboot.org/11919 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-10-29amd/cimx/sb800/late.c: Add comment in `sb800_init()`Paul Menzel
Add a comment explaining what `abcfg_reg(0xc0, 0x01FF, 0x0F4)` does. This is a follow-up for commit 24501cae (AMD cimx/sb800: Initially enable all GPP ports). Change-Id: I5ac263ee088d36a7f7a2d03c1454ed647faa7147 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/12190 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-29amd/sb700: clean up recommended changesMartin Roth
This patch addresses changes requested to commit 85c39a4c (southbridge/amd/sb700: Add Suspend to RAM (S3) support) - remove unused/commented out code - remove unnecessary guards around acpi_get_sleep_type() Change-Id: I2878e038d2f9f8d182615e1f4a75ddce5c45d5f3 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12206 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Tested-by: build bot (Jenkins)
2015-10-29mainboard/asus/kgpe-d16: Properly configure SR5690 southbridge PIKE slotTimothy Pearson
Change-Id: I2f1373905ffd6460ac3c7c21738e2e2a9aa2e463 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11992 Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Tested-by: build bot (Jenkins)
2015-10-29southbridge/nvidia/ck804: Fix boot hang on ASUS KFSN4-DRE w/ K8 CPUTimothy Pearson
Change-Id: Ie4b74f6d63c323ca499a6890defe9b8afe83ea96 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12209 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-29pcengines/apu1: adapt comments in devicetree to boardFelix Held
Change-Id: I09d2449af9c1562f4f3d5af1e8764b82b6550007 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: http://review.coreboot.org/12223 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-10-29northbridge/amd/amdk8: Improve DIMM detection debuggingTimothy Pearson
Change-Id: I93534082d379369352e367c9c24b213513a543b2 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12211 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-10-29mainboard: Convert #ifdef to IS_ENABLED in get_bus_conf.cTimothy Pearson
Change-Id: I254e9e9e65519edcf4d3f1ecc385af16d18c2367 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12208 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-29smmhandler: on i945..nehalem, crash if LAPIC overlaps with ASEGPatrick Georgi
This mitigates the Memory Sinkhole issue (described on https://github.com/xoreaxeaxeax/sinkhole) by checking for the issue and crashing the system explicitly if LAPIC overlaps ASEG. This needs to happen without a data access (only code fetches) because data accesses could be tampered with. Don't try to recover because, if somebody tried to do shenanigans like these, we have to expect more. Sandybridge is safe because it does the same test in hardware, and crashes. Newer chipsets presumably do the same. This needs to be extended to deal with overlapping TSEG as well. Change-Id: I508c0b10ab88779da81d18a94b08dcfeca6f5a6f Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/11519 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-10-28vboot2: Fix flows for TPM_E_MUST_REBOOTFurquan Shaikh
While migrating from vboot1 to vboot2, the tpm_init was moved out of vboot library and implemented in coreboot. However, while doing this, the initial factory flow was missed. We need to ensure following flow for tpm_init: 1. Perform tpm_init 2. If tpm_init fails, set secdata_context flag to indicate to vboot that tpm needs reboot. 3. Call vb2_api_phase1 4. If vb2_api_phase1 returns error code saying boot into recovery, continue booting into recovery. For all other error codes, save context if required and reboot. [pg: everything but step 2 was already done, so this upstream commit is quite minimal] CQ-DEPEND=CL:300572 BUG=chrome-os-partner:45462 BRANCH=None TEST=Verified behavior on smaug. Steps to test: 1. Reboot into recovery 2. tpmc clear 3. Reboot device Expected Behavior: Device should reboot after Enabling TPM. Should not enter recovery Confirmed that the device behaves as expected. Change-Id: I72f08d583b744bd77accadd06958c61ade298dfb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 85ac93137f3cfb28668dcfa18dfc773bf910d44e Original-Change-Id: I38ab9b9d6c2a718ccc8641377508ffc93fef2ba1 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/300570 Original-Commit-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/12205 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-10-28google/glados: Set the type-c flex port to max USB2 settingsDuncan Laurie
Change the tuning setting for the type-c port that is over the flex cable to use the max possible drive strength. Also fix up the comments to indicate what Type-c port goes where instead of just referring to them by number. BUG=chrome-os-partner:45367 BRANCH=none TEST=build and boot on glados Change-Id: Iebcffc9ab95d56289258017248c273090c88bb06 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 824ca87c4bf556d493dc8cdec561f37ab135cd2d Original-Change-Id: I081623bbb1b0f39f1569b9f5cf7933abefe202b3 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/309010 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12204 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-28intel/skylake: Add USB2 port config for max settingsDuncan Laurie
Add a new USB2_PORT_MAX with the max possible settings (56mV) for the TX and Pre-emphasis bias values. Also fix the settings for the detachable tablet config to match the skylake HSIO tuning guide as it was incorrect before. BUG=chrome-os-partner:45367 BRANCH=none TEST=build and boot on glados Change-Id: Id9ccc683fe92c962095347e0d1a0afeb082c821f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e5d56831e75f98a3c75ed333e4b79b1a37f14792 Original-Change-Id: Ia2e3e93236f1463201f83a1cae28349de2836110 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/308729 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12203 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-28google/chell: Set DPTF critical temperature to 99CDuncan Laurie
If we boot without a heatsink then DPTF may power off the system when it starts if the CPU temp is >90C. Since TJmax is 100C set the critical threshold to just below that value. Also remove the active thresholds as chell does not have a fan. This will have DPTF use the default values but without the DPTF active policy it shouldn't get used. BUG=chrome-os-partner:46694 BRANCH=none TEST=build and boot on chell w/o a heatsink Change-Id: Id9e8f2c547468db8ad0edaf6c362a9a9bb5b95a2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 23d9117d5d7a4b44fc2298352eba133747f8e246 Original-Change-Id: Ib8e074098e3956efeed0f9b7f8b16652658db374 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/308728 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12202 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-28google/lars: Add new mainboarddavid
This is based on kunimitsu with minor changes: - update GPIOs based on schematic - update SPD data for memory config - disable ALS BUG=None TEST=emerge-lars coreboot Change-Id: Id1c9edfe3cc665e90683344f1662de2e65caf766 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3201aa573a77fcad3b6b1335d23eb4c2a09c1708 Original-Change-Id: Ifae446e4668569b6100b29bc1f52b0fea1df2952 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/308283 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Bernie Thompson <bhthompson@chromium.org> Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/12201 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-28google/lars: Copy from intel/kunimitsudavid
Change-Id: I95129e6f519735e236c9c13b16e21df25b9ea607 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/12200 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-28vboot: check vb2_shared_data flags for manual recoveryDaisuke Nojiri
vboot handoff should look at flags in struct vb2_shared_data when translating flags to VBSD_BOOT_REC_SWITCH_ON because VBSD_BOOT_REC_SWITCH_ON is supposed to indicate whether manual recovery was triggered or not while vb2_sd->recovery_reason will be able to provide that information only in some cases after CL:307586 is checked in. For example, this fixes a recovery loop problem: Without this fix, vb2_sd->recovery_reason won't be set to VB2_RECOVERY_RO_MANUAL when user hits esc+refresh+power at 'broken' screen. In the next boot, recovery_reason will be set to whatever reason which caused 'broken' screen. So, if we check recovery_reason == VB2_RECOVERY_RO_MANUAL, we won't set vb_sd->flags to VBSD_BOOT_REC_SWITCH_ON. That'll cause a recovery loop because VbBootRecovery traps us again in the 'broken' screen after not seeing VBSD_BOOT_REC_SWITCH_ON. BUG=chromium:501060 BRANCH=tot TEST=test_that -b veyron_jerry suite:faft_bios Change-Id: I69a50c71d93ab311c1f7d4cfcd7d454ca1189586 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d9679b02f6d21ed903bb02e107badb0fbf7da46c Original-Change-Id: I3da642ff2d05c097d10db303fc8ab3358e10a5c7 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/307946 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: http://review.coreboot.org/12199 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-28cpu/intel/fsp_model_206ax: Load microcode in corebootMartin Roth
Intel's FSP 1.0 platforms are moving back to loading microcode in coreboot instead of in the FSP. Update the Ivy Bridge chips to be compatible. Change-Id: I4af155dea51e89ab9595b922c95ceade29a2dc52 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12196 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: York Yang <york.yang@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-28jpeg: add jpeg_fetch_size()Patrick Georgi
This aids the fuzzer test case. Change-Id: Ic7d43b76cf5660e085e7b3b13499de0358c13197 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/12181 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2015-10-28mainboard/asus/kgpe-d16: Add initial support for the KGPE-D16Timothy Pearson
As of this commit S3 suspend does not work on any K10 boards, including this board. Change-Id: Idd3971422fb2473bff7c60fe8d8161d6e20808ed Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11946 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-27southbridge/amd/sb700: Add Suspend to RAM (S3) supportTimothy Pearson
Change-Id: Ic643e31b721f11a90d8fb5f8c8f8a3b7892c0d73 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11949 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 11:56:12 +0000