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2003-09-23update hypertransport setup for khepriStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1124 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-23fix hypertransport setup for quartet.Stefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1123 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-23make coherent ht setup capable of non-standard link configurationsStefan Reinauer
(i.e. with CPU1 not connected to ACROSS link of CPU0) git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1122 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-11update Config.lb and add khepri ht chainStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1111 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-11add new target for DSPACE DS1006 card, make quartet auto.c all verboseStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1109 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-09remove old config files, adopt to new config method. fix resource map (?)Stefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1107 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-08update SOLO code (untested but compiling and pretty much complete!?!)Stefan Reinauer
drop old configuration method. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1102 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-04- Include hypertransport.h in hypertransport.cEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1101 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-04- Remove dead argument to hypertransport_scan_chainEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-03moved init_timer() to static initializationGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-03cosmeticsStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1098 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-02- 1.1.4Eric Biederman
Major restructuring of hypertransport handling. Major rewerite of superio/NSC/pc87360 as a proof of concept for handling superio resources dynamically Updates to hard_reset handling when resetting because of the need to change hypertransport link speeds and widths. (a) No longer assume the boot is good just because we get to a hard reset point. (b) Set a flag to indicate that the BIOS triggered the reset so we don't decrement the boot counter. Updates to arima/hdama mptable so it tracks the new bus numbers git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1097 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-02- Major update of the dynamic device tree so it can handleEric Biederman
* subtractive resources * merging with the static device tree * more device types than just pci - The piece to watch out for is the new enable_resources method that was needed in all of the drivers git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1096 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-01- Update the version number to 1.1.2 and update the NEWS fileEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1095 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-01- Add back in the hard reset code from the freebios1 tree.Eric Biederman
This allows generic code to reset the box. - Update the hypertransport code to automatically calculate link widths and freequencies, and to call hard_reset if neecessary for the changes to go into effect. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1094 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-01- Updates to config.g so that it works more reliably and has initial supportEric Biederman
for paths - Renamed some configuration variables SMP -> CONFIG_SMP MAX_CPUS -> CONFIG_MAX_CPUS MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS - Removed some dead configuration variables MAX_CPUS -> CONFIG_MAX_CPUS MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS SMP -> CONFIG_SMP FINAL_MAINBOARD_FIXUP SIO_BASE SIO_SYSTEM_CLK_INPUT NO_KEYBOARD USE_NORMAL_IMAGE SERIAL_CONSOLE USE_ELF_BOOT ENABLE_FIXED_AND_VARIABLE_MTRRS START_CPU_SEG DISABLE_WATCHDOG ENABLE_IOMMU AMD8111_DEV - Removed some assembly files that are no longer needed killed src/southbridge/amd/amd8111/smbus.inc killed src/southbrideg/amd/amd8111/cmos_boot_failover.inc killed src/ram/ramtest.inc - Updates to config.g so that it works more reliably and has initial support for paths - Renamed some configuration variables SMP -> CONFIG_SMP MAX_CPUS -> CONFIG_MAX_CPUS MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS - Removed some dead configuration variables MAX_CPUS -> CONFIG_MAX_CPUS MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS SMP -> CONFIG_SMP FINAL_MAINBOARD_FIXUP SIO_BASE SIO_SYSTEM_CLK_INPUT NO_KEYBOARD USE_NORMAL_IMAGE SERIAL_CONSOLE USE_ELF_BOOT ENABLE_FIXED_AND_VARIABLE_MTRRS START_CPU_SEG DISABLE_WATCHDOG ENABLE_IOMMU AMD8111_DEV - Removed some assembly files that are no longer needed killed src/southbridge/amd/amd8111/smbus.inc killed src/southbrideg/amd/amd8111/cmos_boot_failover.inc killed src/ram/ramtest.inc killed src/sdram/generic_dump_spd.inc killed src/sdram/generic_dump_spd.inc - Updated the arima/hdama to build with the new configuration system - Updated config.g to list all of the variables with make echo git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-08-28add first bunch of newisys khepri files.Stefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1090 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-08-28more motherboard specific cleanupsStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-08-28cleaning out motherboard specific changes from the generic directories.Stefan Reinauer
Moving tyan resource map to tyan directory. Making IOMMU for hammer choosable via ENABLE_IOMMU git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1088 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-08-27support for new mobos and fixesRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1087 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-08-26fixed irq tables for hdamaRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1086 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-08-07more quartet fixesStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1085 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-08-07fix resource map for quartetStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1084 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-08-07fix quartet buildStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1083 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-08-06add XIP_ROM_[BASE|SIZE] to newconfig for quicker bootupStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1080 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-08-05fixup. SMP works fine.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1078 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-08-05missing file chip.hRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1071 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-08-05now needed.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1070 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-08-04patches from Yh Lu. Tested and working on HDAMARonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1068 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-08-04Commits for the new config static device design, to allow more than one staticRonald G. Minnich
cpu of a certain type and to eliminate the cpu p5 cpu p6 cpu k7 nonsense in the old config files. Next step is to hook into Eric's pci device stuff. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1067 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-08-04- Fix poor resource allocation estimate.Eric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1066 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-08-01- Remove useless definitionsEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1064 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-08-01- Update cpufixup so we support more than 4GB of memoryEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1063 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-08-01- Update raminit.c so it works properly for multiple cpusEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1062 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-31fix for newconfigRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1061 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-30make solo target build againStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1060 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-30updates from YhLu, plus fixes for PPC/K8 issues.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1059 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-28PPC 4XX supportGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1056 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-28use longsGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1055 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-28PVR supportGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1054 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-28added new routinesGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-28deal with different reset vector addressesGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-28made timer more genericGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1051 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-28added ppc_ to function namesGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1050 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-28CPU_OPT for cpu specific flagsGreg Watson
_RESET to specify reset vector address (ppc4xx reset vector is at end of memory, rather than at beginning of ROM) CONFIG_SYS_CLK_FREQ to specify frequency of system clock (needed for ppc4xx clock speed calculation) git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1049 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-28corrected cpu path, added clock.oGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1048 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-28cpus have vendors nowGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1047 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-28moved extern to chip.hGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1046 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-28Fix for RAMBASE.Ronald G. Minnich
remove unused make.base.lb git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1045 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-25change it so linuxbios.rom is the final target.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1044 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-25Fix for ROM_SIZE to ROM_SECTION_SIZERonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1043 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-25one last fix.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1042 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-25fix bugs ron added with new optionsRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1040 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-25Mods for YhLu to enable calls for mainboard init.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1038 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-25YhLu's changes to resolve several memory and other problems.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1036 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-25Corrections for Config.lb for new tool.Ronald G. Minnich
Bump up debugging messages and reduce the size of memory test until that is running correctly. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1035 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-24moved cpu code to cpu/ppc/mpc74xxGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1031 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-24*** empty log message ***Greg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1030 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-24#if was reversedGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1028 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-24slight changes to static initializationGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1027 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-24new register formatGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1026 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-23ep405pc boardGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1020 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-23added post-pci passGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1019 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-23allow logging at spew levelGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1018 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-23code was brokenGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1017 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-23new static configurationGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1016 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-23get CONFIGURE rightGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1011 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-23fixed definesGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1010 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-23static devicesGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1009 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-23*** empty log message ***Greg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1008 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-23new register formatGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1007 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-23getting HDAMA to build.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1005 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-23updates for hdama and other things.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1004 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-23updated for new code.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1003 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-21- First pass at code for generic link width and size determinationEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@999 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-21- First pass at s2880 support.Eric Biederman
- SMP cleanups (remove SMP only use CONFIG_SMP) - Minor tweaks to romcc to keep it from taking forever compiling - failover fixes - Get a good implementation of k8_cpufixup and sizeram for the opteron git-svn-id: svn://svn.coreboot.org/coreboot/trunk@998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-21new chip stuffGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@994 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-21new chip configureGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@992 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-21* update quartet target to latest SMP changes.Stefan Reinauer
* remove dead code from coherent_ht.c * add ldtstop code for link speed changes git-svn-id: svn://svn.coreboot.org/coreboot/trunk@991 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-21more chip stuffGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@990 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-21more chip stuffGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@989 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-20chip stuffGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@988 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-19- Major cleanup of the bootpathEric Biederman
- Changes to allow more code to be compiled both ways - Working SMP support git-svn-id: svn://svn.coreboot.org/coreboot/trunk@987 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-18new config formatGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@984 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-17add AMD Quartet targetStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@980 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-17moved generate_row from coherent_ht.c to board specific auto.c filesStefan Reinauer
due to different routing defaults of different boards. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@979 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-17new config formatGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@977 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-17dont export sandpoint optionsGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@976 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-17sandpoint optionsGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@974 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-17- Update Config so we now have the proper number of cpusEric Biederman
- Remove some debugging code from auto.c - Update coeherent_ht.c so we get the proper broadcast routes. - Fix the dram probing code. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@973 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-17- Get the correct routing tables entries for the hdama's onboard nicsEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@972 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-17Config.lb for this new partRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@971 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-17- Remove excess line from pci_device.cEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@970 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-17- Remove $Id: from crt0.S.lbEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@969 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-17- Implement an enable method for pci devices.Eric Biederman
- Add initial support for the amd8131 - Update the mptable to something possible - hdama/Config add the amd8131 southbridge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@968 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-17- pci_device.c fixes for generic pci bridges to zero the unused portion of ↵Eric Biederman
bridge resources - coherent_ht.c remove dead idle loop. - raminit.c Enable a 64MB mmio window just below 4GB git-svn-id: svn://svn.coreboot.org/coreboot/trunk@967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-16fix some glitches in cht code: always enable routing on node7, plus do ↵Stefan Reinauer
masking right when setting cpucnt/nodecnt git-svn-id: svn://svn.coreboot.org/coreboot/trunk@966 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-16- ldscripb.lb remove another $Id: line..Eric Biederman
- romcc_io.h Add include guards. - hdama/Config nothing really but I have been moving the setting back and forth between 1 and 2 cpus - auto.c Changed the enabled debugging comments. This almost works with 2 cpus - coherent_ht.c First pass at getting this right. It can now find 2 cpus and place them in some semblance of a working state. - raminit.c Fix problems with 4GB of ram. Disable some of the debugging code. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@965 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-16- Commit a binutils safe version of reset16.incEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-14- Compile fixesEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@963 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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