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The family variable was not being set yet for skylake, add this
to the current boards.
BUG=chromium:551715
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: Icf175e4ce89cb47b9eabce1399eb3ef29e7a607f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7e379402f38634eb0204e03b616111fff9515cec
Original-Change-Id: Ia31fb04b5c22defc71a0c02d9fa1eff93ccbc49d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/311213
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12390
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The net names are offset by 1. My board is not stable enough
to really test all of these yet...
BUG=chrome-os-partner:46289
BRANCH=none
TEST=emerge-chell coreboot
Change-Id: I65e17323f2819eca130c1bf0ccbc3ea0ec2f383f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 327194dcfcb3a5c9f431b1a2e26c230cb2b2a48b
Original-Change-Id: I50e9ea091bb6e6a1da3a9434ae0fbf3f652fa354
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/311113
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12389
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: If7b6062fd4df16ae2864b5d9adfdd19c4356691c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12400
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
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Change-Id: I5fee5f5fdf30ab6e3c4f94ed3e54ea66c1204352
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11980
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
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This patch adds CC6 power save support to the AMD Family 15h
support code. As CC6 is a complex power saving state that
relies heavily on CPU, northbridge, and southbridge cooperation,
this patch alters significant amounts of code throughout the
tree simultaneously.
Allowing the CPU to enter CC6 allows the second level of turbo
boost to be reached, and also provides significant power savings
when the system is idle due to the complete core shutdown.
Change-Id: I44ce157cda97fb85f3e8f3d7262d4712b5410670
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11979
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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A wrong function name made an #ifdef'd code path not compile. Fix that,
and also use IS_ENABLED() to make sure that such issues won't come up
again there.
Change-Id: Iccb98842dde498cce32cd86a770e22a506ad4cc2
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/12296
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This is an attempt at better compatibility with driver matching etc.
Change-Id: I26eccbe17a31ba2042d0fe1bb424d9f380c0a82e
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-on: http://review.coreboot.org/12351
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Pulled getpir from the attic and used data provided by it
to create the table a bit more programmatically and
added the AGP slot so the video card is given an IRQ
Change-Id: Id3dc1a77ac6382405f5f36707994287e84e1168b
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-on: http://review.coreboot.org/12350
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Up to now the GPIO set up macros for input sets up GPIOs to be
mapped to memory space while macros for outputs sets up GPIOs
to be mapped to legacy io space. This patch adds two additional
macros for legacy output definition and changes the old macros
to memory space mapping.
In addition, the intel/minnowmax mainboard is modified to use
the legacy macros for outputs to ensure this mainboard stays
unchanged in terms of functionality.
TEST=Booted siemens/mc_tcu3 and ensured GPIO set up in linux.
Change-Id: I99e98d31e1a59e63c58d536f2c493d6dcbfd1e75
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/12340
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: Iae1cbe7d3a6471561abfdb8e182bc764c38bb222
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11978
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
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Change-Id: Ibeb35da3395dc77a21a2f92f0e1d0845be53d175
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11977
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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DRAM training accounts for most of the romstage startup time, yet
if the hardware configuration has not changed from the previous boot
the previously discovered training values are still valid. Use them
if the DIMM configuration has not changed since the last boot.
The SPD values of all installed DIMMs are hashed and stored in the S3
resume data area of the main system Flash device. If a DIMM is changed
the hash will almost certainly change as well, forcing retraining on next
boot.
Change-Id: I37ed277b16476d38e4af76c6ae827a575c6b017d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11976
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Change-Id: Ib6d1be64691cf5a1c0b7464284fbae4e583f383e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12402
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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When we first added ARM support to coreboot, it was clear that the
bootblock would need to do vastly different tasks than on x86, so we
moved its main logic under arch/. Now that we have several more
architectures, it turns out (as with so many things lately) that x86 is
really the odd one out, and all the others are trying to do pretty much
the same thing. This has already caused maintenance issues as the ARM32
bootblock developed and less-mature architectures were left behind with
old cruft.
This patch tries to address that problem by centralizing that logic
under lib/ for use by all architectures/SoCs that don't explicitly
opt-out (with the slightly adapted existing BOOTBLOCK_CUSTOM option).
This works great out of the box for ARM32 and ARM64. It could probably
be easily applied to MIPS and RISCV as well, but I don't have any of
those boards to test so I'll mark them as BOOTBLOCK_CUSTOM for now and
leave that for later cleanup.
BRANCH=None
BUG=None
TEST=Built Jerry and Falco, booted Oak.
Change-Id: Ibbf727ad93651e388aef20e76f03f5567f9860cb
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/12076
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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In order to have a proper runtime-modifyable page table API (e.g. to
remap DRAM after it was intialized), we need to remove any external
bookkeeping kept in global variables (which do not persist across
stages) from the MMU code. This patch implements this in a similar way
as it has recently been done for ARM32 (marking free table slots with a
special sentinel value in the first PTE that cannot occur as part of a
normal page table).
Since this requires the page table buffer to be known at compile-time,
we have to remove the option of passing it to mmu_init() at runtime
(which I already kinda deprecated before). The existing Tegra chipsets
that still used it are switched to instead define it in memlayout in a
minimally invasive change. This might not be the best way to design this
overall (I think we should probably just throw the tables into SRAM like
on all other platforms), but I don't have a Tegra system to test so I'd
rather keep this change low impact and leave the major redesign for
later.
Also inlined some single-use one-liner functions in mmu.c that I felt
confused things more than they cleared up, and fixed an (apparently
harmless?) issue with forgetting to mask out the XN page attribute bit
when casting a table descriptor to a pointer.
BRANCH=None
BUG=None
TEST=Compiled Ryu and Smaug. Booted Oak.
Change-Id: Iad71f97f5ec4b1fc981dbc8ff1dc88d96c8ee55a
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/12075
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Among its other restrictions (which are noted in a comment above the
function prototype and stay in place), our makeshift fine-grained page
table support for ARM32 has the undocumented feature that it relies on
a global bookkeeping variable, causing all sorts of fun surprises when
you try to use it from multiple stages during the same boot. This patch
redesigns the bookkeeping to stay completely inline in the (persistent)
TTB which should resolve the issue. (This had not been a problem on any
of our platforms for now... I just noticed this because I was trying to
solve the same issue on ARM64.)
BRANCH=None
BUG=None
TEST=Booted veyron_jerry. Mapped a second fine-grained memory range
from romstage, confirmed that it finds the next free spot and leaves the
bootblock table in place.
Change-Id: I325866828b4ff251142e1131ce78b571edcc9cf9
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/12074
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Change-Id: Ia5c00f07de81d409e6215cc0944d64d00e47b795
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12401
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
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Change-Id: I4e0a52eb90910604f8640ad7533b5d71be6c8e20
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11983
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: I8ee757d07c82c151b36def6b709163ff144d244f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11984
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I5323462dcb8a4e84786be38cc85070eb48d4a31d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11982
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I147284e6a435f4b96d6821a122c1f4f9ddc2ea33
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11981
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Upon bootup the hardware reads at minimum 256 * 16 bytes (4Kb, or 32KB) over
I2C on a system with all DIMM slots populated. If even one of those reads
has a single flipped bit in it (due to EMI, cross coupling with another trace,
or just poor margins on some cheap DIMM) the system will hang and require a
hard reset. In practice I've seen failure rates as high as 1 failed boot in
50 due to this issue, granted with cheap DIMMs, but even so retrying the read
resolves the corruption issue.
I2C is not designed for continuous data transmission with high reliability, and
there is no hardware error checking, therefore a single retry when transferring
this amount of data makes sense.
Change-Id: Ifab63eca2233c63a6a42ab8b7e742f8e47fb2a09
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11975
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.
Change-Id: I36c2b0290f95f4c0f6bed6a7427fb3aab968d4da
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12376
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
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Change-Id: I1ad581454e08f7a24395f50623f29ec14e07f5fb
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12360
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.
Change-Id: I866440595a0a38b65ce037dc9a1f7e4c02c6beb3
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12385
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.
Change-Id: I41d1f9eac2f4c37bec4d046a68f3f1cf95b51703
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12384
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.
Change-Id: Idd6011302d2164275fe01954ad3e4e13474ec7a9
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12382
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.
Change-Id: I915d5dd4a095b84023a19c9a0474634320207a08
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12381
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.
Change-Id: Icfdcc5d6043987e22ef9b4db84847d62c91bd305
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12380
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.
Change-Id: Ie44a3c46b82e77028921339c50ae4c176e38055c
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12379
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Rev F's SPD address is different from other revision.
0 1
Channel A A0 A2
Channel B A4 AC
Change-Id: I620d1f9c295f9a0e30e3821ea36a05dd9f7d3495
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/12342
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.
Change-Id: I9099f90c073197cc95bb9630788016b7b8221922
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12383
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.
Change-Id: Ifd1dfa35ae13ec01d932250994086edebece924d
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12377
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
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As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.
Change-Id: Idfec80ce79c906717e679d6576dc94e71da994c9
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12378
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
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As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.
Change-Id: Ibf3849dcd7a1ef1d8bc5dfc864172a8254a64b6f
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12375
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.
Change-Id: I460208c18964857be73d9a4449ecfd872ccad98a
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12374
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.
Change-Id: I4a942150590fb69ff97279ff2b48b3be83abafa4
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12372
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.
Change-Id: I5b0fb633b7611e2a69aeb33cd31ca8fd4a83592c
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12369
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.
Change-Id: I180fd548e8f45fc94e5086159c0e3e9465c74598
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12386
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
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As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.
Change-Id: I1913ca75aa6f2a2c6b97d49faaabc16afd2799f5
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12371
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.
Change-Id: If0e0a7f69b77cf4bcab4c0dcb58a153485380069
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12373
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
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As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.
Change-Id: I8854c31f242c13b6f91901452f7eb7ce0ef0b255
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12370
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.
Change-Id: Ic71d8a9137f0bd2a0cc7571a43f9dddb50168d8d
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12368
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
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All boards using this SuperIO have been removed from the tree already.
Change-Id: I3c43a431d92d76b6ed3ec72b203d3e80925cadea
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12247
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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NOTE: This commit switches CacheBase in CAR to use the DCACHE_RAM_BASE
Kconfig variable. There should be no functional difference between
the existing code and the new code, however hardware verfication is
encouraged on lesser used architectures such as AMD Geode.
Change-Id: Ia2e8f99be9df388e492a633c49df21ca1c57ba13
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11970
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Change-Id: Ic16a927a3f1fc6f7cb1aea36a8abe8cc1999cb52
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11973
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The build was changed to remove usage of microcode .h files when
all of the .h files were converted to binary. This is still
needed for some builds when microcode binaries aren't in the
blobs tree.
Change-Id: Ia323c90efe8aa0b8799fc5cce6197509e466a105
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12333
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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The obsolete and removed getpir utility remarked in its output that the
data is autogenerated. The tool was removed because it wasn't very
reliable, so there's no need to point that anymore.
Change-Id: I5d624931ba7872b1fefa8fa3c270ae7367e069fa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/12354
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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'edid->hdmi_monitor_detected' would indicate whether the monitor
interface is HDMI or DVI.
BRANCH=none
BUG=chrome-os-partner:43789
TEST=Previously, my LG monitor couldn't show dev screen. But now I can see
dev screen have been posted normally.
Change-Id: Id71f051b2cd792712e52bee7a763db383c1962a8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 88101589a22d06f0bc25e0750b2862cf66b55391
Original-Change-Id: I157861d327926b834e1e8606b0b676f413491c70
Original-Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/309056
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/12346
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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HDMI driver need to know whether the monitor is DVI
or HDMI interface, so this commit just introduce a
new number 'hdmi_monitor_detected' to struct edid.
There were four bits to indicate the monitor interfaces,
it's better to take use of that. But those bits only
existed in EDID 1.4 version, but didn't persented in
the previous EDID version, so I decided to detect the
hdmi cea block.
BRANCH=none
BUG=chrome-os-partner:43789
TEST=When mickey connect with HDMI monitor, see 'hdmi_monitor_detected' is 'true'.
When mickey connect with DVI monitor, see 'hdmi_monitor_detected' is 'false'.
Change-Id: I1a4f1410e1cce1474ffae858db161a18578cac3a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 409f041805d9fdff2d49faa1a3a262cf4dc609c2
Original-Change-Id: Ife770898b0f2b4f58b8259711101a0cab4a5e4ac
Original-Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/309055
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/12345
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Copy from the CL https://chromium-review.googlesource.com/#/c/307028/
(I40c540dad32beefe249f025b570c347d3ad08c36)
BRANCH=None
BUG=None
TEST=emerge-lars coreboot
Change-Id: I131fb729661f0f3bfd198cdf238c627bf38a46a5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 70d471c507d12924466979c93742944975a03f27
Original-Change-Id: I0128dc65110ba363185db9c2aca5cdb140c344c2
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/310394
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/12344
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
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The on-board eMMC is designed as 2.0. If it is set as 3.0,
it can not be detected.
Change-Id: I9fd913f76535e65c1672924ebdeba3d35dea59cc
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11748
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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1. Bettong Rev A-E are DDR3, Bettong Rev F is DDR4.
2. DDR4 uses different memory configuration in AGESA.
Pass memory configuration parameters in agesawrapper_amdinitpost.
3. Tested on Rev C and Rev F.
Both of them can boot to Windows 8 and have the correct memory size.
Change-Id: Ia0d35ebf1b65c399abc3777ee6bdb107437a4345
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11733
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Bettong uses 3 GPIO(5-7) pins to identify board.
The GPIO ports are mapped to MMIO space.
The GPIO value and board version are mapped as follow:
GPIO5 GPIO6 GPIO7 Version
0 0 0 A
0 0 1 B
......
1 1 1 H
Change-Id: I72df28043057d8c4ccc4a2e645011ca5379e9928
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11732
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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The RAM voltages can be set per socket, which contains two nodes.
Only reset the allowed voltages per socket before processing a new socket and
not after every node.
Change-Id: Ia0e47676c7a3eebd56a17ab6de0e9690bf8cf703
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/12297
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
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Change-Id: I3fbb897feb68d899e5dec075a09d0dd605eca5ce
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/12309
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The Ultra 40 M2 is a dual Socket F workstation with MCP55/IO55 chipset,
DME1737 superio and onboard Firewire. This board port is for family
0Fh (K8) processors.
Due to existing bugs, having memory on the second node will cause
raminit to fail.
Change-Id: I5b62ade908ffeb80e22f14edbe4c1ec04880bd30
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/12304
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: Ia275a697caa73168553b5d588d54df651e0539d7
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/12303
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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TEST: Booted T400 with Intel/ATI hybrid graphics in integrated
mode with native Intel graphics init and verified integrated
panel framebuffer functionality in SeaBIOS and Linux.
Change-Id: I37e72c5dad0d7ab3915cc3d439ae9a4a9b3787e3
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/9319
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
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This is required for flashrom to work...
Change-Id: Icc0a52e0ca103c897d96fa8f3cf83b30780c7b49
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-on: http://review.coreboot.org/12349
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This is in AP code, fixed in preparation for copying
the same check to BSP.
Change-Id: I0750919d9fdb3d4e6666221ad82097e0c479cf14
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-on: http://review.coreboot.org/12359
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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All the deleted mainboard files contain no code besides some print
statements denoting, that the init is executed.
If such statements are desired, this should be done in common code so it
does not have to be added to each mainboard.
Therefore, also delete files with just print statements.
Change-Id: I379e4b1e1b1725648c6231bc6954ac3cc655a596
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/12355
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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The Intel Stargo2 is a communications device reference design.
This mainboard uses the Sandy/Ivy Bridge and is paired with
the i89xx southbridge. The FSP package is available from Intel:
https://intel.com/fsp.
Change-Id: I75c527f0eb0de1ee6ac13d8d276d7cf23b5b120c
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/12170
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Add an additional Sandy(Ivy)bridge processor socket.
Change-Id: I7eff7183d0c003e61fdda5350579f4d3dec7504d
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/12168
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: York Yang <york.yang@intel.com>
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The Intel i8900 Super I/O is similar to the previously
supported i3100.
Change-Id: I9a5b651cab35991c3c3e09fc4668d35ca2d221ba
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/12169
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: York Yang <york.yang@intel.com>
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The Intel northbridge must be paired with a southbridge. Add
the ii89xx southbridge header based on the config setting.
Change-Id: Ied708006310efaba31afe6977ab7e57fe4e5ceec
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/12167
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
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The Intel i89xx is a communications chipset that pairs with
Sandy(Ivy)bridge processors. It has a lot in common with
the bd82x6x chipset, but fewer devices and options.
Change-Id: I11bcd1edc80f72a1b2521def9be0d1bde5789a79
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/12166
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The Winbond WPCD376I is a desktop Super I/O often selected on
Intel mainboards. The support is similar to other Winbond and NSC SIOs.
Based on output from superiotool -d.
Change-Id: Ib4786b410b1d83606e8d79a9f686c14a5d25cadf
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/12165
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Add two functions to set a memory mapped GPIO to a given value.
TEST=Booted siemens/mc_tcu3 board and confirmed GPIO-value after
using this functions.
Change-Id: Idc14c5d4049487e60040cc294ba0cea363d998a6
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/12341
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I76f74ed4ae383f8b1f57eaaa2e025035002430f2
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11967
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The RDK amd/db-ft3b-lc board will use this for on-board DDR3.
Change-Id: I2ffd38e7e949d3a60487e91188ddaab04b03d4b2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/12358
Tested-by: build bot (Jenkins)
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
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Building with Clang without option -Wno-unused-function causes building
error. I don't know why GCC doesn't have that issue.
------------
coreboot/src/commonlib/fsp1_1_relocate.c:47:23: error:
unused function 'le8toh' [-Werror,-Wunused-function]
static inline uint8_t le8toh(uint8_t byte)
^
1 error generated.
------------
Change-Id: Iecd1e84e4321446412ef68d65dc918baf1ab45ce
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/12339
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: York Yang <york.yang@intel.com>
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The additional local data storage requirements of the full DDR3
DRAM training algorithm make a BSP stack overrun a distint
possibility. Increase the BSP stack size to compensate.
Change-Id: I51af31442f2b77cb64a4b788751ccc7186acb283
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11972
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
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Change-Id: I5c12b5ef8564402601634e9f3528bbf9303e0b33
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11969
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
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Change-Id: I019f94b99d2fc33e19567acecaaad93813ab6b04
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11968
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
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Since, SMP support is removed for ARM64, there is no need for CPU
initialization to be performed via device-tree.
Change-Id: I0534e6a93c7dc8659859eac926d17432d10243aa
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/11913
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
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As ARM Trusted Firmware is the only first class citizen for
booting arm64 multi-processor in coreboot remove SMP
support. If SoCs want to bring up MP then ATF needs to be
ported and integrated.
Change-Id: Ife24d53eed9b7a5a5d8c69a64d7a20a55a4163db
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/11909
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
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As ARM Trusted Firmware is the only first class citizen for
booting arm64 multi-processor in coreboot remove spintable
support. If SoCs want to bring up MP then ATF needs to be
ported and integrated.
Change-Id: I1f38b8d8b0952eee50cc64440bfd010b1dd0bff4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11908
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
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With the removal of secmon from coreboot there are no
power down operations required. As such remove the
A57 power down support.
Change-Id: I8eebb0ecd87b5e8bb3eaac335d652689d7f57796
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11898
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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It's been decided to only support ARM Trusted Firmware for
any EL3 monitor. That means any SoC that requires PSCI
needs to add its support for ATF otherwise multi-processor
bring up won't work.
Change-Id: Ic931dbf5eff8765f4964374910123a197148f0ff
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11897
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
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Change-Id: Id69b339bbed03d7a1f64aa5935721e7e8aab62fa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/12265
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
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EHCI functions have moved.
Change-Id: I47e79d3790b272b0fc322d534de733889679622b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/12264
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
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Change-Id: I887f9eb890f1f1c6f88b7984f0520bd17be8b88b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/12284
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Do not mix open-source AGESA and binaryPI includes.
Change-Id: I1e43334ba8d5a17d3580f81e023ca2c8caf86f7c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/12283
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
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This cast only hides errors in matching the API properly.
Change-Id: I9b878ab997b8ff087a7209f94522646b10b94bf6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/12271
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This cast only hides errors in matching the API properly.
Change-Id: Ic396dfb572a50ac5ce5c1c83424e1f17f15bad1d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/12270
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Fixed resources have to be declared early.
Change-Id: I03bb846e0685d47e0befc20bf7bc14c06694cb66
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/12262
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
|
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Fixed resources have to be declared early.
Change-Id: Iedd92e5e7ee43a833bda48e6377da1b78fa4bd81
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/12261
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
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PMIOxEE is for setting USB3 power rail. Set it to S0, otherwise
going into hibernation can not be wake up.
Change-Id: I692497bad24d745738d670897e725a568c1db114
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11373
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
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"-u" is only for GNU cp. Cp of BSD and Solaris don't
take this option.
It is not necessary to compare the files before copying.
Change-Id: I60cf57991275db0e075278f77a95ca5b8b941c7f
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11601
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The plugged devices on PCIe should use IOAPIC2 instead of standard
IOAPIC1. The entries in IOAPIC2 count from the end of IOAPIC1.
The unchanged code worked because the OS uses MSI instead APIC.
To test that, boot linux with parameter pci=nomsi and see if the devices
like NIC work well as they do without the booting parameter.
Change-Id: I893e73f2aab3227381e44406fa285613e4ba2904
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11374
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Ic3cdfa6086a45aa231aa817d5ef6998823589818
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7108
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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- CACHE_ROM is no longer used in the coreboot code. It was removed in
commit 4337020b (Remove CACHE_ROM.)
- CAR_MIGRATION is also no longer used in coreboot code - it was removed
in commit cbf5bdfe (CBMEM: Always select CAR_MIGRATION)
- MARK_GRAPHICS_MEM_WRCOMB was removed in
commit 30fe6120 (MTRR: Mark all prefetchable resources as WRCOMB)
Change-Id: I8b33a08c256f6b022e57e9af60d0629d9a3ffac8
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12327
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The PCH pin names in the schematic were incorrectly labeled.
BUG=chrome-os-partner:46289
BRANCH=none
TEST=build and boot on chell
Change-Id: I6153137b7c04d22db5b3f00f5eaf3f400f4c344c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6f362900b0635dc392c63b25a88a7723f22b467a
Original-Change-Id: If6f8744f020a35a76647366b247723b03c02991a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/310061
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12324
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This patch enables the Fan thermal participant device
in the device tree for thermal active cooling action
for DPTF on SKL-U fan based kunimitsu board.
This patch defines the _ART table in dptf ASL file.
With active cooling policy (_ART), we can control the
fan on/off and speed.
BRANCH=None
BUG=chrome-os-partner:46493
TEST=Built for kunimitsu board. Tested to see that the
thermal devices and the participants are enumerated and
can be seen in the /sys/bus/platform/devices. Also,
checked the FAN type the cooling devices enumerated
in the /sys/class/thermal with sysfs interface.
Change-Id: I40c540dad32beefe249f025b570c347d3ad08c36
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 82ae11643ca23e65780006f3890f1d173363b8af
Original-Change-Id: If44b358052a677d13c74919f09a3eb89611fccad
Original-Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/307028
Original-Commit-Ready: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Tested-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/12323
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This patch adds the ASL file for Fan as cooling device
/participant for thermal active cooling action for DPTF
on SKL-U fan based kunimitsu board.
With active cooling policy (_ART), we can control the fan
on/off and speed.
BRANCH=None
BUG=chrome-os-partner:46493
TEST=Built for kunimitsu board. Tested to see that the
thermal devices and the participants are enumerated and
can be seen in the /sys/bus/platform/devices. Also,
checked the FAN type the cooling devices enumerated
in the /sys/class/thermal with sysfs interface.
Change-Id: Iacfd9152e300ec47895c29deab2c9d4361230849
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d37a089b5196f02cb95f16083c416456e96d54a4
Original-Change-Id: I8293bfe2a2bf213b69fbb4223bbfcf508a9cf0bf
Original-Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/307027
Original-Commit-Ready: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Tested-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/12322
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The MC/SMMU should be resumed by the kernel. And the unexpected value
in the MC_INTSTATUS should be cleared before that. Or it will cause
some noisy MC interrupt once we enable the IRQ in the kernel.
BUG=chrome-os-partner:46796
BRANCH=none
TEST=LP0 suspend/resume test and the EMEM decode/arbitration errors
should not be observed on resume.
Change-Id: I5b32fa58ebcb8e7db6ffc88e13cca050753f621a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 07cb719caf40b59c5519fcf212c2fb50f006812e
Original-Change-Id: I4d34905c04effd54d0d0edf8809e192283db2ca3
Original-Signed-off-by: Joseph Lo <josephl@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/309248
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Original-Commit-Queue: Joseph Lo <yushun.lo@gmail.com>
Original-Tested-by: Joseph Lo <yushun.lo@gmail.com>
Original-(cherry picked from commit 13cbcaf441bd762af9cf00eff24eb7709db38d95)
Original-Signed-off-by: Joseph Lo <josephl@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/309497
Original-Commit-Ready: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: http://review.coreboot.org/12321
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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As vboot verification works on regions outside of CBFS
pass the entire ROM_SIZE to FSP for creating a cacheable
RO region.
Additionally remove the CACHE_ROM_SIZE_OVERRIDE as it doesn't
work with non-power of 2 CBFS_SIZE. In practice the entire
ROM should be attempted to be cached.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados w/ a 3MiB CBFS_SIZE.
Change-Id: I61404c626ab2bcfd039d6eb3c01d9c13a0928446
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 92568c630c48446b1ad9d4f22056f22e0679970c
Original-Change-Id: I032e4d615d2b68d3a2e597555eb1b5034a74bf0a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/309770
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/12260
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Setting the Package Power clamping bits in Power Limit MSR
(MSR_PKG_POWER_LIMIT 0x610) Allows going below the OS requested
P or T state for the time window specified for PL1 or PL2.
BRANCH=none
BUG=chrome-os-partner:47041
TEST=Built and boot on kunimitsu, load the system with Aquarium WebGL,
change the power limit value from default (TDP or 15W) to any lower value
note that the Pkg power comes down and also the CPU frequency is lowered.
Change-Id: I9c0dd90a6660214ae142418aae8b8c5f6a739896
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b0b527991c2d26da5772700a22ff101eaf9993ef
Original-Change-Id: Ia59fcfe2a14cd7f8b1e1b8e967073e67eb452f42
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/309556
Original-Tested-by: Charulatha Varadarajan <charuprasanna@gmail.com>
Original-Tested-by: Charulatha Varadarajan <charulatha.varadarajan@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/12257
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The touched workaround for Sandy Bridge reserves two memory regions that
could cause graphics corruption if mapped by the integrated graphics
device. To the best of our knowledge, the workaround is not needed for
Ivy Bridge revisions.
Tested on kontron/ktqm77 (Ivy Bridge): Booted Linux and checked the
memory regions are not reserved. Couldn't test on Sandy Bridge, due to
lack of hardware.
Change-Id: I4273d1d804b490cf93c23426782eb1ffaf29f7d4
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/12326
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Tested-by: build bot (Jenkins)
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