Age | Commit message (Collapse) | Author |
|
Change-Id: I6f9c992f1a68025ed18de57c5856b3bf9a673bfb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6075
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Change-Id: Idc4c47f3802019c2853ec71f8e9c057c3ab8d3ee
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6074
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Change-Id: I812cc40e50a1e7e13caed48a1693feb8658b645c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6073
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Change-Id: I46906e6d68775edc5cfe199cfeb465db4da2691f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6072
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Change-Id: Icab0aeb2d5bf19b4029ca29b8a1e7564ef59a538
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6071
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Alphabetise headers and a few trivial cleanups.
Change-Id: Ib8c8362962297cb59671d8274df8e4945373f94b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6042
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
|
|
Change-Id: I08b9eef9d6b0f120c17c3293f1f90b847742dc06
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/6064
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
|
|
Pins 41-48 default to being GPIs. This switches the internal
mux to connect them to UARTD.
Change-Id: I61393b8c35cbc664f6520f60eed09ba4bbede0dc
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/5963
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Silence unused function warnings, spotted by Clang.
Change-Id: I5127893e9605ca490ff450faa92af5e9eafe8940
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6054
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
|
|
Change-Id: Iaf5db7153b08ac81b233f967c7a604ed08af91ca
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6040
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
|
|
No need for these.
Change-Id: I1df6e2ef06bd5546a66ee05a15fa2f7c3daf8853
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6039
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
|
|
Change-Id: I8ddd46a573b61eba685efcc15456f288645d214d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5936
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
|
|
Port to recent reference board (AMD Persimmon) changes in commits:
c93a75a AMD/CIMx: Add functions for AMD PCI IRQ routing
Change-Id: I307709bfee554bc64788a973da6d9313ca7c0de2
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5882
Tested-by: build bot (Jenkins)
Reviewed-by: Mike Loptien <mike.loptien@se-eng.com>
|
|
Test explicitly for S3 resume.
Also switch to use IS_ENABLED().
Change-Id: I17ea729f51f99ea8d6135f2c7a807623f1286238
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6070
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Change-Id: I8e0d43293e095c1c76c3cfef1f426737624ea37f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6063
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
|
|
Also update packardbell/ms2290 to match lenovo/x201.
Change-Id: I6bda740cadd81ebe47e57742c507bff322a9fb0e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6062
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
|
|
Change-Id: I7811ee695f35c708144c4af5d43935deb22dd4df
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6061
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
|
|
Add this to reduce the amount of preprocessor conditionals used in the source,
compiler currently resolves this to a constant.
Once we have gone through all #if CONFIG_HAVE_ACPI_RESUME cases, we may change
the implementation to enable/disable S3 support runtime.
Change-Id: I0e2d9f81e2ab87c2376a04fab38a7c951cac7a07
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6060
Tested-by: build bot (Jenkins)
|
|
Change-Id: I6b37cf945db12d2cf8096c9f49fff9e0bec139d6
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6058
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
|
|
Spotted by Clang.
Change-Id: I3e612c0fa050a09fa7e5b1cb643935b84eb2b957
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6053
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
|
|
Change-Id: I0ecc3c5a26251f248234244bf305d3e13e41b9e9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6069
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
|
|
This is implied from DYNAMIC_CBMEM from soc/.
Change-Id: I8cd8c2dff723950377998750377a3168f1f5fc5b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6029
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Martin Roth <gaumless@gmail.com>
|
|
The default FSP location needs to be in the chipset, not the mainboard.
This was removed from the Bayley Bay mainboard in patch 41ea7230f7
reviewed at http://review.coreboot.org/#/c/5982/
Change-Id: Ia26ed34e1401cbd2303166628e7a4e357d79c874
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5985
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: build bot (Jenkins)
|
|
- Add the Bay Trail B0/B1 microcode. These versions of the SOC were
released as a "Super SKU" which had features of all the different
SKUS (M/D/T/I), and identified as a Bay Trail T as noted by the
number 2 in the third character from the left in the microcode name.
- Update the size of the microcode blob. We should be pushing a patch
to eliminate the need for this shortly.
Change-Id: I57ba51eabe9ea0609ab809f18b95e3bc9d5cb191
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5986
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
|
|
Push back any board specific values back into romstage.c #defines and
drop any remaining fragments of CONFIG_SIO_PORT in-tree.
Change-Id: Ieb63fb0c2ab1a82b53bafd86686de7b21ac226c3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6045
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
CONFIG_SIO_PORT is not used anywhere and should not be here any way.
Change-Id: I39eb2d668f1da9f89b7ff6eb219af1a48cb29232
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6044
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
CONFIG_SIO_PORT is not used anywhere and should not be here any way.
Change-Id: I2e7be4337f7f46298b9ca5bd613c58deec2cb01a
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6043
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
This existed for ChromeOS but was no longer used with DYNAMIC_CBMEM.
Change-Id: I558a7ae333e5874670206e20a147dd6598a3a5e7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6032
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
|
|
We implement get_top_of_ram() on these chipset to resolve CBMEM
location early in romstage. Call to set_top_ram() is not required.
Change-Id: I492e436b0c32d2c24677265b35afd05f29dcd0f8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6031
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
|
Needed to resolve CBMEM location early in ramstage. With DYNAMIC_CBMEM
set_top_of_ram() will no longer be available.
Change-Id: If50f1c5455a587b096348ffedadbe1dd2350a714
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6030
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
|
|
S3 resume detection not implemented in romstage.c.
Change-Id: I98277cb483825af2e6c5c8eefa4598b117613478
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6028
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
|
Clang complains about a unused debug function, so remove dead code.
We have copy of dump_smbus_registers() in amdk8/debug.c.
Change-Id: Ibf46deb1de1589d81760841b1d4ba319707915aa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5942
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
|
|
Use the value from hardware for uma_memory_base.
Change-Id: I70351166db6634ef3bca2bf12051ccc3730cab8e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5893
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
|
|
Change-Id: I2a46806a3f0a57497edebd49e69b97f90948adb9
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5117
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
|
|
With the addition of the mainboard PCI IRQ routing tables
for AMD Persimmon, the MPTables can be set to use this
information to accurately reflect the real hardware settings
of the system. Additionally, the IOAPIC gets defined before
the MPTable gets generated so the settings can be read
directly from the IOAPIC registers instead of 'guessing' at
them as was done before.
Change-Id: I96ec046a2208eddf4b5e442214ff43d2a349ca4d
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/5878
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
|
|
Virtual Wire mode is set by writing 0 to the the MPTable
Feature2 bit field 'IMCR'. The virtualwire variable was
initially defined as writing a 1 to this bit field which
would actually set PIC mode instead of Virtual Wire mode.
However, nearly every mainboard called the MPTables with
virtualwire = 0, which actually had the effect of setting
Virtual Wire mode. I am correcting the definition but
leaving the call to write the MPTables with virtualwire = 0,
which is how most mainboards are already setting the tables
up.
See the MP Spec table 4-1 for more details:
Bit 7: IMCRP. When the IMCR presence bit is
set, the IMCR is present and PIC Mode is
implemented; otherwise, Virtual Wire Mode is
implemented.
http://download.intel.com/design/archives/processors/pro/docs/24201606.pdf
Change-Id: I039d88134aabd55166c2b68aa842bacbfcc0f42b
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/5977
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
|
Adding the copyright header to the MP Spec files because
they were not included before.
Change-Id: Ifcd217a53bf8df19b28e251a7cac8b92be68d1fc
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/5981
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
|
|
Try to 'standardize' the otherwise peculiar method naming to be somewhat
more in-line with other ACPI implementations. This makes it easier to
compare with vendor DSDT dumps for example.
Change-Id: I5ba54f7361796669ac0cab7ff91e7de43b22e846
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5888
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
|
|
Forward port commit:
db0e0e2 amd/agesa/*/gcc-intrin.h: Invaild inline asm
Change-Id: I87bf101b15bac7c06afa9cec10e2bd4e0cdfd6c7
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5941
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
|
|
Break out the PNP Super I/O HWM configuration from mainboard.c
Change-Id: Ib4c7f26c7fa2a9845250a61a23c75cb9e440ab93
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5797
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
|
|
Change-Id: I710efc3171e1653241f2dba1217a9560d2d99a16
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5802
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
|
|
For anyone who knows the difference between a header and a variable in C
these depictions are rather useless. Thus, these lines wast essential
screen real estate while working on coreboot.
Change-Id: I7fe55d936c035ef83832716c45bfc57d73c0edc7
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5979
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Intel requested that we remove the version number from the default
vbios path.
Change-Id: I2590fed0db157e3e430212336fc55eb099d28a72
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5984
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
|
|
While pushing the fsp_baytrail code, it was requested that we change
CONFIG_ENABLE_FAST_BOOT to CONFIG_ENABLE_FSP_FAST_BOOT.
These were missed in the change.
Change-Id: If8af3f90b0f5cc9154ff1d3a387f442430f42dee
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5972
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Use the following command to fix all occurences.
$ git grep -l approriate | xargs sed -i 's/approriate/appropriate/g'
Change-Id: I4cbba972bb445c2407ef2e63ffb3068fc948f1c6
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5987
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
The IMC functions were being called and timing out when the
CONFIG_SB800_IMC_FWM/CONFIG_HUDSON_IMC_FWM were defined as 0.
Changing to a IS_ENABLED will keep the IMC handshake from
occuring if the IMC firmware isn't running.
Tested on a Persimmon platform which makes three calls to
spi_claim_bus() with each call timing out after 500ms.
Change-Id: I5d4bbcecf003b93704553b495a16bcd15f66763b
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/5974
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
|
|
Use the default mmconf base address and fsp locations.
Change-Id: Ia9116b0f0fc799592df2a10b10e086cfc88b394c
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5982
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
There was dereference of NULL dev->ops in pnp_enter/exit_conf_mode()
as those calls were made before pnp_enable_devices() was run.
Since hardware did not enter configuration mode, detection failed with
ID and REV read as 0xff.
Change-Id: If13086707cd86e392890ccf4f717e13a87f3317f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5949
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Allow skipping unknown MBP rather than bailing out.
Change-Id: I9a54858c37d73e320de77aea5a05ab5dcf67cd69
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5976
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
|
|
Change-Id: Ieb0d5de37870a359f3a7ea1543640e26f86c1684
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5952
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
The CIMX sb700/sb800/sb900 and agesa/hudson code was treating
the LPC SPI BAR as a normal PCI BAR. This will set the
resources for a fixed size at a fixed address. This was tested
on hp/abm, amd/persimmon, and gizmosphere/gizmo boards.
Change-Id: I1367efe0bbb53b7727258585963f61f4bd02ea1d
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/5947
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Change-Id: Ife3febcc88967386dfae624cd237562a34a68471
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5956
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Change-Id: I68ae49d20a2524f03c4503f2b3be93f07b9cb6e3
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5955
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
The PCI_INTR table is an Index/Data pair of I/O ports
0xC00 and 0xC01. This table is responsible for physically
routing IRQs to the PIC and IOAPIC. The settings given
in this table are chipset and mainboard dependent, so the
table values will reside in the mainboard.c file. This
allows for a system to uniquely set its IRQ routing.
The function to write the PCI_INTR table resides in
cimx_util.c because the indices into the table have
the same definitions for all SBx00 FCH chipsets.
The next piece is a function that will read the PCI_INTR
table and program the INT_LINE and INT_PIN registers in
PCI config space appropriately. This function will read
a devices' INT_PIN register, which is always hardcoded to
a value if it uses hardware interrupts. It then uses this
value, along with the device and function numbers to
determine an index into the PCI_INTR table. It will read
the table and program the corresponding value into the PCI
config space register 0x3C, INT_LINE. Finally, it will set
this IRQ number to LEVEL_TRIGGERED on the PIC because it is
a PCI device interrupt and the must be level triggered.
For example, the SB800 USB EHCI device 0:18.2 has an INT_PIN
value hardcoded to 2. This corresponds to PIN B. On the
Persimmon mainboard, I want the USB device to use IRQ 11. I
will program the PCI_INTR table at index 0x31 (this USB device
index) to 11. This function will then read the INT_PIN register,
read the PCI_INTR table, and then program the INT_LINE register
with the value it read. It will then set the IRQ on the PIC to
LEVEL_TRIGGERED by writing a 1 to I/O port 0x4D1 at bit position 4.
Also, the SB700 has slightly different register definitions than
the newer SB800 and SB900 so it needs its own set of #defines for
the pci_intr registers.
Only the Persimmon mainboard is adapted to this change as an
example for other mainboards.
Change-Id: I6de858289a17fa1e1abacf6328ea5099be74b1d6
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/5877
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
|
The PIC i8259.c file has a lot of #defines and function
definitions in it. I am moving these to the i8259.h file
and also adding a few functions to update the PIC IRQ mask
register. The PIC default configuration has all of its
interrupts masked off except for IRQ2. IRQ2 is where
the Slave PIC is cascaded from the Master PIC.
Change-Id: I78d505358c29fadbc184137a09120863ea1d5c13
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/5950
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
|
S3 resume is expected to work now, however the 3s delay and flash wear
is still there.
Change-Id: I7edbce7bcf9c2160099fd5e371562b1ec63d45d8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5971
Tested-by: build bot (Jenkins)
Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
S3 resume now works, however the 3s delay and flash wear is still there.
Change-Id: I9d2eda5454baf7704807cf67f3aca94a67de3406
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5970
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
|
|
Without this change the IOAPIC memory window would collide
with PCI config space. This was tested on the hp/abm board.
Change-Id: I5dd53463961f75bab80a41dc7beff8d0434b24ae
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/5946
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
The Kabini MMIO region was assigned a 256MB region at
0xA0000000. That location is below TOP_MEM and is getting
carved out of useable system memory which is not being
reclaimed above 4GB. This changes its size to 64MB and
moves it to 0xF8000000.
This was tested on the hp/abm and asrock/imb-a180 boards.
Change-Id: Ib226bc954311a3a2a15f182ab4618f4924e95a5b
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/5945
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Change-Id: I4e4bc09a8f8fabe68519a29dc421af82c76c9873
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/5944
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
The romstage of Nuvoton Super I/O chips (but not Nuvoton BMC chips)
is identical, so the early_serial.c file can be moved under
nuvoton/common.
The Nuvoton BMC chip WPCM450 is however left untouched.
Change-Id: I4663176c1003b24a49a9fe5f9ebd27a1963b5565
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/5909
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
|
|
Change-Id: I5df1f0efdef2592b762fe391edaadbca4593e85a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5689
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Change-Id: I9c8f7cc98c65102486e17ec49fa2246211dffc4f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5688
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Change-Id: Ibbb07ef308c7e92a8a8dfe066f5e3866d5f8aee2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5687
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Change-Id: I158993bcb654ef27a9fc6b7e9dc3fc955fb740fa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5686
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Change-Id: I3ac39441746d739ac19e831bb67c76405c24ba27
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5925
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
|
1. Remove #include .c in romstage.
2. Make romstage component symbols linker-time.
3. Provide header guards and prototypes in superio romstage support.
4. Correct function type-signatures to be static/non-static where
appropriate, avoid 'pretend optimisations' by unnecessarily inlining
functions.
5. Separate out UART enable from various other PNP hard coding
Change-Id: I9b8dad7c02d802e97db73ddf2913d5c6bb33a419
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5916
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
This GCC specific workaround of wrapping of libgcc runtime symbols with
gcc.c is not nessary with libcompiler-rt linkage.
Change-Id: I50a2bc99d97f68a2ad2b51a92ea0e7086bab35fe
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5812
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Rewrite smsc/smscsuperio romstage component to be more consistent and
provide header there-by removing #include's of early_serial.c's in
mainboard's.
Change-Id: I572e0c76422f09d4de88935a36c0a59e5350e6e0
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5915
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Following similar reasoning as commit:
d304331 superio/fintek/f81865f: Avoid .c includes
Avoid any mistaken future inclusion of early_serial.c in mainboard.c
code by providing symbols in romstage.
Change-Id: I9e763a7ad9de090e35acdcf4d6a280d8227c6015
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5508
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
These non-ROMCC boards #include the model specific w83977tf Super I/O
romstage component. The generic winbond_early_serial() function serves
well here to further tighten integration into the new Super I/O
framework and drop dependence on #include'ing .c files, leaving only
ROMCC boards.
Change-Id: Ib63c0f29f994c54e6112702506f288535799706c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5898
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
We have better written generic implementations of these functions
introduced in commit:
a7d14a1 ite/common: Introduce common watchdog and 3.3V VSB helpers
Change-Id: Ic93d78fce18c68d1d1bf3b537e8985a2532a8fcf
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5901
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Move samsung/stumpy board towards generic romstage component and away
from poorly written hard-coded model specific Super I/O component. This
is an incremental step towards getting obj-level abstraction between
board and Super I/O.
Change-Id: I358c5abef85c2ffa1b7178025cde8834a35b0a51
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5899
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Change-Id: I0f39b35fbf8e053ba21454a2847d6bb3ac5d2e1c
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5923
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
The Base of Stolen Memory (BSM) register belongs to device 2,
function 0.
Change-Id: I2381f87ffaccb2f8034c160fc30c1d92f8b19402
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5922
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Change-Id: I280441aadb0575dc0b99584cdcd48cc76a0289a2
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5284
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Seems boards with i945 had TSEG disabled so this had gone unnoticed.
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change-Id: I6a00ea9121847ce2fede22538e1b53a870d761f1
Reviewed-on: http://review.coreboot.org/5892
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
|
|
TSEG appears in memory below graphics UMA region. Seems boards
with i945 had TSEG disabled, so the incorrect order did not make
a difference.
Change-Id: Ie293aab17b60b5f06a871a773cd42577c7dc7c7b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5891
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
|
|
Change-Id: I5cb496d0d582d3dc5c0c0635f632561f8a3dd853
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5897
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
|
|
Change-Id: Iff15ab436e5b7b4e189c7341e7c508faaef07a3a
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5896
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
|
|
The lock bit for UVSVC/LVSVC was set before both registers were programmed.
Change-Id: I000440db5c8dd2f260ebc1b69108b75621faf7b3
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5167
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Without it option ROM run results in just a black screen.
Change-Id: Id203f55ca0f02c290a3f40ac1ec7c5f23c5580bf
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5344
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
thinkpad_acpi checks that BIOS version matches some pattern.
Report version in this form.
Not cleaned up as the idea of this patch seems to be met with resistance.
Can make it Thinkpad-specific if the idea is accepted.
Change-Id: I15e33e87e7a7f42d6a06f12fb39b5172153af8a1
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4650
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Change-Id: If8b3578c4fa31bf9f09c0053a5cac7ebc993b634
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5319
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Change-Id: Ib92142a133445018cd152dabe299792ba5f36548
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5240
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Make superio romstage component link-time symbols.
Change-Id: Icde27465a05946498ff7b8f1aaa7a9e8ba074272
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5880
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Move towards the removal of the superio model specific xxx_serial_enable
implementation. Make remaining superio romstage parts link-time symbols
and fix corresponding mainboards to match.
The following mainboards remain unconverted as they are ROMCC:
- mainboard/supermicro/x6dai_g
- mainboard/supermicro/x6dhe_g
- mainboard/supermicro/x6dhr_ig
- mainboard/supermicro/x6dhr_ig2
and so block the final removal of w83627hf_serial_enable().
Special cases:
- mainboard/supermicro/h8qme_fam10: Provide local pnp_ sio func
Provide local superio pnp_ programming entry/exit functions as to avoid
making superio implementation global symbols. Although this is not the
proper/final solution, it does mitigate possible symbol collisions and
allow for continued superio refactorisation.
Change-Id: Iaefb25d77512503050cb38313ca90855ebb538ad
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5601
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Part 1/2: These are actually not necessary if Super I/O support is
properly utilized.
Change-Id: I39b621e582f8d0762276d29492c91dce500f0665
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5870
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Change-Id: I32461449354155510c0e14e9d0ce396068ea50d4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5890
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
|
|
hardcoded value
Change-Id: I4739c5544aade105399347d239ba64f5115db397
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5869
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Add a define for the register Base of Stolen Memory (BSM) and use it.
Change-Id: I5b1df4e088d88344fac8cd8d218e76b08a885f58
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5884
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
realpath and readlink can be used to do the same thing - in this case
we're turning path1/path2/../path3/path4 into path1/path3/path4 so
that the makefile's wildcard routine can evaluate it.
Debian derivatives don't seem to include realpath. (and even when it's
installed, it's not the gnu coreutils version.)
Change-Id: I0a80a1d9b563810bdf96aea9d5de79ce1cea457a
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/5793
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
|
|
Bay Trail-I Platform – Bayley Bay-I Customer Reference Board
The Bayley Bay CRB-I is a dual-channel DDR3L SO-DIMM non-ECC platform.
It is designed to support the Bay Trail-I SoC.
This implementation uses the Intel FSP (Vist the Intel FSP
website for details on FSP architecture and support).
This code does not currently support S3. All other features and IO
ports are functional. Booted on Ubuntu 14.04, Mint 16,
Fedora 20 with SeaBIOS payload. Memtest86, FWTS, and
other tests pass.
Notes:
- Generates a 2MB binary to be flashed to the upper 2MB of the ROM,
to preserve the existing Intel Flash Descriptor & TXE binary.
- Tested with B0 & B3 Baytrail I parts
Board support page will be updated on acceptance.
Change-Id: I80c836c7590f2dc25ec854e7a0bb939024cea600
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5792
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
The PCI Specification states that devices that implement
a bridge and a secondary bus must swizzle (rotate) the
interrupt pins according to the table below:
Child Dev # Child PIN Parent PIN
0,4,8,12... A/B/C/D A/B/C/D
1,5,9,13... A/B/C/D B/C/D/A
2,6,10,14.. A/B/C/D C/D/A/B
3,7,11,15.. A/B/C/D D/A/B/C
Which is also described by this equation:
PIN_parent = (Pin_child + Dev_child) % 4
When a device is found and its bus number is greater than 0,
it is on a bridge and needs to be swizzled. Following the
string of parents up to the root bus and swizzling as we go
gives us the desired swizzling result. When BIOS_SPEW is
defined, it will print out each step of the swizzling process.
Change-Id: Icafeadd01983282c86e25f560c831c9482c74e68
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/5734
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Mike Loptien <mike.loptien@se-eng.com>
|
|
While similar to the Bay Trail-M/D code based on the MRC, there are
many differences as well:
- Obviously, uses the FSP instead of the MRC binaries.
- FSP does additional hardware setup, so coreboot doesn't need to.
- Different microcode & microcode loading method
- Uses the cache_as_ram.inc from the FSP Driver
- Various other changes in support of the FSP
Additional changes that don't have to to with the FSP vs MRC:
- Updated IRQ Routing
- Different FADT implementation.
This was validated with FSP:
BAYTRAIL_FSP_GOLD_002_10-JANUARY-2014.fd
SHA256: d29eefbb33454bd5314bfaa38fb055d592a757de7b348ed7096cd8c2d65908a5
MD5: 9360cd915f0d3e4116bbc782233d7b91
Change-Id: Iadadf8cd6cf444ba840e0f76d3aed7825cd7aee4
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5791
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
When going from a configuration with fast boot disabled to one with
it enabled, ENABLE_MRC_CACHE was not being enabled properly. This
forces it on with ENABLE_FSP_FAST_BOOT.
Change-Id: If7b6374e0c0a1d5403a50a1b0a958cea6f96cc88
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/5794
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
The FSP clears the bit that tells us whether or not the RTC has lost
power when it sets up memory. Because of this, we need to initialize
the RTC in romstage instead of ramstage.
Change-Id: I158e4339fc539d32cfb2428042df6156d312a5f4
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5735
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
|
|
Depreciate the model specific early_serial.c romstage component for this
Super I/O in favor of the recent generic winbond romstage framework.
Change-Id: I22775dc9b6341c8994d21591b7176abe4dd99911
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5724
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
|
|
Depreciate the model specific early_serial.c romstage component for this
Super I/O in favor of the recent generic winbond romstage framework.
Convert dependent board to generic winbond serial init. Note the clock
function is actually invalid since it never enters into PNP config mode
to twiddle the register. Further, 48MHz is the default (page 9 of
data-sheet) and so romstage.c need not do anything to the clock rate
hence why it presumably works with this invalid function.
Change-Id: I4706a1446c1b391b8390ac0361700ce6f15b9206
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5725
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
|
|
We now have common ite_*_*() functions for romstage and hence no longer
require the model specific portion of this superio support.
Change-Id: I30400abf27008a88072673075bba445f100d9ad3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5838
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
|