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Cherry-pick from Chromium commit 1940eb6.
The unused lines leads to spurious interrupts on few of the systems.
Original-Change-Id: Ie539e1debc15dd1fd8707f8866c65714fc43e44b
Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
Original-Tested-by: Bernie Thompson <bhthompson@chromium.org>
Change-Id: I6f4f7cec8ef11e781c66b6efff4188259469e41c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Cherry-pick from Chromium 2b51633.
Disable unused PCI devices. Update PCI DeviceID.
Original-Change-Id: I34fa6e25f9178de959aad30cc979d787cf76b8ad
Original-Signed-off-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I7a06a1d44ce933000cbfe2eb71823ee66cb46a34
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Cherry-pick from Chromium commit 8f63720.
SoC GPIO to read Memory strap not getting configured
correctly causing incorrect RAMID read during ROMSTAGE
TEST=Build and boot the platform with differnt Memory type and
read RAMID correctly inside spd.c
RAMID = 0 => 4GB Samsung Memory
RAMID = 1 => 4GB Hynix Memory
RAMID = 2 => 2GB Samsung Memory
RAMID = 3 => 2GB Hynix Memory
Original-Change-Id: Ide9d4b5f73565cddd74cedf7afe4b7d168dde74c
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: If2ba9ec5be111b9c30360ffde41a2c644a69ecae
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Needed for to-be-added Google Braswell boards which make use
of common GPIO library function to determine installed RAM type.
Change-Id: Ie9b0c6513f10b252bf0a5014bd038d24879421be
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Set SMBus, SAGV and Skip FSP MPInit configuration from devicetree.cb
Change-Id: Ic810b003bf7fb13447d5d5dcd49cfcc31785b440
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Initialize UPD params based upon config
Change-Id: Ib2ee58f8432a957ef389b40f717533e4cfe774b9
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21175
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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FSP is doing TCO lock inside Post PCI bus enumeration
NotifyPhase(). Hence remove TCO Lock down programming
from coreboot.
TEST= Ensure TCO_LOCK offset 8 bit 12 is set.
Change-Id: Iec9e3075df01862f8558b303a458126c68202bff
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add a function in FAST_SPI library to discrete lock the PR
registers 0 to 4.
BUG=none
BRANCH=none
TEST=Build and boot poppy
Change-Id: I46e1948315ea9489932efdf7d60d6d78ab3948a6
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/21063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch to ensures that coreboot is performing PMC
registers lockdown after PCI enumeration is done.
This requirements are intended to support platform security
guideline where all required chipset registers are expected
to be in lock down stage before launching any 3rd party
code as in option rom etc.
coreboot has to change its execution order to meet those
requirements. Hence PMC register lock down has been moved
right after pci resource allocation is done, so that
PMC registers can be lock down before calling post pci
enumeration FSP NotifyPhase() API which is targeted to
be done in BS_DEV_ENABLE-BS_ON_ENTRY.
TEST=Ensure PMC MMIO register 0xC4 bit 31 is set.
Change-Id: Ibd86a38fa78752ce007da63a9ccdd991ca21ab92
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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FSP is doing PMC ABASE lock inside Post PCI bus enumeration
NotifyPhase(). Hence remove ABASE Lock down programming
from coreboot.
TEST= Ensure GEN_PMCON_B offset 0xA4 bit 17, 18 is set.
Change-Id: I800e654c7d8dc55cc0e8299501c1f85c57882e9d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch to ensures that coreboot is performing LPC
registers lockdown after PCI enumeration is done.
This requirements are intended to support platform security
guideline where all required chipset registers are expected
to be in lock down stage before launching any 3rd party
code as in option rom etc.
coreboot has to change its execution order to meet those
requirements. Hence lpc register lock down has been moved
right after pci resource allocation is done, so that
lpc registers can be lock down before calling post pci
enumeration FSP NotifyPhase() API which is targeted to
be done in BS_DEV_ENABLE-BS_ON_ENTRY.
TEST=Ensure LPC register 0xDC bit 1 and 7 is set.
Change-Id: I705a3a3c6ddc72ae7895419442d67b82f541edee
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch ensures that MRC cache data is already written
into SPI chip before SPI protected regions are getting locked
during BS_DEV_RESOURCES-BS_ON_EXIT.
This requirements are intended to support platform security
guideline where all required chipset registers are expected
to be in lock down stage before launching any 3rd party
code as in option rom etc.
coreboot has to change its execution order to meet those
requirements. Hence storing mrc cache data into SPI has
been moved right after pci enumeration is done, so that
SPI registers can be lock down before calling post pci
enumeration FSP NotifyPhase() API which is targeted to
be done in BS_DEV_ENABLE-BS_ON_ENTRY.
TEST=Ensure MRC training data is stored into SPI chip and power_
Resume autotest is passing.
Change-Id: I8ee26b5cc70433438cf4e45e707b8a54f89cf9b0
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch to provide new config options to perform LPC and SPI
lock down either by FSP or coreboot.
Remove EISS bit programming as well.
TEST=Build and boot Eve and Poppy.
Change-Id: If174915b4d0c581f36b54b2b8cd970a93c6454bc
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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In order to pass type C USB2 eye diagram for sku Santa,
USB2 port#1 PHY register needs to be overridden.
port#1:
PERPORTPETXISET = 7
PERPORTTXISET = 2
BUG=b:64880573
BRANCH=master
TEST=emerge-coral coreboot chromeos-bootimage
Change-Id: I07c0b7b0f08263a348befb7d6fd8d01028314470
Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/21199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Remove the unnecessary #if from around the #include "fchec.h".
Turn #if statements into if().
Change-Id: Ia0582b3ce24c55dd439dfadb727507240accd9d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Move the fchec.h files, which do not seem mainboard specific, out of
the mainboard directories into the southbridge/soc directories.
Change-Id: Idd271c6ab618aa4badf81c702212e7de35317021
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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This is not specific to a board but the binary IMC firmware
used on the platform. Also remove unused IMSP and IMWK methods.
Change-Id: I80026bca55f5ba236c080bcd882fc374559942e6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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While at it, replace LibAmdMemFill() with memset().
Change-Id: I770cab446add8f305f02e365e7c9763df88cd958
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21192
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It was not intentional to change oem_fan_control() to non-static
with commit
23e5ba9 binarypi mainboards: Clean up IS_ENABLED fan control
Every platform except bettong had its own static version of
oem_fan_control, so remove the definition of oem_fan_control from imc.h,
and move it out of imc.c into bettong's BiosCallOuts.c.
Change-Id: Ie95ac1fd3a57259bb35796903aa8753ef0e70d70
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21189
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ibfbb2ff2d9776fe91a8a09561d9c32eb49a56db6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Sort makefile.inc into rom, ram, ver, smm stages and alphabetize.
Change-Id: Ic8c6ca2b57527fcc96c135cc801a098201bf0465
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Set MAX_CPUS and MAINBOARD_FAMILY for cannonlake RVP.
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Change-Id: Ic6ef7e4f247ac2d227bab3b53512c659c5e72da7
Reviewed-on: https://review.coreboot.org/21152
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add initial MP init support. This boots up all CPUs.
Change-Id: Ia33691c17c663d704abf65320d4bf1262239524d
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21081
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove all checks for #if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) around
the imc.h includes. Convert from #if to if() for all fan control
setup code. Where necessary, make functions non-static to match the
prototypes in imc.h.
Change-Id: If88af42d00227285931829441909a982fc292b2b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Remove all checks for #if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) around
the imc.h includes. Convert all #if to if() for fan control setup.
Change-Id: I04a9fbbf6f64f45e1a0b544267bfe840ce7fa1d9
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I91e09757e5eea1eaf9b76921ad032ad2b79c14c5
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Convert from #if to if().
Change-Id: Icf6db485735cb8bbadb3e742a079d0bafaacd79c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Don't include src/include/cpu/amd/car.h in Via motherboards.
Change-Id: I9d2b3cfb619cf831c7a677992ca03d5f42e5ffd1
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Ia55c82f2245335a5d02e4d6567f606596c8439c0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: Ief40319f5ff83c408e5a2b7f13572feabfab03a4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I11ce2a558fe12f8f163dbe3dc52952a273b813ee
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Ie2f1eb5a101b9c392a7bd5cb2338dd6a6fdcfe52
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Iffc176522e943c003e2625d8e15341b281a261eb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I7194eb910cccc454c5f20c23629ff2a45b1a9079
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I3730bf87030b7e20991e1de00d2024e4b02f4c19
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Ia747b3bc149a672a6de2ecf0308141172321a493
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I646a8f4cfc1df8648a72e58814c36ea66b48e9d7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I5e6e4cabe2b93c41da19412ec3ae2dfaa114bcc0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I39a0b4acbe44dca8be63201502be739d954c8a33
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I5a6373ac03d942cd16905c9e8360f7179b8eea61
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20712
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Iac0998a56b4e297c512fcba98d3dbb4253c9b526
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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It is a copy from baseboard/devicetree.cb (coreboot.org ToT)
BUG=b:64880573
BRANCH=master
TEST=emerge-coral coreboot chromeos-bootimage
Change-Id: I5db730c1974a96547fe7fda63689b7c5bfaefc66
Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/21130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch ensures that entire system memory calculation is done
based on host bridge registers.
BRANCH=none
BUG=b:63974384
TEST=Build and boot eve and poppy successfully with below configurations
1. Booting to OS with no UPD change
2. Enable ProbelessTrace UPD and boot to OS.
3. Enable PRMRR with size 1MB and boot to OS.
4. Enable PRMRR with size 32MB and boot to OS.
5. Enable PRMRR with size 2MB and unable to boot to OS due to
unsupported PRMRR size.
Change-Id: I9966cc4f2caa70b9880056193d5a5631493c3f3d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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BRANCH=none
BUG=b:63974384
TEST=Build and boot eve successfully.
Change-Id: Ie5558cdb7acacc34451e1cf63a3e4239e7901c67
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch to add helper functions for memory layout design
based on PCI Host Bridge/DRAM registers.
BRANCH=none
BUG=b:63974384
TEST=Build and boot eve successfully.
Change-Id: I95250ef493c9844b8c46528f1f7de8a42cba88a2
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add gpio pins configuration for cannonlake rvp u/y boards.
Change-Id: Ia077a070979401fe7bd23bda110d2b66a038d9fc
Signed-off-by: john zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change provides interface to override dev tree settings per
board due to many projects share same devicetree.cb.
BUG=b:64880573
TEST=Verify that dev tree settings can be overridden in mainboard
on coral
Change-Id: I349b1678d9e66022b586b6c7f344b831ed631c74
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/21142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Tested on T430s with an external screen connected to every one of the
DP ports (miniDP on mainboard, two DP ports on dock), the GRUB payload
can display on both the external screen and the internal LVDS screen.
This is a copy-paste of I8f270d55 "mb/lenovo/x230: Enable libgfxinit".
Change-Id: Ifb1471ecb18927c30c61c64011cbb0e20a465558
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/21070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: I9afd5eaab5f8e897dea037f32e1666ad31b0f8df
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Sync file with southbridge/amd/common/sleepstates.asl.
SSFG was meant to be used as a mask to enable sleepstates
_S1 thru _S4. However as a logical instead of bitwise 'and'
operation was used, all the states were enabled if only
one was marked available.
Change-Id: I674953f1a5add74e16ddd84c252e8d21501ffefd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Note that against the specs, these definitions repeat
the sleep type also in the reserved fields 3 and 4.
For consistency, don't fix it here now.
Entry for \_S3 is now masked off if HAVE_ACPI_RESUME=n.
Change-Id: Icdc4c81d07fe7a99d5b0f8fa23e9443f58a40ab9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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SSFG was meant to be used as a mask to enable sleepstates
_S1 thru _S4. However as a logical instead of bitwise 'and'
operation was used, all the states were enabled if only
one was marked available.
Note that all boards incorrectly had SSFG == 0x0D that previously
enabled ACPI S3 sleep state even when it was not available.
Change-Id: Ia948becff079383cbf861468da9e8a3ebbf213cb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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SSFG was meant to be used as a mask to enable sleep states
_S1 thru _S4. However as a logical instead of bitwise 'and'
operation was used, all the states were enabled if only
one was marked available.
State _S3 is now set conditionally if HAVE_ACPI_RESUME=y.
For pi/hudson this had been fixed already preprocessor.
Note that all boards had SSFG == 0x0D that previously
enabled ACPI S3 sleep state even when it was not available.
States _S1 and _S2 still appear enabled in ASL/AML
but may not actually work.
TEST: 'cat /sys/power/state' and notice choice 'mem' was
removed from the list of available sleep states.
Change-Id: I27d616871c1771f0c87d8fba23d4ce1569607765
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Return to empty stack before making the switch.
Change-Id: I6d6f633933fac5bc08d9542c371715f737fb42cf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
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Change-Id: I5e7890aafbc8c80716ee49690e306482a482a863
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20573
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
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Avoid conflicting disable_cache_as_ram() declaration and tidy
up include for inlined function.
Change-Id: Iba77c711f5eb023566b7d8ba148583948661bc99
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Denverton_NS SoC
This change adds the FSP header files for FSP version 2.0 (15D50)
for the Intel Denverton_NS SoC.
Change-Id: I9672610df09089c549e74072345781bea0b4d06f
Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com>
Reviewed-on: https://review.coreboot.org/20805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
Reviewed-by: Brenton Dong <brenton.m.dong@intel.com>
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- Populate soc_intel_cannonlake_config
- Add usb.h and vr_config.h for CannonLake
Change-Id: I2a6e737594da1e766b157a38942e19a4f7fb9dfa
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This enables adding the backlight driver to boards that may or may not
come with a keyboard backlight function.
It's the responsibility of the EC to report if that feature exists, but
that's not a big extra burden given that it already keeps track of
everything else related to the backlight.
BUG=b:64705535
BRANCH=none
CQ-DEPEND=CL:620595
TEST=configured KBLE manually and noticed the presence/absence of
/sys/devices/platform/GOOG0002:00/ on a Chrome OS Linux kernel,
corresponding to the value reported by the EC.
Change-Id: Idc36bfaa6e69581ba19b52d37af6956f63cfdb8f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The Sideband Acces locking code is skipped from FSP by setting an
FSP-S UPD called PchSbAccessUnlock. This locking is being done in
coreboot during finalize.c.
This is done because coreboot was failing to disable HECI1 device
using Sideband interface during finalize.c if FSP already locks
the Sideband access mechanism before that.
So, as a solution, coreboot passes an UPD to skip the locking
in FSP, and in finalize.c, after disabling HECI, it removes the
Sideband access.
BUG=b:63877089
BRANCH=none
TEST=Build and boot poppy to check lspci not showing Intel ME
controller in the PCI device list.
Change-Id: I8dba4c97480200507969b0f2873337f97bd2ff6a
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Kahlee has an ambient light sensor connected to the EC.
TEST=Can see the device in /sys/bus/iio
BUG=b:62030268
Change-Id: Id1138a0fc5270489a734bdf8b1f4ac02d358c0df
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/21146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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devicetree.cb of cannonlake-u and y variant gets picked up
from src/mainboard/intel/cannonlake_rvp/variants/cnl_[u/y]
Change-Id: I83f636c93407a6fe17114582506397c46d1b4e20
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Define and populate PCI devices in devicetree for CNL-Y RVP
Change-Id: I311437798274dd48b0898f0832bf03d86fd9d3a6
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Define and populate PCI devices in devicetree for CNL-U RVP
Change-Id: Id04f5efe77a04c180b5dd392da777195bd9fb7a3
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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This patch assigns the code of coral family, such that,
the 'mosys platform family' returns 'Google_Coral'.
BUG=b:64467244, b:64501879
BRANCH=none
TEST=Examine 'mosys platform family' w/ new firmware.
Change-Id: I1d8f8ca2166a1d80855608cf5b64b0cc7bf3dc93
Signed-off-by: Harry Pan <harry.pan@intel.com>
Reviewed-on: https://review.coreboot.org/21136
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This update changes Cannonlake to use the new common PMC code. This
will help to reduce code duplication and streamline code bring up.
Change-Id: Ia69fee8985e1c39b0e4b104c51439bca1a5493ac
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Configure core PRMRR first on all the cores and then follow
the SGX init sequence. Second microcode load would run the
MCHECK. To pass MCHECK, PRMRR on all cores needs to be
configured first. Hence, PRMRR configuration would be called
from soc_core_init while MP init for each core and then from
soc_init_cpus, BSP would call sgx_configure for each core
(including for itself). This code flow satisfies the MCHECK
passing pre-conditions; and apparently this patch fixes the
behavior of calling configure_sgx() “again” for BSP. (So
removed the TODO comment also).
Change-Id: I88f330eb9757cdc3dbfc7609729c6ceb7d58a0e1
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21007
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To correct the SGX init sequence; PRMRR on all cores first
needs to be set, then follow the SGX init sequence. This
patch would refactor the common SGX code (and add needed
checks in the init sequence) so that SOC specific code can
call SGX init in correct order.
Change-Id: Ic2fb00edbf6e98de17c12145c6f38eacd99399ad
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Remove passing microcode patch pointer as param while calling
- soc_core_init()
- soc_init_cpus()
Also change callbacks in apollolake/geminilake and skylake/kabylake
common code to reflect the same function signature.
Change-Id: Ib03bb4a3063d243d97b132e0dc288ef3868a5a7b
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21010
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Early serial for W83627[HF|EHG] superios are handled by
superio/winbond/common/early_serial.c. Remove code
thus deprecated.
Build tested on select affected mainboards.
Change-Id: Idad6e0281f7a272e184feff686ce1407825429c7
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Six mainboards with Winbond superios directly configure
them in romstage.c. All use the common Winbond romstage
code. Change them to use the common config entry code to
allow for code refactoring such as [1]. Build tested.
[1] https://review.coreboot.org/20988
Change-Id: Icecd52ec622b9da86edb07c52893f4db001e5562
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Tested:
- i5-3550 and DIMM configurations: 2+0+2+2, 0+2+2+2, 2+2+2+2, 4+2+4+2
- debug output from serial port, EHCI debug port not found
- Arch Linux (Linux 4.11.5) loaded from SeaBIOS, GRUB2, and Linux payload
- all PCI and PCI Express slots
Issues:
- sometimes the machine fails to boot, with serial debug output it can
be seen it stucks after SMM initialization, and more likely to fail
to boot when serial cable is attached
- no S3 resume (not tested in vendor firmware)
Change-Id: I94fbfcee06921538b32aa3c23efa642e7e405ef6
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/20227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Add two additional LED IDs.
Add Kconfig menu entries to allow selecting the action
to execute on death.
Overwrite weak die_notify method to notify user on death.
Flash all LEDs and play beep code 10 depending on Kconfig
options.
Successfully tested on:
Tested on Lenovo T500.
Tested on Lenovo X200.
Tested on Lenovo T430, but only LEDs are flashing.
Change-Id: Id34d399f154952a48c1f4ccb0c41a238b2d7ccb8
Signed-off-by: Patrick Rudolph <siro@das-labor.org
Reviewed-on: https://review.coreboot.org/19695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Current coreboot does not create ACPI device for OS to recognize Raydium
touchscreen.
List the touch screen in the devicetree so that the correct ACPI device
are created.
BUG=b:64821783
BRANCH=reef
TEST=emerge-snappy coreboot
Change-Id: I8852e38f01f82b80c2c9718b93baf5894dbd745b
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/21083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
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Current coreboot does not create ACPI device for OS to recognize MELFAS
touchscreen.
List the touch screen in the devicetree so that the correct ACPI device
are created.
BUG=b:64779224
BRANCH=reef
TEST=emerge-snappy coreboot
Change-Id: If2bc910d641e0cf2b120ed883c5788542959f568
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/21067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Get microcode patch pointer from intel_mp_current_microcode() api
of mp_init and change sgx_configure function signature to drop
microcode_patch param.
Change-Id: I9196c30ec7ea52d7184a96b33835def197e2c799
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21009
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Select LPSS UART Base address based on LPSS UART port index.
Change-Id: I31b239e7e6b7e9ac8ea2fcfbcbd8cb148ef9e586
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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Select LPSS UART Base address based on LPSS UART port index.
Change-Id: I306d3d299f8d6a890ae519c74008f9d0d9dd1a76
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Cannonlake SOC has two possible ways to make serial
console functional.
1. Legacy IO based access using Port 0x3F8.
2. LPSS UART PCI based access.
This patch to provide option to select index for LPSS
UART port: 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2
PCI based LPSS UART2 is by default enabled for Chrome Design.
Change-Id: I7afa5ab2c5eb06e6df8eeb1cb1cd0de00d2b2a28
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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Skylake/Kabylake SOC has two possible ways to make serial
console functional.
1. Legacy IO based access using Port 0x3F8.
2. LPSS UART PCI based access.
This patch to provide option to select index for LPSS
UART port: 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2
PCI based LPSS UART2 is by default enabled for Chrome Design.
Change-Id: I9647820fe59b5d1a1001a611b9ae3580946da0ae
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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Remove the duplicate MISCCFG_GPE0_DW* macros that are already present
in the common gpio code.
Change-Id: Iad75e5f7e276b37b5861f0c9a3bb0bb2824a638c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Add mp_current_microcode() function to get the microcode patch pointer.
Use this function to avoid reading the microcode patch from the boot
media. init_cpus() would initialize microcode_patch global variable to
point to microcode patch in boot media and this function can be used
to access the pointer.
Change-Id: Ia71395f4e5b2b4fcd4e4660b66e8beb99eda65b8
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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FSP might have done some settings for us there. Use pci_update_config32()
since the register is documented to be 32 bits wide.
Change-Id: I995e8a731a6958f10600174d031bb94f5a0a66db
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/21072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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Update Psi2Threshold, IccMax, ACLoadline and DCLoadline VR config
settings to match that of soraka.
BUG=b:62063434
BRANCH=None
TEST=Build and boot poppy.
Change-Id: I2c294eb14257d319e1e2d4d1e529481d921ba6f8
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21105
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
|
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Poppy uses MPS2949 IMVP8 controller and does not need the VR
workaround similar to Eve.
Change-Id: If6fb1890e024e1488d278bbe0a71a1a63ee321af
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21104
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
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Relevant changes (commit 2e8761e):
* Add an option to truncate the ME image file
* Add full support for Skylake (ME 11) and following, including
modules removal, truncation informations and partition
relocation
* Add two options to generate a shrinked ME image file and the
corresponding descriptor with a modified flash layout
* Update README.md
* Bug fixes
Also add a link to the usage guide in the Kconfig help.
Change-Id: I690c5d558139f64f38babf3c0988b53834ba8b37
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/20915
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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Clear LAST_BYTE flag at beginning of block commands.
For reads, slave device determines in the message format how
many bytes it has to transfer out, host firmware only dictates
the maximum buffer length. Return SMBUS_ERROR if only
partial message was received.
For writes, return SMBUS_ERROR if length > 32.
For writes, fix off-by-one error reading memory one
byte past the buffer end.
Change-Id: If9e5d24255a0a03039b52d2863bc278d0eefc311
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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A small typo in the dll setting code prevented this combination from
booting.
TESTED on ga-g41m-es2l with 800MHz FSB CPU and 667MHz ddr2
Change-Id: Ib013471773c20336ba0902b7f328bfb6ef970747
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Moves receive enable calibration to a separate file to lighten
raminit.c a bit.
Receive enable calibration is quite similar to gm45 so it reuses some
of its function names.
The functional changes are:
* the minimum coarse is now reset for each channel;
* on the second fine search for DQS high, TAP overflow is handled by
increasing medium;
* start coarse at CAS + 1 instead of CAS - 1. Other Intel northbridges
do the same and the results are more in line with register dumps
from vendor bios.
These might improve stability.
TESTED on ga-g41m-es2l
Change-Id: I0c970455e609d3ce96a262cbf110336a2079da4d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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On this device libgfxinit successfully initializes textmode and
framebuffer mode on the device connected to the HDMI1 port.
VGA port is not tested, due to lack of VGA with valid EDID.
Every ports works on GNU/Linux with kernel version 4.9+80+deb9u1.
Due to limitations within the libgfxinit's current build system,
it needs "select NORTHBRIDGE_INTEL_IVYBRIDGE" to work, even it is
PCH instead of CPU for which libgfxinit should be configured here.
Change-Id: Ib1513fc57b79eebc5d047c2e24585731c44bc215
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/21071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Fail at build-time if one of the following happens:
Platform includes SMI handler setup function smm_init()
in the build when configuration has HAVE_SMI_HANDLER=n.
Platform does not implement smm_init_completion() when
HAVE_SMI_HANDLER=y.
Change-Id: I7d61c155d2b7c2d71987980db4c25d520452dabf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Fix low memory corruption on S3 resume path.
Affected platforms were sandy/ivybridge.
Change-Id: I7379e7396b61ee4dc2438276d530feffaa1bc8f2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21100
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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SMM relocation code overwrite low memory owned by OS.
Change-Id: Ifa3d28bed3d3db65b0707bde62ae2b424a231f1a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19405
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I7c138758707f87c0d7a827b6887c7752d3714cde
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I2d6fdfd0465fe5f558daa04c6f980f7226596b55
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21087
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Instead of enabling power button SMI unconditionally, add a boot state
handler to enable power button SMI just before jumping to
payload. This ensures that:
1. We do not respond to power button SMI until we know that coreboot
is done.
2. On resume, there is no need to enable power button SMI. This avoids
any power button presses during resume path from triggering a
shutdown.
BUG=b:64811381
Change-Id: Icc52dc0103555602c23e09660bc38bb4bfddbc11
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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... is enabled. Otherwise we are compiling an effectively
empty file.
Change-Id: I4e3d982066d1fa66a3da5f37e278ec7fd5bb1ea8
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
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Reuse generic I2C functions that work for SMBus operations as well.
Change-Id: I5a93f17b905de38752254891aa4347ba4ed3b205
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: Ib31e77eec639c231520198c0b978d6c3c1eadaed
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Do not use the global platform_i2c_transfer() function that can only be
implemented by a single driver. Instead, make a `struct device` aware
transfer() function the only interface function for I2C controller dri-
vers to implement.
To not force the slave device drivers to be implemented either above
generic I2C or specialized SMBus operations, we support SMBus control-
lers in the slave device interface too.
We start with four simple slave functions: i2c_readb(), i2c_writeb(),
i2c_readb_at() and i2c_writeb_at(). They are all compatible to respec-
tive SMBus functions. But we keep aliases because it would be weird to
force e.g. an I2C EEPROM driver to call smbus_read_byte().
Change-Id: I98386f91bf4799ba3df84ec8bc0f64edd4142818
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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