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2020-02-18mb/intel/glkrvp/chromeos.fmd: Correct indentationAngel Pons
Tested with BUILD_TIMELESS, no changes. Change-Id: Iaf615e95a30e9c02ad49351a3c0db253ad713ad4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-18cpu: Allow to configure microcode at pre-defined addressAndrey Petrov
FSP-T takes microcode pointer and location parameters, and FSP-T is invoked before CAR is set-up and before memory is trained. So it is not possible to modify supplied microcode pointer in runtime. Because of that we have to hardcode the pointer in bootblock. Also, current FSP-T on Xeons require microcode (it is not optional). Reasons for that are currently unclear and are being investigated. However for the present time we need to be able to add microcode at a certain offset so FSP-T can be used. TEST=test on OCP TiogaPass board, as well as out-of-tree CPU/board Change-Id: I6c02601a7ac64078e556e2032baeccaf27f77da2 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-02-18mb/facebook/monolith: Use serial number and UUID from VPDWim Vervoorn
The serial number and UUID returned by DMI are retrieved from VPD. The solution supports a 16 character "serial_number" and a 36 character "UUID" string. BUG=N/A TEST=tested on monolith Change-Id: I0b6ce769cfa81a1e248a35f6149b7d1bbcf1f836 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-02-18mb/facebook/monolith: Enable use of VPDWim Vervoorn
Enable use of VPD for monolith. This will be used to store the UUID and Serial number. BUG=N/A TEST=build Change-Id: I32b60fef44929c51427a124cbb81e5246db2546c Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-02-18soc/intel/common: Add function to wait for CSE to enter Soft Temp Disable modeSridhar Siricilla
Below helper function is added: cse_wait_com_soft_temp_disable() - It polls for CSE's operation mode 'Soft Temporary Disable'. CSE enters this mode when it boots from RO(BP1) partition. The function must be called after resetting CSE to wait for CSE to enter 'Soft Temporary Disable' Mode. BUG=b:145809764 Change-Id: Ibdcf01f31b0310932b8e834ae83144f8a67f1fef Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-02-18soc/intel/common: Check prerequisites for HMRFPO_GET_STATUS commandSridhar Siricilla
Send HMRFPO_GET_STATUS command when CSE's current working state is Normal. TEST=Verified on hatch. Change-Id: I4380e5096c6346d88aae6826d19a2f4ed1e97036 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-02-18cpu/x86/name: Make name.c file available in romstageUsha P
In this patch, name.c file that includes the function definition for fill_processor_name which is used by the report_cpu_info function is been made available in romstage. This is done to facilitate the report_platform_info to be called from romstage, as the intention is to move the report_platform_info to romstage for all SOC's due to the bootblock size constraint. BUG=None TEST=Build and boot APL, GLK and CNL platforms. Change-Id: Ifd6d4b80c2e07d02adaed676a56efeb6fb704552 Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-02-18ec/google/chromeec: Add SSDT generator for ChromeOS ECTim Wawrzynczak
Upcoming patches for the Linux kernel (5.6 ?) would like to consume information about the USB PD ports that are attached to the device. This information is obtained from the CrOS EC and exposed in the SSDT ACPI table. Also, the device enable for this PCI device is moved from ec_lpc.c to a new file, ec_chip.c, where EC-related ACPI methods can live. It still allows other code to call functions on device enable (so that PnP enable for the LPC device still gets called). BUG=b:146506369 BRANCH=none TEST=Verify the SSDT contains the expected information Change-Id: I729caecd64d9320fb02c0404c8315122f010970b Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-18security/vboot: Correct help text of VBOOT_STARTS_IN_ROMSTAGEYu-Ping Wu
Since CB:37231 [1], the vboot working data has been replaced with vboot work buffer, so corrrect the help text of option VBOOT_STARTS_IN_ROMSTAGE accordingly. [1] security/vboot: Remove struct vboot_working_data BRANCH=none BUG=chromium:1021452 TEST=none Change-Id: I80783274179ae7582bbb4c8f9d392895623badce Signed-off-by: Yu-Ping Wu <yupingso@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com>
2020-02-18nb/intel/sandybridge: Add Xeon E3-1200 (v1) hostbridge PCI IDJonathan A. Kollasch
Change-Id: I70187d09ecdaa8149299cdd8f6f8fc9517b05e15 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-18nb/intel/sandybridge: use list of northbridge device IDsJonathan A. Kollasch
Change-Id: Ida311a7b0c1f33b1724a07c7cd64ea9834cfc179 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38882 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-18volteer: allow empty SPD_SOURCESPaul Fagerburg
Some Volteer variants might not use SPD files. Allow SPD_SOURCES in spd/Makefile.inc to be empty. BUG=None BRANCH=None TEST=Build coreboot and see that it builds without error Signed-off-by: Paul Fagerburg <pfagerburg@google.com> Change-Id: I5a8231b999e16503867d3c8df571b11fa0c1f6a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-17treewide: capitalize 'BIOS'Elyes HAOUAS
Also replace 'BIOS' by coreboot when the image is 'coreboot.rom'. Change-Id: I8303b7baa9671f19a036a59775026ffd63c85273 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-17ec/lenovo/h8/acpi: Add alternative Fn-F2 and Fn-F3 layoutNicola Corna
thinkpad_acpi maps the battery hotkey (KEY_BATTERY) on scancode 0x01 and the lock hotkey (KEY_COFFEE) on scancode 0x02. On the Thinkpad X1 Carbon (and possibly others), the hotkeys for Fn-F2 and Fn-F3 are different from the default one so a new layout has to be defined. Change-Id: Ib2d96be1a7815d7d03e6e8c6d300fd671c8598ca Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-02-17mb/google/slippy: Fix IRQ of the ambient light sensorNicolò Veronese
Change based on google/auron that is similar to peppy. This will be helpful for the next follow-up commit that will add ACPI for the ambient light sensor. Change-Id: Ib2a8356d261d211d5ed5c0b035c94ec56b9c25b3 Signed-off-by: Nicolò Veronese <nicveronese@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-02-17soc/intel/tigerlake: Enable Audio on TGLSrinidhi N Kaushik
Configure UPDs to support Audio enablement. Correct the upd name in jslrvp devicetree to avoid compilation issue. BUG=b:147436144 BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Idd3927a33d303ed5a663b5b838f43ed4ebc7a0db Reviewed-on: https://review.coreboot.org/c/coreboot/+/38147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-02-17nb/amd/pi/00730F01: enable ACS and AER for PCIe portsMichał Żygowski
Enable Access Control Services and Advanced Error Reporting for PCI Express bridges in order to have PCIe devices in separate IOMMU groups for correct passthrough. TEST=run dmesg on Debian Buster on PC Engines apu2 and check whether PCIe devices have separate groups Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I10a8eff0ba37196692f9db6519e498fe535ecd15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-17vboot: rename GBB flag FAFT_KEY_OVERIDE to FLAG_RUNNING_FAFTJoel Kitching
This was renamed in vboot_reference CL:1977902. BUG=b:124141368, chromium:965914 TEST=make clean && make test-abuild BRANCH=none Change-Id: I79af304e9608a30c6839cd616378c7330c3de00a Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-02-17src/intel: Define HFSTS3 registerSridhar Siricilla
Changes: 1. Define HFSTS3 register across SoCs(apl/cnl/icl/tgl). 2. Define cse_is_hfs3_fw_sku_custom() which checks ME's Firmware SKU is Custom or not. TEST=Verified on hatch, soraka, bobba and iclrvp. Change-Id: I4188e58a4a08d87be2d84674e00ed1407fb8bf82 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-02-17mb/google/drallion/variants/drallion: Update thermal configuration for DPTFJohn Su
Follow thermal table for fine tuning. 1. Update PSV values for sensors. 2. Change PL1 min value from 4W to 5W. 3. Change PL1 max value from 15W to 12W. 4. Change PL2 min value from 15W to 12W. BUG=b:148627484 TEST=Built and tested on drallion Change-Id: I957d41e3c14f6dbcec8c3555382895698beabe40 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2020-02-17soc/intel/skl: Rename me_hfs union into me_hfstsSridhar Siricilla
Rename below union tags for consistency: me_hfs2 -> me_hfsts2 me_hfs3 -> me_hfsts3 me_hfs6 -> me_hfsts6 TEST=Verified on Soraka Change-Id: Ibb53e6a5f2b95021f86b3e42e100b711b7d6e64e Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-17src/soc/tigerlake: Accomodate JSP specific changes in iomap.hMeera Ravindranath
Updating MCH, GSPI And I2C base addresses for JSP in iomap header. BUG=None BRANCH=None TEST=Compilation for Jasper lake board is working Change-Id: Ia8e88e02989fe80d7bd1f28942e005cb0d862fcb Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38754 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-17mb/google/drallion: Set cpu_pl2_4_cfg to baseline for DrallionJohn Su
Proper VR settings will be selected by CPU SKU and cpu_pl2_4_cfg. BUG=b:148912093 BRANCH=None TEST=build coreboot and checked IA_TDC from TAT tool. Change-Id: Ie471dee0c70e1831a822860c0a44455772a2b8be Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Mathew King <mathewk@chromium.org>
2020-02-17drivers/intel/gma: Print EDID with leading instead of trailing spacePaul Menzel
This way, the block is a little indented below `EDID:` making it a little more structured for the eye. Change-Id: I12066efefb23c5ffa8ba6b8c486cd54e142d4dc1 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-02-17drivers/intel/gma: Remove space between `printf ()`Paul Menzel
Fix the warning below. WARNING: space prohibited between function name and open parenthesis '(' Change-Id: I28d9ba64c790c659040cd34eda37125e191dab39 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-02-17lib/edid: Zero struct only when usedPaul Menzel
Change-Id: I1c14e7458153fb992b17f30d7015321fae533bb2 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-17lib/edid.c: Remove trailing space from detailed mode outputPaul Menzel
When the bit for interlaced mode is not set, a trailing space is added to the end. As the space is already accounted for in `" interlaced"`, remove that space. TEST=Boot on Lenovo X60t, and verify the trailing space in the detailed mode is gone. Change-Id: I4114c9e61a040fa005c806404ec51c12e2f02f4d Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/17644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-02-17mb/google/octopus/variants/dood: add two new SKU IDsKenneth Chan
add SKU ID 3 and 4 for dood DVT 1: Dood WiFi + LTE (evt) 2: Dood WiFi (evt) 3: Dood WiFi + LTE + dual camera (dvt) 4: Dood WiFi + dual camera (dvt) BUG=b:148988979 TEST=build firmware and verify on the DUT of sku 3 and 4 check LTE module is enabled or not Change-Id: If86efe2a2f7b2e165ad44220b6dd59e9080b5892 Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38730 Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-17mb/google/drallion: Correct USB3 OC pin configurationEric Lai
USB3 OC pin is configured for the wrong pin. Follow HW circuit (schematics) to set it correctly. BUG=b:147869924 TEST=USB function works well and OC function is corresponds to the right port. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I61234a2054ab52fa508482d3dd0f94b13f96a5c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38885 Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-17mb/google/puff: Enable SPD_READ_BY_WORD to short the boottimeJamie Chen
Puff uses the smbus to access the SPD of memory DIMMs. It will short the SPD reading time if enabling SPD_READ_BY_WORD. BUG=b:149360051 BRANCH=None TEST=build puff and boot up OS ran cbmem -t | grep FspMemoryInit Without this patch: 950:calling FspMemoryInit 643,199 (257,588) With this patch: 950:calling FspMemoryInit 477,714 (154,612) Signed-off-by: Jamie Chen <jamie.chen@intel.com> Change-Id: I161e8eb386ab604b16746f0deeecc3d6c9063c3a Reviewed-on: https://review.coreboot.org/c/coreboot/+/38848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-02-17soc/mediatek: dsi: Correct bits_per_pixel for MIPI_DSI_FMT_RGB666Yu-Ping Wu
The number of bits per pixel for MIPI_DSI_FMT_RGB666 should be 24 instead of 18. BRANCH=none BUG=none TEST=none Change-Id: I9574502b2dec4b5a042df3886922ddd8c755da1a Signed-off-by: Yu-Ping Wu <yupingso@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jitao Shi <jitao.shi@mediatek.corp-partner.google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-02-17mb/google/kukui: fine tune the video timing of panel-BOE_TV101WUM_N53Jitao Shi
Fine tune the video timing of panel-BOE_TV101WUM_N53 to avoid noise. The parameters are based on BOE NV101WUM-N53 preliminary product spec. BRANCH=kukui BUG=b:147378025 TEST=bootup pass Change-Id: Ia9e2cc90f233e87d712c2dc6f4441ca2e5423162 Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38401 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-17soc/mediatek: dsi: reduce the hbp and hfp for phy timingJitao Shi
The extra data transfer in DSI, namely, lpx, hs_prepare, hs_zero, hs_exit and the sof/eof of DSI packets, will enlarge the line time, which causes the real frame on dsi bus to be lower than the one calculated by video timing. Therefore, hfp_byte is reduced by d_phy to compensate the increase in time by the extra data transfer. However, if hfp_byte is not large enough, the hsync period will be increased on DSI data, leading to display scrolling in firmware screen. To avoid this situation, this patch changes the DSI Tx driver to reduce both hfp_byte and hbp_byte, with the amount proportional to hfp and hbp, respectively. Refer to kernel's change in CL:1915442. Also rename 'phy_timing' to 'timing' to sync with kernel upstream. Since the phy timing initialization sequence has been corrected, the m value adjustment in the analogix driver can be removed. BUG=b:144824303 BRANCH=kukui TEST=emerge-jacuzzi coreboot TEST=Boots and sees firmware screen on krane and juniper TEST=No scrolling issue on juniper AUO and InnoLux panels Change-Id: I10a4d8a4fb41c309fa1917cf1cdf19dabed98227 Signed-off-by: Yu-Ping Wu <yupingso@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-02-17soc/mediatek: dsi: Increase pcw precisionYu-Ping Wu
When configuring MIPI DSI Tx, the value of pcw was calculated from data rate in MHz, leading to loss of precision. This patch changes to use data rate in Hz for the calculation so that the resulting value should be consistent with the one in kernel (CL:1786327). In addition, change the type of data rate to u32, and calculation of data rate from pixel clock is changed to use DIV_ROUND_UP for consistency with kernel (CL:1761843). Also remove unused variable txdiv. BRANCH=kukui BUG=b:149051882 TEST=emerge-jacuzzi coreboot TEST=No scrolling issue on Juniper AUO and InnoLux panels Change-Id: I23220d446833b956431006027bbc8cb20fc696a5 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38827 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-17mb/google/kukui: Add panel for KakaduCasper Chang
Declare the following panel for Kakadu: - BOE_TV105WUM_NW0 BUG=b:148997748 TEST=build Kakadu image passed BRANCH=kukui Signed-off-by: Casper Chang <casper_chang@bitand.corp-partner.google.com> Change-Id: I394b8cafa8be40e5fd6bf8ceb81b520df73718a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38822 Reviewed-by: Peichao Li <peichao.wang@bitland.corp-partner.google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-17soc/tigerlake: Add Device id for Tiger Lake Dual CoreSrinidhi N Kaushik
Add device id for Tiger Lake Dual core part. BUG=b:148965583 BRANCH=none TEST="emerge-tglrvp coreboot chromeos-bootimage", flash and boot Change-Id: Ied0cef2fcc8ae6f25949f98f886c4d79f64b54cd Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-02-17mb/google/octopus: Add custom SAR values for BipshipTony Huang
Bipship is a sustaining project of Blooguard. SAR value follow Blooguard. BUG=b:149414960 BRANCH=octopus TEST=build and verify load correct SAR value by sku-id Change-Id: Ic45ed10fc147401d4278f1811a86cd2b2e4c63ac Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-02-17mb/google/dedede: Configure I2C portsKarthikeyan Ramasubramanian
Enable I2C ports that are used. Add GPIO configuration for the I2C ports. Enable config items that are required for I2C HID & Generic devices. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I12e974530fb5f61fae5d12cadbb3f928e617d73a Reviewed-on: https://review.coreboot.org/c/coreboot/+/38847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-02-17mb/google/dedede: Add console UART configurationKarthikeyan Ramasubramanian
Enable UART Port 2 as console UART and configure the concerned GPIOs. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I30a64a3c96226ce3244d55919b6d65fbf0a096e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38776 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-17mb/google/dedede: Enable AP <-> H1 CommunicationKarthikeyan Ramasubramanian
Turn on the H1 device in the devicetree. Configure the concerned GPIOs and enable the required config items. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I37972635454cd0d35608623e7be4110012ace658 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38772 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-17cpu/x86/smm: Remove blank line in codeEugene Myers
Remove blank line to maintain the relation between the previous comment and the remainder of the block. Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov> Change-Id: Ib9754c6723ecd5e4895898490fc7228e1c3839d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38821 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-17cpu/x86: Remove unnecessary guardEugene Myers
The is_smm_enabled is not necessary because it is done previously in this code path. Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov> Change-Id: I20d50acbea891cb56ad49edc128df25d21c5f1ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/38820 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-17cpu/x86: Adjust STM smm_save_state_sizeEugene Myers
Initial testing of STM support revealed a sizing issue for greater than 4 threads. This patch reduces the STM smm_save_state_size, which should allow for 24 threads. Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov> Change-Id: I025694185469577e072a92ea75cbbb53c24b2c24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38819 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-17ec/purism/librem: Add ACPI temp reportingMatt DeVillier
Add EC ACPI reporting of current temp and platform critical temp. Adapted from ACPI dump of ODM AMI firmware. TEST: check reporting of current/critical temps via lm-sensors from ACPI on Librem 13v1 and 13v4 boards. Change-Id: I92641fbbdda46e0c388607a37f7a7cc2dcd6c26d Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-17Revert "mb/google/hatch: Override CPU flex ratio"Tim Wawrzynczak
This reverts commit a017e5fb3dda5ea6bbc94ee15b2e981eeaa2d918. Reason for revert: The extra reset in the FSP after the flex ratio is changed causes recovery reasons to be lost. There are some vboot changes that recently landed that could help with this issue, but for now, we are working on a new AU image for Kohaku and this is causing our automated testing to fail. Change-Id: Ic38b390842e2a533033587b3247b7c8d982b1dff Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-17mb/apple/macbookair4_2: Add CMOS supportEvgeny Zinoviev
Added CMOS support for MacBook Air 4,2. In future, I hope there will be more useful options available, because I'm working on macbooks support. Also, it may be necessary for hyper_threading support (#29669) once it will be ready. Change-Id: I369ed9aeff2098a4840918531be6a34cfc8d2a1e Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
2020-02-17soc/intel/{cnl,icl,skl,tgl}/bootblock: Update text for DMI PCR 2774Wim Vervoorn
Make sure the Skylake comment refers to the correct BWG paragraph and update the text for all. BUG=N/A TEST=build Change-Id: Id383f200e079bdb91cea2240bd7a957d723a7b89 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-02-17soc/intel{cnl,icl,skl,tgl}/bootblock: Make sure DMI PCR 2770 is setWim Vervoorn
DMI PCR 2770 (LPC IO DECODE RANGES) should be identical to LPC PCI offset 0x80. This is specified in PCH BWG par 2.5.1.5. Add the support to make sure this PCR is always set correctly. BUG=N/A TEST=tested on facebook monolith. Change-Id: I33ff2b96dea78b5ff1c7c9416cf74f67d79f265d Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38746 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-17nb/intel/gm45: Fix typo in console messageElyes HAOUAS
Change-Id: Ia0d7d5ecf376af97ee54ff3ca536160202e43f79 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-02-17nb/intel/nehalem: Remove unused MRC_CACHE_SIZEElyes HAOUAS
Change-Id: I5d00fb238be6399ea6e9f394d8f899b03b1d44cf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-02-17vboot: remove VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT optionJoel Kitching
With CL:1940398, this option is no longer needed. Recovery requests are not cleared until kernel verification stage is reached. If the FSP triggers any reboots, recovery requests will be preserved. In particular: - Manual requests will be preserved via recovery switch state, whose behaviour is modified in CB:38779. - Other recovery requests will remain in nvdata across reboot. These functions now only work after verstage has run: int vboot_check_recovery_request(void) int vboot_recovery_mode_enabled(void) int vboot_developer_mode_enabled(void) BUG=b:124141368, b:35576380 TEST=make clean && make test-abuild BRANCH=none Change-Id: I52d17a3c6730be5c04c3c0ae020368d11db6ca3c Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38780 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-17vboot: push clear recovery mode switch until BS_WRITE_TABLESJoel Kitching
Serves two purposes: (1) On some platforms, FSP initialization may cause a reboot. Push clearing the recovery mode switch until after FSP code runs, so that a manual recovery request (three-finger salute) will function correctly under this condition. (2) The recovery mode switch value is needed at BS_WRITE_TABLES for adding an event to elog. (Previously this was done by stashing the value in CBMEM_ID_EC_HOSTEVENT.) BUG=b:124141368, b:35576380 TEST=make clean && make test-abuild BRANCH=none Change-Id: I30c02787c620b937e5a50a5ed94ac906e3112dad Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-02-15mb/intel/jasperlake_rvp: Enable only required PCIE root portsUsha P
Jasper Lake SOC has 8 PCIe root ports. Cleaning up the root ports as per Jasper Lake. This patch updates the devicetree to enable WLAN and NVME for jasperlake_rvp and removes the other root port configurations which are not required. Change-Id: I6c801d81ccece6b45a7c45212533bb33a6805367 Signed-off-by: Usha P <usha.p@intel.com> Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38679 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-15soc/tigerlake: Update xhci ACPI files for JSPMeera Ravindranath
ACPI files for xhci in JSL is different from TGL. Hence, renaming xhci.asl to xhci_tgl.asl and adding a new file xhci_jsl.asl for JSL. Also, allowing xhci.asl to choose the correct file based on the SoC selected. BUG=None BRANCH=None TEST=Compilation for JasperLake board is working Change-Id: Ia8e88e02989ff80d7cd1f28941e005cb0d842fcb Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-02-15soc/intel/tigerlake: Update PMC Register Base and platform check for JSPUsha P
Change: 1. PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP to 0X0A00 for JSP 2. Platform check in espi.c BUG=None TEST= 1. Test for JSL RVP Boot 2. Verify PMC register values are valid for GEN_PMCON and GBLRST_CAUSE from the coreboot console logs. Change-Id: I6017a9703764b5454e7be479c1e08afe614908f1 Signed-off-by: Usha P <usha.p@intel.com> Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38704 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-15soc/intel/tigerlake: Update Kconfig related to JSLUsha P
Update Kconfig: 1. select INTEL_CAR_NEM for SOC_INTEL_JASPERLAKE 2. Update the right value of MAX_ROOT_PORTS and MAX_PCIE_CLOCKS for SOC_INTEL_JASPERLAKE Change-Id: I4aa52c80bfd6134164a0925ea548579b3cc54a55 Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-02-14mainboard/supermicro: x11ssm-f: disable SUART3/4Michael Niewöhner
SUART3/4 are unused on this board (verified by checking registers on vendor BMC firmware). Further they break the console for an unknown reason. Thus disable them. Change-Id: I30bb8184d03ee1037d9ec33eb1d93ee540563fc5 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38818 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-14mainboard/supermicro: x11ssh-tf: drop leftovers of SUART3/4Michael Niewöhner
SUART3/4 are unused on this board (verified by checking registers on vendor BMC firmware). Thus drop the remaining settings. Change-Id: I2ababd92fcd7016c508aa3119e798f75eeb90a1c Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38817 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-14vboot: fix up some includesJoel Kitching
These header files need to make use of vb2_shared_data. Remove the last vestiges of vboot1 data structures in coreboot. BUG=b:124141368, chromium:1038260 TEST=Build locally with CL:2054269 TEST=make clean && make test-abuild BRANCH=none Change-Id: I61b27e33751c11aac9f8af261a75d83b003b5f92 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38884 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-13mainboard/supermicro/x11-lga1151: correct board idsMichael Niewöhner
X11SSM-F has a different board id (0896) than X11SSH-TF (089C). Use the right id for the right board. Change-Id: Ib0d5e66ce1a973f29a1da78f04f7ef677b260cd8 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-02-13mb/pcengines/apu2: Remove unnecessary initializationPaul Menzel
The variable is never read before being assigned a value at the end of the function. Change-Id: I3b42dcd564480005b2c520316933940d87b6e418 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2020-02-13mb/pcengines/apu2: Use variable `len` holding same valuePaul Menzel
Change-Id: Ia5916f191a7b1a846231b7e36924a16f3a658961 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2020-02-12arch/arm64/Makefile.inc: Avoid # in variable definitionNico Huber
Interpretation if # starts a comment inside a variable definition varies between GNU make versions. Use a wildcard to match the first # and use `sed` instead of `grep | cut` to avoid unbalanced quoting chars. Tested with GNU make 4.2.1 and 4.3. Both produce the same output as 4.2.1 did before the patch. Change-Id: Ib7c4d7323e112968d3f14ea0590b7dabc57c9c45 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-02-12nb/intel/sandybridge/acpi: Fix MMCONF size computationPatrick Rudolph
Calculate the correct MMCONF size, which was only correct for 256MiB, but not for smaller values. Tested on HP Z220: Fixes "Not using MMCONF" warning in dmesg. Change-Id: I986681126637c28f6442ab7c34acea5bb58ea3d2 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jonathan Kollasch <jakllsch@kollasch.net>
2020-02-12nb/intel/sandybridge/acpi: Update PEG codePatrick Rudolph
* Use new ACPI syntax * Return either 0 or 0xf for PCI root port. That will make the device show up in Windows. This might help users and possibly Windows drivers working with PCIe ports. Change-Id: I1e76b735ab1472f6a4ea493c733cd6b2e6fca29e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-02-12soc/intel/{skl, common}: Move ME Firmware SKU Types to common codeSridhar Siricilla
1. Move ME firmware SKU types into common code. 2. Define ME_HFS3_FW_SKU_CUSTOM SKU. TEST=Verified on hatch & soraka. Change-Id: Iaa4cf8d5b41c1008da1e7aa63b5a6960bb9a727b Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-11vendorcode/intel: Remove Ice Lake FSP BindingsJohanna Schander
By updating the FSP submodule we now got all FSP headers from within that repo. This commit changes the default paths to use these and fixes some include paths to allow the usage of vendorcode/intel/edk2/UDK2017 together with the official Intel distribution. We are also adding back the CHANNEL_PRESENT enum, that is missing in the official headers. This was tested on the Razer Blade Stealth (late 2019). Change-Id: I7d5520dcd30f4a68af325125052e16e867e91ec9 Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37579 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christoph Pomaska <github@slrie.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-11mb/google/volteer: use new Tiger Lake memory configNick Vaccaro
Some of the common memory code that was being performed in mainboard has moved into the soc to reduce redundant code. This change adapts volteer to use Tiger Lake's new common code. BUG=b:145642089, b:145238504, b:145564831 BRANCH=none TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer, boot to kernel, "cat /proc/meminfo" and verify it reports "MemTotal: 8038196 kB". Change-Id: I32c9b8a040728d44565806eece6cf60b6b6073b6 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-11arch/x86/acpi: Change message in acpi_write_dbg2_pci_uart to BIOS_DEBUGWim Vervoorn
When acpi_write_dbg2_pci_uart is called and no pci uart is available the function prints "Device not found" as an error. This is not correct. Change the error level to BIOS_DEBUG so coreboot reports the device is not available but doesn't flag this as an error. BUG=N/A TEST=build Change-Id: I14567bcfcf5a6ff427e418d15bc2675ae7a28f53 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-02-11mb/facebook/monolith: Enable the 2nd EC UART at 0x2f8Wim Vervoorn
BUG=N/A TEST=tested on facebook monolith Change-Id: I36e652e66c66eeb770a5a5d987bb57c7eaa11382 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38749 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-11soc/intel/common/block/lpc: Add lpc_get_fixed_io_decodeWim Vervoorn
Add function to return the fixed io decode ranges contained in register 0x80 of the LPC interface. BUG=N/A TEST=build Change-Id: Ie46d7c9d7a399a8489c030d906f75ba61db19cc4 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38745 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-11sb/intel/lynxpoint: Don't use_ADR and _HIDElyes HAOUAS
To be compliant with ACPI specification, device object requires either a _HID or _ADR, but not both. Change-Id: I45cf2b8d455aa4d288de1ac53cf9ae801f758a9a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38351 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-11mb/lenovo/x201/acpi_tables: Default to lid openPeter Lemenkov
It's really hard to power up this laptop with the lid closed so let's make it open by default, as done on many other laptops. Change-Id: I5bb2f716865c2bb569a4735f135842526043713c Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-11Kconfig: Add CONFIG_PCI dependency for CONFIG_MINIMAL_PCI_SCANNINGSubrata Banik
Make sure MINIMAL_PCI_SCANNING has right dependency over PCI kconfig symbol. Change-Id: I30b18345976e5d21ccedf8906985ff71e7d2815c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38801 Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-11Kconfig: Guard CONFIGURABLE_RAMSTAGESubrata Banik
This patch guards CONFIGURABLE_RAMSTAGE symbol (which is default enable for all x86 systems) with another Kconfig that can be selected by platform that actually planning to use it. TEST=CONFIG_CONFIGURABLE_RAMSTAGE is not enabled by default. Change-Id: I2113445d507294df59fbc7fb1373793b47c6c31c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-02-10vboot: correct workbuf size when VBOOT_STARTS_IN_ROMSTAGEJoel Kitching
Part of the design of vboot persistent context is that the workbuf gets placed in CBMEM and stays there for depthcharge to use in kernel verification. As such, the space allocated in CBMEM needs to be at least VB2_KERNEL_WORKBUF_RECOMMENDED_SIZE. In the VBOOT_STARTS_IN_ROMSTAGE case, prior to this CL, vboot_get_context() would get invoked for the first time after CBMEM comes up, and it would only allocate VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE. Initialize the workbuf directly in vboot_setup_cbmem() instead with the correct VB2_KERNEL_WORKBUF_RECOMMENDED_SIZE. BUG=b:124141368, chromium:994060 TEST=make clean && make test-abuild TEST=boot on GOOGLE_EVE with VBOOT_STARTS_IN_ROMSTAGE set BRANCH=none Change-Id: Ie09c39f960b3f14f3a64c648eee6ca3f23214d9a Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38778 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-09intel/stm: Add platform opt-in KconfigNico Huber
Selecting STM on an arbitrary platform would likely result in a brick, so let's hide the prompt by default. Change-Id: I50f2106ac05c3efb7f92fccb1e6edfbf961b68b8 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: <cedarhouse1@comcast.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-09cpu/intel: Drop unused fileElyes HAOUAS
Change-Id: I1b41ddc5e99838f0585089974e995f3de7be1791 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37161 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-09mb/lenovo/t400: Configure panel-power sequencingNico Huber
If the panel-power sequencer is not configured, libgfxinit falls back to very conservative defaults (210ms before EDID is probed). This results in a boot penalty of >100ms (depending on how long it takes to probe other ports). Values are taken from the VBTs already checked in. Untested. Change-Id: I189776ce8684b4c3c01acd6d2fc433ca33a050d5 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-02-09mb/lenovo/t400: Correct display port list for R500 variantNico Huber
The second digital display connector is unused, but strapped as if it were used. Versions with a discrete GPU seem to use PM45 (i.e. no IGD), so we can ignore these. Based on schematics only, not tested. Change-Id: Ibb47fdeef2adb9c574b7f3ec8e2b1d61d28f21da Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-02-09mb/lenovo/t400: Correct display port list for [TW]500 variantsNico Huber
T500 and W500 (Coronado-5) use both digital display connectors. Both with the DP AUX channel implemented, so add DP2 to the list. Versions with a discrete GPU don't use external, digital connectors but seem to have the straps correctly configured. So we hopefully won't have to handle these specifically. Based on schematics only, not tested. Change-Id: I31e1415eff2d5d00c4a231906e3d861d2a59b629 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-02-09mb/lenovo/t400: Correct display port list for [RT]400 variantsNico Huber
The first digital display connector is unused, but strapped as if it were on later revisions. The DP AUX channel of the second connector is implemented, though, so add DP2 to the list. Versions with a discrete GPU don't use external, digital connectors but seem to have the straps correctly configured. So we hopefully won't have to handle these specifically. Based on schematics only, not tested. Change-Id: I7d3e8b3a2123ddc407bb5a0cce86a3634b575f4a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-02-09mb/lenovo/t400: Move `gma-mainboard.ads` to variantsNico Huber
Some board revisions have the straps for display port detection wrongly configured. So with a single list covering all variants' possible outputs, we make libgfxinit probe unimplemented ports which may stall the GMBUS controller and delay the boot for some hundred milliseconds. This just copies the list to the various variants with different display ports, so we can test the actual changes individually. Change-Id: I48cdea1d71d9553b6bdbce432eae986996329239 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-02-09sb/amd/{agesa,pi}/hudson/Kconfig: Change default SATA mode to AHCIPiotr Kleinschmidt
The attempt to install pfSense on hard disk on PC Engines apu2 board ended up in a SATA driver error. The problem is related only to BSD and didn't occur with Linux kernel. Changing SATA mode from IDE to AHCI solved the problem. Additionally AHCI is faster than IDE so it speeds up the installation. Since AHCI works perfectly with SeaBIOS, Linux and BSD, make it a default choice for all Hudson southbridges. Change-Id: I1b0322392712d797dd5a8931150c8d0ff1b60940 Signed-off-by: Piotr Kleinschmidt <piotr.kleins@gmail.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35891 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-09mb/google/octopus/variants/lick: Increase TCC offset to 15Hash.Hung
Change tcc offset from 0 to 15 degree celsius for lick. BUG=b:147198431 BRANCH=octopus TEST=Build, and verify test result by thermal team. Signed-off-by: Hash.Hung <hash1.hung@lcfc.corp-partner.google.com> Change-Id: Ife6b02321145837e05c82f979998466b83317f86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38506 Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-09mb/google/dedede: Add initial configuration for serial IO portsKarthikeyan Ramasubramanian
Add initial configuration for GSPI, I2C and UART ports and leave them in disabled state. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I1cd7659337e6330a8ece34df247e399a085d21d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-02-09mb/google/dedede: Turn on ESPI device in devicetreeKarthikeyan Ramasubramanian
BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I12a63e5776619e5a7684cf1edad78b0fd6fac12c Reviewed-on: https://review.coreboot.org/c/coreboot/+/38739 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-09mb/google/dedede: Add GPE configurationKarthikeyan Ramasubramanian
Configure the GPIO groups to be routed to the GPE0 block. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ife4d0179bd9fe1785e971686478f7c76de805e87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-09mb/google/dedede: Add Compute & PCH Global device IDsKarthikeyan Ramasubramanian
Add compute and PCH Global device IDs with the concerned devices turned off. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I6f226abd52d4a27535de6711e93355b5f84a1941 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-09soc/intel/tigerlake: add memory configuration supportNick Vaccaro
Move some of the common memory code that was being performed in mainboard into the soc to reduce redundant code going forward. BUG=b:145642089 BRANCH=none TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer, log into kernel and verify memory size shows 8GB. Change-Id: I8de502d4f05d52b9dae34e3b013c6d5b1886fa55 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-09mb/google/volteer: add volteer mainboard initial supportNick Vaccaro
Created a new Google baseboard named volteer from scratch. BUG=b:142961277 BRANCH=master TEST="emerge-volteer coreboot" compiles successfully. Change-Id: I03a13f3df4e819ab9cf63ad69867c807d2a1b651 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-09mb/google/drallion: Add new SPD files for drallionIan Feng
Add new SPD files for drallion: 1. Hynix H5AN8G6NDJR-XNC 2. Samung K4AAG165WA-BCWE 3. Samung K4A8G165WC-BCWE BUG=b:148642500 TEST=Compile successfully and check SPD info in cbmem log. Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I0e9b444f6f1e0c7e1da197fbd2e70e686568ab47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38731 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-09mb/google/drallion: Tuning WWAN power sequenceEric Lai
Change GPP_C10 from pltrst to deep to meet the warmboot power sequence. BUG=b:146935222 TEST=measure WWAN power sequence is meet spec Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia1513ed38fbc1c99a10a5fa531a78cc92a3ebfc2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2020-02-09mb/google/dedede: Log mainboard events to elogKarthikeyan Ramasubramanian
BUG=b:148410914 TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I7dffa5c021787dca75786ead42164bd29ba56828 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-09mb/lenovo/t440p: Enable dGPU on Lenovo T440PChris Morgan
Enable the dGPU on the Lenovo T440P. It uses the same code (roughly) of the T430S. By default, it is set to be disabled however it can be enabled via the nvram option enable_dual_graphics. Removed hybrid graphics options too as they are not valid for the T440p. Tested on a T440P with Ubuntu 18.04.4 with Kernel 5.3.0-29 (successful). Tested on same machine with Windows 10 1909 (machine check exception bluescreen). Change-Id: Idf8c2c0d1ae34bda8736448d3e350396e3cf7a93 Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-02-09mb/google/octopus: Override VBT selection for BloogTony Huang
Since most of Bloog series SKUs need to disable DRRS support. If Bloog and Unprovisioned SKUs then return vbt.bin to enable DRRS support, return vbt_blooguard.bin for other SKUs to disable DRRS support. Bipship follow blooguard to disable DRRS support. BUG=b:148892903, b:147021309 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage check i915_drrs_status shows DRRS supported NO when SKU ID is bipship. Change-Id: I61f12d4ddea17a05255751fde2a5ce822dd2e782 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-02-09soc/intel/{cnl,icl,skl,tgl,common}: Make changes to ↵Sridhar Siricilla
send_heci_reset_req_message() Below changes have been implemented in send_heci_reset_req_message(): 1. Modify return values to align with other functions in the same file. 2. Add additional logging. 3. Replace macro definitions of reset types with ENUM. 4. Make changes to caller functions to sync with new return values. 5. Rename send_heci_reset_req_message() to cse_request_global_reset(). Test=Verified on hatch board. Change-Id: I979b169a5bb3a5d4028ef030bcef2b8eeffe86e3 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37584 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-09soc/intel/common: Add description to HMRFPO statusSridhar Siricilla
Below changes are implemented: 1. Fix typos. 2. Rename 'padding' field of hmrfpo_get_status_resp struct to 'reserved' to match with ME BWG Guide. 3. Add documentation for HMRFPO Status. TEST=Build and boot hatch Change-Id: I4db9bdf7386c48e17ed0373cf334ccff358d1951 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-09soc/intel/common: Rename functions for consistent namingSridhar Siricilla
Below changes are done: 1. Rename below functions to have consistent naming: set_host_ready() -> cse_set_host_ready() wait_cse_sec_override_mode() -> cse_wait_sec_override_mode() send_hmrfpo_enable_msg() -> cse_hmrfpo_enable() send_hmrfpo_get_status_msg() -> cse_hmrfpo_get_status() 2. Additional debug messages are added in cse_wait_sec_override_mode(). TEST=Build and Boot hatch board. Change-Id: Icfcf1631cc37faacdea9ad84be55f5710104bad5 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-09soc/intel/{common,skl,cnl,icl,apl,tgl}: Move HFSTS1 register definition to SoCSridhar Siricilla
Below changes are implemented: 1. Move HFSTS1 register definition to SoC since HFSTS1 register definition is specific to a SoC. Moving structure back to SoC specific to avoid unnecessay SoC specific macros in the common code. 2. Define a set of APIs in common code since CSE operation modes and working states are same across SoCs. cse_is_hfs1_com_normal(void) cse_is_hfs1_com_secover_mei_msg(void) cse_is_hfs1_com_soft_temp_disable(void) cse_is_hfs1_cws_normal(void) 3. Modify existing code to use callbacks to get data of me_hfs1 structure. TEST=Build and Boot hatch, soraka, tglrvp, bobba and iclrvp boards. Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-22 20:26:48 +0000