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2007-05-11Clean up whitespace in preparation for another patch to fix fan control.Ward Vandewege
This is nothing more than the result of running indent -npro -kr -i8 -ts8 -sob -l80 -ss -ncs adm1027.c Signed-off-by: Ward Vandewege <ward@gnu.org> Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2663 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-11The Super I/O needs 0x87 sent twice to 0x2e (or 0x4e) to enable extendedRoger Zauner
function (power-on strapping). Although this is already done in superio.c, it's not being done when w83627thf_early_serial.c is executed. As such, no console_init() without it. Signed-off-by: Roger Zauner <roger@eskimo.com> Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2662 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10Fixup the 440BX northbridge.c (self-ack as this wasn't working anyway).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2661 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10This fix properly hides the UDC and OTG PCI headers when the cs5536 isMarc Jones
setup as the host on USB port4. In client mode the headers remain available. Also fixes an outb to 0x80 to use the post_code() function. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2660 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10Changes by Richard Smith and Peter Stuge from the LinuxBIOS symposium 2006.Peter Stuge
With CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=0, 1 million outb():s are used for timer calibration, which takes about one second. All EPIA-M boards have timer2 so we use it to boot faster. Only some EPIA boards have the Nehemiah CPU with timer2 so we default to IO calibration but add the TSC options so that they can be set in Config.lb. src/mainboard/via/epia*/reset.c is dead code (entire file within #if 0) so we set HAVE_HARD_RESET=0 for both boards. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2659 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10This patch cleans up and clarifies Geode source code comments.Marc Jones
Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2658 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10This patch cleans up \r left in the print strings. They were required for ↵Marc Jones
romcc code but no longer needed in cache as ram code. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10This patch updates the PCI ID of the Geode IDE device to include the revision.Marc Jones
Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2656 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10Fixed a bug within the 440BX RAM size calculation. Since the DRB valuesCeri Coburn
on the 440BX are 8 MB units we need to shift left by 13 to get it into KB. Signed-off-by: Ceri Coburn <ceri.coburn@gmail.com> Signed-off-by: Roger Zauner <roger@eskimo.com> Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2655 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10indent is by no means as harmless as one might think ;-)Stefan Reinauer
trivial fix. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2654 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10The attached patch sets the MA map type correctly for all DIMMs I wasAlex Mauer
able to find to test with the Epia. Signed-off-by: Alex Mauer <hawke@hawkesnest.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2653 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10This patch removes auto.c from the Norwich mainboard directory. Marc Jones
Acked-by: Stefan Reinauer <stepan@coresystems.de> Signed-off-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2652 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10Fix the indent and whitespace to match LinuxBIOS standardsJordan Crouse
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2651 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10Fix the indent and whitespace to match LinuxBIOS standardsJordan Crouse
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2650 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10Fix the indent and whitespace to match LinuxBIOS standardsJordan Crouse
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2649 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10Fix the indent and whitespace to match LinuxBIOS standardsJordan Crouse
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2648 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10Add missing licenses to several of the files.Jordan Crouse
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2647 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10Add missing licenses to several of the files.Jordan Crouse
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2646 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-09The superio needs 0x87 sent twice to 0x3f0 to enable extended functionRoger Zauner
(power-on strapping). Although this is already done in superio.c, it's not being done when w83977tf_early_serial.c is executed. As such, no console_init() without it. Signed-off-by: Roger Zauner <roger@eskimo.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2645 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-09Uncomment compression config variables. This should fix the abuildUwe Hermann
problems with the asi/mb_5bmlp (trivial). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2644 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-09This patch uses auto.c from Uwe's tyan s1846 for both boards, with someCorey Osgood
minor changes, to bring them up to par. It also should remove (but might just clean out) the irq_tables.c from both boards, because they were just copied from Via Epia to begin with, and weren't usable. As far as I can tell, these are the only changes needed to the targets for now, aside from fixups to reset.c when the time comes. Both have been build tested, but not checked on hardware since I don't have it. I have left Uwe as the copyright holder since the only changes I've made are trivial. Signed-off-by: Corey Osgood <corey_osgood@verizon.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2642 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-09Add initial support for the ASI/BCom MB-5BLMP mainboard, as used inUwe Hermann
the IGEL Winnet III thin client. It boots a Linux kernel, but there are some problems. The login prompt is never reached, it simply hangs at some point. One possible reason is the IRQ table, which needs fixing. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2641 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-08New irq table, and a correct setting forRonald G. Minnich
the 5c register in the southbridge so that interrupts are routed correctly. With this patch, ethernet works quite well. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2640 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-07Add missing licenses to several of the files.Jordan Crouse
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2639 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-05This is the final patch to enable the msm800sev to build. This patchRonald G. Minnich
adds a symbol to the model_lx/cache_as_ram.inc, and modifies some files in the mainboard directory. This patch has been tested but there is a remaining problem which I am tracking down. Expect one more patch to "get it all working". Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2638 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-05With this patch, the msm800sev runs FILO and boots a kernel.Ronald G. Minnich
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> -This line, and those below, will be ignored-- M cs5536.c git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2637 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-04This patch as a cache_as_ram_auto.c for the msm800sev.Ronald G. Minnich
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2636 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-04Drop src/mainboard/amd/norwich/debug.c as it is not used.Uwe Hermann
I'm self-acking as this is pretty trivial. I tested both a normal build and an abuild-run, and nothing breaks. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2635 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-04Some minor fixes in it8716f/superio.c:Uwe Hermann
- Add Ward Vandewege <ward@gnu.org> as copyright holder. - Use explicit 'uint16_t' instead of 'unsigned long'. - Minor cosmetics. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2634 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-04patch to fix the IDE configuration on EPIA boards. At some point thisBen Hewson
broke and stopped FILO from being able to boot. The fix is a simple one line change plus a comment to src/mainboard/via/epia/auto.c to write to the IDE configuration register 0x42 . This has always been done here, however at some point something broke it. The same register was also being set correctly in ide_init(), however for some reason this does not work. Possibly the register needs to be set before the IDE peripheral is enabled or maybe it is a timing issue. The section of code in ide_init() ( src/southbridge/via/vt8231/vt8231_ide.c ) that does write to register 0x42 has been commented out as it is superfluous and I have added a comment to indicate the reason, should someone at a future date wonder why. I have also changed the default COM speed from 19200 to 115200 in src/mainboard/via/epia/Options.lb There has been mention before about the EPIA board not being able to use 115200 but I have seen no such problems with my board. Signed-off-by: Ben Hewson <ben@hewson-venieri.com> This patch worked for me and allowed me to boot Debian kernel 2.5.16-4-486 on an epia 800 mhz system. It is able to consistently get through the initialization and start init now. However, after that it crashes at various points in the boot process. Acked-by: Alex Mauer <hawke@hawkesnest.net> Note from comitter: I am commiting this, although: 1. it's not the exact right way to fix it up, the chip.h for the sb should change 2. Alex reports problems, which are almost certainly memory issues. But it is as close as we've gotten. I can't test it. Ron Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2633 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-04This repairs the other Geode mainboards so they'll build with the newMarc Jones
Geode changes. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2632 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-04This patch re-implements support for the CS5536 companion chip for theMarc Jones
AMD GX and LX processors. This aguments the previous code, which was very specific to the OLPC platform with general purpose support and better integration with the VSA and CPUs. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2631 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-04This patch adds support for the northbridge integrated into the AMDMarc Jones
Geode LX platform, including memory and graphics. (rediffed for whitespace) Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2630 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-04This patch adds support for the AMD Norwich development platformMarc Jones
based on the Geode LX processor. The Norwich is the canonical Geode reference, and will server as a good basis for other Geode based platforms. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2629 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-04This patch adds support for the AMD Geode LX CPU. (rediffed)Marc Jones
Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2628 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-04Cosmetics (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2626 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-03Add missing license headers to some Geode LX related files.Jordan Crouse
The following original authors agreed to the license: - Ronald G. Minnich <rminnich@gmail.com> - Indrek Kruusa <indrek.kruusa@artecdesign.ee> - Stefan Reinauer <stepan@coresystems.de> - Andrei Birjukov <andrei.birjukov@artecdesign.ee> Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2625 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-03Correct the RAM checking code to _not_ check the range from 640 KB - 1 MB,Uwe Hermann
as that is not RAM but used for other stuff. First try at PCI init added to src/mainboard/tyan/s1846/Config.lb. Use a real payload (FILO) per default now. Note: this cannot boot a payload, yet, but it gets a lot further now. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2623 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-30Fix typo: s/PRINT_DEBUG_/PRINT_DEBUG/ (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2622 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-27Add fan control support to ITE IT8716F.Ward Vandewege
Signed-off-by: Ward Vandewege <ward@gnu.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2620 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-26Activate EC for access to fan speeds and temperature sensors.Ward Vandewege
Signed-off-by: Ward Vandewege <ward@gnu.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2619 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-24trivial: fix filename in comment. Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2616 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-22Add explicit license headers to all files in src/device.Uwe Hermann
For files derived from the Linux kernel we merely add a small header which states the origin of the file and the copyright owners of the modifications to the file. We know all files from Linux are licensed under the GPLv2. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2615 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-22Use __PAYLOAD__ instead of PAYLOAD as replacement template for abuild.Uwe Hermann
Comment out code which currently doesn't compile. Needs fixing later. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2614 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-14This patch makes a some elf debugging information available at log levelStefan Reinauer
debug instead of spew. (trivial) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2611 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-12On behalf of AMD:Yinghai Lu
Drop AMD prototype mainboards that were for internal testing & validation use only. Note: These boards could never be purchased. No reasons to worry. Questions welcome via private mail. Signed-off-by: Yinghai Lu <yinghai.lu@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2609 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-12add uses CONFIG_COMPRESSED_PAYLOAD_* to allow building the board inStefan Reinauer
abuild with a payload. Trivial Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2608 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-12Fix two boards broken by the large patches of late.Peter Stuge
artecgroup/dbe61 Add CONFIG_COMPRESSED_PAYLOAD_NRV2B to Options.lb since it's used in Config.lb. Change default for CONFIG_PCI_ROM_RUN to 1 so VGA ROM can run. technologic/ts5300 Removed CONFIG_CONSOLE_VGA, the embedded board has no VGA without the development addon card anyways. Changes to target Config.lb so it actually builds. Signed-off-by: Peter Stuge <peter@stuge.se> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2607 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-12Vendor specific patch, thus self-acked.Stefan Reinauer
* going back to old board specific dsdt for agami aruma. This is hopefully dropped again some day, but until then here's a working solution. * Some minor Agami specific changes. * drop obsolete bringup workaround hyperclocking.diff * increase image size again, x86emu wants it. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2606 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-09This patch corrects r2587. It makes sure that the VGA is initializedRoman Kononov
when CONFIG_CONSOLE_VGA==0 and CONFIG_PCI_ROM_RUN==1 Signed-off-by: Roman Kononov <kononov@dls.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2600 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-07Fix epia-m build after u8/u16/u32 changes in Yh Lu's patch.Peter Stuge
Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2597 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-06YhLu's patch from January 18th.Yinghai Lu
hypertransport specific updates Signed-off-by: Yinghai Lu <yinghai.lu@amd.com> Signed-off-by: Ed Swierk <eswierk@arastra.com> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ward Vandewege <ward@gnu.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2596 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-06This commit is part of YhLu's patch from January 18th.Yinghai Lu
Drop a lot of debugging code from northbridge.c Signed-off-by: Yinghai Lu <yinghai.lu@amd.com> Signed-off-by: Ed Swierk <eswierk@arastra.com> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ward Vandewege <ward@gnu.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2595 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-06YhLu's patch from January 18th. This part is mostly cleaning up Yinghai Lu
dead code and adding a few fixmes. Signed-off-by: Yinghai Lu <yinghai.lu@amd.com> Signed-off-by: Ed Swierk <eswierk@arastra.com> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ward Vandewege <ward@gnu.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2594 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-06next part of YhLu's large patch. I am not sure whether the tables.cYinghai Lu
changes are correct. If someone could look into this, thank you. Signed-off-by: Yinghai Lu <yinghai.lu@amd.com> Signed-off-by: Ed Swierk <eswierk@arastra.com> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ward Vandewege <ward@gnu.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2593 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-06Disable USB console on the m57sli for now.Ed Swierk
Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2592 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-06Part IVYinghai Lu
Signed-off-by: Yinghai Lu <yinghai.lu at amd.com> Signed-off-by: Ed Swierk <eswierk at arastra.com> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ward Vandewege <ward at gnu.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2591 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-06Part III of YhLu's patch from January 18thYinghai Lu
Signed-off-by: Yinghai Lu <yinghai.lu at amd.com> Signed-off-by: Ed Swierk <eswierk at arastra.com> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ward Vandewege <ward at gnu.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2590 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-06two more directories from YhLu's mcp55 megapatch.Yinghai Lu
Signed-off-by: Yinghai Lu <yinghai.lu at amd.com> Signed-off-by: Ed Swierk <eswierk at arastra.com> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ward Vandewege <ward at gnu.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2589 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-06This is part of the outstanding mcp55 commit from January 18th. It willYinghai Lu
likely break the build, since it is only a small part, but it needs to go in at some point and doing it directory by directory makes things easier. Signed-off-by: Yinghai Lu <yinghai.lu at amd.com> Signed-off-by: Ed Swierk <eswierk at arastra.com> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ward Vandewege <ward at gnu.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2588 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-06This patch makes sure that VGA is initialized before it is used. WithoutRoman Kononov
this fix, LinuxBIOS crashes if the CONSOLE_LOG_LEVEL is high enough. Additionally, The VGA option rom will be executed if either CONFIG_PCI_ROM_RUN=1 or CONFIG_CONSOLE_VGA=1. Signed-off-by: Roman Kononov <kononov195-lbl@yahoo.com> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2587 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-06Trivial patch:Stefan Reinauer
* Drop empty file (0 bytes) northbridge/amd/amdk8/cpu_rev.c and references to it. * move config option decision to preprocessor instead of code since config options can not change during runtime * slightly more verbose output in built_opt_tbl.c Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2586 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-05Fix typo, add datasheet info, minor cosmetic fixes (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2584 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-05Coding style and cosmetics (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2583 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-05Add early serial support for the Fintek F81705F Super I/O.Corey Osgood
Signed-off-by: Corey Osgood <corey_osgood@verizon.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2582 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-03Add initial framework for the Tyan S1846.Uwe Hermann
It's not fully working, among other things because the Intel 440BX northbridge isn't working, yet. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2580 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-02The *_early_serial.c pre-RAM code should do just that -- enable the serialUwe Hermann
port(s), and nothing else. The code in superio.c will initialize the rest when RAM is available... Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2579 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-01Initial Intel 440BX RAM initialization framework.Uwe Hermann
This does _not_ fully work, yet. You will _not_ be able to boot any payload with this code, yet. Add missing license headers. Base the northbridge.c file on the Intel 855PM version, that comes closer to what we want. The raminit.c file is written from scratch and hardcodes several values for now. This needs to be fixed later by reading the correct values via SPD. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2576 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-03-31Add support for the NSC PC87309 Super I/O.Uwe Hermann
Pre-RAM serial output on COM1 and COM2 has been tested. The rest is not yet tested on real hardware. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2574 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-03-20fix a stupid cut and paste error.Stefan Reinauer
This is pretty trivial, as it was correct in the original non-CAR code. Suddently, CAR works nicely. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2572 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-03-17Add initial pre-RAM serial output support for the VIA VT82C686(A/B)Corey Osgood
southbridge (with integrated Super-I/O). Signed-off-by: Corey Osgood <corey_osgood@verizon.net> Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Corey Osgood <corey_osgood@verizon.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2571 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-03-02This patch splits console.c into 3 different files to get a betterCarl-Daniel Hailfinger
overview of the code, facilitate future cleanups and reduce the diff to Yinghai's tree at the same time. No functional changes, only moving lines between files. Copyright headers will be added later. Right now we benefit from keeping the diff as small as possible. Most of the work was done by Yinghai Lu. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2567 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-03-02Add missing it8716f_early_init.c file, which got lost in the commit ofUwe Hermann
http://www.openbios.org/pipermail/linuxbios/2007-February/018330.html in revision 2559. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2566 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-28This is (most of) the usb2 debug console code ripped out of Yinghai Lu
Uwe's version of yh_rest_of_patch.patch (13.02.07 - [PATCH] Rest of huge MCP55 patch). I dropped a lot of stuff, like broken indenting, removed copyright messages, and this printk_ram_* stuff (what the heck is this supposed to be) This codebase is really a mess. Further tarball contributions without a _CLEANED UP_ patch will be denied, especially if they are not from an up to date svn tree. Signed-off-by: Yinghai Lu <yinghai.lu@amd.com> Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2563 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-27This is another fixup round for Yinghai Lu's great patch.Stefan Reinauer
It does the ROM_STREAM -> PAYLOAD rename that afaik was done after Yinghai sent his work to legal, so it is required to get that code building. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2561 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-24Improve ITE IT8716F support.Yinghai Lu
Signed-off-by: Yinghai Lu <yinghai.lu@amd.com> Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2559 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-24Remove unused defines.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2558 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-19Fix some CHIP_NAME() entries to use canonical names.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2557 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-17Fix typo (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2556 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-17Initial support for the following new mainboards:Yinghai Lu
* Nvidia l1_2pvv * Gigabyte m57sli * Supermicro h8dmr * Tyan s2912 -- with HTX The boards will currently _not_ compile, two further patches from Yinghai Lu are still missing. Please be patient :) Signed-off-by: Yinghai Lu <yinghai.lu@amd.com> Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2554 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-09Add support for the MSI K9ND Master Series (ms9282) board.Bingxun Shi
Signed-off-by: Bingxun Shi <bingxunshi@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2552 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-03Add support for the Winbond W83627EHG Super I/O.Yinghai Lu
Signed-off-by: Yinghai Lu <yinghai.lu@amd.com> Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Bingxun Shi <bingxunshi@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2549 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-03Nvidia MCP55 uses CMD to send/receive bytes instead of DAT0, bxshi
that's the same as broadcom/bcm5785. Signed-off-by: bxshi <bingxunshi@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2548 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-03This eliminates an illegal and annoying warning.Roman Kononov
'rom' is the current read pointer. 'rom_end' points to last valid byte of the stream. Signed-off-by: Roman Kononov <kononov195-lbl@yahoo.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2547 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-02I have Sun Ultra40 workstation. Southbridge is nVidia CrushK8-04/nforceRoman Kononov
2200 (too many names, sounds like a criminal). 1) Linuxbios loads kernel A; kernel A loads kernel B. Everything works fine. 2) Then I push the reset button. 3) Linuxbios loads kernel A; kernel A loads kernel B. Kernel B complains about wrong checksum of the mptable and crushes later. An investigation showed that in 3), short after kernel A (v2.6.19.2) sets the Bus Master Enable bit of the nVidia's USB1 controller (pci_set_master()), the mptable gets two bytes at physical address 0x80 damaged. Nothing is plugged to the USB ports. Other two Sun workstations had the same behavior. This does not make sense to me unless the controller has a HW bug. I believe, this should better be fixed in the kernel USB driver. For now this patch offers a possibility for linuxbios to reset the USB controller by setting HostControllerReset bit in HcCommandStatus Register. It is enablead by using 'register "usb1_hc_reset"="1"' in 'chip southbridge/nvidia/ck804' section of the mainboard's Config.lb. Signed-off-by: Roman Kononov <kononov195-lbl@yahoo.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2546 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-02Remove hardcoded gcc versions otherwise the build will break forUwe Hermann
most people. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2545 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-01Fix typo which breaks the build ('defalut' should be 'default').Ed Swierk
Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2544 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-01This patch adds the MCP55 PCI IDs (without which the southbridge codeEd Swierk
won't compile), and breaks an unnecessary dependency on the usbdebug code. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2543 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-01great check-in message:Roman Kononov
Linuxbios boots an Opteron motherboard with 1GB memory. Linuxbios directly loads a recent linux kernel. The memory layout is like this: BIOS-provided physical RAM map: BIOS-e820: 0000000000000000 - 0000000000000e18 (reserved) BIOS-e820: 0000000000000e18 - 00000000000a0000 (usable) BIOS-e820: 00000000000c0000 - 00000000000f0000 (usable) BIOS-e820: 00000000000f0000 - 00000000000f0400 (reserved) BIOS-e820: 00000000000f0400 - 0000000040000000 (usable) The f0000-f0400 region contains IRQ and ACPI tables. At some point the kernel builds a resource table containing all physical address ranges and type of hardware the addresses are mapped to. The table is accessible via /proc/iomem: # cat /proc/iomem 00000000-00000e17 : reserved 00000e18-0009ffff : System RAM 000a0000-000bffff : Video RAM area 000c0000-000cbfff : Video ROM 000f0000-000fffff : System ROM e0000000-efffffff : PCI Bus #03 e0000000-efffffff : 0000:03:00.0 f0000000-f3ffffff : GART f4000000-f60fffff : PCI Bus #03 f4000000-f4ffffff : 0000:03:00.0 f5000000-f5ffffff : 0000:03:00.0 f6000000-f601ffff : 0000:03:00.0 f6100000-f6100fff : 0000:00:01.0 f6101000-f6101fff : 0000:00:02.0 f6101000-f6101fff : ohci_hcd f6102000-f6102fff : 0000:00:04.0 f6103000-f6103fff : 0000:00:07.0 f6103000-f6103fff : sata_nv f6104000-f6104fff : 0000:00:08.0 f6104000-f6104fff : sata_nv f6105000-f6105fff : 0000:00:0a.0 f6106000-f61060ff : 0000:00:02.1 f6200000-f620ffff : 0000:40:01.0 As you can see, the 00000000000f0400-0000000040000000 region is not listed. It is not listed because the kernel unconditionally adds "000f0000-000fffff : System ROM" first (look for "request_resource(&iomem_resource, &system_rom_resource)"), and then the attempt to add f0400-40000000 range fails because of overlapping. The kernel does not care that the range is not listed there. Kexec does. It uses the /proc/iomem file to instruct the kexec system call how to place the segments of a new kernel in the physical memory. Kexec fails to start a new kernel because it cannot locate enough physical memory. This must be fixed either in linux or linuxbios. Assuming that linuxbios is to be fixed, I cooked a patch which provides this memory layout: BIOS-provided physical RAM map: BIOS-e820: 0000000000000000 - 0000000000000e18 (reserved) BIOS-e820: 0000000000000e18 - 00000000000a0000 (usable) BIOS-e820: 00000000000c0000 - 00000000000f0000 (usable) BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved) BIOS-e820: 0000000000100000 - 0000000040000000 (usable) The /proc/iomem contains: # cat /proc/iomem 00000000-00000e17 : reserved 00000e18-0009ffff : System RAM 000a0000-000bffff : Video RAM area 000c0000-000cbfff : Video ROM 000f0000-000fffff : System ROM 00100000-3fffffff : System RAM 00100000-00203c61 : Kernel code 00203c62-00248c3f : Kernel data e0000000-efffffff : PCI Bus #03 e0000000-efffffff : 0000:03:00.0 f0000000-f3ffffff : GART f4000000-f60fffff : PCI Bus #03 f4000000-f4ffffff : 0000:03:00.0 f5000000-f5ffffff : 0000:03:00.0 f6000000-f601ffff : 0000:03:00.0 f6100000-f6100fff : 0000:00:01.0 f6101000-f6101fff : 0000:00:02.0 f6101000-f6101fff : ohci_hcd f6102000-f6102fff : 0000:00:04.0 f6103000-f6103fff : 0000:00:07.0 f6103000-f6103fff : sata_nv f6104000-f6104fff : 0000:00:08.0 f6104000-f6104fff : sata_nv f6105000-f6105fff : 0000:00:0a.0 f6106000-f61060ff : 0000:00:02.1 f6200000-f620ffff : 0000:40:01.0 Kexec is happier with the patch. Regards, Signed-off-by: Roman Kononov <kononov195-lbl@yahoo.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2542 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-01This fixes a small typo.Roman Kononov
Signed-off-by: Roman Kononov <kononov195-lbl@yahoo.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2541 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-01Add support for the NVIDIA MCP55 southbridge.Yinghai Lu
Signed-off-by: Yinghai Lu <yinghai.lu@amd.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Yinghai Lu <yinghai.lu@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2540 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-01-16Change 'ram' to 'RAM' in user-visible output (closes #60).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2535 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-28A patch to add initial support for the i82801db southbridge basedJon Dufresne
heavily on the code for i82801dbm and i82801er Signed-off-by: Jon Dufresne <jon.dufresne@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-20htx card on io apic on htx slot of dk8_htxYinghai Lu
Signed-off-by: Yinghai Lu <yinghai.lu@amd.com> Acked-by: Yinghai Lu <yinghai.lu@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2533 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-20ck804 pref mem 4G above supportYinghai Lu
Signed-off-by: Yinghai Lu <yinghai.lu@amd.com> Acked-by: Yinghai Lu <yinghai.lu@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2532 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-15Apply linuxbios-rename-other-payload-options.patchEd Swierk
(Patch 2, refs #14) Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2529 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-15Apply linuxbios-rename-compressed-payload-options.patch, refs #14Ed Swierk
Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2527 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-14In the file mainboard/intel/i82801dbm/i82801dbm.c the variableJon Dufresne
southbridge_intel_i82801dbm_control should be named southbridge_intel_i82801dbm_ops. Otherwise a compile error occurs if this device is included in Config.lb of the mainboard. Closes #62 Signed-off-by: Jon Dufresne <jon.dufresne@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2526 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-14Add support for the SMSC FDC37M60x Super I/O (tested on FDC37M602).Uwe Hermann
Serial output on serial port 1 is tested and works, the rest probably not yet. Closes #59. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2525 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-14In src/southbridge/intel/i82801ca, first the smbus registers are mapped at i/ochn
space offset 0x1000, and later is the acpi registers also mapped at 0x1000. This patch fixes this behavior. Closes #44 Signed-off-by: <chn@virtutech.se> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2523 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 12:07:07 +0000