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2018-10-04mb/google/nocturne: Define GPP_D17 as EC_SYNC_IRQDuncan Laurie
Use GPIO GPP_D17 pin as the EC sync interrupt and provide this value to the embedded controller to be exported to the OS. This interface was tested on a reworked Nocturne board with modified EC and a modified kernel driver to ensure that the interrupt asserts as expected and can be used by the kernel driver. Change-Id: Ie2b33692367b5d9ecc2b128180d8cfe4f6b347b1 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/28759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-04ec/google/chromeec: Define a sync IRQ if neededDuncan Laurie
Some boards are adding a second pin used for synchronization between the EC and AP. This is a direct connection between the EC and the SOC that is intended to provide a lower latency interrupt signal for sensors on the EC. Currently the runtime EC interrupts assert an SCI before eventually resulting in a Notify() on the MKBP device that the sensor driver users. These extra layers add processing time and require additional EC communication to determine the event source. This interface was tested on a reworked Nocturne board with modified EC and a modified kernel driver to ensure that the interrupt asserts as expected and can be used by the kernel driver. Change-Id: I49a11363ce82882e572bcb8923fd114ab6593fea Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/28758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-04mc_apl1: Set up SPI OPCODE menu before lockingWerner Zeh
In order to enable the OS SPI driver to use the software interface of this controller the OPCODE menu has to be set up properly before locking the controller. This is done on baseboard level so that all variants will get this done as well. Change-Id: I0bf0619ff0610c00325f03d13b6794aee8a62504 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/28834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2018-10-03mb/google/kahlee: Update careena Audio/TP i2c timingKevin Chiu
After adjustment on Careena Audio: 402.805 kHz -> 396.8 kHz TP: 406.1 kHz -> 399.5 kHz BUG=b:110984023 BRANCH=master TEST=emerge-grunt coreboot Change-Id: Ia3eb91ca3772d5f122498e3989ec03838fce06a5 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/28868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-03google/kahlee: Enable IOMMU deviceMarc Jones
Enable the IOMMU device on all kahlee based mainboards. BUG=b:116196614 TEST=Check dmesg for AMD-Vi messages. Change-Id: I18b9ba1a970c6973226e736d72f82fd53010f31c Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/28754 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-03soc/amd/stoneyridge: Add IOMMU supportMarc Jones
Enable the IOMMU in AGESA and copy the AGESA generated IVRS ACPI table. BUG=b:116196614 TEST=Check dmesg for AMD-Vi messages. Change-Id: I688d867c7bd4949a57b27c1b6a793c6a6e4a717a Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/28753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-03soc/intel/commom/block/i2c: Make I2C controller out of resetSubrata Banik
This patch ensures I2C controllers are out of reset without any assumptions. BUG=b:116191230 BRANCH=none TEST=Dump MMIO offset 0x204 to check if I2C host controller is NOT at reset (by reading Bit 0-1 as 3) Change-Id: I4b335a834333e01cfa2d802e4aad0735d0212dcc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-02src/soc/intel/broadwell/me.c: Correct HMRFPO misspellingAngel Pons
`HMRFPO` was spelled as `HMRPFO` twice. Change-Id: Ibd04004ac5edcdeee49a6a69fcdd5c73603e92e2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-10-02soc/intel/skylake: Fix spelling mistakeSubrata Banik
Make correct spelling for THERMAL_IRQ macro in irq.h file. Change-Id: I83593822e2abbb07e60fc336b774199fea3b368f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2018-10-02soc/intel/skylake: Replace white space with tabSubrata Banik
This patch unified line indentation. Change-Id: Ife3396e36a0684490d9ed9b31b4c0a543a3e3d24 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2018-10-01drivers/intel/wifi: Add DID for Intel WIFI module 8260, 8275Subrata Banik
Change-Id: I38d83370e96cff6822a96da5fa3d9af797ba1dc1 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-01mb/google/octopus: Operate touchpad I2C CLK in specChris Zhou
Need to tune I2C bus 6 clock frequency under the 400K Hz Bug=b:115600671 TEST=flash coreboot to the DUT and measure I2C bus 6 clock frequency whether arrive to 398.07K Hz Change-Id: I5cc1f67f0db0553cb8424f81408ed4686cddb2fb Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-01src/Kconfig: Drop a superfluous wordJonathan Neuschäfer
Change-Id: I2d658e57d52f79c77be08599b9e525a46e30f732 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-01google/kahlee: Run FCH PTS and WAK methodsMarshall Dawson
The FCH ASL is now capable of controlling the D-states of most AOAC devices, as well as properly reinitializing the xHCI firmware on a resume. Call the FPTS and FWAK methods. BUG=b:77602074 TEST=On Grunt, go to S3 and wake with a USB keyboard Change-Id: I4df8523569dc3dfbd87f79e780c18d39f0d9a37f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28773 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-01amd/stoneyridge: Add USB ASL for D0/D3coldMarshall Dawson
Add methods, and call them, for transitioning EHCI and xHCI to D0 or D3cold. Add device objects necessary for waking the system via USB. In order for USB to wake the system, it must be in the D3cold state. Then on resume, its firmware must be reloaded. This code relies heavily on AMD's FchCarrizo.asl (delivered in NDA PI package), and has been modified to fit the coreboot ASL names. In addition, AMD's methodology is to generate a SW SMI for saving/restoring certain settings. This has been ported into U3D0 and U3D3, as the necessary registers are now publicly documented. BUG=b:77602074 Change-Id: I83d0dce13411601691318cc67c99adf291ccf3bb Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28772 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-01amd/stoneyridge: Add ASL helper for AOAC PwrGood ControlMarshall Dawson
Add a method to assist with setting the PwrGood Control register, which will be useful for various devices. BUG=b:77602074 Change-Id: Ief602c4bc42d27b3e236d24db815b990f3a2419c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-01amd/stoneyridge: Add FCH WAK and PTS methodsMarshall Dawson
Add methods that can be used for preparing all controller hub devices for sleep, and that will turn the devices back on. BUG=b:77602074 Change-Id: I4b0c48e96aff23b4c31c9e89582b9fa80dba7bda Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28770 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-01amd/stoneyridge: Add ASL for D-states on AOAC devicesMarshall Dawson
Duplicate ASL from AMD's FchCarrizo.asl (available in NDA PI package) that can put AOAC devices into D0 or D3cold. The argument numbers coincide with the AOAC register offsets for the various devices. SATA, USB, and SD require additional device configuration. Add a placeholder and mark as todo. BUG=b:77602074 Change-Id: I32426f744a5ebbad9e8d3f2f37c4d214ad6dd3d4 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28769 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-01amd/stoneyridge: Add ACPI MMIO and PCI offsets to ASLMarshall Dawson
Define various AMD_SB_ACPI_MMIO_ADDR registers at 0xfed80000. Define various PCI config space registers. These are duplicated from AMD's FchCarrizo.asl file. BUG=b:77602074 Change-Id: Ie7447fef682424b05fa912b60c7b80112c6202de Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28768 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-01amd/stoneyridge: Load AOAC and USB gnvs valuesMarshall Dawson
Indicate the devices that are enabled. This is somewhat rudimentary, but could be improved in a later patch (e.g. get settings from devicetree). Calculate values that may be used for reinitializing the xHCI firmware. Add the EHCI BAR's current base address to gnvs. BUG=b:77602074 Change-Id: I8af69c030eb2353ad75beeb2bfd3bef24abff04c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28767 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-01amd/stoneyridge: Add USB settings to gnvsMarshall Dawson
A later patch will rely on two USB settings from the BIOS. Add these to the global_gnvs_t structure. The first is a data that will be used to locate the xHCI firmware for reloading after a resume. Although the existing calculations will be somewhat simple, keeping this on the coreboot side will help in the event multiple FWs are eventually in the build. The second item is a usable EHCI base address that may be programmed during S3 suspend and resume. At the time the PTS and WAK code runs, the BAR will be clear. BUG=b:77602074 Change-Id: I32205ac8a6908cca4a38dd68a7c7b591e76c06bb Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-01amd/stoneyridge: Create gnvs entries for AOAC devicesMarshall Dawson
A later patch will leverage AMD's ASL support for handling AOAC devices. This will gather coreboot's device enables from a bitwise field, where each bit corresponds to the register offset used to control each devices. Create an identical structure, and add it to the nvs ASL and global_nvs_t structure. BUG=b:77602074 Change-Id: I40f0161cc0bbc574ad703e34278372f2504de100 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-01drivers/spi/winbond: Fix read protection bitsPatrick Rudolph
Don't care about SRPx and print correct protected range. Change-Id: I051f1459c585a7ed6a4878dc217d11df5ef00d74 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/28731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-01soc/intel/fsp_broadwell_de: Fix IA32_MC0_* namesElyes HAOUAS
Regarding the SDMs, IA32_MC0_STATUS register is at 0x401, and IA32_MC0_CTL is at 0x400. So replace MSR at (0x400+1) by IA32_MC0_STATUS and the one at 0x400 by IA32_MC0_CTL. Change-Id: I3f53c80f39078bd0c47c25013657e1169fc6c4a6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-10-01siemens/mc_apl1: Activate clock spreading for PTN3460Mario Scheithauer
In order to minimize Electromagnetic Interference (EMI) on the LVDS interface driven by PTN3460, clock spreading must be activated for mc_apl1 mainboard. The modulation ratio is set to 1 % of the nominal frequency. Change-Id: Ie457fcdbb6239dc0b25e2c35ad7a310ee80383f9 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28761 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-30mainboard/opencellular/elgon: Add mainboard supportPhilipp Deppenwiese
Tested on Elgon EVT board and boots into GNU/Linux. TODO: * Add hard reset function for VBOOT. * Add EC code * Add SPI flash write protection Change-Id: I9b809306cc48facbade5dc63846c4532b397e0b5 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/28024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-09-30soc/cavium/cn81xx/spi: Add function to return SPI clockPatrick Rudolph
Change-Id: I07c95b9ea14d47da0497470487fa3f162f8012c8 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/28789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-09-28amd/stoneyridge: Make gnvs ASL whitespace consistentMarshall Dawson
The globalnvs.asl file had become mixed with tabs and spaces to align columns. Use all tabs to align the comments. BUG=b:BUG=b:77602074 Change-Id: Ife4cf86372a8e24e78b38cca0254dd9fa00dd6b0 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-28mb/lenovo/t400: Add 154WX5-TLB2 to display backlight PWM freq listArthur Heymans
Vendor VBT on ThinkPad R500 intends to set a 220MHz backlight PWM frequency which seems to work well. Change-Id: Ic1a12c7e3173468561ed5615319962d0abc6d61b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-09-28mb/lenovo/t400: Link the gpio.c settingsArthur Heymans
Linking this file instead of including a header makes it possible to easily change gpio settings for a variant. Change-Id: Ifd496510d4868f5901a9dbbf7f1523ccffaf15ab Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28628 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-28mb/lenovo/t400: Trim down the gpio.h fileArthur Heymans
Some settings like direction are only used if the mode is GPIO. Change-Id: I4efc54dfef3721b528b90d49f490014d9132cdf8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28627 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-28vendorcode/amd/pi/00670F00/Lib: Remove folderRichard Spiegel
Now that the last dependency was resolved, remove AmdLib folder. BUG=b:112525011 TEST=Build and boot grunt. Change-Id: Ibd9a20bc358742520138b9b01f76d7fd2fac92ab Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28742 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Charles Marslett <charles.marslett@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-28soc/amd/stoneyridge/BiosCallOuts: Remove #include <AmdLib.h>Richard Spiegel
In preparation to remove AmdLib, remove reference to AmdLib.h in soc/amd/stoneyridge/BiosCallOuts. BUG=b:112525011 TEST=Buildgrunt. Change-Id: If80eb64fb736ff26ab226a16b583c8b1c29831f4 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28741 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Charles Marslett <charles.marslett@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-28src/mb/asrock/g41c-gs: Add variant g41m-s3Angel Pons
This board is pretty much like the G41M-GS, but with DDR3 memory instead. The PCB layout is almost identical. What works: - S3/S4 resume - RAM init - Booting to Debian - Display lights up w/ libgfxinit - Both PS/2 work - Ethernet - Graphics card on PEG - USB - SATA ports - NVRAM debug_level - Internal flashing - PCI slots (tested with CT4810 audio card) - fancontrol (Only CPU fan can be regulated) - Audio (Rear ports only) What does not work: - Hell knows what might be wrong What is not tested: - PCIe x1 - IDE - Floppy - Parallel port Change-Id: I66b216af740680c390ea82e4fe07737c20227cc6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-09-28soc/intel/cannonlake: Fix ACPI FADT table generationDuncan Laurie
The function to fill out the FADT table exits early if the devicetree config option to disable the legacy timer is set. This means it never gets to the later check for s0ix config option and so the flag to indicate that it supports low-power idle in S0 is not set. Change-Id: Ia0416f21b6445f6feecb6f0301d48fdf2522b8a6 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/28755 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-28mb/intel/coffeelake_rvp: Enable GbE supportLijian Zhao
Enable Gigabit Ethernet network controller on whiskey lake rvp platform, add NVM bin file as well. BUG=N/A TEST=Build and boot up into chromeos on whiskey lake rvp platform, and check eth0 can get IP address assigned, Change-Id: Ia299a2aa78108175074e084cc34a7d2b38cf1c72 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/27848 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-28soc/intel/cannonlake: Move SkipMpInit config to FSPMLijian Zhao
SkipMpInit UPD had ben moved from Fsp SiliconInit UPD to Fsp MemoryInit UPD, hence change the settings in coreboot side as well. The old options in SiliconInit get deprecated, so leave the code as is will be harmless. Make the changes limited to coffeelake itself. Change-Id: If968de78117068668e4f0006c412442c50658ba9 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28740 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-28soc/amd/common/block/pi: Remove references to AmdLibRichard Spiegel
In preparation to remove AmdLib, remove all references to AmdLib.h in folder common/block/pi. BUG=b:112525011 TEST=Buildgrunt. Change-Id: I3530857b872d0cb5ed2e3f3a294cc50b45ff6969 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28737 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Charles Marslett <charles.marslett@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-28soc/intel/cannonlake: Add ACPI entry for LANLijian Zhao
Add ACPI DSDT entry for integrated Gigabit LAN controller. Change-Id: I15bf1d4065894531871380b3318f553b637f4a97 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28743 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-28mainboard/google/poppy/variants/rammus: Modify VR settingstatham_chu
We refer to Intel Doc#594883. The recommended Ac/Dc loadline values are as below: # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | #+----------------+-------+-------+-------+-------+ #| Psi1Threshold | 20A | 20A | 20A | 20A | #| Psi2Threshold | 2A | 2A | 2A | 2A | #| Psi3Threshold | 1A | 1A | 1A | 1A | #| Psi3Enable | 1 | 1 | 1 | 1 | #| Psi4Enable | 1 | 1 | 1 | 1 | #| ImonSlope | 0 | 0 | 0 | 0 | #| ImonOffset | 0 | 0 | 0 | 0 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | #| AcLoadline | 14.4 | 4.2 | 5.7 | 4.47 | #| DcLoadline | 14.0 | 4.17 | 4.2 | 4.3 | #+----------------+-------+-------+-------+-------+ BUG=b:112167318 BRANCH=master TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure system boots up. Change-Id: I2d83d835ec841ac4cc811a0a69f74d203d5ea173 Signed-off-by: statham_chu <statham_chu@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-28soc/intel/cannonlake: Update UPD from device switchLijian Zhao
Some of the FSP silicon UPD entry can be updated base on device switch in pci device tree, have both static config setting and device tree "on" and "off" will be redundant. BUG=N/A TEST=Build and boot up fine with Whiskey Lake RVP platform. Change-Id: Ia36cfab03c4613786e5580a039d89007b630adf9 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/27766 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-28src/*: normalize Google copyright headersPatrick Georgi
As per internal discussion, there's no "ChromiumOS Authors" that's meaningful outside the Chromium OS project, so change everything to the contemporary "Google LLC." While at it, also ensure consistency in the LLC variants (exactly one trailing period). "Google Inc" does not need to be touched, so leave them alone. Change-Id: Ia0780e31cdab879d2aaef62a2f0403e3db0a4ac8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/28756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com>
2018-09-27siemens/mc_apl1: Add new mainboard variant mc_apl2Mario Scheithauer
This mainboard is based on mc_apl1. In a first step, it contains a copy of mc_apl1 directory with minimum changes. Special adaptations for mc_apl2 mainboard will follow in separate commits. Change-Id: I0af60ab0dfe556dd95da2cf1a49c685a8f0ae4eb Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-09-27siemens/mc_apl1: Make the DDR memory swizzle data configurableMario Scheithauer
In preparation for a future MC Apollo Lake board which will be equipped with LPDDR4 modules, it is necessary to make the swizzle data configurable. Starting from the mc_apl1 baseboard, which is equipped with DDR3L memory and therefore does not need swizzle data, the structures are initialized with zero. Change-Id: I4954d0a00d1d5fc28a8dda45a9fb27f98d5c3f1e Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-09-26mb/google/poppy/variants/nocturne: Update PowerLimit1 maximum valueSumeet Pawnikar
Increase power limit1 maximum value from 5W to 7W. This value as per recent measurement on closed system which shows better performance results. BUG=None TEST=Build and tested on Nocturne system. Performance tests show better results. Change-Id: I7485b1d2afde46ec28d548c13be35a43e7572918 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/28686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-26mb/google/poppy/variants/nocturne: Add tdp_pl1_override valueSumeet Pawnikar
Add tdp_pl1_override value as 7W. BUG=None BRANCH=None TEST=Build coreboot for Nocturne board Change-Id: I16d3894da68bc3be6eff526062f9a88ef2df60c7 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/28708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Puthikorn Voravootivat <puthik@chromium.org>
2018-09-26mb/google/poppy/variants/nocturne: Update DPTF settingsPuthikorn Voravootivat
The previous does not work well enough when testing with high ambient temperature. Update DPTF settings to make it work better. List of tweaks: 1. Raise DRAM Critical temperature from 48C to 55C Note that there are mechanisms in EC that complement this because of DPTF limitation that we can't have multiple passive temperatures. 2. Lower response time for DRAM temp sensor from 60s to 5s. 3. Increase throttle priority to the charger when DRAM hit passive temperature from 100 to 200. BUG=b:112550414 BRANCH=None TEST=Manually tested by thermal team. Change-Id: Idf7efa76b2c6085cf97aa9f65c6ce066e8cff99a Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-on: https://review.coreboot.org/28738 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-26soc/sifive/fu540: Document #if ENV_ROMSTAGE lineJonathan Neuschäfer
Change-Id: Idcd72c558e46637b1b99e9613963436fedd4a8b9 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28699 Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-26soc/sifive/fu540: Remove PLL parameters from sdram.cJonathan Neuschäfer
These parameters are not used and not necessary in sdram.c, because the DDR PLL is configured in clock.c. Change-Id: I8060bd21e05765cedf7bdabc28052c32774f9ca1 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28710 Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-26arch/riscv: Advance the PC after handling misaligned load/storeJonathan Neuschäfer
After emulating an instruction in the misaligned load/store handler, we need to increment the program counter by the size of instruction. Otherwise the same instruction is executed (and emulated) again and again. While were at it: Also return early in the unlikely case that the faulting instruction is not 16 or 32 bits long, and be more explicit about the return values of fetch_*bit_instruction. Tested by Philipp Hug, using the linuxcheck payload. Fixes: cda59b56ba ("riscv: update misaligned memory access exception handling") Change-Id: Ie2dc0083835809971143cd6ab89fe4f7acd2a845 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-09-26vendorcode/amd/pi/00670F00/Proc/PspBaseLib: Remove folderRichard Spiegel
Now that PspBaseLib is no longer used, fully remove the folder. BUG=b:116579642 TEST=Build grunt Change-Id: I441b3f46e2312c12771766f87b25d1dc15ff3af0 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-09-26cheza: Wrap FMAP sections with calibration data in RO_PRESERVE sectionJulius Werner
The Cheza board contains a couple of non-standard FMAP sections that contain per-board calibration data. When flashing new firmware to the board, care should be taken to copy these sections over so that all features can still function correctly afterwards. This patch wraps a new RO_PRESERVE FMAP section around these sections to make them easier to preserve as a group. Change-Id: I77919336f609a1be399598736f46921c3da99e68 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/28728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: T Michael Turney <mturney@codeaurora.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-09-26src/mainboard/pcengines/apu2/Kconfig: Clean up PINMUX settingsMichał Żygowski
Configuration of pins exposed by superIO are inconsistent between board variants. Each platform should have UARTs enabled, this is expected behaviour of these pins. Given that APU2_PINMUX_UART_x can be set for all boards as default. Change-Id: Ifb7dfe23a95ba0e572adc38212333d9fdd234d53 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/28720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-26cpu/intel/model_206ax: detect number of MCE banksDan Elkouby
My CPU (3770k) supports 9 MCE banks, but the code is hardcoded to reset only 7. This causes Linux to spuriously log errors during boot and S3 resume. Fix this by reading the real value from the right MSR. Change-Id: Id05645009259fd77b4de49bde518361eeae46617 Signed-off-by: Dan Elkouby <streetwalkermc@gmail.com> Reviewed-on: https://review.coreboot.org/28443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-09-26mb/lowrisc: Remove the Nexys4DDR portJonathan Neuschäfer
This board doesn't support the newest RISC-V Privileged Architecture spec (1.10), and it's based on an FPGA so it's a moving target. Now that there's actual RISC-V silicon out there (from SiFive), mb/lowrisc/nexys4ddr will only continue to bitrot. Change-Id: I4e3e715106a1a94381a563dc4a56781c35883c2d Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-09-26src/mainboard/pcengines/apu2/Kconfig: Remove TPM1 optionMichał Żygowski
Apu2 boards use Infineon SLB9665 TT 2.0 module which is TPM2.0. Remove TPM1 option to allow choice between TPM1 and TPM2. SLB9665 TT 2.0 detection fixed in change 21983. Change-Id: Ie9788c43d8b32b2f6329a072b88c962c34eca119 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/28000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-26soc/intel/common/block: Don't use device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: Id82059898844fbe20665250062b67652d6cc1f9e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-26mb/google/octopus: Touchpad I2C CLK (405.25KHz)over spec(＜400KHz)peichao.wang
Need to tune I2C bus 6 clock frequency under the 400KHz Bug=b:116543001 TEST=flash coreboot to the DUT and measure I2C bus 6 clock frequency whether arrive to 399.1KHz Change-Id: I95b535a6b429fc34961a4953004a1c51e53a9be6 Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28747 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-26Revert "mb/google/poppy/variants/nautilus: Set grip sensor threshold"Seunghwan Kim
This reverts commit aef592d9b66aa18d83b0a211ead26013ff1f7d98. Reason for revert: Use values from driver instead of hardcoding in firmware (b:113303916) Change-Id: I02d21803f38da227f1d85b00cb6b5274d81dbbb4 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/28690 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Enrico Granata <egranata@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-26mb/google/octopus: Close unused I2C bus 7 include SCL and SDA for PhaserPeichao Wang
Since I2C bus 7 attached the touchscreen device however Phaser units that haven't it. So for avoiding side effects, we need close I2C bus 7 SCL and SDA respectively. BUG=none TEST=according to sku_id (Phaser: 0x1, Phaser360: 0x2, Phaser360s: 0x3) distinguish whether close these gpios. Change-Id: I8ad17761f2a053dc329bbec0a0a3284d47289666 Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28669 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Jett Rink <jettrink@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-25mainboard/google/kahlee: Only read a single vendor from oem.binMartin Roth
Since each variant has a separate build, we don't need to support multiple manufacturers in a single file. BUG=b:79874904 TEST=Build, boot, see updated mainboard manufacturer Change-Id: I0ccf207ba8d5e5200aa4b19c46784bbda82f7b6e Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/28729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-09-25mb/google/kahlee/variants/liara: Disable NbP-state on LiaraAmanda Huang
To disable NB-Pstate, the system wouldn't auto restart on EVT board when idling. BUG=b:116082728 Change-Id: Iec4f0355cb6eb1c2b0372e3d131cc5e6ba36635e Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-25src/cpu/via/nano: Remove unneeded includeElyes HAOUAS
Change-Id: I656b11add77012271ccc0c80dfcf97d20937dba2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-25northbridge: Use 'unsigned int' to bare use of 'unsigned'Elyes HAOUAS
Change-Id: Ib70eb33fac654a773ea39a5fd4206435dffdabb7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-25mb: Use 'unsigned int' to bare use of 'unsigned'Elyes HAOUAS
Change-Id: I3a8e077656df02912b4e67c3947bd5af054a18bf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-25mb/asrock/g41m_vs3_r2: Add mainboardArthur Heymans
The following was tested: - CPUs with 800, 1067, 1333MHz FSB (1333MHz FSB needs a jumper set) - The VGA output with libgfxinit - USB - COM1 - Ethernet - SATA - PCIe - PCI Has the following problems: - The Ethernet NIC is not usable after S3 resume and requires Linux to reload the driver. Vendor firmware also has this problem so it is quite likely it is just a atl1c driver problem. TODO: Add documentation Change-Id: Ibce9ecdc0e44db3703401f116c9a8bff5b66437f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-09-24amd/common/psp: Remove use of PspBaseLibCharles Marslett
Eliminate the references to PspBaseLib.c and PspBaseLib.h in agesa_headers.h. Fix psp.c references to definitions in those files by adding them to include/amdblocks/psp.h. BUG=b:78514564 TEST=Build and boot grunt/ChromeOS and restore an image from the internet. Change-Id: I2740ceb945736c6e413f7d0bd0c41a19e19c7d5a Signed-off-by: Charles Marslett <charles.marslett@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27619 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-24soc/amd/stoneyridge/romstage.c: Move STAPM code to SOC specificRichard Spiegel
STAPM programming was created inside function OemCustomizeInitEarly(). It should be SOC specific, and called by agesawrapper just before the call to OemCustomizeInitEarly(). BUG=b:116196626 TEST=build and boot grunt Change-Id: I8a2e51abda11a9d60a9057b38f2a484e1c8c9047 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28705 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-22skylake,kabylake: Add support to set eMMC tuning param from dev treePratik Prajapati
Add support to set eMMC tuning params from the device tree so that it can be configured per board. BUG=b:112718426,b:112690628 BRANCH=none TEST=Build nocturne image and checked values passed in dev tree is set by FSP. Change-Id: Ic71934dce9a1c380a057e579ca3fda41983b9385 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/28274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-09-21mb/google/octopus: Create ampton variantJustin TerAvest
This commit creates an ampton variant for Octopus. The initial settings are copied from Bip, but the following changes are made to support hardware differences: * GPIO_66 is not connected (LTE). * GPIO_67 is not connected (LTE). * Updated comment for GPIO_134 (EC_AP_INT_ODL), but not configured yet. * GPIO_143 is not connected. * GPIO_144, GPIO_145 mapped to PEN_EJECT are not connected. * EN_PP3300_TOUCHSCREEN moved from GPIO_213 to GPIO_146. * GPIO_213 is not connected. * GPIO_214 is not connected. BUG=b:111498206 TEST=None Change-Id: I7d6cf19c906df19115b1101e3d91c62f5f3f61e3 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/28663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-21mb/intel/coffeelake_rvp: Add whiskey lake rvpLijian Zhao
Add new mainboard variant of whiskey lake rvp, which is primary validation platform for whiskey lake silicon, support socket DDR4 memory module. BUG=N/A TEST=Build and flash, confirm boot up into kernel on whiskey lake rvp platform. Change-Id: I4a5e8a9ec76d5e55e55ef9bf968825c17fbe9816 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/27628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-21mb/google/poppy/variants/rammus: Disable command TriState for rammusmarxwang
This patch sets the MRC UPD "CmdTriStateDis" to disable TriState for the rammus boards. Rammus is LPDDR3 design without RTT for CMD/CTRL. BUG=none TEST=Run memtester app and also webgl fishtank on the LPDDR3 kabylake boards and also check the margin data is proper in FSP. Change-Id: Iee115f49ba5b36dc5b0425e9da02b58cd19b2236 Signed-off-by: Marx Wang <marx.wang@intel.com> Reviewed-on: https://review.coreboot.org/28568 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-21mb/intel/coffeelake_rvp: Correct LPDDR4 to DDR4 in mainboard infoLijian Zhao
There's only DDR4 or LPDDR3 support for coffelake processor line, details can be found out on EDS #570805. BUG=N/A TEST=N/A Change-Id: I8ba6b6861b15b40b01237f87c8d55394f7fd6706 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-21mb/intel/coffeelake_rvp: GPIO support for whiskey boardLijian Zhao
Add gpio programming difference for whiskeylake rvp platform. BUG=N/A TEST=N/A Change-Id: I35a0384f828fd3219e0c3adb4830f5bdab800e32 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28367 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-21soc/intel/denverton_ns/csme_ie_kt.c: Don't use device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: I9dde92314af8ef87a5acb550f0fb25b8ce875174 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-21soc/intel/braswell/ramstage.c: Add SoC stepping D-1 supportFrans Hendriks
No support for SoC D-1 stepping is available. According to Intel doc #332095-015 stepping C-0 has revision id 0x21 and D-1 revision ID 0x35. Also correct the RID_C_STEPPING_START value for C-0. BUG=none TEST=Built, Intel Cherry Hill Rev F. Change-Id: I29268f797f68aa4e3b6203e098485e0bd4a44fc4 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/27471 Reviewed-by: Wim Vervoorn Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-21sb/intel/bd82x6x: Don't use device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: I4909ebffc978f537bbf6269d9e27dbaca43daa10 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-21soc/intel/quark/uart.c: Don't use device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: Ia50aa96901b979b947fd4d269b077814c06f60c6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28677 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-21arch/{mips,power8}/include/arch: Don't use device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: I8790bc333caa367ef46bf80b5fecc3e90ef89ca0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-09-21include/device/pnp.h: Don't use device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: I9364c9681dd89f09480368a997f6d1f04cde1488 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-21nb/via/vx900: Get rid of device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: I70dcefd5bc9864931f66bece1f044f806f5d7ae0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-09-21soc/intel/skylake: Don't use device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: Ifd1471a9cd76d2cea72262ed81b7071f31f7b375 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-21soc/broadwell: Don't use device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: Ifdf3d1870500812a417eaa5e93fcc168629c094f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-21arch/riscv/include/arch: Don't use device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: If52de0d87b02419090b29a7cf1952905d3f975f6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28691 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-21soc/intel/skylake: Include some microcode blobsArthur Heymans
This included the microcode for some CPUID's found in soc/intel/skylake/bootblock/report_platform.c (others are likely pre-release SKU's) The amount of FIT entries needed is currently 7 so setting CPU_INTEL_NUM_FIT_ENTRIES is set to a safe 10 will be able to fit them all. Change-Id: I3ba504a07b2697fe55ff8f28a934f761ae05a4ec Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-09-21google/kukui: Set up EC_IN_RW GPIO for ChromeOSTristan Shieh
Set up EC_IN_RW GPIO to boot depthcharge. Without this patch, depthcharge will fail to tell if the EC firmware is RW. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui and see in logs, that depthcharge detects EC_IN_RW GPIO. Change-Id: Icb39d663f65b72e0ad54059c9590d9693106ee25 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/28670 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-21mb/google/poppy/variant/nocturne: set DMIC1 to NCNick Vaccaro
Change GPP_D17 and GPP_D18 to no connects as DMIC was moved to DMIC0. BUG=b:113744731,b:111106010 TEST=none Change-Id: I8ef42627e542182707c81389af9da33a114bc184 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/28689 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-21mainboard/google/kahlee: allow oem.bin file to update smbiosMartin Roth
Grunt variants need a way to customize the mainboard vendor based on the platform. For future boards, this can probably be done via CBI, but grunt doesn't support that method. BUG=b:79874904 TEST=Build, boot, see updated mainboard vendor Change-Id: I997dc39c7f36f70cf4320ef335831245889eb475 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/28651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@google.com>
2018-09-21mb/google/octopus/variants/fleex: Update DPTF parametersSumeet Pawnikar
Update Power Limit1 and Power Limit2 values along with stepsize. Correct the charger effect for Temperature sensor2. BUG=b:112448519 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: I01e0a94fe694537d9eebe3b92c11d0c83137d716 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/28530 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-21soc/intel/cannonlake: Correct ITSS port id.praveen hodagatta pranesh
According to cannon lake PCH BIOS specification document #570374 target port id for interrupt and timer subsystem(ITSS) is C4 instead of C2. BUG=None TEST=None Change-Id: I9f8783c682d2c4c4a86e1c9cf4b9c27a18fdf494 Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/28698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Kin Wai Ng <nelsonaquik@gmail.com>
2018-09-20mb/lenovo/{T500, R400, W500}: Unify variants under T400Arthur Heymans
A negative side-effect is that those boards disappear from the board-status output, but this is an issue on all variants. Change-Id: Ic80804dc1f7d9c6f83ceee3db667019532c31d4c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28626 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-20soc/intel/cannonlake: Remove const for spd_smbus_addressLijian Zhao
Remove const define for spd_smbus_address, the value can be updated depends on platform configuration. TEST=Build and Run on Whiskey Lake rvp platform. Found-by: Converity Scan #1395725 Change-Id: Ib933ed872e9f85087bb3cd76a1f1e29cca75cd54 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28664 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-20soc/amd/stoneyridge/romstage.c: Remove obsolete commentRichard Spiegel
When preparing transition of AGESA calls to romstage, I placed a comment indicating the place to move a particular call. Now that the AGESA call has been moved to romstage, the comment became obsolete. BUG=b:116095766 TEST=none. Change-Id: I2811657385ab088747e32d4c66b99fdd01e7315e Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-09-20src/vendorcode/amd/agesa: Improve formatting of some f12 and f14 microcodesMike Banon
It is much more convenient to view these files if there are 8 values per line, not 1 value which results in a very long file. The contents remain the same: these microcodes are still the latest publicly available at the time of writing. Change-Id: I3e5296a5b5e895702a60aca1ded7418bb345263d Signed-off-by: Mike Banon <mikebdp2@gmail.com> Reviewed-on: https://review.coreboot.org/28391 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-20src/vendorcode/amd/agesa/f12: Update microcode to version 0x3000027 2011-09-13Mike Banon
This microcode update for CPU ID 0x300F10 should improve the system stability. It is a part of microcode_amd.bin officially released by AMD at linux-firmware: it starts at 0x217C offset, and size is 0x03C0 as specified priorly at 0x2178. Old version: 0x300000F [2010-04-10] replaced by New version: 0x3000027 [2011-09-13] Change-Id: I9650fab377d957904318ebb393323c2509cfea26 Signed-off-by: Mike Banon <mikebdp2@gmail.com> Reviewed-on: https://review.coreboot.org/28378 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-20mb/google/zoombini: Use Chrome EC BOARDID definitionKarthikeyan Ramasubramanian
The board_id() definition is the duplicate of chrome EC board_id definition. Remove the duplicate definition and select EC_GOOGLE_CHROMEEC_BOARDID Kconfig item. BUG=b:114001972,b:114677884,b:114677887 Change-Id: Id8b7027d653649e8e5791e455652c4e893a746c2 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org> Tested-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org> Reviewed-on: https://review.coreboot.org/28609 Reviewed-by: Jett Rink <jettrink@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-20ec/google/chromeec: Update google_chromeec_get_board_version prototypeKarthikeyan Ramasubramanian
The helper function to get the board version from EC returns 0 on failure. But 0 is also a valid board version. Update the helper function to return -1 on failure and update the use-cases. BUG=b:114001972,b:114677884,b:114677887 Change-Id: I93e8dbce2ff26e76504b132055985f53cbf07d31 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Tested-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/28576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@google.com>
2018-09-20mb/google/poppy/variants/nocturne: Update DPTF settingsPuthikorn Voravootivat
Update DPTF settings based on recommendation from thermal team. BUG=b:112550414 BRANCH=None TEST=Manually tested by thermal team. Change-Id: I26f09392a3293ce4b3481f2be341a667d606bc10 Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-on: https://review.coreboot.org/28666 Reviewed-by: Todd Broch <tbroch@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-20mb/google/octopus: Enable DRAM_PART_NUM_IN_CBI feature for meepWisley Chen
Enable DRAM_PART_NUM_IN_CBI feature to get DRAM part number from CBI and set DRAM_PART_IN_CBI_BOARD_ID_MIN to 1 for EVT. BUG=b:115965629 TEST=verified it in meep proto board which rework ram id. Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Change-Id: I962b099d5b9fbe0ca29708be1e9c6ed60b10d363 Reviewed-on: https://review.coreboot.org/28658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-09-20nb/amd/pi/00730F01: use MMIO and performance counters from AGESAPiotr Król
This patch contain minimal set of changes to initial IVRS implementation to make it work reliably. Code in this patch was tested with Xen 4.8 and Debian 4.14.y - this software stack survived 100x reboots without any hang on PC Engines apu2c4. Previously using IVRS provided by AGESA lead to 29/100 hangs. MMIO base shall not be hard coded since this value depends on platform design. Performance counters were selected experimentally, since lack of them cause 4.14.y panic: [ 1.064229] AMD-Vi: IOMMU performance counters supported [ 1.069579] BUG: unable to handle kernel paging request at ffffaffc4065c000 [ 1.073554] IP: iommu_go_to_state+0xf8a/0x1260 [ 1.073554] PGD 12a11f067 P4D 12a11f067 PUD 12a120067 PMD 129b69067 PTE 0 [ 1.073554] Oops: 0000 [#1] SMP NOPTI [ 1.073554] Modules linked in: [ 1.073554] CPU: 1 PID: 1 Comm: swapper/0 Not tainted 4.14.50 #13 [ 1.073554] Hardware name: PC Engines apu2/apu2, BIOS 4.8-1174-gf12b3046f0-d2 [ 1.073554] task: ffff8d5d69b9f040 task.stack: ffffaffc40648000 [ 1.073554] RIP: 0010:iommu_go_to_state+0xf8a/0x1260 [ 1.073554] RSP: 0018:ffffaffc4064be28 EFLAGS: 00010282 [ 1.073554] RAX: ffffaffc40658000 RBX: ffff8d5d69bae000 RCX: ffffffff99e57b88 [ 1.073554] RDX: 0000000000000000 RSI: 0000000000000092 RDI: 0000000000000246 [ 1.073554] RBP: 0000000000000040 R08: 0000000000000001 R09: 0000000000000170 [ 1.073554] R10: 0000000000000000 R11: ffffffff9a435e2d R12: 0000000000000000 [ 1.073554] R13: ffffffff9a29a830 R14: 0000000000000000 R15: 0000000000000000 [ 1.073554] FS: 0000000000000000(0000) GS:ffff8d5d6ec80000(0000) knlGS:00000 [ 1.073554] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 1.073554] CR2: ffffaffc4065c000 CR3: 000000010fa0a000 CR4: 00000000000406e0 [ 1.073554] Call Trace: [ 1.073554] ? set_debug_rodata+0x11/0x11 [ 1.073554] amd_iommu_init+0x11/0x89 [ 1.073554] pci_iommu_init+0x16/0x3f [ 1.073554] ? e820__memblock_setup+0x60/0x60 [ 1.073554] do_one_initcall+0x51/0x190 [ 1.073554] ? set_debug_rodata+0x11/0x11 [ 1.073554] kernel_init_freeable+0x16b/0x1ec [ 1.073554] ? rest_init+0xb0/0xb0 [ 1.073554] kernel_init+0xa/0xf7 [ 1.073554] ret_from_fork+0x22/0x40 [ 1.073554] Code: d2 31 f6 48 89 df e8 d8 15 02 ff 85 c0 75 d1 48 8b 44 24 2 [ 1.073554] RIP: iommu_go_to_state+0xf8a/0x1260 RSP: ffffaffc4064be28 [ 1.073554] CR2: ffffaffc4065c000 [ 1.073554] ---[ end trace 44588f98aa7c7c0b ]--- [ 1.255973] Kernel panic - not syncing: Attempted to kill init! exitcode=0x09 [ 1.255973] [ 1.259934] ---[ end Kernel panic - not syncing: Attempted to kill init! exi9 Possible future improvements: - compare device entries with values returned by AGESA - enable EFRSup (this is enabled in AGESA) - try various IVHD flags (there is difference between initial implementation and AGESA) Change-Id: I7e3a3d21f295ae96962d7718b9568fc4b67eb23d Signed-off-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-on: https://review.coreboot.org/27602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 02:41:10 +0000