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2018-08-03soc/intel/coffeelake: Add initial coffeelake supportLijian Zhao
Add coffeelake config and include path to coffeelake fsp header files. BUG=N/A TEST=Using private mainboard file can boot up on coffeelake rvp platform. Change-Id: Ide180de32a9d1896bed85b9e093963721c3d6041 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/27468 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-03mb/google/poppy/variants/atlas: Apply correct AC/DC loadlinesGaggery Tsai
This patch applies correct AC/DC loadline settings for Atlas from VRTT report. BUG=b:111419622 BRANCH=None TEST=emerge-atlas coreboot chromeos-bootimage and use DbC to check the AC/DC loadline settgins. Change-Id: I6e85b885a6d3a1db9a980d12f3cfc036a771422a Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/27788 Reviewed-by: Caveh Jalali <caveh@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-02google/cheza: Deassert USB hub reset pinJulius Werner
This patch makes sure we deassert the USB hub reset pin so the hub will work with the next board revision that drops the external pull-up. (Actual USB support comes in a later patch.) Change-Id: I1efdc3594cfa3229891d42d445a21c1739170b79 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27790 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-02cheza: Add board ID, RAM code and SKU IDJulius Werner
This patch adds the required callbacks to read all strapping IDs on Cheza. Change-Id: I6437bbd03bdd00dfeedcafebabeb00b13588d052 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-08-02mb/lenovo/x1_carbon_gen1: add vbtAlexander Couzens
Extracted from live running Thinkpad x1 carbon gen1 with vendor firmware. Thanks to Igor Lee. Change-Id: Id59517d9040c98e67a42fbce537f42f6b0c6db2d Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: Igor Lee <getrun@gmail.com> Reviewed-on: https://review.coreboot.org/27782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-02mb/google/poppy/variants/nami: Tune Fan speedSumeet Pawnikar
Tuning of fan speed for different temperature values. Earlier while running few benchmarks, fan was always getting on and starting at higher speed. With this change fan will start with lower speed and slowly speed gets increased if temperature continue going high. Thermal team provided these data after fine tuning of fan speed. BUG=None. TEST=Verified on Nami running with different benchmarks and observed fan speed. Change-Id: Ic3be9e44deef9570200c71807a2ee712d9f20876 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/27683 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-02mb/google/poppy/variants/nami: Enable mbox command for ISL VR c-state issueShelley Chen
There is a potential IMVP8 issue for KBL that affects Intersil VRs Nami is using one of the affected parts. The fix is to use an updated microcode and also send a mailbox box command from FSP. BUG=b:112081534 BRANCH=None TEST=Build and boot Nami Verify that suspend/resume and consecutive reboots are working Change-Id: I6ec18a4c3fae6a66cf8a95685d91a8ba51e2697c Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/27780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-02google/banon: Add support for additional RAM types/configsMatt DeVillier
Adapted from chromium commits 831a372 and cc96c27 [Banon: board 2nd source DDR memory] Add support for hynix/H9CCNNN8GTALAR-NUD and Nanya/NT6CL256T32CM-H1 Original-Change-Id: Ifd161ba5ade44e71c88655f760ca66668b5c5178 Original-Change-Id: I5cba13701ed8e037e21d34ed55162ee56291a842 Original-Signed-off-by: T.H. Lin <T.H_Lin@quantatw.com> Original-Tested-by: TH Lin <t.h_lin@quanta.corp-partner.google.com> Original-Reviewed-by: Vincent Wang <vwang@chromium.org> Original-Reviewed-by: YH Lin <yueherngl@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I2166d1025ede33148c7ab623ba59190a342c4736 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-02google/edgar: Add support for additional RAM types/configsMatt DeVillier
Adapted from chromium commits 2319742 and 3b59fb2 [Edgar: Add Micron MT52L256M32D1PF-107 SPD data] [Edgar: Add Hynix H9CCNNN8GTALAR-NUD and Nanya NT6CL256T32CM-H1 SPD data] Supported 2nd source Hynix, Micron, and Nanya memory. TEST=Built and used mosys command by "mosys -k memory spd print all" Original-Change-Id: Iec9160b74d2812620d2d28f841d503e2d63c8579 Original-Change-Id: I610f01a0198f835a2038511ff78bf0cfba7812a0 Original-Signed-off-by: Hank2_Lin <Hank2_Lin@pegatroncorp.com> Original-Reviewed-by: Vincent Wang <vwang@chromium.org> Original-Reviewed-by: YH Lin <yueherngl@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: If2379d6e58425616f49d77b0cdea1cd90f9a8bfa Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-02google/cyan: Configure WLAN_CLKREQ as GPIO and always assert lowMatt DeVillier
Adapted from chromium commit adcb858 [cyan: Configure WLAN_CLKREQ as GPIO and always assert low] This is a workaround for issue b/35648315 as proposed by Intel to ensure that WLAN_CLKREQ always stays low. BUG=b:35648315 Original-Change-Id: I178b3e4fbf74cf08eadfa8bd31b80b018f330e77 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/1055652 Original-Reviewed-by: Rajat Jain <rajatja@chromium.org> Original-Tested-by: Rajat Jain <rajatja@chromium.org> Change-Id: Ie3458b3fbd1ecadf6b99b9804fb98440cf8d6938 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-02google/cyan: Mask Audio IRQ on bootMatt DeVillier
Adapted from chromium commit cf18ab6 [Strago: mask Audio IRQ on boot] Do not start with audio interrupt unmasked; this causes interrupt storms on newer kernels that no longer mask all interrupts when initializing Cherryview pincontrol driver. TEST=Boot various cyan boards with kernels 3.18 and 4.14; verify everything works. Original-Change-Id: Id621682d3b59fea3ac54fb0ab92c8df9c78a6d43 Original-Signed-off-by: Dmitry Torokhov <dtor@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/894688 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Icb55c885ea661c41168d3bd24109d2cdbb225546 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-02google/cyan: Mark GpioInt() resources as PullDefaultMatt DeVillier
Adapted from chromium commit 3750e09 [Strago: mark GpioInt() resources as PullDefault] coreboot considers GPIO resources first-class citizens and initializes all pads according to their intended use, with necessary pull settings applied. Therefore let's use PullDefault as pull qualifier in AML, letting the kernel know that it should not attempt to alter pull settings when using GPIOs. TEST=Built and booted on celes, cyan, and egdar; built for other cyan devices. Original-Change-Id: Iff58a324e73a7eeac9b38df05a095fcfe7acd31b Original-Signed-off-by: Dmitry Torokhov <dtor@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/898259 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I0c69e77c58b8ceca71bc0c99e16d10c3e539f783 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27760 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-02google/cyan: Switch Touchpad and Touchscreen interrupts to be level-triggeredMatt DeVillier
Adapted from chromium commit 126d352 [Strago: switch Touchpad and Touchscreen interrupts to be level-triggered] The Elan and other touch controllers found in this device work much more reliably if used with level-triggered interrupts rather than edge-triggered. TEST=Boot several cyan boards, verify that touchpad and touchscreen work. Original-Change-Id: I59d05d9dfa9c41e5472d756ef51f0817a503c889 Original-Signed-off-by: Dmitry Torokhov <dtor@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/894689 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ia4f8cf83351dae0d78995ce0b0ed902d1e4ac3e8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-02google/cyan: do not hardcode virtual interrupt numbersMatt DeVillier
Adapted from chromium commit ee7a150 [Strago: do not hardcode virtual interrupt numbers] Instead of hardcoding virtual interrupt numbers that may change as the kernel changes, use GpioInt() resources to describe keyboard, touchpad, and touchscreen interrupt lines. TEST=Build and boot several cyan variant boards, verify keyboard, touchpad and touchscreen work with newer kernels (4.14+). Original-Change-Id: I98d5726f5b8094d639fb40dfca128364f63bb30b Original-Signed-off-by: Dmitry Torokhov <dtor@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/894687 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Iecfb45be433249d274532eb746588483fedb3f52 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-02mb/google/octopus: Enable EC SW sync for allJustin TerAvest
Since this works on Yorp and Bip, we should enable EC SW sync for all known boards so that it doesn't get forgotten. BUG=None TEST=None Change-Id: Ifee8e0b6620dc7554160a10a8e4663db25b6413d Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/27755 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-01sdm845: Add GPIO APIDavid Dai
Introduces new and required GPIO APIs, using common pinmux definitions for GPIO configuration. TEST=build & run Change-Id: I8cef9dae2072da32cb0678efefeb8f0070cdde9c Signed-off-by: David Dai <daidavid1@codeaurora.org> Reviewed-on: https://review.coreboot.org/26233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-08-01mb/google,samsung/*: Add LPC TPM chip driver to devicetreeMatt DeVillier
With commits 9987534 [southbridge/intel: Remove leftover TPM ACPI code] and 66ce18c [soc/intel: Remove legacy static TPM asl code] removing TPM ASL code from the southbridge's LPCB device, the LPC TPM chip driver (drivers/pc80/tpm) must be added to devicetree in order to ensure the new acpigen code is used to replace it. Test: boot various google/samsung boards, verify SSDT created with LPBC.TPM device and TPM visible to and usable by SeaBIOS and Linux Change-Id: Iedaa01f26fb357914549bb3dda24b0bd6ef67480 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27786 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-01sandybridge/raminit_common: use MCHBAR AND/OR macros in remaining placesFelix Held
Change-Id: I1c81eb7c8ed0b819bb76196208cc1269180aca55 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-08-01sb/intel/i82801gx: Select INTEL_TOP_SWAP_BOOTBLOCK_SIZEArthur Heymans
This effectively means it is possible to run another bootblock located at top_of_flash - 64K. The i82801gx southbridge has the ability to swap the two top 64K ranges by flipping the BUC.TS bit (RCBA[3414] bit0). This allows coreboot to build roms with a bootblock at the top swap offset by selecting CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK. Change-Id: Id96e10aea3e5fd955d45287134eb8643be414de9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2018-08-01riscv: remove redundancy in MakefileXiang Wang
src/arch/riscv/stages.c is an entry of romstage/ramstage, and does not needs to be bootblock. src/arch/riscv/id.S src/arch/riscv/id.ld is used to generate some compile/board/time information, which is repeated with src/lib/version.c Change-Id: Ic736b378e24df387584c5f86a2b04078fc55723d Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/27557 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-01soc/amd/stoneyridge/lpc.c: Fix LPC host control namingRichard Spiegel
2 bits of LPC host control were originally not public, and wrongly identified as IMC related. Now that the bits are available in public BKDG, fix the naming of the bits. BUG=b:111912080 TEST=build and boot grunt. Change-Id: I1921f46c6be54eda6329c98267cec27004caadd5 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27744 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-01mb/google/poppy/variant/nami: Overwrite AC/DC loadlinesGaggery Tsai
This patch adds a function to overwrite AC/DC loadlines for differnt projects. BUG=b:111761175 BRANCH=None TEST=emerge-nami coreboot chromeos-bootimage and use DCI to dump AC/DC loadline settings. Tested on Vayne and Akali. Change-Id: Id0068c5334c257b9f4c32b6088becbfe8391a864 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/27644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-01sandybridge/raminit_common: use macro for execute command queue registerFelix Held
This patch doesn't change the hash of a timeless build. Change-Id: I5d329f65be0eee741fd330c0926881ff4f956624 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-08-01sandybridge/raminit_common: use FOR_ALL_CHANNELS macroFelix Held
Change-Id: I01bd69605760e8a03787dcfa3da9f47576e3144a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-08-01sandybridge/raminit_common: use MCHBAR AND/OR/AND_OR macros [2/2]Felix Held
This patch contains the parts that changed the hash of the generated binary; probably due to the compiler optimizing things slightly different. Change-Id: Ide0b3296864e24edb646956e47221bfef8182e3d Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27725 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-01sandybridge/raminit_common: use MCHBAR AND/OR/AND_OR macros [1/2]Felix Held
When using timeless builds and coreboot crossgcc 6.3.0, the checksum of the resulting binary doesn't change with applying this commit. Change-Id: I2b1dc8befa3381f3edac06704e31e7ef50f86fa4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27724 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-01northbridge/sandybridge: add MCHBAR32 AND/OR/AND_OR access macrosFelix Held
Change-Id: I5d91674ebd281a595e7c0462671f4715ca09cb5c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27723 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-01nb/intel/gm45: Don't use PCI operations on the pci_domain deviceArthur Heymans
pci ops happen to work on this struct device since the device_path is an union. This patch still keeps adding the fixed resources in the pci_domain ops since moving it to the PCI ops which could properly use the function argument for PCI operations would require all PCI IDs to be added or else breakages are to be expected. Change-Id: I598b056d5fb1ce23b390b2f0ab4e9fb242d3685a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27242 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-01nb/intel/pineview: Don't use PCI operations on the pci_domain deviceArthur Heymans
pci ops happen to work on this struct device since the device_path is an union. This patch still keeps adding the fixed resources in the pci_domain ops since moving it to the PCI ops which could properly use the function argument for PCI operations would require all PCI IDs to be added or else breakages are to be expected. Change-Id: Iea5a09c62cca102b2c211e9256295c24cf3e9fa0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27243 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-01nb/intel/x4x: Don't use PCI operations on the pci_domain deviceArthur Heymans
pci ops happen to work on this struct device since the device_path is an union. This patch still keeps adding the fixed resources in the pci_domain ops since moving it to the PCI ops which could properly use the function argument for PCI operations would require all PCI IDs to be added or else breakages are to be expected. Change-Id: Iabfd15884ec8feb846d01b6af3c4afe5c1494feb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27245 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-01nb/intel/sandybridge: Don't use PCI operations on the pci_domain deviceArthur Heymans
pci ops happen to work on this struct device since the device_path is an union. This patch still keeps adding the fixed resources in the pci_domain ops since moving it to the PCI ops which could properly use the function argument for PCI operations would require all PCI IDs to be added or else breakages are to be expected. Change-Id: Id73c16fad4fb9ece78595844a39da993d169f057 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27244 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-01soc/intel/common/block: Add WhiskeyLake (WHL) IDsKrzysztof Sywula
Specifically PCI device ID for graphics and PCI device ID for northbridge. Change-Id: Ide237d3274df0543409c8a23b9bb50c8e0a6b7a3 Signed-off-by: Krzysztof Sywula <krzysztof.m.sywula@intel.com> Reviewed-on: https://review.coreboot.org/27519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kin Wai Ng <kin.wai.ng@intel.com>
2018-07-31security/tpm/tspi: Set return type of tcpa_log_add_table_entry as voidFurquan Shaikh
Change f849972 (security/vboot: Enable TCPA log extension) enabled support for adding TCPA log to CBMEM. However, if CBMEM is not online, this function doesn't do anything and returns early. This condition is not really a valid error condition as it depends on when the call to tcpa_log_add_table_entry is made. Since tcpa_log_add_table_entry returns -1 when cbmem is not online, tpm_extend_pcr prints an error message with prefix "ERROR:". This can confuse any scripts trying to catch errors in boot flow. This CL makes the following changes: 1. Removes the print in tpm_extend_pcr since tcpa_log_add_table_entry already prints out appropriate ERROR messages in case of failure to add log entry. 2. Since the return value of tcpa_log_add_table_entry is not used anymore, return type for tcpa_log_add_table_entry is changed to void. BUG=b:112030232 Change-Id: I32d313609a3e57845e67059b3747b81b5c8adb2a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-07-31mb/google/octopus: add lpddr4 skus for new memory sourcesnickchen
Add lpddr4 skus for new memory sources K4F6E3S4HM-MGCJ and MT53E512M32D2NP-046. BUG=b:111964159 BRANCH=master TEST=emerge-octopus coreboot chromeos-bootimage Change-Id: Id39a332998b28262e5aa45822078f3c4087f163f Signed-off-by: nickchen <nickchen@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27747 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Peichao Li <peichao.wang@bitland.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-31mb/google/octopus: Enable EC SW sync for fleexJustin TerAvest
This never got enabled for fleex; we should enable this to make it easier to have updated EC firmware. With this commit, here's the relevant console messages: sync_one_ec: devidx=0 select_rw=4 update_ec: Updating RW(active)... Trying to locate 'ecrw' in CBFS update_ec: image len = 137580 EFS: EC is verifying updated image... send_packet: CrosEC result code 1 EFS: EC doesn't support EFS_VERIFY command vboot_hash_image: No valid hash (status=0 size=0). Compute one... print_hash: RW(active) hash: 35ba735cf97dd990f6f7f0895264382aa20beb4e7ba57270b0a7b24686e26afd Trying to locate 'ecrw.hash' in CBFS sync_one_ec: jumping to EC-RW send_packet: CrosEC result code 12 EC returned from reboot after 27753us BUG=b:112038021 TEST=Successful boot after EC update via sync Change-Id: I2dc97c8e2b07f3bdef0d723789cc12c23b32c135 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/27753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-31riscv: fix issues (timestrap & PRIu64)Xiang Wang
When I tried to compile the RISC-V code (202e7d4f3c), I found some errors: `PRIu64` is undefined src/arch/riscv/timestamp.c does not exist Currently RISC-V does not have the implementation and use of timestamp, so I temporarily delete the code related to timestamp in the Makefile. And define PRIu64. Change-Id: I7f1a0793113bce7c1411e39f102cf20dbadda5d6 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/27543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-07-31samsung/stumpy: Add support for libgfxinitMatt DeVillier
Add support for libgfxinit Test: boot stumpy, verify all outputs operational prior for pre-OS display Change-Id: Ia720814c2225502316de5c5e9639c67df65a2ed0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-31mainboard/google/kahlee: Update VBIOS imageRichard Spiegel
The careena board requires a different setting within VBIOS in order to pass the eDP eye diagram test. Update all kahlee boards to use the new vBIOS. CQ-DEPEND=CL:1153080 BUG=b:111673328 TEST=Verify, via SOME unspecified method, that the new vBIOS is built into the Grunt/Careena ROM files. Change-Id: I268cd3dbce6ba1f7bd781d768f470463846a4e10 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27643 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-31src/vendorcode/amd/pi/00670F00: Remove IMC supportRichard Spiegel
Per AMD, the Integrated Micro Controller is not a supported feature of the Stoney Ridge APU. Systems are expected to implement an external EC for desired features. Remove all stoney IMC files and functions from vendor code. BUG=b:111780177 TEST=Build grunt and gardenia Change-Id: I06e993fa498cc0978c1d037bc6001682407f7fac Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27652 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-31src/soc/amd/stoneyridge: Remove IMC supportRichard Spiegel
Per AMD, the Integrated Micro Controller is not a supported feature of the Stoney Ridge APU. Systems are expected to implement an external EC for desired features. Remove all stoney IMC files and functions from src/soc/amd/stoneyridge. There are 2 "IMC bits" left (and used) that are not truly IMC. New BKDG describe these bits, so a new patch will be released later to fix the names and comment. BUG=b:111780177 TEST=Build grunt and gardenia Change-Id: I6a24e4c3f03d04713a030b884c611d9c64c4cb3a Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27651 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-31mb/amd/gardenia: Remove IMC supportRichard Spiegel
Per AMD, the Integrated Micro Controller is not a supported feature of the Stoney Ridge APU. Systems are expected to implement an external EC for desired features. Remove IMC files and functions from gardenia. BUG=b:111780177 TEST=Build gardenia Change-Id: I570b7f8e364b0c2937592590cc033d5a6c9fade0 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27650 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [1/2]Felix Held
When using timeless builds and coreboot crossgcc 6.3.0, the checksum of the resulting binary doesn't change with applying this commit. Change-Id: I057abe314622e92000c7e4ff2faa4595edb5244b Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-30nb/intel/gm45: Use common code for SMM in TSEGArthur Heymans
This makes i82801ix use the common smm southbridge code to set up smm relocation and smi handler setup. This is needed in this change for the the smm relocation code relies on some southbridge functions provided in the common code. Some of the old code is kept for the Q35 qemu target. This also caches the TSEG region and therefore increases MTRR usage a little in some cases. Currently SMRR msr's are not set on model_1067x and model_6fx since this needs the MSRR enable bit and lock set in IA32_FEATURE_CONTROL. This will be handled properly in the subsequent parallel mp init patchset. Tested on Thinkpad X200: boots and going to and resuming from S3 still works fine. Change-Id: Ic80c65ea42fcf554ea5695772e8828d2f3b00b98 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23419 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30northbridge/x4x: add MCHBAR AND/OR/AND_OR access macrosFelix Held
Change-Id: Ie95321f3eb6fb17b17eb25e8a54670654c373706 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-30cpu/intel/smm/gen1: Use correct MSR for model_6fx and model_1067xArthur Heymans
According to the "Intel® 64 and IA-32 Architectures Software Developer’s Manual" the SMRR MSR are at a different offset for model_6fx and model_1067x. This still need SMRR enabled and lock bit set in MSR_FEATURE_CONTROL. Change-Id: I8ee8292ab038e58deb8c24745ec1a9b5da8c31a9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-30riscv: delete src/arch/riscv/prologue.incXiang Wang
This code was copied from x86. It is not needed for RISC-V. Change-Id: If6c3bfdc4090e45d171e68a28d27c38dabe91687 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/27544 Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30ec/lenovo/h8/acpi: Fix ACPI error in _INIPatrick Rudolph
Store the power on defaults in the _REG method after the ERAM region is ready for use. It might not be ready when accessed from _INI. Tested on Lenovo T430. Change-Id: I70f22f8ac61dd850180fa159313bb0f8e4ab31d9 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/27710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-30mb/google/stout: Use new PMBASE APIPatrick Rudolph
Change-Id: Ibb13627bcd2ad023f7686b5ae0bd7331e09cf5b4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-30mb/samsung/lumpy: Use new PMBASE APIPatrick Rudolph
Change-Id: Ife344d1699a2eff7d93738221a0e87d0481f05d7 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-30mb/google/link: Use new PMBASE APIPatrick Rudolph
Change-Id: If4d6c80e95469341f0c978f302f04508f50280bd Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-30sb/intel/bd82x6x/finalize: Use new PMBASE APIPatrick Rudolph
Change-Id: Id42bbea1f2deb0be80af2c8008045d37a926126a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-30mb/google/parrot/smihandler: Use new PMBASE APIPatrick Rudolph
Change-Id: Ie95d9c04375e0125bae9bc01ae5caef423faf33e Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/27679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-30mb/google/kahlee/OemCustomize.c: Enable eDP HIGH_VDIFFRichard Spiegel
The careena board needs different video settings to pass eye diagram test, which does not affect negatively the grunt board. In preparation for new VBIOS, AGESA environment needs eDP high vdiff enabled. BUG=b:111673328 TEST=Add debug code to AGESA to display set eDP. Build AGESA. Build and boot grunt. Add new code to grunt, build and boot, verify eDP changed. Change-Id: I3e6b409699e8192eb39cc189628ff95b9f985e54 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-30soc/amd/stoneyridge/northbridge.c: Create a way to change eDP training valueRichard Spiegel
The careena board needs different video settings to pass eye diagram test, which does not affect negatively the grunt board. In preparation for new VBIOS, create code that allows changing eDP training parameter. BUG=b:111673328 TEST=Tested in child patch. Change-Id: Ic0452618bfc5e05b9ef8280bb8ba398ec7b4ce95 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-30mb/google/poppy/variants/atlas: Add new Nanya memory optionTim Chen
- add Nanya NT6CL256T32CM-H1 to memory strapping table BUG=b:111906760 BRANCH=none TEST=none Change-Id: I1432b9ab84f01a7fee1bc562aa40c714ddbf639e Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Caveh Jalali <caveh@google.com>
2018-07-30mainboard/google/nocturne: simplify camera power referencesMatt Delco
This change primarily moves the PowerResource up to a more common scope so that the _PRx references are simpler. The ^ scope modifier isn't well supported everywhere amongst OSes and drivers. Windows 10 will BSOD early during boot with ACPI_BIOS_ERROR (code 0x6, which means it could not find the object referenced by a _PRx) with the way things are currently laid out). I've also not seen a firmware outside of coreboot that tries to reference count _ON and _OFF. Isn't it up to the OS to deference count, and whatever it tells ACPI is what should happen (i.e., on means on and off means off)? Some of the _UIDs are also duplicated. This change makes them unique. A few cosmetic changes are made so that diffing cam0.asl against cam1.asl has fewer extraneous differences. Change-Id: I9c9f6c712b075450539d5b84ac5bb221b3cbb57e Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/27605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
2018-07-30google/caroline: Change debounce time for jack insertion and ejectionMatt DeVillier
Adapted from chromium commit 7633daa [caroline: Change debounce time for jack insertion and ejection] We are using max debounce time. During this time line, MICBIAS will be zero because of jack chasis. At the moment we got 0 button (PLAY/PAUSE) We need to reduce this time to below 100ms for caroline device. BUG=b:79559096 TEST=see there is no more irq before jack insertion/ejection irq complete Original-Change-Id: Ib6abdb4ff041823ca89f74cf59e2bfa644bb0d6a Original-Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Original-Reviewed-on: https://chromium-review.googlesource.com/1143109 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Wonjoon Lee <woojoo.lee@samsung.com> Change-Id: I8f605989d6ffc8a75127ed6722e7a37db95029ed Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27659 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30google/kukui: Enable eMMC in bootblock.Hung-Te Lin
On kukui board, the eMMC is routed to EC for boot ROM emulation when loading bootblock, and should be set back to real eMMC as early as possible after bootblock is loaded. BUG=b:80501386 TEST=make; boots and verified BOOTBLOCK_EN_L GPIO is enabled. BRANCH=None Change-Id: Ifefb2e26ed048c38595907cc0875757410129828 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/27601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30cpu/intel/microcode: Add helper functions to get microcode infoRizwan Qureshi
Add 4 helper functions to get microcode info. * get_current_microcode_rev return the the version of the currently running microcode. * get_microcode_rev extract microcode revision from the given patch. * get_microcode_size extract microcode size from the given patch. * get_microcode_checksum extract checksum from the given patch. The simpler thing would be to just move the struct microcode to microcode.h so that the structure members can be dereferenced. To encapsulate the structure details added the helper functions. This information will be used in future to compare microcodes for update. Change-Id: I67a08ba40b393874d8cc17363fefe21e2ea904f3 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/27365 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30soc/intel/common: Add support to configure top swap featureAamir Bohra
RTC BUC control register provides a software interface to configure the top swap feature. This patch adds implementation to enable/disable top swap feature and gets it accessible in romstage as well. The top swap control functions are exposed only if INTEL_HAS_TOP_SWAP is selected. To use the topswap feature a second bootblock has to be added to the cbfs. Below configs aid in doing that, INTEL_HAS_TOP_SWAP INTEL_ADD_TOP_SWAP_BOOTBLOCK INTEL_TOP_SWAP_BOOTBLOCK_SIZE Enabling and Disabling topswap, using the added API enables user to boot alternatively from either bootblock. Change-Id: Iea31b891f81e76d4d623fcb68183c3ad3dcadbad Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/25805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-30mb/google/poppy/variants/nocturne: enable FPMCU powerNick Vaccaro
Enable power to FPMCU by default on power-on and deassert the PCH_FPMCU_RST_ODL reset line. BUG=b:111880258 BRANCH=none TEST='emerge-nocturne coreboot chromeos-bootimage', flash and boot nocturne to kernel, login and execute "powerd_dbus_suspend" at kernel prompt, wait a few seconds, press power button to wake, then execute "cat /var/log/cros_fp.log | grep 'Reset cause'" and assure search comes up empty. Change-Id: I7f8419dd58f79816f8061d0da4a0d3984c814289 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/27658 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30mb/google/poppy/variants/nocturne: enable ec host event wakeNick Vaccaro
Enable nocturne to wake from lid attach/detach events. BUG=b:111803637 BRANCH=none TEST="emerge-nocturne coreboot chromeos-bootimage", verify EC has commit a5abbbb4eb9b15a72624dddbfd727d0b324c3f36, and verify nocturne wakes from suspend on a lid attach/detach event. Change-Id: I22b957d741426ca8b49d1819cf39c940f55198eb Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/27649 Reviewed-by: Aseda Aboagye <aaboagye@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30mb/google/nautilus: Remove obsolete fieldsAlan Chiang
Some fields were only required during early stages of IPU3. Remove some fields that aren't used for the current version of IPU3. BUG:None TEST=Launch camera app and check if it works properly. Change-Id: I72bcba13cc353a1b16fedeb7543fbbac432fbf5d Signed-off-by: Alan Chiang <alanx.chiang@intel.com> Reviewed-on: https://review.coreboot.org/27617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andy Yeh <andy.yeh@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-30mb/cavium/cn8100_sff_evb: Compile devicetree for LinuxPatrick Rudolph
Compile the linux devicetree using dtc and add it to CBFS. Change-Id: I8a98ed7b128f65a6e0109963dbabca91563a315c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-30soc/cavium/cn81xx: Use ATF from blobs repoPatrick Rudolph
Use precompiled BL31 from blobs repo. There's no check for USE_BLOBS here as the included file is "free": The BL31 is Open-Source and licensed under BSD. Change-Id: I7e9eb429d11150d43aa070d1bd6a11ea71951ce3 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-30soc/cavium/bootblock: Get rid of register X1Patrick Rudolph
The register X1 isn't used. Document it and remove it. Change-Id: I9324ea9de24ba4baaef9dde890c443dd0f921ad9 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/23792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-30mb/google/octopusi/variants/bip: Fix unused pins and those with external ↵Furquan Shaikh
terminations For unused pins, configure them as GPIO input and use the default termination. For the pins where board has an external termination, remove SOC's internal termintation. BUG=b:110654510 TEST=On Bip, flashed image and verified that it boots to OS. Also executed a few suspend resume cycles. Change-Id: I343fed54ebc04199acecab257d7b8253d0a3d83b Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/27634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-30drivers/i2c/da7219: Allow disabling micbias-pulse featureDaniel Kurtz
These two da7219_aad properties are optional: - dlg,micbias-pulse-lvl : Mic bias higher voltage pulse level (mV). [<2800>, <2900>] - dlg,micbias-pulse-time : Mic bias higher voltage pulse duration (ms) When the Mic Bias Higher Voltage feature is not required, firmware should just not provide the dlg,micbias-pulse-lvl and dlg,micbias-pulse-time properties. Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> BUG=b:111700809 TEST=On grunt: No "Invalid micbias pulse level" in dmesg Change-Id: Ie99a8962e78c68b3f6927d0de34168f265d4efa9 Reviewed-on: https://review.coreboot.org/27613 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Akshu Agrawal <akshu.agrawal@amd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30security/tpm: Use unique CBMEM names for TCPA logsPhilipp Deppenwiese
Fix regression introduced in commit f18dc5c7 "Add TCPA logging functionality": Introduced TCPA log got overwritten in acpi.c of x86/arch, due to CBMEM name collision. Use a different cbmem name to have two independent TCPA logs. Change-Id: Iac63ac26989080a401aac2273265a263a3fdec56 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/27726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-30security/vboot: Enable TCPA log extensionPhilipp Deppenwiese
* Implement TCPA log for tspi extend function. * Hook tcpa_log_init into vboot tpm_setup function. * Add TCPA log output for vboot GBB flags and HWID Change-Id: I22b1aa8da1a95380c39715727615ce5ce4c9443f Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/27727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-30soc/intel/fsp_baytrail: Add VBOOT supportPhilipp Deppenwiese
* Add vbnv_cmos_failed function to SoC. * Add VBOOT starts in romstage select. Change-Id: I90a051e2b8d303c918bef976d0bb07aae0b1f5b3 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/27728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-30northbridge/nehalem: add MCHBAR AND/OR/AND_OR macrosFelix Held
The newly added macros are used for cleaning up the RAM initializatiion code. Change-Id: I3d3782ee1fa524cf69b63ccc7eb73e9a2ace84ec Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-30northbridge/nehalem: clean up header fileFelix Held
* remove duplicate macro definitions * add brackets to macros Change-Id: I1f758203afdcb1b18f3c0d786698f9fbf2246e0e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-30mainboard/opencellular/rotundu: Add FMAP supportzaolin
* Add 8M and 16M fmap configurations. * Fix kconfig selects. * Add vboot options and fixes Change-Id: I49d97a9d324207e45520d43b814b03a20005122a Signed-off-by: zaolin <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/25084 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30mb/google/poppy/variants/nautilus: Set GPP_D21 to high as defaultSeunghwan Kim
Currently, default GPP_D21(LTE3_BODY_SAR) output level is low, it means LTE tx power is backoff mode as default. We would set GPP_D21 to high to change LTE tx power to normal mode as default. BUG=None BRANCH=poppy TEST=Verified default LTE tx power mode is normal mode as default Change-Id: I62e77196c2116924f437f61368f0ae7efd0e144c Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/27661 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30mb/google/poppy/variants/nami: Fix fan is always ONJohn Su
Add the new setting for fan performance state. BUG=b:111860513, b:11865138 TEST=Fan do not run below trip point Change-Id: I894460b8b418217e2477608094c37018437cbb78 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-07-30mainboard/google/kahlee: Pad SPD serial Number with spacesMartin Roth
All of the other SPDs are padded with spaces to make them use the full size of the serial number field. The hynix-H5AN8G6NCJR-VKC SPD was not, and that seems to be causing problems with some tools. BUG=b:111903749 TEST=Mosys correctly identifies memory on board using that SPD. Change-Id: I0e831873acab2f6fc7d76e85647198d3b7af4b12 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/27676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
2018-07-29sandybridge/raminit_common: use MCHBAR32 macro everywhereFelix Held
Change-Id: I22f1c7dbdaf42722115d9e5913d47aa2c9dc7e9a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-29sandybridge/raminit: use MCHBAR32 macro everywhereFelix Held
Change-Id: I42d97d278c81ce2cfd0010830c2e0bacddd947d6 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-29sandybridge: add brackets to MCHBAR/EPBAR/DMIBAR access macrosFelix Held
Change-Id: If8b8fd123e0dd15a0fc9dfe178076f8541e29d56 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-29pnp_device: don't treat missing PNP_MSC devicetree entry as errorFelix Held
Change-Id: I8da01cd462225b633bf2043ab33b35aeddc8d55a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-29device/pnp_device: rewrite pnp_get_ioresourceFelix Held
The rewrite simplifies the code and fixes the limit on the case of IO resources with the length of 1 byte. This patch is inspired by the comment of Nico Huber on Ia99b785dcd9cf56fb236ad7ade54656851f88a5e If the ones in the mask aren't a continuous block, now a warning message gets printed. Change-Id: I0089278f5adf65e8f084580bc5bc1eb2f77b87f7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-29soc/intel: Remove legacy static TPM asl codePhilipp Deppenwiese
Since the TPM software stack refactoring static TPM ACPI code isn't needed anymore. Change-Id: I36a99cbc420ecfa55aa5c89787151d482225adf2 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/27715 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-29nb/intel/sandybridge: Bump MRC_CACHE_VERSIONPatrick Rudolph
Commit 74203de "intel/sandybridge: Don't hardcode platform type" changed the MRC layout. Bump the version to prevent a boot error, if the cache isn't cleared on flashing a new coreboot version. Change-Id: Icd6f31bf0b30a42c66e18ab83d2434f9c3084211 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/27712 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-29mb/google/octopus: Perform EC init before bootblock gpio configurationFurquan Shaikh
A variant might talk to the EC to get board id in order to identify the right GPIO configuration. Thus it is important to ensure that the LPC IO windows are configured before this. This change moves the call to perform EC init before configuring bootblock GPIOs. BUG=b:111933657 TEST=Verified that reading board id does not fail on phaser. Change-Id: Ic23c6fd7597a314e0b6421be39ccc0b1dfb46567 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27671 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-28mainboard/opencellular/rotundu: Enable TPM 1.2 supportPhilipp Deppenwiese
* Enable support for all variants. Change-Id: Ibdd43d8cff23d3fa1154e2b72aa6095682783fe5 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/27685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-28mainboard/opencellular/rotundu: Add supabrck EMMC supportPhilipp Deppenwiese
Change-Id: Icf9feaf6f74cfe33a817bb2f1ecd3d49aa5e9a43 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/27684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-28sb/intel/bd82x6x: Fix watchdogPatrick Rudolph
* Fix comments * Use defines instead of magic values * Use new PMBASE API to modify registers Change-Id: Idd2ded19e528427db29fa87d87481b91bae2b512 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-28opencellular/rotundu: Introduce variants for OCPhilipp Deppenwiese
* Add Supabrck v1 variant * Modify rotundu base board Change-Id: Id20e9d4ed7ac071d25a69eee63c9ec544d2ad152 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-28util/cbmem: Add cbmem TCPA log supportPhilipp Deppenwiese
* Read and print the TCPA ACPI log. Change-Id: Ie2253d86cfc675d45b0a728794cc784215401f4a Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/26244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-28security/tpm: Add TCPA logging functionalityPhilipp Deppenwiese
* TCG spec only applies to BIOS or UEFI. * Therefore implement coreboot TCPA compliant log in CBMEM. * Write CBMEM log into the coreboot table for CBMEM tool access Change-Id: I0a52494f647d21e2587231af26ed13d62b3a72f5 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-28nb/intel/sandybridge/report_platform: Move remaining code to sb folderPatrick Rudolph
Change-Id: I2ced3f2bb9d1d150341a57ff333ca14c897c4fa3 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-28nb/intel/sandybridge: Move CPU report to cpu folderPatrick Rudolph
Change-Id: Ie973923b90eca0bfabd474fed85a6cc33fce7e19 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-28intel/sandybridge: Don't hardcode platform typePatrick Rudolph
* Add a function to return CPU platform ID bits * Add a function to return platform type ** Platform id is 4 on Lenovo T430 (mobile) ** Platform id is 1 on HP8200 (desktop) * Use introduced method to handle platform specific code * Use enum for platform type * Report platform ID Change-Id: Ifbfc64c8cec98782d6efc987a4d4d5aeab1402ba Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-28sb/intel/gpio: Cache gpiobase in ramstage and romstagePatrick Rudolph
Implement caching like it's done with pmbase. Change-Id: I26d56a9ff1a8d6e64c164f36e23b846b8b459380 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27664 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-28mainboard/google/kahlee: Fix Micron MT40A512M16LY-075:E POST CRC errorKevin Chiu
Fix Micron MT40A512M16LY-075:E DRAM SPD CRC error in AGESA MemSPDChecking: ERROR Event: 04011200 Data: 0, 0, 0, 0 BUG=b:111901461 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I85c82fd9294f9146fc23e649436cbcc337c4c961 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/27657 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-27soc/amd/stoneyridge: Add IGFX device ACPI ASL entryMarc Jones
Add internal graphics device 00.01.00 to the ACPI tables so that the ACPI PCI option ROM save functions have a proper scope to save the ROM to. BUG=b:111697181 TEST=Check coreboot log doesn't have "PCI: 00:01.0: Missing ACPI scope" and check _ROM method is added in the SSDT1. Change-Id: I2c9ef8d9dff76805b1fcde2ccceef958a5b53b4f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/27653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-07-27chromeec: Read EC uptime info on bootJonathan Brandmeyer
Additional diagnostic information about the EC and the most recent reasons why it has reset the AP are read out and logged via printk. This may aid in debugging spurious hangs and/or resets on the AP by providing traceability to the EC when it triggered the reset. Merely knowing that the EC was also recently reset may provide valuable intelligence. See also https://crrev.com/c/1139028. Change-Id: Ie6abe645d5acefb570b9f6a3c4a4b60d5bcd63cd Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-on: https://review.coreboot.org/27621 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-27chromeec: Sync ec_commands.h with CrOS upstreamJonathan Brandmeyer
Update ec_commands.h to be a verbatim copy of upstream, except retain the complete copyright notice found in coreboot's copy. Upstream refers to a file not present in coreboot. Change-Id: Ic3daa09ffd83c089b6874e0ea9aab8aa60016775 Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-on: https://review.coreboot.org/27620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-27sb/intel/common/pmutil: Use new PMBASE APIPatrick Rudolph
Change-Id: I0f37f0c49fd58adafd8a508e806e0f30759a6963 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27287 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>