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2015-09-24coreboot: move TS_END_ROMSTAGE to one spotAaron Durbin
While the romstage code flow is not consistent across all mainboards/chipsets there is only one way of running ramstage from romstage -- run_ramstage(). Move the timestamp_add_now(TS_END_ROMSTAGE) to be within run_ramstage(). BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. TS_END_ROMSTAGE still present in timestamp table. Change-Id: I4b584e274ce2107e83ca6425491fdc71a138e82c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11700 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-23chromeos: vboot and chromeos dependency removal for sw write protect statePaul Kocialkowski
This removes the dependency on chromeos and vboot for the sw write protect state function: vboot_get_sw_write_protect, renamed to get_sw_write_protect_state to both reflect this change and become consistent with the definition of get_write_protect_state that is already in use. Change-Id: I47ce31530a03f6749e0f370e5d868466318b3bb6 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: http://review.coreboot.org/11496 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-23google: veyron: CBFS_SIZE to match the available size for Coreboot in ChromeOSPaul Kocialkowski
When building for ChromeOS, it is expected that Coreboot will only occupy the first MiB of the SPI flash, according to the veyron fmap description. Otherwise, it makes sense to use the full ROM size. Change-Id: I168386a5011222866654a496d8d054faff7a9406 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: http://review.coreboot.org/11117 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-23RISCV: modify arch_prog_run to handle payloads correctly.Ronald G. Minnich
Unlike the other stages, the payload requires virtual memory to be set up and also a privelege level change. Change-Id: Ibbe2a55f7719d917f121a53a17c6d90e6b2ab3d1 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/11699 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-09-22linking: link bootblock.elf with .data and .bss sections againAaron Durbin
Currently coreboot expects the loader to clear the bss section for all stages. i.e. stages don't clear their own bss. On ARM SoCs the BootROM would be responsible for this. To do that one needs to include the bss section data (all zeros) in the bootblock.bin file. This was previously being attempted by keeping the .bss info in the .data section because objcopy happened zero out non-file allocated data section data. Instead go back to linking bootblock with the bss section but mark the bss section as loadable allocatable data. That way it will be included in the binary properly when objcopy -O binary is emplyed. Also do the same for the data section in the case of no non-zero object values are in the data section. Without this change the trick of including .bss in .data was not working when there wasn't a non-zero value object in the data section. BUG=None BRANCH=None TEST=Built emulation/qemu-armv7 and noted bootblock.bin contains the cleared bss. Change-Id: I94bd404c2c4a8b9332393e6224e98940a9cad4a2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11680 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-22commonlib: add endian related accessor functionsAaron Durbin
This commit adds read/write functions for both big and little endian interpretations. Additionally there are variants that allow an offset to be provided into the source buffer. BUG=None TEST=Wrote test harness for functions. Also booted ARM QEMU through end of payload. Change-Id: If44c4d489f0dab86a73b73580c039e364c7e517d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11677 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-09-22coreboot: introduce commonlibAaron Durbin
Instead of reaching into src/include and re-writing code allow for cleaner code sharing within coreboot and its utilities. The additional thing needed at this point is for the utilities to provide a printk() declaration within a <console/console.h> file. That way code which uses printk() can than be mapped properly to verbosity of utility parameters. Change-Id: I9e46a279569733336bc0a018aed96bc924c07cdd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11592 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-09-17broadwell: Switch to using common ACPI _SWS codeDuncan Laurie
Use the common ACPI _SWS code and provide a function to fill out the wake source data. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-samus coreboot Change-Id: I3d2ceca8585314122b78317acb7f848efb6e9a14 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d8afaee8e27222639c5e249d53be28cddcb78f72 Original-Change-Id: Ie551ecf3397c304216046cc2046c071f7b766e5f Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298168 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11647 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17braswell: Switch to using common ACPI _SWS codeDuncan Laurie
Switch braswell to use the common code for filling out the NVS data used by ACPI _SWS methods. This code was out of date on braswell so also update it to provide the \_GPE.SWS method. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-cyan coreboot Change-Id: I41c2a141c15f78dc0d9482954c157f81bd0759fa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4c4d1ee76f337addf687ca5a9ae2da5e898c2de0 Original-Change-Id: I44424784d5d3afb06d0d58c651a9339c7b77418c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298230 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11649 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17skylake: Use common ACPI _SWS codeDuncan Laurie
Enable and use the common code for filling out the NVS data used by the _SWS methods. Add a function to provide the wake source data. With Deep S3 enabled skylake does not retain the contents of the PM1_EN register so instead just select the wake related events in PM1_STS. BUG=chrome-os-partner:40635 BRANCH=none TEST=tested on glados by checking for valid _SWS string in /sys/firmware/log after suspend/resume. Wake sources that were tested are RTC, power button, keypress, trackpad, and wifi. Change-Id: I93a4f740f2e2ef1c34e948db1d8e273332296921 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cb4d4705b87ef7169f1979009c34a58de93c4ef0 Original-Change-Id: Ib6b4df09ea3090894f09290d00dcdc5aebc3eabb Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298169 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11648 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17glados/kunimitsu: remove the implementation of mainboard_add_dimm_inforobbie zhang
This is a follow-up patch to https://chromium-review.googlesource.com/#/c/286877, after fsp support is landed in v1.5. BUG=chrome-os-partner:42975 BRANCH=none TEST=execute "mosys memory spd print all" on glados and kunimitsu Change-Id: I949e287372b190affac36a0efde8a30402eecdc8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 71a2e1838ff8bbaa358c167dad905b63d23c43fa Original-Change-Id: I64103af4f8456a053a955845a067062122f47af3 Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/298967 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11657 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17kunimitsu: Enable wake-on-wifiDuncan Laurie
- Assign GPE DW0 to GPP_B block - Enable GPP_B16 as ACPI_SCI for wake - Define PCIe WLAN device in ACPI with GPE0_DW0_16 for _PRW Note that current designs cannot wake from Deep S3 via wifi. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-kunimitsu coreboot Change-Id: I1fe15a5a9b3d868a0e4f1bfb102b69f024c3aa48 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: de9dfee840246866a8dcca2e1c42c0292e820529 Original-Change-Id: I926d74b6bcf6d64c3db61ed23d7c17b51a98b052 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298232 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11651 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17glados: Enable wake-on-wifiDuncan Laurie
- Assign GPE DW0 to GPP_B block - Enable GPP_B16 as ACPI_SCI for wake - Define PCIe WLAN device in ACPI with GPE0_DW0_16 for _PRW Note that current designs cannot wake from Deep S3 via wifi. BUG=chrome-os-partner:40635 BRANCH=none TEST=tested on glados: 1-disable deep s3 in devicetree.cb 2-enable magic packet with "iw phy phy0 wowlan enable magic-packet" 3-powerd_dbus_suspend to go to S3 4-wake system with magic packet Change-Id: I989768615e9da8ecf6354852d2db7aae8069aa82 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 894354c5bfd499b911b7f89310c48b503dbaadc2 Original-Change-Id: I9a7a317fc2eccc70fdb4862843de1a654fbc2eee Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298231 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11650 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17Skylake: update C state latency and power numbersrobbie zhang
The values are taken from latest BWG as well fsp src. BRANCH=none BUG=chrome-os-partner:45208 TEST=Built and boot on kunimitsu Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Change-Id: Ia6bd336a71b0313801b59990c78822fa0d789e36 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c955ab43245153d76932daa527f1b5ebea859164 Original-Change-Id: I3f7307951753c2bbe6319f627a82a93359c4e61b Original-Reviewed-on: https://chromium-review.googlesource.com/299480 Original-Commit-Ready: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11659 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17drivers/intel/fsp1_1: split relocation code for tool useAaron Durbin
In order for easier consumption in userland tools split the FSP 1.1 relocation logic into a single file w/ an aptly named function name. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Change-Id: I49998b8621611c638375bc90884e80d0cd3bdf78 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bc898e1c528df60683575d553d6194a1e8200afa Original-Change-Id: I736c0059d43f6d0be4fdb6e6f47cdb5c189a7ae8 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298833 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11665 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-17drivers/intel/fsp1_1: handle UEFI endiannessAaron Durbin
UEFI defines everything as little endian. Additionally the EDK II header files assume they are used on machines which are running UEFI -- thus little endian. This patch attempts to fix up all the possible endian violations when running on a big endian machine. This is for in preparation of using the FSP 1.1 code in userland for relocating FSP images. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Change-Id: I39f4de84688e48978a4650303b8af8345f44fd03 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3c7eab9b7c10765355feffa3c3cac403275f9479 Original-Change-Id: I33a7661281307cf31ae33899d1a4eb6a2fbd01a1 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298832 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11664 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-17drivers/intel/fsp1_1: prepare relocation code for sharingAaron Durbin
In order to integrate fsp 1.1 relocation with cbfstool one needs to be able to supply the address to relocate the FSP image. Therefore, allow this by returning offset for return values. Note that exposed API has not changed. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Confirmed relocation values matched. Change-Id: I650a08ffb9caf7e0438a988cae9bec56dd31753c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 53870b0df809418e9a09e7d380ad2399a09fb4fb Original-Change-Id: Ic2ec63681ed4e652e2624b40e132f95d1e5a0887 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298831 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/11663 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-17linking: Repair special treatments for non-x86 bootblocksJulius Werner
Patch b2a62622b (linking: move romstage and bootblock to use program.ld) unified the linker scripts between different stages. Unfortunately it omitted several special cases from the old bootblock.ld script that are required for non-x86 environments. This patch expands program.ld to once again merge the .BSS into the program image for bootblocks (ensuring correct initialization by the external loader). It also revives the .id section (which adds a human-readable blurb of information to the top of an image) and fixes a problem with unintended automated section alignment. BRANCH=None BUG=None TEST=Jerry and Oak boot again. Change-Id: I54271b8b59a9c773d858d676cde0218cb7f20e74 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6fddbc00963e363039634fa31a9b66254b6cf18f Original-Change-Id: I4d748056f1ab29a8e730f861879982bdf4c33eab Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/299413 Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11660 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17t210: lp0_resume: Configure unused SDMMC1/3 pads for low power leakageYen Lin
In LP0 resume, a couple of SDMMCx pad settings need to be set to 0 to reduce power leakage. BUG=None BRANCH=None TEST=Tested on Smaug; able to suspend/resume >100 times Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9f35a90a8af2180443db2c4be75d4566d0990de5 Original-Change-Id: Ifc946b0cea437ef0807cea0c11609d8e09387e8e Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/298195 Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Tested-by: Joseph Lo <josephl@nvidia.com> Original-(cherry picked from commit be3ac49a6bc4c9088d3799555d69c87c8ce1693c) Original-Reviewed-on: https://chromium-review.googlesource.com/298154 Original-Commit-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Change-Id: If5d5cebc89b8220480b3c72293a410e782eb437e Reviewed-on: http://review.coreboot.org/11656 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-09-17intel/skylake: Create "RtcLock" Silicon UPD from corebootBarnali Sarkar
FSP should not lock CMOS unconditionally. coreboot sends Silicon UPD parameter "RtcLock" to FSP to take action on CMOS region locking/un-locking. This patch has CB generic code for creating the Silicon UPD paramater. BUG=chrome-os-partner:44484 BRANCH=none TEST=Build and booted in kunimitsu, tested using below command- When DIsabled RtcLock from devicetree in coreboot, booted to kernel and run following commands - >> crossystem fw_result=success >> crossystem | grep fw_result It should reflect the value that is set. Here, success. If ENabled RtcLock from Coreboot devicetree, The same commands will fail to update the fw_result status from crossystem utility. CQ-DEPEND=CL:*229144 Change-Id: I7f63332097cdaf6eedefbc84bec69ce4e9cc59d7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c7b8293a2c55117d7ca2001ac9ec0de24d35b80b Original-Change-Id: If708e2c782644dcf7f03785d1bfa235ef5385d80 Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/297980 Original-Commit-Ready: Subrata Banik <subrata.banik@intel.com> Original-Tested-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11655 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17vbnv: check alignment of nvram in advanceDaisuke Nojiri
Currently, erase operation only works if the region is sector-aligned. These asserts ensure we can erase the region when it's all used up. Erase operation can be updated to handle unaligned erases by read, update, write-back cycle. However, these asserts will still remain useful in case the adjacent region contains critical data and mis-updating it can cause a critical failure. Additionaly we should write a FAFT test but it's more reliable to catch it here since FAFT can fail in many ways. BUG=none BRANCH=master TEST=tested on samus using misaligned nvram region Change-Id: I3add4671ed354d9763e21bf96616c8aeca0cb777 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fc001a4d3446cf96b76367dde492c3453aa948c6 Original-Change-Id: Ib4df8f620bf7531b345364fa4c3e274aba09f677 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297801 Reviewed-on: http://review.coreboot.org/11654 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17kunimitsu: Remove code to set USB charge behavior on sleepDuncan Laurie
The EC doesn't support these commands so sending them is not working. We have had a default policy of wake on USB for a long time now and this runtime config isn't really needed any longer. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-kunimitsu coreboot Change-Id: I547d92b4e852664567792060bf1f7b60976bb9a6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4a929eb9ec422e145006505ea4d5fbd1ef3950be Original-Change-Id: I01e80de65e6e1cdcabb24edb43bc671f5a8aa437 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298234 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11653 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17glados: Remove code to set USB charge behavior on sleepDuncan Laurie
The EC doesn't support these commands so sending them is not working. We have had a default policy of wake on USB for a long time now and this runtime config isn't really needed any longer. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: Ib789ae3a7ba56a11dfb5918cb40bfa2f044d1dc3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0ed7391942afed94bfc7ad04880d4c2b865e5655 Original-Change-Id: I6fe10952f32673a447001b832ac6c6b04b22aef0 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298233 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11652 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17intel/common: Add common code for filling out ACPI _SWSDuncan Laurie
Add common code for filling out the NVS fields that are used by the ACPI _SWS methods. The SOC must provide a function to fill out the wake source data since the specific data inputs vary by platform. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I4f3511adcc89a9be5d97a7442055c227a38c5f42 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cee5fa176c16ca44712bce8f3c8045daa5f07339 Original-Change-Id: I16f446ef67777acb57223a84d38062be9f43fcb9 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298167 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11646 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-16riscv-virtual-memory: move page tables into virtual address spaceThaminda Edirisooriya
If we use a linux payload/any payload that wants to manage virtual memory, and the payload is a supervisor (thus requiring virtual addressing before being started), we need to make sure that the page table is mapped into the virtual address space. Move the start address of the tables so the payload can manage virtual memory. Change-Id: I1d99e46f38a38a163fb1c7c517b1abca80cde0dc Signed-off-by: Thaminda Edirisooriya <thaminda@google.com> Reviewed-on: http://review.coreboot.org/11621 Tested-by: build bot (Jenkins)
2015-09-16riscv-memlayout: fix existing memlayout issues, add sbi interfaceThaminda Edirisooriya
Existing memlayout code placed sections in overlapping areas, and would overwrite the payload if it was large enough. Update memlayout.ld in src/mainboard/emulation/spike-riscv to represent the spike emulator, and add sbi interface which now has room into src/arch/riscv/bootblock.S. Add utility code to qemu-riscv, but emulator itself has yet to be updated to new ISA and as such should not be used. Update Makefile to include all the files necessary for sbi interface. Clean up unused include in src/arch/riscv/include/atomic.h and whitespace in src/mainboard/emulation/spike-riscv/memlayout.ld Fixed whitespace issues in spike_util.c Change-Id: Id97fe75e45ac1361005bec6d421756ee3f98a508 Signed-off-by: Thaminda Edirisooriya <thaminda@google.com> Reviewed-on: http://review.coreboot.org/11370 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-09-16kunimitsu: Enable ALS connected to ECDuncan Laurie
Kunimitsu has an ambient light sensor connected to the EC which is presented to the OS as a standard ACPI0008 device. BUG=chrome-os-partner:43493 BRANCH=none TEST=emerge-kunimitsu coreboot Change-Id: I7998c19e5514eda781cc20888cdb0732f81389ae Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a67e5ddfccea0776841fabe04be55c1854bf31f2 Original-Change-Id: I381dc9c5777370df2ea4c41c9e153b3277082718 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298252 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11645 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-16glados: Enable ALS connected to ECDuncan Laurie
Glados has an ambient light sensor connected to the EC which is presented to the OS as a standard ACPI0008 device. BUG=chrome-os-partner:43493 BRANCH=none TEST=test ALS functionality on glados P2 board Change-Id: I4a4913a1b407720d85f6e630b674e550bf5e36df Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: aee2b2446ca45039f1b4866feb83754861dba054 Original-Change-Id: I61f3f31ba077f63b36aa0cd9707e128e65c9ea7d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298251 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11644 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-16kunimitsu: Disable Deep S3 on kunimitsu platformSubrata Banik
This patch will reset Deep S3 flag, hence S3 will work. BUG=chrome-os-partner:40635 BRANCH=None TEST=Build and Boot Kunimitsu and verify S3 is working. Change-Id: Iad87b7a8f7bf560861a270a8c19153cfc3850bc4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fbfaa29041be49e4c39d19cb94f01ad10d12c7d5 Original-Change-Id: I5ae1738c5de1bee1ad9a45ebde074a6a378492af Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/297903 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11643 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-16Move final Intel chipsets with ME to intel/common/firmwareMartin Roth
This switches the final 4 Intel platforms that use ME firmware from using code specific to the platform to the common IFD Kconfig and Makefile. braswell, broadwell, bd82x6x (cougar point & panther point) and ibexpeak Change-Id: Id3bec6dbe2e1a8a90f51d9378150dbb44258b596 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10876 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-09-16x86: remove double link step for romstageAaron Durbin
Now that cbfstool supports XIP for romstage utilize it. This removes the double link steps with the cbfstool locate and add-stage sandwich. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted on glados. Change-Id: I1ec555f523a94dd4b15fe8186cbe530520c622c0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11670 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-16AMD Merlin Falcon: update vendorcode header files to CarrizoPI 1.1.0.0WANG Siyuan
This is required the BLOB change Icb7a4f07 "AMD Merlin Falcon: Update to CarrizoPI 1.1.0.0 (Binary PI 1.4)" This is tested on Bettong Alfa(DDR3) and Beta(DDR4). Both of the boards can boot to Windows 8.1. PCIe slots, USB and NIC work. Change-Id: Ibe141c16f8f9eac2adc5d5f45a1f354fb2a7f33c Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/11148 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2015-09-16AMD Steppe Eagle: update vendorcode header files to MullinsPI 1.0.0.AWANG Siyuan
This is required the BLOB change I67817dc59 AMD Steppe Eagle: Update to MullinsPI 1.0.0.A (Binary PI 1.1). This is tested on Olive Hill Plus. The board can boot to Windows 7. PCIe slot, USB and NIC work. Change-Id: I605df26b61bdffabd74846206ad0b7bf677ebed1 Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/11225 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-09-15riscv-trap-handling: Add functionality, prevent stack corruptionThaminda Edirisooriya
Trap handling code was bugged in that it loaded in the wrong stack pointer, overwriting the space the processor uses to talk to its host for doing device requests. Fix this issue, as well as add support for handling misaligned loads the same way we handle misaligned stores. Change-Id: I68ba3a114b7167b3212bb0bed181a7595f0b97d8 Signed-off-by: Thaminda Edirisooriya <thaminda@google.com> Reviewed-on: http://review.coreboot.org/11620 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-09-14qemu: initialize lapicGerd Hoffmann
Recently qemu stopped doing a basic lapic setup and expects the firmware to handle this properly (like on real hardware). So let's do that so coreboot works properly on qemu 2.4+. Here is the qemu commit message for the change: <quote> commit b8eb5512fd8a115f164edbbe897cdf8884920ccb Author: Nadav Amit <namit@cs.technion.ac.il> Date: Mon Apr 13 02:32:08 2015 +0300 target-i386: disable LINT0 after reset Due to old Seabios bug, QEMU reenable LINT0 after reset. This bug is long gone and therefore this hack is no longer needed. Since it violates the specifications, it is removed. Signed-off-by: Nadav Amit <namit@cs.technion.ac.il> Message-Id: <1428881529-29459-2-git-send-email-namit@cs.technion.ac.il> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> </quote> Change-Id: I022f3742475d3f3477fc838b1e2bce69287b6b8e Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/11611 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-14AGESA S3 support: Fix excessive stack usageKyösti Mälkki
Commit 300caced9 introduced stack overflow when HAVE_ACPI_RESUME is selected as the temporary storage for MTRRs is 4KiB. Change-Id: I993df6abc04436fb135822729c4931c5c7496e5a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/11633 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-11endian: fix le64toh()Aaron Durbin
This change was sitting in my git index, and I failed to push it in the original patch. Change-Id: If6f49c3c2b7908f93a99c23a80536ad5937959c7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11622 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-09-10endian: add portable endian functionsAaron Durbin
The current endian API support in coreboot doesn't follow any known API that can be shared in userland as well as coreboot proper. To that end provide big and little endian helper functions that can be used in code that can be shared within coreboot proper and userland tools. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi Change-Id: I737facab0c849cb4b95756eefbf3ffd69e558b32 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11618 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-09-10fsp1_1: provide binding to UEFI versionAaron Durbin
FSP has some unique attributes which makes integration cumbersome: 1. FSP header files do not include the types they need. Like EDKII development it's expected types are provided by the build system. Therefore, one needs to include the proper files to avoid compilation issues. 2. An implementation of FSP for a chipset may use different versions of the UEFI PI spec implementation. EDKII is a proxy for all of UEFI specifications. In order to provide flexibility one needs to binding a set of types and structures from an UEFI PI implementation. 3. Each chipset FSP 1.1 implementation has a FspUpdVpd.h file which defines it's own types. Commonality between FSP chipset implementations are only named typedef structs. The fields within are not consistent. And because of FSP's insistence on typedefs it makes it near impossible to forward declare structs. The above 3 means one needs to include the correct UEFI type bindings when working with FSP. The current implementation had the SoC picking include paths in the edk2 directory and using a bare <uefi_types.h> include. Also, with the prior fsp_util.h implementation the SoC's FSP FspUpdVpd.h header file was required since for providing all the types at once (Generic FSP 1.1 and SoC types). The binding has been changed in the following manner: 1. CONFIG_UEFI_2_4_BINDING option added which FSP 1.1 selects. No other bindings are currently available, but this provides the policy. 2. Based on CONFIG_UEFI_2_4_BINDING the proper include paths are added to the CPPFLAGS_common. 3. SoC Makefile.inc does not bind UEFI types nor does it adjust CPPFLAGS_common in any way. 4. Provide a include/fsp directory under fsp1_1 and expose src/drivers/intel/fsp1_1/include in the include path. This split can allow a version 2, for example, FSP to provide its own include files. Yes, that means there needs to be consistency in APIs, however that's not this patch. 5. Provide a way for code to differentiate the FSP spec types (fsp/api.h) from the chipset FSP types (fsp/soc_binding.h). This allows for code re-use that doesn't need the chipset types to be defined such as the FSP relocation code. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted on glados. Signed-off-by: Aaron Durbin <adubin@chromium.org> Change-Id: I894165942cfe36936e186af5221efa810be8bb29 Reviewed-on: http://review.coreboot.org/11606 Reviewed-by: Duncan Laurie <dlaurie@google.com> Tested-by: build bot (Jenkins)
2015-09-10riscv-trap-handling: Add implementation for trap calls in riscvThaminda Edirisooriya
RISCV requires the bios/bootloader to set up an interface by which it can get information about memory, talk to host devices, etc. Put implementation for spike in src/mainboard/emulation/spike-riscv/spike_util.c, and src/arch/riscv/trap_handler.c Change-Id: Ie1d5f361595e48fa6cc1fac25485ad623ecdc717 Signed-off-by: Thaminda Edirisooriya <thaminda@google.com> Reviewed-on: http://review.coreboot.org/11368 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-09-10riscv-virtual-memory: Add virtual memory setupThaminda Edirisooriya
Execution in supervisor level code in RISCV requires early setup of virtual memory. Add initialization calls in src/arch/riscv/virtual_memory.c to implement the required page table setup, and helper functions to use when jumping to the payload correctly in riscv. Change-Id: I46e080e0ee8dc13277d567dcd4bf0f61a4507b76 Signed-off-by: Thaminda Edirisooriya <thaminda@google.com> Reviewed-on: http://review.coreboot.org/11369 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-09-10intel/skylake: HAVE_UART_MEMORY_MAPPED doesn't exist anymorePatrick Georgi
... the configuration is handled further below in the file by virtue of select DRIVERS_UART_8250MEM Change-Id: Ie5481d23cd3ac3561958fd100bd05c0e4b03ce00 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11612 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-09-10skylake: Move ACPI init to SOC instead of mainboardDuncan Laurie
Move some remaining ACPI init code to the SOC instead of being done in each mainboard: - acpi_create_gnvs is now a local function - add a weak acpi_mainboard_gnvs() that can be used for mainboards to override or set additional NVS - add acpi_fill_madt() function for skylake - remove acpi_create_serialio_ssdt() function as it is unused BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I52225e8d38ed846c29d44872e3f4d6ebaf4a7e52 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c717bb418a0cb6002582572632e42b44b473f718 Original-Change-Id: I0910ac8ef25de265ae1fde16b68f6cbacedb4462 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297800 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11581 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10kunimitsu: Remove functions from acpi_tables.cDuncan Laurie
Remove the acpi_tables.c functions so these functions can move to SOC init code. The file itself is included by x86/arch code and must exist for the build to succeed. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-kunimitsu coreboot Change-Id: Ia9657f4a39c30ed7a0fd7ca4815bb2614f049911 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 93ae87f2429af5cb9d497f8b5ef8b8dffe370df4 Original-Change-Id: Ifc2f64dc1693e7bd3f5a43144d84ff033b2cfe8b Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297759 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11580 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10glados: Remove functions from acpi_tables.cDuncan Laurie
Remove the acpi_tables.c functions so these functions can move to SOC init code. The file itself is included by x86/arch code and must exist for the build to succeed. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I18e6a0be5eac053598b613b30b622c4963417919 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: af04eb112adf58578c8d2c9d3d182d4c2024abb2 Original-Change-Id: Ibe026d493c25d771357ea39e4b956629fbb799ac Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297758 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11579 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10sklrvp: Remove thermal.h and functions from acpi_tables.cDuncan Laurie
Remove thermal.h as it is not used by this board. Remove functions from acpi_tables.c so they can move to SOC. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-sklrvp coreboot (does not compile due to GPIO changes) Change-Id: I934fcc451a722f853034c0970074ee3259cc704f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7e3b5c0ed8295091d3d5761b8456f3c13c6bd8bc Original-Change-Id: If855f598e895e38c58657af17130158b2f73de81 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297757 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11578 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10intel/common: Print board ID if enabledDuncan Laurie
Read and print the board ID if it is enabled in the mainboard. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I9d50089242b3a2f461dff2b1039adc8f0347179e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f245854b30c40eda38453c1b0ae5d3b8b18c010f Original-Change-Id: Ifbd7c2666820ea146dc44fbc42bfe201cb227ff6 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297756 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11577 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10kunimitsu: Clean up mainboard code to match gladosDuncan Laurie
Clean up the intel/kunimitsu mainboard code to match the code and cleanups in glados. Many of these are trivial changes that do not impact things in a meaningful way but will make it easier to diff the code and keep the mainboards in sync. - use relative path for mainboard includes to make porting easier - fix trivial style issues to match glados so diffs are clean - pull GPIO configuration into gpio.h and use from there - remove thermal.h as it is not used on this board - make info message BIOS_INFO instead of BIOS_ERR - add support for SPD manufacturer and part number in SMBIOS BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-kunimitsu coreboot Change-Id: I64a053bcec0e0ff25a57f65659f391ab64d9a11a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e47f0fd3e00a665f07098c7ea0018d51b105d1be Original-Change-Id: Ib787f3ccc63115de48c4d608ca2bd81b58d24b6c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297752 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11576 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10kunimitsu: Select EC PD and software sync and do early initDuncan Laurie
Select the EC PD and software sync kconfig options so they are supported by the mainboard and call the EC early init function to reboot into RO in recovery mode. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-kunimitsu coreboot Change-Id: I48316df99b796c568c2481c72588b41f7147bec0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c7507470f82848062bc98da809d3c5fe1ca31998 Original-Change-Id: I822aac9c24718f226819e5d3fcc82a4024b7c5a7 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297751 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11575 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10kunimitsu: Select BOARD_ID_AUTO and clean up boardid codeDuncan Laurie
Select the BOARD_ID_AUTO kconfig option to have the coreboot tables populated with the board ID and print it early in romstage as well. Also clean up the code for it. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-kunimitsu coreboot Change-Id: I90bd85ef14543717287cbeaaab77e6c54b94df97 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1fed7de4a0650a497a240b091fd2eb99d59e1433 Original-Change-Id: I82e9d17ab618b1aae1fd874d9247b7d52b42334d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297750 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11574 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10glados: Add Board ID supportDuncan Laurie
Add support for reading board id and populating it in the coreboot tables so it is exposed to payloads. BUG=chrome-os-partner:40635 BRANCH=none TEST=boot on glados and look for reported board ID Change-Id: Iba93a913b67e3b3230aded289c2e25585dec1195 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 472cb7bc84136a1a8b284d661868e64eca4ec004 Original-Change-Id: I478dc0b2f96310b7adbd84701e70598a57306628 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297746 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11570 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10glados: Enable DPTFDuncan Laurie
- Add ACPI code for DPTF support with placeholder thresholds - Do not have custom PDL for mainboard - Do not have enable charger control for DPTF as there is already a complicated charge profile in the EC. We may still want to enable this but it would need to be tuned to work well with the EC profile. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I8cd2e0ea9c322ea92c101995e8e706f063428a45 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 55d3614441d6701a6d6f0f9d1ade94364ef2594a Original-Change-Id: Ie4587572742d3bcdba7c008fc195213ac50c9d9e Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297745 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11569 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10glados: Misc code cleanupsDuncan Laurie
- romstage.c is using gpio_configure_pads so it should really include soc/gpio.h instead of relying on it to come from "gpio.h" - consistent formatting of array initializers in pei_data.c - remove pei_data->ec_present flag as this is unused in skylake - fix printk level in spd/spd.c to be BIOS_INFO instead of BIOS_ERR - clean up acpi_slp_type usage in ec.c, remove unnecessary post codes, and cleaner console output message. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I0f76a560dc2c4197e66999752c52573ff0278430 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 67c29f900b7709b73bd0d1e0da26f96cca32828b Original-Change-Id: Ia2a320acf879fa85e9f6b06265cfe38e50e51e46 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297744 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11568 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10glados: Remove thermal.hDuncan Laurie
The constants defined in thermal.h are never used since there is no defined thermal zone. Remove it to result in less code to worry about in board ports. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: Idb716b47875b20e2110741ae9c154cc52307fbcf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 01be180b14b5381a8d339dab6c28428c7ac40c10 Original-Change-Id: Ibb710abc301b18d5632f4e01765ea0374b2fe787 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297743 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11567 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10glados: Change include headers to relative pathDuncan Laurie
To make it easier to port glados to a new board name change the include headers to use relative path name instead of including the mainboard name. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I6d184adab5b6b2df970ddd3998d3413f1330c12e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 11dd6b73f298cf4867f4a089478132d5e543ea90 Original-Change-Id: Ia8de127fb176784acbbee975e8b950f8c9824c5c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297742 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11566 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10skylake: Enable DPTF based on devicetree settingDuncan Laurie
Enable DPTF flag in ACPI NVS based on devicetree setting for the mainboard. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glaods coreboot Change-Id: I06ec6b050eb83c6a7ee1e48f2bd9f5920f7bfa51 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5728a8a37b1a50a483aa211563fb7ad312002ce5 Original-Change-Id: I08d61416c24b3c8857205cf88931f0bb2b38896c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297755 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11565 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10Skylake: Print GPIO MMIO base and pad config using gpio_debug tokenSubrata Banik
This will help development activity. Default GPIO print settings is disable, need to set gpio_debug = 1 to get GPIO MMIO dump. BUG=None BRANCH=None TEST=build coreboot and boot on Kunimitsu. Change-Id: I70c0a7bee1593cbc8e9fe1599f45bb50e3fc0f42 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 19102612ea40184307ecb0ce8b165b5b989f6911 Original-Change-Id: I4ea6349866c108382de9787bb9ed09fc78d9c770 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/296280 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11552 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10FSP: Pass FSP image base address to find_fspLee Leahy
Add a parameter to find_fsp which is the image base address. Adjust the fake stack in cache_as_ram.inc to pass in the read-only FSP image base address. In fsp_notify, pass in the read-only FSP image base address when the FSP header pointer is NULL. In find_fsp, validate the FSP binary image starting from the specified image base address. BRANCH=none BUG=None TEST=Build and run on Skylake Change-Id: Iac43c8aac8491390479af551765b514ca919928a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 592dae53f3b32694190cc5cb0fa6ca94df68aa95 Original-Change-Id: I7d6a415458a81f3b6bcdcfc9a90eceb2ac22144e Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/295593 Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11545 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-09glados: Select EC PD and call early EC initDuncan Laurie
Select the EC PD support in kconfig and call the EC early init code that will reboot into RO for recovery mode. BUG=chrome-os-partner:40635 BRANCH=none TEST=boot on glados in recovery mode Change-Id: Ifa1e2afd91a247c3830d8e705d9d34fb02239fe4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 135ef6e0e2c4864be1c25a9761e04cfe17aec51e Original-Change-Id: Iac8c092453bfbd94210462be0b377fb77410941d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297749 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11573 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-09samus: Use EC PD kconfig instead of manual PD rebootDuncan Laurie
Use the new kconfig entry to select the EC PD chip and have it be rebooted before the EC automatically insetad of being done manually by the board. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-samus coreboot Change-Id: I9e7baffec500a83af1fcf9b1e43d418489172918 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 53b086725d9d595e8eff7e1e35b9ba8db17ca199 Original-Change-Id: I9c9a7dd2ba2b78d681b448839f2c5d15ba9dfe60 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297748 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11572 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-09chromeec: Add kconfig entry for EC PD supportDuncan Laurie
Add a kconfig entry to indicate that a board has a PD chip and try to put it in RO mode before the EC during early init. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I170271de9b929fcb73d6b0e09171385a6d23f153 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 17e2d13261f4e35a8148039e324e22ec1da64b3c Original-Change-Id: I44eed5401beb1dc286e316cf0cc958da791580a5 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297747 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11571 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-09skylake: dptf: Add TSR3 thermal sensor and CPU code cleanupDuncan Laurie
- glados has more thermal sensors that could be used so add another entry in the DTPF thermal sensor ACPI code. - fix indentation block in cpu.asl. - declare \_SB.MPDL as external (it is already CondRefOf) so it does not need to be present in mainboard config if the mainboard does not want to override the default. BUG=chrome-os-partner:44622 BRANCH=none TEST=emerge-glados coreboot Change-Id: I1afe7013a24ee1215f5e968e25594f746bbdd17c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8d357437d06349039a94869b088c3c50b32933c0 Original-Change-Id: Ie87d52e735bf930a003e525cf1918789920922a5 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297335 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11558 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-09braswell: acpi: Allow DPTF thresholds to be defined at board-levelShawn Nematbakhsh
Similar to Skylake, allow braswell mainboards to override the default DPTF thresholds. BUG=chrome-os-partner:43884 TEST=Build for Strago BRANCH=Strago Change-Id: Id2574e98c444b8bf4da8ca36f3eeeb06568e78e0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 799a7006e8fcacfea8e8e0de5c99c3ce3c4ac34f Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Change-Id: If69627163237674a28fb8a26b4ce1886e5dbfc17 Original-Reviewed-on: https://chromium-review.googlesource.com/296033 Original-Commit-Ready: Shawn N <shawnn@chromium.org> Original-Tested-by: Shawn N <shawnn@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11546 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-09intel/skylake: ACPI: Clean up formatting in and fix ASL codeDuncan Laurie
Clean up the formatting in various ASL files and remove unused and/or incorrect field definitions. Add back the methods to set the USB power in S3 field in NVS as it is called by the chromium kernel at boot and is currently complaining that the method is not found. BUG=chrome-os-partner:44622 BRANCH=none TEST=emerge-glados coreboot Change-Id: I9726fb337bf53fa7dce72c5f30524b58abb4cab6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3a47eeba2792c3abed07be175034c709dbf60879 Original-Change-Id: I8e8388c9b834fd060990f8e069929ba829e29ab6 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295952 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11539 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-09x86: link ramstage the same way regardless of RELOCATABLE_RAMSTAGEAaron Durbin
Previously there were 2 paths in linking ramstage. One was used for RELOCATABLE_RAMSTAGE while the other was fixed location. Now that rmodtool can handle multiple secitons for a single proram segment there's no need for linking ramstage using lib/rmodule.ld. That also means true rmodules don't have symbols required for ramstage purposes so fix memlayout.h. Lastly add default rules for creating rmod files from the known file names and locations. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi. Inspected ramstage.debug as well as rmodules created during the build. Change-Id: I98d249036c27cb4847512ab8bca5ea7b02ce04bd Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11524 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09linking: add and use LDFLAGS_commonAaron Durbin
Add an LDFLAGS_common variable and use that for each stage during linking within all the architectures. All the architectures support gc-sections, and as such they should be linking in the same way. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi and analyzed the relocatable ramstage. Change-Id: I41fbded54055455889b297b9e8738db4dda0aad0 Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11522 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-09-09x86: link romstage and ramstage with 1 fileAaron Durbin
To reduce file clutter merge romstage.ld and ramstage.ld into a single memlayout.ld. The naming is consistent with other architectures and chipsets for their linker script names. The cache-as-ram linking rules are put into a separate file such that other rules can be applied for future verstage support. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi and dmp/vortex86ex. Change-Id: I1e8982a6a28027566ddd42a71b7e24e2397e68d2 Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11521 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09rmodule: use program.ld for linkingAaron Durbin
Bring rmodule linking into the common linking method. The __rmodule_entry symbol was removed while using a more common _start symbol. The rmodtool will honor the entry point found within the ELF header. Add ENV_RMODULE so that one can distinguish the environment when generating linker scripts for rmodules. Lastly, directly use program.ld for the rmodule.ld linker script. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi and analyzed the relocatable ramstage, sipi_vector, and smm rmodules. Change-Id: Iaa499eb229d8171272add9ee6d27cff75e7534ac Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11517 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09verstage: use common program.ld for linkingAaron Durbin
There's no reason to have a separate verstage.ld now that there is a unified stage linking strategy. Moreover verstage support is throughout the code base as it is so bring in those link script macros into the common memlayout.h as that removes one more specific thing a board/chipset needs to do in order to turn on verstage. BUG=chrome-os-partner:44827 BRANCH=None TEST=None Change-Id: I1195e06e06c1f81a758f68a026167689c19589dd Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11516 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09x86: link romstage like the other architecturesAaron Durbin
All the other architectures are using the memlayout for linking romstage. Use that same method on x86 as well for consistency. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Analyzed readelf output. Change-Id: I016666c4b01410df112e588c2949e3fc64540c2e Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11510 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09linking: move romstage and bootblock to use program.ldAaron Durbin
Instead of having separate <stage>.ld files in src/lib one file can be used: program.ld. There's now only one touch point for stage layout. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Analyzed readelf output. Change-Id: I4c3e3671d696caa2c7601065a85fab803e86f971 Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11509 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09x86: link ramstage like the other architecturesAaron Durbin
All the other architectures are using the memlayout for linking ramstage. The last piece to align x86 is to use arch/header.ld and the macros within memlayout.h to automaticaly generate the necessary linker script. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Analyzed readelf output. Change-Id: I012c9b88c178b43bf6a6dde0bab821e066728139 Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11508 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09linking: lay the groundwork for a unified linking approachAaron Durbin
Though coreboot started as x86 only, the current approach to x86 linking is out of the norm with respect to other architectures. To start alleviating that the way ramstage is linked is partially unified. A new file, program.ld, was added to provide a common way to link stages by deferring to per-stage architectural overrides. The previous ramstage.ld is no longer required. Note that this change doesn't handle RELOCATABLE_RAMSTAGE because that is handled by rmodule.ld. Future convergence can be achieved, but for the time being that's being left out. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Change-Id: I5d689bfa7e0e9aff3a148178515ef241b5f70661 Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11507 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-09-09x86: provide minimum alignment for romstageAaron Durbin
The current way the XIP address of romstage is calculated is by doing a 'cbfstool locate' using a bin file of romstage linked at address 0. That address is then used for re-linking romstage at the address spit out by cbfstool. Currently, the linker actually sets minimum alignment on the text sections as 32 bytes, but it doesn't actually honor that value. Instead, provide a minimum alignment for romstage so as not to fight the linker. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built asus/kfsn4-dre. Confirmed ROMSTAGE_BASE == gdtptr. Change-Id: Id6ec65d257df9ede78c720b0d7d4b56acfbb3f15 Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11588 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09rules.h: add fall through where no ENV_<STAGE> is setAaron Durbin
There are cases where rules.h can be pulled in, but the usage is not associated with a particular stage. For example, the cpu/ti/am335x build creates an opmap header. That is a case where there is no stage associated with the process. Therefore, provide a case of no ENV_>STAGE> being set. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Analyzed readelf output. Change-Id: Ia9688886d445c961f4a448fc7bfcb28f691609db Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11513 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09drivers/pc80: Do not initialize PS2 keyboard by defaultAlexandru Gagniuc
The most common payloads do not need this set, so optimize for the common case. Change-Id: I2e5b68d74e9b91b41bbbcffc17d31d5c1bb38fd4 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8599 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-09-09intel/model_2065x/Kconfig: Don't use LAPIC_MONOTONIC_TIMERMartin Roth
The LAPIC_MONOTONIC_TIMER symbol doesn't do anything in the code unless UDELAY_LAPIC is selected. Since this chip uses UDELAY_TSC, LAPIC_MONOTONIC_TIMER generates a Kconfig warning and should be removed. Change-Id: I5caa60ca7ab9a24d25c184c85184f9492b453706 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11342 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-09-09x86: remove unused sections from romstage.ldAaron Durbin
Now that the only source of ELF sections for romstage are from directly included .inc files or ROMCC generated inc files the subsection globs can be removed. i.e. Remove .rom.data.* and .rom.text.* listings. Lastly, put the .rom.data section directly after the .rom.text. They are by definition read-only and they are generated from the same place. BUG=chrome-os-partner:44827 BRANCH=None TEST=Spot checked !ROMCC and ROMCC boards. Confirmed only .rom.text .rom.data sections exist. Change-Id: Id17cf95c943103de006c5f3f21a625838ab49929 Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11505 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09x86: add romstage.S to bind program flow and orderingAaron Durbin
The build system was previously determining the flow of the romstage code by the order of files added to the crt0s make variable. Those files were then concatenated together, and the resulting file was added to the build dependencies for romstage proper. Now romstage.S is added that can be built using the default object file rules. The generated romstage.inc is pulled in by way of an #include in the newly added romstage.S. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built vortex, rambi, and some asus boards. compared readelf -e output. Change-Id: Ib1168f9541eaf96651c52d03dc0f60e2489a77bd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11504 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09x86: don't create MAINBOARDDIR/romstage.inc for !ROMCC boardsAaron Durbin
Previously, the x86 romstage build process was unconditionally creating a romstage.inc and adding it to crt0s. This step is inherently not necessary in the !ROMCC case becaue the romstage.inc was created by the compiler outputting assembler. That means MAINBOARDDIR/romstage.c is truly a C environment that requires some sort of assembler stub to call into (cache_as_ram.inc from the chipset dirs). Therefore, remove this processing. The result is that MAINBOARDDIR/romstage.c can use the normal build steps in creating an object and linking. The layout of romstage.elf will change but that's only from a symbol perspective. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built multitude of boards. Compared readelf -e output. Change-Id: I9b8079caaaa55e3ae20d3db4c9b8be04cdc41ab7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11503 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09x86: bootblock: remove linking and program flow from build systemAaron Durbin
The build system was previously determining the flow and linking scripts bootblock code by the order of files added to the bootblock_inc bootblock-y variables.Those files were then concatenated together and built by a myriad of make rules. Now bootblock.S and bootblock.ld is added so that bootblock can be built and linked using the default build rules. CHIPSET_BOOTBLOCK_INCLUDE is introduced in order to allow the chipset code to place include files in the path of the bootblock program -- a replacement for the chipset_bootblock_inc make variable. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built vortex, rambi, and some asus boards. Change-Id: Ida4571cbe6eed65e77ade98b8d9ad056353c53f9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11495 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-08cpu: fix cpu_microcode classAaron Durbin
There's no reason defining another class compiler which overrides the first one. The microcode files are just built into a binary and added to cbfs. There's no reason to change compilers. Change-Id: Icb47d509832e7433092a814bad020f8d66f2a299 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11596 Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Tested-by: build bot (Jenkins)
2015-09-08rk3288: Allow board-specific APLL (CPU clock) settingsDavid Hendricks
This changes the API to rkclk_configure_cpu() such that we can pass in the desired APLL frequency in each veyron board's bootblock.c. Devices with a constrainted form facter (rialto and possibly mickey) will use this to run firmware at a slower speed to mitigate risk of thermal issues (due to the RK808, not the RK3288). BUG=chrome-os-partner:42054 BRANCH=none TEST=amstan says rialto is noticably cooler (and slower) Change-Id: I28b332e1d484bd009599944cd9f5cf633ea468dd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d10af5e18b4131a00f202272e405bd22eab4caeb Original-Change-Id: I960cb6ff512c058e72032aa2cbadedde97510631 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297190 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/11582 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08skylake: igd: clean up igd.cDuncan Laurie
Remove unused constants, remove unused headers, and fix the use of acpi_slp_type variable. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I2d041f61605e0fc96483a1e825ab082668a0fa44 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bc57147cb7fa3c38169fcdd62cc9e35d8058414a Original-Change-Id: If411ad50650e6705da7de50f5be8b1d414766a8c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297741 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11564 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08braswell: Tristate CFIO 139 and CFIO 140Ravi Sarawadi
CFIO 139 and CFIO 140 are consuming ~5 during stanndby. The reason for this leakage is internally it is configured to 1K PU. So there is leakage of ~2mW in standby. Total impact ~2.5 mw in Srandby. Configure these CFIOs as tristate for ~5mW power saving at platform level. BRANCH=none TEST=PnP Team to verify that the CFIO's are tri-stated. Change-Id: I6d78d2ccc08167b2cd6fc3405cfcb5c69a77d4b8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f11eb98cb36c504dfebe6f0fa53e9af120d21f24 Original-Change-Id: Ib309ad0c6abffa4515fdf2a2f2d9174fad7f8e8d Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com> Original-Signed-off-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292863 Original-Commit-Ready: Rajmohan Mani <rajmohan.mani@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11556 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08drivers/pc80/tpm: Set "Found TPM" message to BIOS_INFO levelDuncan Laurie
Having no supplied printk level makes this info message printed at all levels and so it shows up when booting with DEFAULT_CONSOLE_LOGLEVEL=3. BUG=chrome-os-partner:40635 BRANCH=none TEST="USE=quiet-cb emerge-glados coreboot" Change-Id: I6c52aafbe47fdf297e2caeb05b4d79a40a9a4b9d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e6cffc6d5a9fcda60a04f8a31f2b2ffe4b620c77 Original-Change-Id: Ie6715d15f950d184805149619bebe328d528e55a Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297336 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11559 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08veyron: Unify identical mainboardsJulius Werner
This patch removes a lot of code duplication between the virtually identical Veyron Chromebook variants by merging the code into a single directory and handling the different names solely within Kconfig. This also allows us to easily add all the other Chromebook variants that have only been kept in Google's firmware branch to avoid cluttering coreboot too much, making it possible to build these boards with upstream coreboot out of the box. The only effective change this will have on the affected boards is removing quirks for early board revisions (since revision numbers differ between variants). Since all those quirks concerned early pre-MP revisions, I doubt this will bother anyone (and the old code is still available through the Google firmware branch if anyone needs it). It will also expand a recent fix in Jerry that increased an LCD power-on delay to make it compatible with another kind of panel to all boards, which is probably not a bad idea anyway. Leaving all non-Chromebook boards as they are for now since they often contain more extensive differences. BRANCH=None BUG=None TEST=Booted Jerry. Change-Id: I4bd590429b9539a91f837459a804888904cd6f2d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 10049a59a34ef45ca1458c1549f708b5f83e2ef9 Original-Change-Id: I6a8c813e58fe60d83a0b783141ffed520e197b3c Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/296053 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11555 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08kunimitsu: Modify DQ/DQS mappingMike M Hsieh
Modify DQ Byte Map and DQS Byte Swizzling to match up with design BUG=chrome-os-partner:44647 BRANCH=none TEST=System boot up and pass memory initialization Signed-off-by: Mike Hsieh <mike.m.hsieh@intel.com> Change-Id: I2018b9e6f8b557689d15acfe1f9404a9de5ae3bb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7d0a30d4b12bf4dc588d525399a8d223ff35e3de Original-Change-Id: I6001c853e4c5540717acf813e039c5c5dbe14c78 Original-Reviewed-on: https://chromium-review.googlesource.com/295518 Original-Commit-Ready: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11551 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08Skylake:Set DISB inside romstage after mrc initDhaval Sharma
Set DISB inside romstage right after successful mrc init such that any reset events afterwards can take fast boot path and in turn achieve better boot performance BRANCH=NONE BUG=chrome-os-partner:43637 TEST=Built for kunimitsu and tested DISB is set correctly and fast boot path is taken. Change-Id: I230ff76287f90c5d3655a77bbaca666af37c4aae Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7bdc6900012c99187bb90904df18c2b3f9e52c61 Original-Change-Id: Ie08b4a4f29a7c5cb47e508bc59a5e95f8e36fa00 Original-Signed-off-by: Dhaval Sharma <dhaval.v.sharma@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/295509 Original-Commit-Ready: dhaval v sharma <dhaval.v.sharma@intel.com> Original-Tested-by: dhaval v sharma <dhaval.v.sharma@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11550 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08skylake: Clean up chip.hDuncan Laurie
Remove config options that do not apply and are unused on skylake. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: Ic410f8e6b8ecc06d6f4fb1f229017df18c6045f3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3224b89e310909c2836ef2c669c6b2ee826b1b28 Original-Change-Id: I2b4fe85f78480eac5635e78ce4e848f73967bd27 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297740 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11563 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08kunimitsu: Clean up devicetree.cbDuncan Laurie
Fix the PCI device list comments to be consistent between mainboards and remove unused and incorrect register settings. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-kunimitsu coreboot Change-Id: Ib1c0eb80c57661502a4d4cfb4622a34effaa1c4a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 17c4f0d306194e7086f39f7ab560841999c318d8 Original-Change-Id: Ia1c138e52cbc3e81c0d12aa97d7f564e723d61f9 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297339 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11562 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08glados: Clean up devicetree.cbDuncan Laurie
Clean up the PCI device list comments to be consistent between the skylake mainboards. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I0080ab21db006365f34995db06480dae68ac547d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fa21f77cbaafbc9ca0b98d6951df92c4349fa28d Original-Change-Id: Ie70f94dcc12da141d82b4445643cc0cbe08bb766 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297338 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11561 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08sklrvp: Clean up devicetree.cbDuncan Laurie
Remove devicetree.cb settings that do not apply to skylake so they can be removed from chip.h and clean up the pci device comments and add missing devices. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-sklrvp coreboot Change-Id: I232bd62853685bdcda771e3cbaba2d8ee7437b81 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a22e1fa56c68b06192acbeeb5c76862d84b8f509 Original-Change-Id: I61f0581069d87ab974b0fffa6478b44a71bdd69b Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297337 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11560 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08kunimitsu: Fix incorrect comment format in devicetree.cbDuncan Laurie
The devicetree.cb compiler can't handle C style /**/ comments, they need to be shell-style #. Due to a last minute formatting change in my commit to enable USB ports this broke the kunimitsu build. BUG=chrome-os-partner:44662 BRANCH=none TEST=emerge-kunimitsu coreboot Change-Id: I7a77f0f51345f779fcae43338cdc078bc91bb51c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6454b377f865ec3d4e426fce3259f4df5d513ef5 Original-Change-Id: I19bde397018890db37257b55d0481e0c9f3a41f2 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/296302 Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11554 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08glados: Fix incorrect comment format in devicetree.cbDuncan Laurie
The devicetree.cb compiler can't handle C style /**/ comments, they need to be shell-style #. Due to a last minute formatting change in my commit to enable USB ports this broke the glados build. BUG=chrome-os-partner:44662 BRANCH=none TEST=emerge-glados coreboot Change-Id: I46ee4e5a94d61eefbd2c9a1ba3cafcb6a9e7d71b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8fa92f77b3ef13ede1029292d886351ab5ed87d2 Original-Change-Id: Ibff02a4fd6132def81006a2c6502d34bd4b72823 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/296301 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11553 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08kunimitsu: Disable unused USB portsDuncan Laurie
Enable only the USB ports that are connected on-board or to an external port, all others will be disabled. BUG=chrome-os-partner:44662 BRANCH=none TEST=emerge-kunimitsu coreboot, change verified in schematic but not tested Change-Id: I909a6fab553bba829349dd08fa9cc3f26e5adeb2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1b0ce28d093e3b12273d7e0f56b47fb5b13d712f Original-Change-Id: I0c4b7de6e559595efa97d756e43f8398feccdffd Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/296036 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11549 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08glados: Disable unused USB portsDuncan Laurie
Enable only the USB ports that are connected on-board or to an external port, all others will be disabled. BUG=chrome-os-partner:44662 BRANCH=none TEST=build and boot on glados, ensure expected USB ports still work Change-Id: I8c999e3b17478effc39cf078f8420f63413d091b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b86268c70f86991f8c2cdd6763f8efe2ce7f9163 Original-Change-Id: I2fce2c401d07639892c4a0c01527173d3f0b2557 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/296035 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11548 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08skylake: Apply USB2 and USB3 port enable/disable settingsDuncan Laurie
The USB port enable/disable settings were never getting applied to the UPD configuration and so were not getting used by FSP. BUG=chrome-os-partner:44662 BRANCH=none TEST=build and boot on glados Change-Id: I13d4eb901215308de4b59083339832d29ce0049f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4fd83caa8087cc349fa933eafac98c2563f501a4 Original-Change-Id: Ia5fa051782eeb837756a14aecb4aa626d25b2bdb Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/296034 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11547 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08skylake: Remove dead codeLee Leahy
Remove dead code not called by any part of coreboot. BRANCH=none BUG=None TEST=Build and run on skylake Change-Id: I3d457a196d12d03340bceb444d1d6c95afef13df Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 58ea135813afeef773f37023fda58f36d544beef Original-Change-Id: Id8f4591f20d41f875348c6583618bbcaaf9d9a3a Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/294953 Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11544 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08skylake: refactor flash_controller codeAaron Durbin
There's no need to add any typedefs nor guard code with ENV_ROMSTAGE. The linker will garbage collect unused functions. Additionally there were a few errors in the code including the operation mask wasn't wide enough to clear out old operations as well as component size decoding was incorrect. The big difference in the code flow is that the operation setup is now in one place. The stopwatch API is also used in order to not open code time calculations. BUG=chrome-os-partner:42115 BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted. Suspended and resumed. event log is populated for all. Change-Id: I0ddd42f0744cf8f88da832d7d715663238209a71 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9893fe309104c05edfb158afda6bb029801c0489 Original-Change-Id: I6468f5b9b4a73885b69ebd916861dd2e8e3746b6 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295980 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11543 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>