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The current HID "RX6110SA" does not comply with the ACPI spec in terms
of the naming convention where the first three caracters should be a
vendor ID and the last 4 characters should be a device ID. For now
there is a vendor ID for Epson (SEC) but there is none for this
particular RTC. In order to avoid the reporting of a non ACPI-compliant
HID it will be dropped completely for now.
Once Epson has assigned a valid HID for this RTC, this valid HID will be
used here instead.
Change-Id: Ib77ffad084c25f60f79ec7d503f14731b1ebe9e2
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47706
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It was supposed to return true for both S2 and S3, but
level S2 was never stored in acpi_slp_type or otherwise
implemented.
Change-Id: Ida0165e647545069c0d42d38b9f45a95e78dacbe
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Id4728b637c784ee2bff7b175e13f4c10419b7f1b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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By renaming the AMD SOC common Kconfig file the wildcard to source all
AMD SoC-specific Kconfig files won't match to it and it can be sourced
after all SoC-specific Kconfig files in the sub-directories are sourced.
This change allows adding new SoCs without having to edit the soc/amd
Kconfig file.
Change-Id: Iaaa5aad23eb6364d46b279101f3969db9f182607
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Extend the Kconfig option text of L140CU with L141CU since the hardware
of both is equal.
Change-Id: If0e5061fc345208688a678a4cdf7c5ecaf47c17d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: I531865416b1bf9c5a73c809590059e7d7c8f373a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47715
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Volteer has a new Audio option in FW_CONFIG. This patch adds
support for it and when enabled, programs GPIO pins for I2S
functionality.
BUG=b:171174991
TEST=emerge-volteer coreboot
Change-Id: I85bc37980957a3fb6c795858a4e4f44f3e3cc332
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Ambassador is similar to puff. This change matches the
PcieRpSlotImplemented configuration with Puff's, originally made for
Puff in https://review.coreboot.org/c/coreboot/+/39986.
Signed-off-by: Matt Ziegelbaum <ziegs@google.com>
Change-Id: I5b6246f58c10e03a0d02278ad3621ded39bb6d6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Fan table: provided by the ODM (see attachment in bug) based on
measurements with EVT unit.
BUG=b:173134210
TEST=flash to DUT
Change-Id: I9f727f0f7e2eb7fe70385ebc843558d51e1860c5
Signed-off-by: Matt Ziegelbaum <ziegs@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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HPD_1: A19 -> E14
HPD_2: A20 -> A18
Change-Id: Idf3c8f4931bf8364bb9216a9369df7e05dcde047
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I4499c383e63cd12a0fc11efd94ef396d9ad23789
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Different models within family 17h have different PCI IDs for their PCIe
GPP port and internal bus devices.
Change-Id: I386df908ce5451b4484be2a2e4a9018c3d47d030
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Different models within family 17h have different PCI IDs for their data
fabric PCI devices.
Change-Id: I44f8d32c950710e962dc519495b08c92f357ed20
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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The code uses PCI_DEVICE_ID_AMD_17H_MODEL_101F_NB instead;
Change-Id: Ia88550d377643741f78ff068e57d6a2d783306f3
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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The code that uses the GPU device ID uses the correct ATI vendor ID, but
the description wrongly used AMD as vendor. In the AMD APUs the GPU PCI
device and the corresponding audio controller use the ATI PCI vendor ID
while all other PCI devices in the SoC use the AMD PCI vendor ID.
Also move the two entries in a separate section right below the one they
were in.
Change-Id: Ia0b5bd4638f5b07c487f223321872563b36337e9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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SOC_AMD_COMMON needs to be selected to be able to select
SOC_AMD_COMMON_BLOCK which only includes the Kconfig files from the
function block sub-folder. Removing SOC_AMD_COMMON_BLOCK and the
corresponding Kconfig file and make SOC_AMD_COMMON include all Kconfig
files from the sub-folders simplifies this a bit.
Change-Id: I9068d57a80bdc144e73d2b8c00e7b2cae730d4b6
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Drop extra function in the middle and adjust the post_code()
to happen right before jump to wakeup vector.
Change-Id: I951c3292f5dbf52a58471da9de94b0c4f4ca7c20
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42613
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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SMSC/Microchip 1036 can be strapped to 4E/4D and 164E/164D so make
source code support 16 bits addressing.
Change-Id: I2bbe6f5b6dbd74299b34b0717e618dc736e7ad6f
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Configure the pins for SD to msdc1 mode and change the driving
value to 8mA. Enable VCC and VCCQ power supply for SD.
Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
Change-Id: I11151c659b251db987f797a6ae4a08a07971144b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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SD Card driver needs to access two regulators - MT6360_LDO5 and
MT6360_LDO3. These two regulators are disabled by default.
Two APIs are implemented:
- mainboard_enable_regulator: Configure the regulator as enabled/disabled.
- mainboard_regulator_is_enabled: Query if the regulator is enabled.
BUG=b:168863056,b:147789962
BRANCH=none
TEST=emerge-asurada coreboot
Change-Id: I391f908fcb33ffdcccc53063644482eabc863ac4
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46687
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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google_chromeec_regulator_enable is for enabling/disabling
the regulator. google_chromeec_regulator_is_enabled is for
querying if the regulator is enabled.
BUG=b:168863056,b:147789962
BRANCH=none
TEST=emerge-asurada coreboot
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Ia804242042b0026af19025a0c4a74b3ab8475dab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Currently, five regulator controls are implemented for DRAM
calibration and DVFS feature.
The regulators for VCORE and VM18 are controlled by MT6359.
The reguatlors for VDD1, VDD2 and VMDDR are controlled by MT6360
via EC.
BUG=b:147789962
BRANCH=none
TEST=verified with DRAM driver
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Id06a8196ca4badc51b06759afb07b5664278d13b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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MT6315 is a buck converter for Mediatek MT8192 platform.
Reference datasheet: MT6315 datasheet v1.4.2.pdf, RH-D-2019-0616.
BUG=b:155253454
BRANCH=none
TEST=boot asurada correctly
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: I6b47473ee5d56a197bd21d4ab9b539d9663b6636
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45400
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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MT6359P is a PMIC chipset for Mediatek MT8192 platform.
Reference datasheet: MT6359_PMIC_Data_Sheet_V1.5.docx, RH-D-2018-0205.
BUG=b:155253454
BRANCH=none
TEST=boot asurada correctly
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: I62f69490165539847b8b7260942644533b15285b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45399
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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MT8192 uses power management interface (PMIF) to access pmics by spmi
and spi, so we add pmif driver to control pmics.
BUG=b:155253454
BRANCH=none
TEST=boot asurada correctly
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: I32fc28f72d9522133baa06f9d67c383f814d862c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45398
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This function is no longer required to be implemented since
EC/AUXFW sync was decoupled from vboot UI. (See CL:2087016.)
BUG=b:172343019
TEST=Compile locally
BRANCH=none
Signed-off-by: Joel Kitching <kitching@google.com>
Change-Id: I43e8160a4766a38c4fa14bcf4495fc719fbcd6c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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The current CSE firmware update implementation adds CSE RW binary to
FW_MAIN_A/B and this increases the boot time due to the size increase
of these regions leading to higher loading and hashing time.
To mitigate this issue, CSE RW binary is moved from FW_MAIN_A/B to new
region, ME_RW_A/B under RW_SECTON_A/B, and this updates the flashmap to
add ME_RW_A/B region for CSE RW binary.
BUG=b:169077783
TEST=build with cse rw binary, flash and verify volteer2 boots to OS.
Verify me_rw binary is added to ME_RW_A/B region.
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: I87da3824933ed2dd8e8ed0fed8686d2a3527faea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46431
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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CSE RW blob which will be used by coreboot to update CSE's RW partition,
is packed part of FW_MAIN_A and FW_MAIN_B. This will increase the size of
FW_MAIN_A and FW_MAIN_B. So, accordingly load and hash calculation of
FW_MAIN_A (or FW_MAIN_B) increases during verstage. It increases the boot
time by around 300ms.
The patch address the boot time by pulling CSE RW blob outside of
FW_MAIN_A and FW_MAIN_B. So, it creates new FMAP region within
RW_SECTION_A and RW_SECTION_B and adds CSE RW blob in the new regions
(ME_RW_A and ME_RW_B) as a CBFS file.
Boot Time Measurement details when CSE RW blob is added in the
ME_RW_A and ME_RW_B.
--------------------------------------------------------
| Platform | Old Boot Time | New Boot Time |
--------------------------------------------------------
| JSL | 1.3s | 1.06s |
--------------------------------------------------------
| TGL | 1.63s | 1.36s |
--------------------------------------------------------
Changes:
1. Makefile change to accommodate CSE RW blob into ME_RW_A/ME_RW_B
2. Kconfig change to define CBFS name and default file name for RW blob
metadata.
3. CSE Lite Driver
BUG=b:169077783
TEST=Verified on JSL & TGL platforms
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: If043c9cb99fb822b62633591bf9c5bd75dfe8349
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This patch modifies flash layout to add ME_RW_A/B to add
the CSE RW blob and also enable the CSE RW update feature for
JSLRVP
BUG=b:169077783
TEST= Built for jslrvp. Verified that CSE RW and metadata files
are included in cbfs.
Change-Id: I13baa317a06d00cec0337f08754892c7c8737f5d
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Existing implementation adds the CSE RW update binary to FW_MAIN_A/B
regions and this has significant impact on boot time due to the
increase in the size of these regions leading to higher loading
and hashing time.
This patch modifies flash layout to add new ME_RW_A/B fmap regions
in the RW_SECTION_A/B.
BUG=b:169077783
TEST= Built for dedede. Verified that CSE RW binary is added to the
CSE_RW_A/B fmap region.
Change-Id: I23a3e22a569488b39beb4d12f5b6309c7c742992
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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In the existing implementation CSE RW metadata file is generated by
scripts and to avoid incompitable issues between coreboot and the
scripts this patch adds the follwing changes,
* Move the metadata generation to the coreboot Makefile.
* Add CBFS component type struct to create a metadata file during
the compile time.
* Extract the CSE RW version from SOC_INTEL_CSE_RW_VERSION config
and update the major, minor, hotfix and build versions using the
compile time flags.
* Compute the hash of CSE RW binary in hex format using the openssl
and use the HASH_BYTEARRAY macro to convert the 64 character hex
values into the array.
* Add the me_rw.metadata cbfs file to FW_MAIN_A and FW_MAIN_B
regions.
BUG=b:169077783
TEST= Built for dedede. Verify that metadata file was generated
and added to the FW_MAIN_A/B. Extracted it using cbfstool and
verfied that metadata was generated properly.
Change-Id: I412581400a9606fa17cf4398faffda923f07b320
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add the Kconfig to enable the CSE FW Update feature and also to
ensure all the configs are set by the mainboards to enable this
feature.
This config by default disables the CSE FW update feature for JSL
and TGL platforms. It will be enabled after splitting and including
the CSE RW and CSE RW metadata blobs in the CBFS.
BUG=b:169077783
Change-Id: I12810031224f79aba8a4057725ae0ed5a9b36d7e
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This patch adds a kconfig SOC_INTEL_CSE_RW_VERSION to pass the
CSE RW firmware version from the mainboard. This will be extracted
by makefile to update the cse_rw_metadata structure.
Right now the required tool to extract the CSE RW version from
the blob is still under development and after the official version
of the tool is released, version will be extracted by parsing the
CSE RW blob.
BUG=b:169077783
Cq-Depend: chrome-internal:3402224, chrome-internal:3397863,
chromium:2473603, chromium:2473603, chromium:2535950
Change-Id: I62691ee3ede7d4cd21f821381f5d1519f9061fd9
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47430
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add Elan and Goodix touchscreen settings.
BUG=b:169813211
BRANCH=None
TEST=build metaknight firmware
Change-Id: Ib2acd31a8076533c3b927d37127e7d27bac0bb57
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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SKX FSP doesn't support X2APIC setup, but CPX does. The CPX DMAR
table needs the X2APIC opt out flag set. This fixes the hang loading
a kexec'd kernel. The change is easy to see in the coreboot output:
[DMA Remapping table] Flags: 0x3
or in the DMAR ACPI table.
Change-Id: Iec977c893b70e30875d9a92f24af009c1e90389e
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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When the system shuts down, turn the fingerprint sensor off. This sets
the GPIOs correctly for the next boot. The fingerprint sensor was
previously left on, and was just powering down when the rails went low.
On suspend, the fingerprint sensor stays awake and puts itself in a low
powerstate mode based on the SLP_Sx_L pin states.
BUG=b:171837716
TEST=Fingerprint sensor still works after S3, GPIO state on the boot
following a shutdown is low.
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I3837b58372d8f4a504535e76bd21c667d68f8995
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47311
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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"Die()" needs <console/console.h>.
Change-Id: I250988d77b0b0a093a1d116bea44a0cbb84189dd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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"printk()" needs <console/console.h>.
Change-Id: Iac6b7000bcd8b1335fa3a0ba462a63aed2dc85b8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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BUG=b:172843935
BRANCH=coral
TEST=emerge-coral coreboot chromeos-bootimage
Signed-off-by: James Chao <james_chao@asus.corp-partner.google.com>
Change-Id: I70195acc33218d3ad4c77acfdbc8f6ed93ab144e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47382
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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At this point, the zork platform will only use psp_verstage, so remove
the VBOOT_STARTS_IN_BOOTBLOCK option and set code for VBOOT_STARTS-
BEFORE_BOOTBLOCK to always be used.
TEST=Build & Boot Morphius
BRANCH=Zork
BUG=b:172848137
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I30d90fe82c37966a860b52c07a3550dcecf8d19d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This partially reverts commit 67910db907fb3d5feacdbfaa40952a88f673795a.
The symbol X86_RESET_VECTOR continues to live, for the time being,
under soc/amd/picasso.
Change-Id: Ib6b2cc2b17133b3207758c72a54abe80fc6356b5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This change drops the inclusion of entry16.ld and reset16.ld and
instead adds the content of those files directly in memlayout_x86.ld
in amd/picasso. This is done to allow the work for top-aligning
bootblock to happen independent of Picasso layout. Once that is
complete, Picasso layout can be re-evaluated to see if it can make use
of the common bootblock linker file includes.
TEST=Verified that coreboot.rom generated using --timeless is the same
with and without this change for trembyle.
Change-Id: Ib1218b24a06d0f69b856fb21458a6183fd21fcbc
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The current I2C2 bus frequency is 344 kHZ, which does not meet the spec. This change updates scl_lcnt, scl_hcnt, sda_hold value for I2C2 to bring
the bus frequency closer to 400 kHz.
BUG=b:153588771
TEST=Verified that I2C2 frequency is 380 kHz.
Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com>
Change-Id: I96fa5ed586de41324733ac7537b6bd73f39fc176
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47558
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add G2Touch touchscreen support for bobba.
BUG=b:171636614, b:169730666
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage, and check touchscreen
work.
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Ia361a56c050d7cbd7325b3c09fc34d8707441cc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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In the file uintptr_t that is defined in stdint.h and struct device that
is defined in device/device.h are used, so include them directly to
avoid having to rely on them being included in the file that includes
this header file.
Change-Id: I9893619924d45e5690a5cfc65252ace4cb7f1486
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Add a NULL check and only skip setting the default operations
if `.ops` was set by a driver. It's fairly unlikely that some-
body adds a driver and forgets the `.ops` pointer. So this is
mostly to increase readability: Nobody should have to wonder
if we're missing a NULL-check.
The condition is moved out of the loop to reduce indentation
levels. Alternatively, we could jusk skip drivers that don't
have `.ops` set (i.e. continue the loop).
Change-Id: I5dcc05ebb092fb9c4be929c81ea2b05a10b1311b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46297
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Devices of class type "system" are arbitrary devices and it's not clear
which of them need bus mastering. Therefore, enable bus mastering
conditionally based on Kconfig option PCI_ALLOW_BUS_MASTER_ANY_DEVICE.
Change-Id: Ia04e83606a0a081c0758ec59e52627aa1dbd2622
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: Ic7cacce28f473dda76ca203016dbb8e00149a990
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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While Ada makes pointers harder to use, it is still useful to provide a
pointer type for use in C interfaces.
Change-Id: I3a30ef0147a459ba82c79a1f85a3d3fb97b0f3a1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47393
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This Kconfig option was just added incorrectly, so would never add
the verstage.c file.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I4c39dca9d429ed786ea42c0d421d6ee815e8c419
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The CONFIG_TPM_I2C_BURST_LIMITATION was never added, so this has never
been turned on. The Kconfig linter generates three warnings about this
block:
Warning: Unknown config option CONFIG_TPM_I2C_BURST_LIMITATION
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I53fa8f5b4eac6a1e7efec23f70395058bad26299
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47367
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is a trivial patch to fix some comments that were generating
notes in the kconfig lint test.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I26a95f17e82910f50c62215be5c29780fe98e29a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47366
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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- Write ACPI DMAR Table if VT-d is enabled.
- The entries are defined to follow FSP settings.
Change-Id: I263b03b96280599266d4c5e193583ecdfe9697b7
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25446
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I2b8c54fd3851d1c2a9f4c3c36828922067bec79f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47071
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Reusing the 'size' variable for a different purpose later on in the
function makes the code harder to read.
Change-Id: Iceb10aa40ad473b41b7da0310554725585e3c2c2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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If the stub size would be larger than the save state size, the stagger
points would overlap with the stub.
The check is placed in the stub placement code. The stub placement
code is called twice. Once for the initial SMM relocatation and for
the permanent handler in TSEG. So the check is done twice, which is
not really needed.
Change-Id: I253e1a7112cd8f7496cb1a826311f4dd5ccfc73a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47069
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Put names and expand comments for some parts of the code.
Change-Id: If1f83bf113ef08469768a9e4dd13819f76633f18
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: I8271911695f41ef7cac1bb228309af0568e5bb0c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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There's no need to use size_t to store a boolean.
Change-Id: I0069fa8d75583dc34b402004d753220943406a04
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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The only reason to write the MR values to the training result registers
is for EV (Electrical Validation) usage. The hardware doesn't need it.
Tested on Asus P8H61-M PRO, still boots.
Change-Id: I808174494729453f4ebcaa13258d735faae68d72
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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It is only used once, and can thus be moved to the same file.
Change-Id: I4ee0621449da7fa1970a475d5a2f6e66546357ea
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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It is usually written to right after programming a pattern, because its
lower byte contains the number of cachelines of the programmed pattern.
The other cases merely reset the WDB data write and compare pointers.
Change-Id: I97196d404bf70542db28499e0d2e24b7cdab07b6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Add information regarding the privacy pin on the overridetree and gpio.
BUG=b:172807539
Change-Id: Ic1bfa63e35a16d71a26adc3ec07b1ba36e6dc168
Signed-off-by: Ricardo Ribalda <ribalda@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47362
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a soc specific callback for getting the IIO IOAPIC enumeration ID.
Tested on ocp/deltalake.
Change-Id: Id504c2159066e6cddd01d30649921447bef17b12
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Change-Id: Id1a0e02174456bb25df0721cfd3865645641a01a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Make the code follow the coding style.
Replace 8 spaces by TAB
Move comment between the corresponding #if #endif
Tested on Facebook FBG1701
Change-Id: I55cb071eb58a24f78e231cd36e6575fd13817e86
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I50390f66d9570eb0fd703e3ad8a2735125d76b61
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47566
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create the lantis variant of the waddledee reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.2.0).
BUG=b:171546871
BRANCH=dedede
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_LANTIS
Change-Id: Ie3d15a687b870afc7d8bbeb6b5cab0792650da31
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Reduce PRERAM_CBMEM_CONSOLE buffer from 63K to 19K and reserve
0x00115000 ~ 0x0011ffff for MCUPM.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Ic82a194736eecd7bdc8df80b493290090a2ccba5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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WRDD table is needed for Intel WiFi module to enable SAR function.
BUG=b:173066178
BRANCH=zork
TEST=dump ACPI and check WRDD exist with Intel WiFi module.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I9fd6fd19ed188f7ab91faab9e2599b9b09ca5b22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
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1. Enable panel stop GPIO in ramstage
2. generic.reset_delay_ms change to 30
BUG=b:171365316
Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Change-Id: I90ca39312252c668da6298183e598392bc9f9f28
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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Update memory array handle for SMBIOS type 19.
TEST=Execute "dmidecode -t 19" to check if memory array handle is correct.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I49078b870bac3c6162913b91651ec09632800f1f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add a function that initializes GPIOs based on the sleep type that
the system is coming back from. This allows initialization of the
fingerprint GPIOs which need to be handled differently between wake
from S3 and boot from S5.
On initial boot, the state of the FP sensor could be either
enabled or disabled. Because of this, on boot, we power off
the sensor for >200ms, to reset its state, then power it back on.
In suspend/resume, the fingerprint sensor should remain powered
the entire time.
If fingerprint is disabled on the trembyle-based board, set the pins
to no-connect. Dalboz doesn't have fingerprint and the GPIOS are
configured differently due to the FT5 chip having fewer GPIOS than
FP5, so nothing needs to be initialized there.
There were also a couple of trivial comment clean ups regarding the
FPMCU GPIOS.
BUG=b:171837716
TEST=Boot & Check GPIO states.
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I16a2e621145782e0a908bb3e49478586c09a0e0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This fixes all of the current code in coreboot/src where a bare
unsigned is used incorrectly. A follow-on will fix the comments
so that we can enable the unsigned lint checker for src/coreboot.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I37f34a95bb1894e70cd9e076d4b81ebac665eaeb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Tested=On OCP Delta Lake, verify the memory map hob data are correct.
Change-Id: I86bd809e21270395c4115788e5521606e9dcc2fb
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add a timestamp entry to allow forced delays to to be seen and accounted
for in the timestamp data.
BUG=None
TEST=Build only
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I26c9fa5c8599a349de2631ac24b9ea8858d8d6c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This change adds memory parts used by variant voema to
mem_parts_used.txt and generates DRAM IDs allocated to these parts.
Added memory
1. H9HCNNNCRMBLPR-NEE
2. H9HCNNNFBMBLPR-NEE
3. MT53D1G64D4NW-046 WT:A
BUG=b:172751925,b:172781673,b:172782100,b:172781562
TEST=emerge-volteer coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ic832155448fb07152b906aa04ca49d384ec47b34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47351
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change adds the following memory parts to LP4x global list of
available LP4x parts and to the global JSON file containing LP4x parts
and their characteristics.
1. H9HCNNNCRMBLPR-NEE
2. H9HCNNNFBMBLPR-NEE
3. MT53D1G64D4NW-046 WT:A
BUG=b:172751925,b:172781673,b:172782100,b:172781562
TEST=cd <path_to_coreboot_src>/util/spd_tools/lp4x &&
./gen_spd <path_to_coreboot_src>/src/soc/intel/tigerlake/spd \
global_lp4x_mem_parts.json.txt "TGL"
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I37702770f707fe078920694468552c5db59c478f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47350
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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When the host sends data in i2c bus, device might not send ACK. It means
that data is not processed on the device side, but for now we don't
check for that condition thus wait for the response which will not come.
Designware i2c detect such situation and set TX_ABORT bit. Checking for
the bit will enable other layers to immediately retry rather than
wait-timeout-retry cycle.
BUG=b:168838505
BRANCH=zork
TEST=test on zork devices, now we see "Tx abort detected" instead of I2C
timeout for tpm initializtion.
Change-Id: Ib0163fbce55ccc99f677dbb096f67a58d2ef2bda
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Since coreboot is written in C and not C++, having the double
underscores as a prefix is not an issue, but it also doesn't add much
information, so drop them and the trailing ones as well.
Change-Id: I1028fb9097efab8ffae5ffa9fe85a97feebc78a9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47583
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I0cc06e33ed5c9b9bd97ed1f10f9c2d8019b1b5ac
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47582
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I980cdd03d4283cd4bd9db8bd90fde9a43bebc1e5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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This also reduces the difference to the equivalent file from
stoneyridge.
Change-Id: I3fc44f057047995cc4054a85a1bb69427aa28531
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47581
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The T3 that PPVARN_LCD low to LCM_RST_1V8 high is 0.1269ms and
it does not meet the LCD specification that the T3 must be larger
than 5ms. Because there is a delay between PPVARN_LCD_EN and
PPVARN_LCD. An extra 9ms delay should be added on LCM_RST_1V8
in order to meet the specification "ProductSpec_NV105WUM-A51_
V4.3_P2(TLCM).pdf".
BUG=b:172201138
BRANCH=kukui
TEST=The LCD sequence T3 is larger than 5ms when power on.
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: Iaf7ae494e30c4c207103d949287b335288688c54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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The SMU mailbox access code from Picasso can be reused in the next
generation, so factor out the code to soc/amd/common/block/smu. Since
the mailbox register offsets in the indirect address space, the number
of arguments and the message IDs don't always match between different
devices, keep those in the soc-specific directories.
Change-Id: Ibaf5b91ab35428e4c771e7163c6e0c4fc50371e7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Update FSP headers for Tiger Lake platform generated based on FSP
version 3444. Previous version was 3425.
BUG=b:173160613
BRANCH=none
TEST=build and boot delbin
Cq-Depend:chrome-internal:3403586, chrome-internal:3403392
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I9e5de1617d00cd7543d4de1660f448e2fe220b0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47555
Reviewed-by: Dossym Nurmukhanov <dossym@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable CPPC entries generation, needed for Intel SpeedShift.
Test: dumped SSDT from Clevo L140CU and checked decompiled version
Change-Id: I0c8066a31d3bec27776836aac54c335c0e5d74e6
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47541
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Copy the code for CPPC entries generation, needed for Intel SpeedShift,
from SKL to common ACPI code.
SKL is going to use common ACPI code, too, in the future, so this code
duplication will vanish soon.
Test: dumped SSDT from Clevo L140CU and checked decompiled version after
enabling CPPC entries via Kconfig
Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45535
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The PCH IOAPIC ID is 0x8 so it needs to be generated before the IIO
IOAPICs. Since we will get rid of the ioapic_id array this makes it
more readable.
Change-Id: I64a3b259e438ef666fb68a433cceda10aebdb1bf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Currently the decision of whether or not to use mrc_cache in recovery
mode is made within the individual platforms' drivers (ie: fsp2.0,
fsp1.1, etc.). As this is not platform specific, but uses common
vboot infrastructure, the code can be unified and moved into
mrc_cache. The conditions are as follows:
1. If HAS_RECOVERY_MRC_CACHE, use mrc_cache data (unless retrain
switch is true)
2. If !HAS_RECOVERY_MRC_CACHE && VBOOT_STARTS_IN_BOOTBLOCK, this
means that memory training will occur after verified boot,
meaning that mrc_cache will be filled with data from executing
RW code. So in this case, we never want to use the training
data in the mrc_cache for recovery mode.
3. If !HAS_RECOVERY_MRC_CACHE && VBOOT_STARTS_IN_ROMSTAGE, this
means that memory training happens before verfied boot, meaning
that the mrc_cache data is generated by RO code, so it is safe
to use for a recovery boot.
4. Any platform that does not use vboot should be unaffected.
Additionally, we have removed the
MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN config because the
mrc_cache driver takes care of invalidating the mrc_cache data for
normal mode. If the platform:
1. !HAS_RECOVERY_MRC_CACHE, always invalidate mrc_cache data
2. HAS_RECOVERY_MRC_CACHE, only invalidate if retrain switch is set
BUG=b:150502246
BRANCH=None
TEST=1. run dut-control power_state:rec_force_mrc twice on lazor
ensure that memory retraining happens both times
run dut-control power_state:rec twice on lazor
ensure that memory retraining happens only first time
2. remove HAS_RECOVERY_MRC_CACHE from lazor Kconfig
boot twice to ensure caching of memory training occurred
on each boot.
Change-Id: I3875a7b4a4ba3c1aa8a3c1507b3993036a7155fc
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46855
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update I2C address for Goodix touchscreen and add ELAN touchscreen &
Synaptics trackpad device. Follow CB:47415 to correct HID over I2C
device to be level triggerd.
BUG=b:160013582
TEST=emerge-volteer coreboot and check system dmesg and evtest can get
device.
Change-Id: I070fb0e06b588f128253270502c9c2c427c62b84
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The option `HeciEnabled` was partly replaced by use of the device on/off
state in the devicetree in commit 3de90d1. The option has been removed
from the corresponding boards, so `HeciEnabled` is always 0 and ME
always gets disabled during soc finalize, when `HECI_DISABLE_USING_SMM`
is set.
Replace the option in the finalize function by the same dt state check
that sets the FSP option and drop the remaints of `HeciEnabled`.
Devicetrees still having `HeciEnabled` have been adapted to keep the
current behaviour.
Change-Id: Ib4cca9099b9aa3434552a41fbafca7cf6a0dd0eb
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47195
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In order for USB Type-C idisplays to be detected prior to loading Kernel
PMC IPC driver is needed to communicate with PMC in order to correctly set
the USB Mux settings. This patch is adding in support for early detection
of both Displays.
BUG=b:151731851
BRANCH=NONE
TEST=built and verified that TCSS MUX is being set on Volteer
Change-Id: I58e66f21210d565fb8145d140d2fc7febecdd21a
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42079
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To align MADT generation with DMAR, we loop over HOB entries instead
of over copied HOB entries fetched from get_iio_stacks(). This makes
it easier to see what is going on.
Tested on ocp/deltalake
Change-Id: I8ffe0322bb182b7ec5887354ec801e1f9f3d3288
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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All this function does is looping over IIO stacks in the FSP HOB. The
only 'SOC/FSP specific' thing is the way to detect if the stack is an
IIO stack so add a callback to determine this.
Change-Id: I4fa9c54d50279213a4174186a23c3cc156e21c9a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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The somewhat unrelated return value makes the function harder to
understand and the return type is not consistently used. Use a
different helper function to get the HOB Pci64BitResourceAllocation
data.
Change-Id: I9a03cbb0ebbb48cc052d4c082d359c0087aaeb3e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Change-Id: Ieae9f221ffb27cf52cab21a130e18aa3929caea3
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47540
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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WWAN_RST#: E10 -> F14
WWAN_PWR_EN: E13-> F21
Change-Id: I7182f384eb7a404dfe623c64e29467b41c6b0bdd
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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List of changes:
1. FSP-M Header:
- Add new UPD Lp5CccConfig
- Adjust Reservedxx UPD Offset
2. FSP-S Header:
- Adjust UPD Offset for Reservedxx, PsOnEnable, RpPtmBytes, PmSupport,
GtFreqMax, Hwp, TccActivationOffset, Cx, PchLockDownGlobalSmi,
PcieRpLtrMaxSnoopLatency, PcieRpLtrMaxNoSnoopLatency, UnusedUpdSpace45
Change-Id: I973f48b2af0336f04ee16cd1c4c91940a49af0e3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47244
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Select `PM_ACPI_TIMER_OPTIONAL` to enable the new PM ACPI Kconfig and
set the FSP option for PM ACPI timer enablement from its value instead
of using the old devicetree option.
Also drop the obsolete devicetree option from soc code and from the
mainboards and add a corresponding Kconfig entry instead.
Change-Id: I10724ccf1647594404cec15c2349ab05b6c9714f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45955
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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