| Age | Commit message (Collapse) | Author |
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Fix the following FWTS error:
FAILED [MEDIUM] AMLAsmASL_MSG_RETURN_TYPES: Test 1, Assembler warning in line
3038
Line | AML source
--------------------------------------------------------------------------------
03035| Return (One)
03036| }
03037|
03038| Method (_Q09, 0, NotSerialized) // _Qxx: EC Query
| ^
| Warning 3115: Not all control paths return a value (_Q09)
03039| {
03040| If (Acquire (PATM, 0x03E8))
03041| {
================================================================================
ADVICE: (for Warning #3115, ASL_MSG_RETURN_TYPES): Some of the execution paths
do not return a value. All control paths that return must return a value
otherwise unexpected behaviour may occur. This error occurs because a branch on
an conditional op-code returns a value and another does not, which is
inconsistent behaviour.
_Q09 is a reserved method and can't return a value. Change the logic
so that no return is used and avoid this test error.
BUG=b:112476331
TEST=Run FWTS.
Change-Id: Ibbda1649ec2eb9cdf9966d4ec92bfd203bb78d07
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/28123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Fix the following failure from FWTS:
FAILED [LOW] AMLAsmASL_MSG_SERIALIZED_REQUIRED: Test 1, Assembler remark in line
131
Line | AML source
--------------------------------------------------------------------------------
00128| }
00129| }
00130| })
00131| Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
| ^
| Remark 2120: Control Method should be made Serialized (due to creation of named objects within)
00132| {
00133| Name (RBUF, ResourceTemplate ()
00134| {
================================================================================
ADVICE: (for Remark #2120, ASL_MSG_SERIALIZED_REQUIRED): A named object is
created inside a non-serialized method - this method should be serialized. It is
possible that one thread enters the method and blocks and then a second thread
also executes the method, ending up in two attempts to create the object and
causing a failure.
BUG=b:112476331
TEST= Run FWTS.
Change-Id: I6f4f6e7e94b01f673afc97d9415481ee63e406e3
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/28122
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fix the IASL build warnings:
Object is not referenced (Name [CDW2] is within a method [_OSC])
Object is not referenced (Name [CDW3] is within a method [_OSC])
Remove the not referenced objects. They are not needed.
BUG=b:112476331
TEST=IASL doesn't give the warning.
Change-Id: I5b38d4de3f9875c5b013a49eb5146bf5916b96a6
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/28121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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This change adds some MSRs that are needed in a subsequent change to add
support for Continuous Performance Control.
Change-Id: Id4ecff1bc5eedaa90b41de526b9a2e61992ac296
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/28067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This change adds 2 methods for Conginuous Performance Control that was
added in ACPI 5.0 and expanded twice in later versions. One function
will create a global table based on a provided struct, while the other
function is used to add a _CPC method in each processor object.
Change-Id: I8798a4c72c681b960087ed65668f01b2ca77d2ce
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/28066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The existing code for modifying the power state after power loss of the system
only implemented the transitions from power off to either power on or power keep
properly.
Since I don't have a board with this chip, I couldn't test the patch on real
hardware. The two cases described above were tested before the original patch
was merged, so I'd expect this to work.
Change-Id: I3c26a2837e451dbfd3cee82e9beedc0f4a90af03
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Update SPD details to match with Coffeelake U RVP board
BUG=none
BRANCH=none
TEST=Boot on coffelake U rvp board and check if memory training is
passing and board boots till payload.
Change-Id: I953354cf5c6045731262f4f4e9da230187c2d246
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/27906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Update GPIO table as per board schematics.
GPIO table for other variants will be added later.
Change-Id: Ieb55d160ae2d6bff940840b1fba9411979332d4d
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/27907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
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Nami doesn't support wakeup from hibernation by CR50. This causes the
device to remain turned off after CR50 update.
This patch disables turning off EC on cr50 update. CR50 resets the
whole system. So, EC reset is not required.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=b:112604277
BRANCH=none
TEST=gsctool -a -u /media/removable/cr50.bin && reboot
Verify EC reboots. AP prints 'Waiting for CR50 reset to pick up update'
then reboots.
Change-Id: I06f5eb6100e8af6ffec45d4de2b40eff44f89709
Reviewed-on: https://review.coreboot.org/28113
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch allows boards to disable turning off EC on cr50 update.
If CR50 resets the whole system, an EC reset is not required.
BUG=b:112604277
BRANCH=none
TEST=gsctool -a -u /media/removable/cr50.bin && reboot
Verify EC reboots. AP prints 'Waiting for CR50 reset to pick up update'
then reboots.
Change-Id: I60a7aa50a549e7a5a1a114245fbf7b9646d813bb
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/28110
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The only board left in the tree (aopen/dxplplusu) with
this socket is the slower of the mPGA604 variants with
FSB 533.
Change-Id: I04707a0dcb8f5b6235ead8c02ddfddfe7c3b8b1b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/28116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This change permits the subsystem ID to be specified via Kconfig for the
devices on the SoC.
Some devices are getting zero'ed subsystem IDs because the unset (and thus
zero'ed) config options are overwriting the fsp defaults. With this change
the fsp defaults will only be overwritten by non-zero config values.
Change-Id: I0f7bb8e465f55e5dd6d8e0fad71b9b2a22f089dc
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/27609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Header files AcpiLib.h, FchDef.h and FchBiosRamUsage.h became obsolete when
VENDORCODE_FULL_SUPPORT was removed. Therefor they should be removed.
BUG=b:112602580
TEST=Build grunt and gardenia.
Change-Id: If4fdb9ae1e106ba15f2a073f592499e638e40c65
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28093
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: If7650ac4d9be2614a9665c7f2aba9ac5cc413efe
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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These files are being updated to match the prevailing style
of cmos.default files.
Change-Id: I47d31d6fec8c9eb856aed0c63824d9556b7705e4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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change I2C irq to EDGE trigger
BUG=b:112616824
BRANCH=master
TEST=emerge-grunt coreboot
Raydium TS is working.
Change-Id: I86ec32bb3f2626e65d76c3259e3c4244a970e5de
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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The specification updates for ICH 9 & 10 require to leave the
register in its default state by reserving all of its bits.
Writing to it does not seem to make a difference anyway since
reading it afterwards does not reflect the write (tested on ICH10).
Therefore we should omit the writes but document this fact in the
code because it is easy to miss from the datasheet alone.
Change-Id: Iec0d79f926a826a80b90907f7861d0cb2ca30a5b
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/28094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Print the PMxC0 S5/Reset status bits to the console.
TEST=Inspect console for Grunt
BUG=b:110788201
Change-Id: Ia905bb325a535fd4aa7082011cdfe92f08dff2cb
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://review.coreboot.org/28020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Used default console log level is 7 in src/console/Kconfig.
So let cmos.default use the same level as default.
Change-Id: Ia39ee457a8985142f6e7a674532995b11cb52198
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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All of the callers to acpigen_write_register() also make calls to
acpigen_write_resourcetemplate_[header|footer](). This change introduces
acpigen_write_register_resource() to unify all of those trio of calls
into one. I also made the input parameter const.
Change-Id: I10b336acf9f03c423bee9dc38955b1617e11c025
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/27672
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove VENDORCODE_FULL_SUPPORT from /soc/amd/stoneyridge/Kconfig and
from vendorcode/amd/pi/00670F00/Makefile.inc, thus completing the removal
of VENDORCODE_FULL_SUPPORT from coreboot.
BUG=b:112578491
TEST=none, VENDORCODE_FULL_SUPPORT already not used.
Change-Id: Idb5f6dc7add1617f7a97a97ae110901b2dec0996
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Remove VENDORCODE_FULL_SUPPORT from file above mentioned file, in
preparation to full removal of VENDORCODE_FULL_SUPPORT functions.
BUG=b:112578491
TEST=none, VENDORCODE_FULL_SUPPORT already not used.
Change-Id: Ic23dcf245b2cee24f7363ca3bb9918eb2f11179c
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Remove VENDORCODE_FULL_SUPPORT from file above mentioned file, in
preparation to full removal of VENDORCODE_FULL_SUPPORT functions.
BUG=b:112578491
TEST=none, VENDORCODE_FULL_SUPPORT already not used.
Change-Id: Id91e76282509743070e34c02082d3f3f46a14059
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Remove VENDORCODE_FULL_SUPPORT from file:
vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c
BUG=b:112578491
TEST=none, VENDORCODE_FULL_SUPPORT already not used.
Change-Id: I0d590b175a3cf0426580dc9ee5164b3cedc838e2
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Remove VENDORCODE_FULL_SUPPORT from files FchLib.c and FchPeLib.c.
BUG=b:112578491
TEST=none, VENDORCODE_FULL_SUPPORT already not used.
Change-Id: If24eb7f005720a62a1280fe78ddb54c9d2690150
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Now that the functions that used them were safely removed, remove
LibAmdIoRMW(), LibAmdMemRMW() and LibAmdPciRMW().
BUG=b:112541697
TEST=Build grunt and gardenia
Change-Id: I570bd91cd9eba7798ea39d9685e214fee10824be
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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The functions that use LibAmdPciRMW() are not used by coreboot and can be
safely removed in preparation to remove LibAmdPciRMW() itself. The
functions to be removed are:
From vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c:
ProgramPciByteTable().
From vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c: RwXhciIndReg(),
RwXhci0IndReg() and RwXhci1IndReg().
From vendorcode/amd/pi/00670F00/Proc/Fch/Common/PciLib.c: RwPci().
BUG=b:112541697
TEST=Build grunt and gardenia
Change-Id: I0b96d3d6b98140ed8e9298817dbe29d55b9e22cb
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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The functions that use LibAmdMemRMW() are not used by coreboot and can be
safely removed in preparation to remove LibAmdMemRMW() itself. The
functions to be removed are: ProgramFchAcpiMmioTbl() and GetEfuseStatus(),
both from vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c.
BUG=b:112541697
TEST=Build grunt and gardenia
Change-Id: Ib935b1797c4bf8b504fdda6f676fca369169a7f1
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Side effect was observed that after override BayHub EMMC
driving strength to the max, EMMC CLK will be reduced to
51.x Mhz from 200 Mhz.
This will cause OS installation fail on Samsung EMMC sku.
BUG=b:111964336
BRANCH=master
TEST=emerge-grunt coreboot
Change-Id: I848ab0cae474b15fbc4264c8ade63d5c6b4e489d
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/28084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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This file contains two instances of "dptf_enable" = "1". This change
removes the 2nd instance (it doesn't have an explicit comment like the
1st instance).
The dptf devices still seem to be present even with this change, as
expected.
Change-Id: I890006644be9176ebaf555cc121c816e12f2b596
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/28076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The spec of the sx9310 says the I2C interface can handle standard
(100kb/s) and fast mode (400kb/s). The current setting is using fast
plus (1000kb/s) so this change is reducing the speed to fast mode.
I've been using the sensors with this change for a few weeks now, though
I also don't recall seeing an issue prior to this change.
Change-Id: I337fc02c52565d6ec4d7bac1b3564f65238962dc
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/28075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This reverts commit 1fdb76945a9d06bbff37dee9da69e13a86c933f4.
Camera power is now handled by ACPI rules - no need to force the GPIOs
on by default.
BUG=b:80106316,b:111141128
Change-Id: Ifefec320884989f106a4b09c956d3a3279a1491a
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/28072
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Ping-chung Chen <ping-chung.chen@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This defines new GPIO pin for controlling the display panel CABC
function. The default value is high (enabled).
BUG=b:112154569
Change-Id: I29083ab18e37f929a55b450b143463c67fe0abea
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/28070
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This updates the DPTF sensor names to reflect the sensor locations on
the board.
BUG=b:75454415
TEST=verified new strings show up in
/sys/devices/LNXSYSTM:00/LNXSYBUS:00/INT3400:00/*/description
Change-Id: Ibffe6cb361de212ca03e75deaa8c454546d267a5
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/28069
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ia38c6f8d978065090564d449cae11d54ddb96421
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Within procedure LzmaDecode(), the variable len can be assigned a value
that is never read after, thus causing a static analysis error. Tell the
coreboot scan-build static analysis we know it can happen.
BUG=b:112253891
TEST=Build and boot grunt.
Change-Id: I37bc3ff19ca85f819ba1cbb2a281c1ad55619da9
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add a method in bootblock that can be used for printing registers.
BUG=none
TEST=compiled grunt
Change-Id: I8dff30e589761fbad92cfc2709546dba169993d8
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28059
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Under some conditions, cr50_i2c_read() can return without actually reading
the TPM, which will leave access uninitialized. Set an initial value for
access, and if TPM fails to respond in time check if at least TPM was read.
This way avoids printing an uninitialized value.
BUG=b:112253891
TEST=Build and boot grunt.
Change-Id: I5ec7a99396db32971dc8485b77158d735ab1d788
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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FAKE_IFD depends on out tree flashrom patches for which there are better
alternatives available now, so don't build with FAKE_IFD by default.
Change-Id: I2c6a6586da9a6d26b0a5bf7d3ba8f3ffe3205647
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I909d7dd4968aa2f76df00c03e603e8e82a4824c0
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/28052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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There is a confusingly named section in cbmem called vdat.
This section holds a data structure called chromeos_acpi_t,
which exposes some system information to the Chrome OS
userland utility crossystem.
Within the chromeos_acpi_t structure, there is a member
called vdat. This (currently) holds a VbSharedDataHeader.
Rename the outer vdat to chromeos_acpi to make its purpose
clear, and prevent the bizarreness of being able to access
vdat->vdat.
Additionally, disallow external references to the
chromeos_acpi data structure in gnvs.c.
BUG=b:112288216
TEST=emerge-eve coreboot, run on eve
CQ-DEPEND=CL:1164722
Change-Id: Ia74e58cde21678f24b0bb6c1ca15048677116b2e
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/27888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch updates Power Limit (PL) for AML.
- PL1 as 5W TDP as POR
- PL2 as 18W TDP as POR
BUG=None
BRANCH=None
TEST=Build coreboot for Nocturne board and check default PL1/PL2 TDP.
cat /sys/class/powercap/intel-rapl/intel-rapl\:0/constraint_0_power
5000000 (5W TDP)
cat /sys/class/powercap/intel-rapl/intel-rapl\:0/constraint_1_power
18000000 (18W TDP)
Change-Id: Icb02a8a7c5fcd5e6aee45f14eba540a6b3ed3d67
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/27427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add TSR2 DART/DTRT package
BUG=b:110451144
BRANCH=nami
TEST=emerge-nami coreboot chromeos-bootimage
Test image with dptf.dv
Change-Id: I3328e17328415f5ebdcf84263e5456e11e55f769
Signed-off-by: T.H. Lin <t.h_lin@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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This change updates GPIO configuration for bobba boards with id >= 1
This follows the same model as fleex:
a. Dynamically update touchscreen power enable GPIO in devicetree.
b. Provide default and bid0 tables for GPIO configuration in ramstage.
c. Configure WLAN enable GPIO differently in bootblock based on
boardid.
BUG=b:112354568
TEST=Built firmware for bobba
Change-Id: Id4ee4a1815e16ddfe60ed268688a8aaf4fb75579
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/28071
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Coffeelake U has 32MB flash chip support. Adding fmd file and enabling
CFL U board's Kconfig to output 32MB rom file.
Change-Id: I21431b7ac813781b12b95f80c6f8960a78caf4bc
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/27905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
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Add support for new board coffeelake RVP.
This patch is a copy patch and copies entire coffeelake_rvp folder from
cannonlake_rvp.
Changes done on top of copy:
1. Change copyright year from 2017 to 2018
2. Rename Cannonlake to Coffelake whenever applicable
3. Update entries in Kconfig and Kconfig.name
4. Rename variant directories to match coffeelake boards
Change-Id: Id37bfeb0ae51fd630fec96273216dbb2900782c7
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/27904
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Unfortunately stmicro.c does not distinguish the 1.8V version from
the 3.3V versions (yet) although they have distinct RDIDs.
I have at least ordered the ID macros accordingly and used a proper name
in this patch.
Change-Id: Id4fd8d46dcc9e51c1ae5504a32c2f8c5cfd863a1
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/27861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I189c981f3334836ab24bbc74491e9b58a2d403a4
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/27921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The paths defined in southbridge/intel/common/firmware/Kconfig should work just
fine.
Change-Id: Iaa780d9b3080416c6b1a7f24d97ecb8214962405
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28012
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All broadwell board set HAVE_IFD_BIN to default n, overloading the option in
soc, therefore just use the defaults in sb/intel/common/firmware.
Change-Id: I250dbbc9d61ecedc1a1eb48751ad966732604349
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28011
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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There is no need to redefine option present in
southbridge/intel/common/firmware/Kconfig.
FAKE_IFD depends on out tree flashrom patches for which there are better
alternatives available now, so don't build with FAKE_IFD by default.
Change-Id: Icd41137a1bbfe519c89a71cc0c7c3755558bd834
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28010
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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FAKE_IFD depends on out tree flashrom patches for which there are better
alternatives available now, so don't build with FAKE_IFD by default.
Change-Id: I21bc5bdc8b733fbfdb1b2a4fbcb572c76701074a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28009
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
There is no need set the default HAVE_IFD_BIN explicitly to n.
Change-Id: I4a5fe45e7f8f6dd018937861b0fb92a8da49904e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28008
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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There is no need to redefine option present in
southbridge/intel/common/firmware/Kconfig.
Change-Id: I9999440031b07006e2df11e00dfb9f3dbe04f832
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28007
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Fix to accomodate for boards with more than 16 cores.
Change-Id: I35b61d94491c21ef76717f761e566ca815880f27
Signed-off-by: Samuel Jimenez <aerojsam@gmail.com>
Reviewed-on: https://review.coreboot.org/27847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Change-Id: I90d1997254f6766f4c61ff55449109adbdd783e3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Change-Id: I2c5edadfd035c9af08af9ee326a5a2dc8b840faa
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Change-Id: I3108193c0e0b644cecb74ae0c7a7b54e24a75b58
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Change-Id: I80dd65484fd52e9048635091fb20a123e959e999
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27869
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I1415c18779bc481fdec5f72f83c06a58ce6d5c39
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26797
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Current coreboot does not create ACPI device for OS to recognize Raydium
touchscreen.
List the touch screen in the devicetree so that the correct ACPI device
are created.
BUG=none
BRANCH=master
TEST=emerge-octopus coreboot
Change-Id: Ic61a69e19e97520da0702dfe6cb7496563fc34f4
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This binary needs to be at a specific offset and will therefore always
be located in the COREBOOT fmap region.
This is needed when VBOOT_SEPARATE_VERSTAGE is selected.
Change-Id: Ia73d468ab23932f92331ef40b8e8066cef55af2c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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This was blindly copied from logs created under vendor BIOS in non-descriptor
mode which apparently set LAND in BUC.
Change-Id: I94c917600421ee742ece7f6f71309da80261da28
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
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Since commit 372d0ff1d1 (arch/arm64: mmu: Spot check TTB memory
attributes), we already check the memory attributes that the TTB region
is mapped with to avoid configuration mistakes that cause weird issues
(because the MMU walks the page tables with different memory attributes
than they were written with). Unfortunately, we only checked
cachability, but the security state attribute is just as important for
this (because it is part of the cache tag, meaning that a cache entry
created by accessing the non-secure mapping won't be used when trying to
read the same address through a secure mapping... and since AArch64 page
table walks are cache snooping and we rely on that behavior, this can
lead to the MMU not seeing the new page table entries we just wrote).
This patch adds the check for security state and cleans up that code a
little.
Change-Id: I70cda4f76f201b03d69a9ece063a3830b15ac04b
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/28017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
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In procedure smm_load_module, variables fxsave_size and fxsave_area are set
to 0 and NULL, but if CONFIG_SSE is enabled, they are overwritten. Change
the code setting the value to an "else" of the "if" testing CONFIG_SSE, thus
avoiding static analysis error.
BUG=b:112253891
TEST=Build and boot grunt.
Change-Id: I3042b037017a082378b53ee419c769c535632038
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
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There's two cases of 1 being used. This changes the
eighth instance to use 8.
Change-Id: I7057a4345dadcc6f8fb43093844d27007444f481
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/27603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
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There's two instances od _UID 1 for PNP0C02. This change moves the
more system-specific instance of the two to a higher number. I
believe these are the 4 I'm seeing.
soc/intel/skylake/acpi/systemagent.asl
Device (PDRC)
Name (_HID, EISAID ("PNP0C02"))
Name (_UID, 1)
soc/intel/skylake/acpi/lpc.asl
Device (LDRC)
Name (_HID, EISAID ("PNP0C02"))
Name (_UID, 2)
ec/google/chromeec/acpi/superio.asl
Device (ECMM) {
Name (_HID, EISAID ("PNP0C02"))
Name (_UID, 1)
ec/google/chromeec/acpi/superio.asl
Device (ECUI) {
Name (_HID, EISAID ("PNP0C02"))
Name (_UID, 3)
Change-Id: I2b0f1064726a1fa3940ccfb2a4627c79a26684e4
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/27604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
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This patch changes the mapping of SRAM from non-secure to secure.
Without this patch, mmu_config_range() can not work when MMU is
enabled. The new config is still in non-secure cache since TTB section
is allocated in SRAM which is mapped as non-secure.
BUG=b:80501386
TEST=Boots correctly on Kukui and Elm
Change-Id: Ia5b8716cfcca64d1d716a177225ea2f7ac2920a6
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
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Remove icc_max overrides to allow SoC code to set proper
icc_max based on CPU SKU.
BUG=b:78122599
BRANCH=none
TEST='emerge-nocturne coreboot chromeos-bootimage', flash to
nocturne, boot to kernel and verify device doesn't hang after
a few minutes.
Change-Id: I37c44e2428b802d754f2b12b8a57601d257e6582
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27996
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This patch adds a function to overwrite PL2 setting based on CPU
sku. From doc #594883, PL2 is 18W for AML-Y.
BUG=b:110890675
BRANCH=None
TEST=emerge-nocturne coreboot chromeos-bootimage & test with AML-Y
and KBL-Y skus.
Change-Id: Idfdc0c2434fdef56a7c25df05e640837a5096973
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27997
Reviewed-by: Caveh Jalali <caveh@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This patch adds a function to overwrite PL2 setting based on CPU
sku. From doc #594883, PL2 is 18W for AML-Y.
BUG=b:110890675
BRANCH=None
TEST=emerge-atlas coreboot chromeos-bootimage & test with AML-Y
and KBL-Y skus.
Change-Id: I468befcd2c4ad6c2bb9ae91b323a43f87ff65a26
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/27765
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Fix define typo in dptf.asl
BUG=none
TEST=emerge-octopus coreboot PASS
Change-Id: I1c3bd55d1507e6fffe638bba38c99a9851b8a96a
Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
|
Follow thermal table (b:112274477 comment#1) for first tunning.
BUG=b:112274477
TEST=Match the result from DPTF UI.
Change-Id: I63b2e50a4f6fc5453e6564e277600498ac0e6244
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
|
Add DRAM resource in ramstage to load payload.
BUG=b:80501386
TEST=Load bl31 and depthcharge correctly on Kukui with more patches
applied.
Change-Id: Ie793b403bbbdb3c231dfa2caef29dcbb596b1a61
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27971
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The make `file` command is apparently a v4.2 feature only. Replace it
with a shell cat.
BUG=none
TEST=verified fwid.region was created correctly
Change-Id: I5e32a521ad3e6759853f0cde2e4c4db6e564d3be
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
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* Needed for additional code in later patches.
* SOC is obsolete anyway.
Change-Id: I5bbdf19cc886103e9e7a6b75219d6881cfe9c757
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/23764
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enable the GEO SAR feature for Octopus. Program wifi_sar VPD key.
coreboot reads the VPD and creates the ACPI table as per the WGDS spec.
BUG=b:112288077
TEST=Program VPD key, extract acpi table ssdt and valiate WGDS entry.
Change-Id: I40a6fd9e0ec8b440996bf3389322fd89bcca15a4
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/27966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
PERST signal is asserted/deasserted by ACPI routines during
suspend/resume. Configuring IOStandby for WLAN_PE_RST can result in
failure to resume from suspend state with wake-over-WLAN. This change
removes the IOStandby configuration for WLAN_PE_RST.
BUG=b:112371978
Change-Id: Ic7c0b2aa144233f8bbb4e5169d96347a1290abe1
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
When CNVi is being used, external wake using GPIO_119 is not
required. This change configures GPIO_119 as PAD_NC if CNVi is taken
out of reset.
BUG=b:112371978
Change-Id: Ifee90f428ed43c4d7c612c170476aff43b4a33ce
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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There is no need to add a special cnvi.asl file for the CNVi
device. This can be handled by drivers/intel/wifi just like a PCIe
WiFi device. This change gets rid of the cnvi.asl file and its usage
in southbridge.asl file.
BUG=b:112371978
Change-Id: I0b798cdd430768730b7ada61ca4cb1f63c2a4229
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change uses drivers/intel/wifi chip for CNVi device to ensure
that:
1. Correct device name shows up in ACPI node
2. It is possible to pass any parameters from devicetree to wifi
driver for SSDT generation.
BUG=b:112371978
Change-Id: Ia49820dd4f9cf2e0a9ef14931fbddd8a723208c0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change gets rid of unused wrdd.asl in intel wifi driver. This
file became redundant when all boards moved to using SSDT for wifi
device.
Change-Id: I8b5b3816d77c90e75052c58a3120ab62185873a7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27963
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change checks to ensure that device is enabled before adding
entry into SSDT.
BUG=b:112371978
Change-Id: Ibe4811bef8cf0978b7a82d66a32f96247b9c823d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This change checks to see if CNVi module is out of reset:
1. If yes, then PCIe device for WiFi is disabled.
2. If no, then CNVi device is disabled.
BUG=b:112371978
Change-Id: I6e6cf2e646c897df017913056db87ac0cffa1a8e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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This change adds CNVi device to list of PCI devs.
BUG=b:112371978
Change-Id: I6def98db3846c2244812a9a2ce84340bd2149b48
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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I2C2 is unused on all octopus variants. This change disables it in
devicetree.
BUG=b:112458032
Change-Id: I55abef864c06a448011f9570d3e6c0aa8bfdc5bc
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28016
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change updates GPIO configuration for fleex boards with id >= 1
This follows the same model as phaser:
a. Dynamically update touchscreen power enable GPIO in devicetree.
b. Provide default and bid0 tables for GPIO configuration in ramstage.
c. Configure WLAN enable GPIO differently in bootblock based on
boardid.
d. Disable unused I2C devices in devicetree.
BUG=b:112458032
TEST=No errors observed on boot-up on fleex.
Change-Id: Ib4c449168b08e2393e2395d6b49469be5599c2ce
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The file `data.vbt` matches the VBT in the latest version of the vendor
firmware (version 3603). Tested with Linux 4.9 and everything works as
expected.
Change-Id: I8e3b1d274ac0df63989d966f477013e780611fa1
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/28050
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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SLB9665 are not initialized correctly. It looks like SLB9665 and SLB9660
return the same DEV ID. Initialize these devices according to TPM Kconfig
selections.
Tested on apu2 with following change:
https://review.coreboot.org/#/c/coreboot/+/28000/
Change-Id: Ic20b9a65ef6a4ee392a9352f7c9bf01b2496f482
Signed-off-by: Kamil Wcislo <kamil.wcislo@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/21983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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Change-Id: Ib0839933f8b59f0c87cdda4e5374828bd6f1099f
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/23759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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* Move cbmem.c to cn81xx folder
* Store CBMEM below 4 GiB
* Make sure CBMEM doesn't overlap with ATF scratchpad
* Fix ATF scratchpad not marked as reserved due to wrong calculation
* The scratchpad is the last 1 MiB at the end of DRAM.
Tested on Cavium CN81xx EVB:
The ATF scratchpad is now marked reserved and the configuration tables
are located below 4 GiB. Linux still boots.
Change-Id: Ibbc8b586f04bd6867c045f5546b32a77c057ac74
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27955
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It's broken.
Change-Id: I3ec8fff99e21cbdf4ad3f4562ff9bbc1cd3c135b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/28003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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Store initrd offset as 64bit integer.
Tested on Cavium CN81XX EVB: The initrd could be loaded when placed
above 4GiB. Previously it failed to find the initrd.
Change-Id: I5d1ae860ae4a4465546bc0ef89937d611d1e56ab
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/28002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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Allow for shared dram configuration by introducing a new table
that collapses the common settings after removing the part
numbers. When employing this scheme the part number comes
from CBI.
BUG=b:112203105
TEST=Placed part number in cbi. Faked out memory sku id. And enabled
DRAM part num always in cbi. Everything checked out.
Change-Id: I5229695ce3eb686421b89ac55d8df4b9fcec705c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/27991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: I689c5663ef59861f79b68220abd146144f7618de
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I9144937b72a98517cbd41c093cff7bad543b4140
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27916
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Options that were deemed unneceesary on other code reviews have
been removed from the layout files. In addition, the checksummed
range has been extended to cover sata_mode and gfx_uma_size.
Change-Id: Id9e904f447809231806a786e39ed638f21e1bc5a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/27217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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I ported ga-h61m-s2pv based on the two Gigabyte b75m boards.
Based on another mainboard's code review comments, this patch
improves the code quality of these three similar boards.
ga-h61m-s2pv is tested and confirmed to be working, but I cannot
say the same regarding the other two mainboards as I do not have them.
Change-Id: Ib7747cceb5ba56f791677204cdc4c54c129c70c3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/27211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Set payload to NULL in case of decompression errors.
Fixes the attempt to boot a kernel that couldn't be decompressed.
Change-Id: I3a602b0e90923a0b5a3683c4a0adf9e4733d5a2a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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1. Add new device IDs for SATA, GT and Northbridge to pci_ids.h
2. Add entry to identify CFL U GT and CPU to respective files
3. Add entry to identify CFL U to report_platform.c
BUG=none
BRANCH=none
TEST=Boot to CFL U RVP board with this patch and check if coreboot is
able to enumerate various devices and display correct component names properly
in serial logs.
Change-Id: I47c97fb9eb813587cd655e2bce05a686091619ed
Signed-off-by: Maulik <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/27522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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