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2016-07-15rockchip/rk3399: add/remove local variables to sdram_initDerek Basehore
This adds two local variables for dramtype and ddr_freq to sdram_init since those two values are commonly used in the function. It also removes a variable that is just used once and directly uses the value for a function call instead. BRANCH=none BUG=none TEST=on kevin/gru, run "stressapptest -M 1024 -s 3600" and check that it passes Change-Id: I4e9dbc97803ff3300b52a5e1672e7e060af2cc85 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: b7d1135c65298a73e6bf2a4a34b7c9b84f249ea8 Original-Change-Id: I4e1a1a4a8848d0eab07475a336c24bda90b2c9f8 Original-Signed-off-by: Derek Basehore <dbasehore@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/355666 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15653 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15lib/version: Correct whitespace alignmentPaul Menzel
Remove and add spaces for a consistent alignment. Change-Id: I612800cd60d97f50737c235465d7d0a87f2251a8 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/15596 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-07-14spike-riscv: Look for the CBFS in RAMJonathan Neuschäfer
Change-Id: I98927a70adc45d9aca916bd985932b94287921de Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15285 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2016-07-14soc/intel/quark/bootblock: Remove clear_smi_and_wake_eventsJonathan Neuschäfer
It is not used in this file. Change-Id: I59bb41370b97b79073c0fd82b1dbcae9fd8a62d0 Reported-by: GCC 6.1.0 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15552 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-07-14arch/riscv: Unconditionally start payloads in machine modeJonathan Neuschäfer
Ron Minnich writes: "we'll change cbfstool to put a header on the payload to jump to supervisor if that is desired. The principal here is that payloads are always started in machine mode, but we want to set the page tables up for them." Change-Id: I5cbfc90afd3febab33835935f08005136a3f47e9 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15510 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-07-14spike-riscv: Register RAM resource at 0x80000000Jonathan Neuschäfer
Without this patch, the CBFS loader won't load segments into the RAM. Change-Id: If05c8edb51f9fe2f7af84178826f93b193cfd8a9 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15511 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-07-14siemens/mc_bdx1: Add usage of external RTC PCF8523Werner Zeh
This mainboard contains an external RTC chip PCF8523. Enable usage of this chip and add some initialization values to device tree. Change-Id: I25c0a017899ee904f3aa02bdc7dcaf61dee67e3a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15642 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-14drivers/i2c: Add new driver for RTC type PCF8523Werner Zeh
This driver enables the usage of an external RTC chip PCF8523 which is connected to the I2C bus. The I2C address of this device is fixed. One can change parameters in device tree so that the used setup can be adapted in device tree to match the configuration of the device on the mainboard. Change-Id: I2d7e161c9e12b720ec4925f1acfd1dd8ee6ee5f5 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15641 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-14fsp_broadwell_de: Add SMBus driver for ramstageWerner Zeh
There is currently a SMBus driver implemented for soc/intel/broadwell which nearly matches Broadwell-DE as well. Use this driver as template and add minor modifications to make it work for Broadwell-DE. Support in romstage is not available and can be added with a different patch. Change-Id: I64649ceaa298994ee36018f5b2b0f5d49cf7ffd0 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15617 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-14intel/amenia: Add mainboard SMI handlerShaunak Saha
This patch adds a mainboard SMI handler file which has functions to set proper Wake mask before going to sleep so that system can wake up on lidopen, key press etc. Also SCI mask is set on boot which will enable timely update of battery UI on charger connect/disconnect. BUG = chrome-os-partner:53992 TEST = Amenia platform wakes from S3 on lidopen, key press and also sysfs entry for AC is updated on charger connect/disconnect. Change-Id: If3dc6924c51c228241b7a647566b97398326ec0e Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15616 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-14google/reef: Add mainboard SMI handlerShaunak Saha
This patch adds a mainboard SMI handler file which has functions to set proper Wake mask before going to sleep so that system can wake up on lidopen, key press etc. Also SCI mask is set on boot which will enable timely update of battery UI on charger connect/disconnect. BUG = chrome-os-partner:53992 TEST = Reef Platform wakes from S3 on lidopen, key press and also sysfs entry for AC is updated on charger connect/disconnect. Change-Id: I8c087994b48223b253dcf1cbb3ed3c3a0f366e36 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15615 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-14intel/amenia: Add Maxim98357a supportHarsha Priya
Adds Maxim98357a support for amenia using the generic driver in drivers/generic/max98357 Change-Id: I333d4e810e42309ac76dd90c19f05cf3e3a518f1 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/15624 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-14google/reef: Enable touchscreen in ACPIFurquan Shaikh
Add support for ELAN touchscreen on I2C3. Change-Id: Id8b07a3a3fd4beca0d7ce804ba8d6859275c70d9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15499 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-14intel/amenia: Update gpio config for audioHarsha Priya
This changelist updates gpio config for speaker SDMODE pin. It disables speaker by default. Audio kernel is expected to enable this when audio rendering starts. Change-Id: Id33ad29e637bf1fe6b02e8a4b0fd9e220e8983b6 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/15623 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-14nb/intel/pineview/northbridge.c: Remove legacy_hole_size_k declarationJonathan Neuschäfer
Change-Id: I7c3973ff325f11a86728e8660c70839776981aa5 Reported-by: GCC 6.1.0 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15554 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-14tpm2: implement and use pcr_extend commandVadim Bendebury
TPM PCRs are used in Chrome OS for two purposes: to communicate crucial information from RO firmware and to protect FW and kernel rollback counters from being deleted. As implemented in a TPM1 compatible way, the PCR extension command requires a prebuilt digest to calculate a new PCR value. TPM2 specification introduces a PCR_Event command, where the TPM itself calculates the digest of an arbitrary length string, and then uses the calculated digest for PCR extension. PCR_Event could be a better option for Chrome OS, this needs to be investigated separately. BRANCH=none BUG=chrome-os-partner:50645 TEST=verified that the two PCRs are successfully extended before the RW firmware is called. Change-Id: I38fc88172de8ec8bef56fec026f83058480c8010 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 73388139db3ffaf61a3d9027522c5ebecb3ad051 Original-Change-Id: I1a9bab7396fdb652e2e3bc8529b828ea3423d851 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/358098 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Darren Krahn <dkrahn@chromium.org> Reviewed-on: https://review.coreboot.org/15639 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-07-14tpm2: implement locking firmware rollback counterVadim Bendebury
TPM1.2 is using the somewhat misnamed tlcl_set_global_lock() command function to lock the hardware rollback counter. For TPM2 let's implement and use the TPM2 command to lock an NV Ram location (TPM2_NV_WriteLock). BRANCH=none BUG=chrome-os-partner:50645 TEST=verified that TPM2_NV_WriteLock command is invoked before RO firmware starts RW, and succeeds. Change-Id: I52aa8db95b908488ec4cf0843afeb6310dc7f38b Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 2f859335dfccfeea900f15bbb8c6cb3fd5ec8c77 Original-Change-Id: I62f22b9991522d4309cccc44180a5ebd4dca488d Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/358097 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Darren Krahn <dkrahn@chromium.org> Reviewed-on: https://review.coreboot.org/15638 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-13tpm2: fix tpm_write() error reportingVadim Bendebury
The code misses the cases when a response was received but the command failed. This patch fixes the problem. BRANCH=none BUG=chrome-os-partner:50645 TEST=none Change-Id: I3d50a4b67e3592bb80d2524a7c7f264fddbd34ae Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 8f4d6185e13beead7156027e1cb40f7944e46569 Original-Change-Id: I914ab6509d3ab2082152652205802201a6637fcc Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/358096 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15637 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-07-13tpm2: add tlcl_force_clear and use it before factory initVadim Bendebury
tlcl_force_clear() needs to be issued each time when the device mode switches between normal/development/recovery. This patch adds command implementation using TPM_Clear TPM2 command, and also invokes it before factory initialization. BRANCH=none BUG=chrome-os-partner:50645 TEST=verified that TPM_Clear command succeeds at factory startup and the boot proceeds normally. Change-Id: Ia431390870cbe448bc1b6f1755ed17953be9bdf1 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 347ff17b97da45fa4df547ff32f9dd2c8972cefd Original-Change-Id: I2a0e62527ad46f9dd060afe5e75c7e4d56752849 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/358095 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Darren Krahn <dkrahn@chromium.org> Reviewed-on: https://review.coreboot.org/15636 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-07-13tpm2: use pcr0 dependent nvram space policy definitionsVadim Bendebury
The TPM2 specification allows defining NV ram spaces in a manner that makes it impossible to remove the space until a certain PCR is in a certain state. This comes in handy when defining spaces for rollback counters: make their removal depend on PCR0 being in the default state. Then extend PCR0 to any value. This guarantees that the spaces can not be deleted. Also, there is no need t create firmware and kernel rollback spaces with different privileges: they both can be created with the same set of properties, the firmware space could be locked by the RO firmware, and the kernel space could be locked by the RW firmware thus providing necessary privilege levels. BRANCH=none BUG=chrome-os-partner:50645, chrome-os-partner:55063 TEST=with the rest of the patches applied it is possible to boot into Chrome OS maintaining two rollback counter spaces in the TPM NV ram locked at different phases of the boot process. Change-Id: I889b2c4c4831ae01c093f33c09b4d98a11d758da Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 36317f5e85107b1b2e732a5bb2a38295120560cd Original-Change-Id: I69e5ada65a5f15a8c04be9def92a8e1f4b753d9a Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/358094 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/15635 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-07-13tpm2: add TPM_Clear command processingVadim Bendebury
The command is sent in session mode, but has no parameters associated with it. BRANCH=none BUG=chrome-os-partner:50645 TEST=with the following patches verified that TPM_Clear command is handled successfully by the TPM. Change-Id: I3c9151e336084160acd3bb1f36f45b4d5efd4a33 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 503ad5e72fd5bd902325d74fd680c17c7c590e36 Original-Change-Id: Ida19e75166e1282732810cf45be21e59515d88e2 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/357973 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15634 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-07-13tpm2: refactor session header marshallingVadim Bendebury
For coreboot TPM2 the use case session header is always the minimal possible size, the only difference is that some commands require one and some require two handles. Refactor common session header marshalling code into a separate function. This will be useful when more commands marshalling code is added. BRANCH=none BUG=chrome-os-partner:50645 TEST=flashed the TPM and rebooted the device a few times, it successfully loaded chrome os on every attempt. Change-Id: I9b1697c44f67aab32b9cd556b559a55d5050be06 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: a97a7fa16ceeb484e90e2e1f0573e58a468350b2 Original-Change-Id: I86e6426be5200f28ebb2174b418254018e81da8e Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/357972 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15633 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-07-13tpm2: clean up tpm_marshal_command()Vadim Bendebury
The function is reusing some variables which confuses the reader as the variable names do not match their second function. This patch edits the code for readability without changing functionality. BRANCH=None BUG=chrome-os-partner:50465 TEST=with the rest of the patches applied Kevin still boots into chrome OS. Change-Id: I396206a64403229ba3921a47b5a08748d8a4b0a3 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 3cf02c365d098c9d2ca57def7cf349ef2291d140 Original-Change-Id: I95a07945d9d2b00a69d514014f848802b82dd90f Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/358915 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15611 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-07-13tpm2: avoid comparison between signed and unsigned intsVadim Bendebury
The marshaling/unmarshaling code is using integer values to represent room left in the buffer, to be able to communicate three conditions: positive number means there is room left in the buffer, zero means that the exact amount of data in the buffer was unmarshaled and negative value means that the result of the operation did not fit into the buffer. The implementation is wrong though, as it compares directly signed and unsigned values, which is illegal, as signed values get promoted to unsigned by the compiler. This patch changes the marshaling code to use size_t for the size, and use zero as marshaling failure indication - after all the buffer where the data is marshaled to should definitely be large enough, and it is reasonable to expect at least some room left in it after marshaling. The unmarshaling situation is different: we sure want to communicate errors to the caller, but do not want to propagate error return values through multiple layers. This patch keeps the size value in int, but checks if it is negative separately, before comparing with positive values. BRANCH=none BUG=chrome-os-partner:50645 TEST=with the rest of the patches applied kevin successfully boots up. Change-Id: Ibfbd1b351e35e37c8925a78d095e4e8492805bad Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: b1e862c2a650fa5f6cb25a01fe61e848a696cf17 Original-Change-Id: Ie7552b333afaff9a1234c948caf9d9a64447b2e1 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/358772 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15610 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-13tpm2: drop unused structuresVadim Bendebury
Some structures were included in tpm2_tlcl_structures.h that are not needed for tpm2 commands used by coreboot. Drop them from the include file. BRANCH=none BUG=none TEST=coreboot image for gru/kevin still builds fine. Change-Id: Id3a01f7afbddc98b4d14125452ae6a571f1b19cb Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 9375eef5a3f5ed2ba216b1cc8a4ce5c78ebe53d8 Original-Change-Id: I89b46900e5356989f2683d671552ecca5103ef90 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/358093 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15608 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-13tpm2: remove unused buffer size definitionVadim Bendebury
TPM2 structure definitions use pointers instead of buffers where possible. One structure was left behind. Replace that buffer definition with a pointer to be consistent. BRANCH=none BUG=chrome-os-partner:50645 TEST=compilation succeeds, the code using the changed structure in the upcoming patches allows to successfully boot chrome OS on Kevin Change-Id: Iea59943aa0ad6e42fcd479765a9ded0d7a1680d7 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 02b2909b1875ba65cd56cf8e3697a2b67ddaea07 Original-Change-Id: I9856ac516be13f5892ba8af0526708409a297033 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/358771 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/15609 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-13rk3399: allow more room for CBMEM consoleVadim Bendebury
With recent bootblock code additions the CBMEM console buffer is not large enough to store the entire log accumulated before DRAM is initialized, spilling 700 bytes or so on the floor. This patch adds 1 KB to the CBMEM console buffer, at the expense of the bootblock area in SRAM. The bootblock is taking less then 26K out of 31K allocated for it after this change. Placing CBMEM console area right after the bootblock makes sure other memory regions are not going to be affected should memory distribution between bootblock and CBMEM console need to change again. BRANCH=none BUG=none TEST=examining /sys/firmware/log after device boots up into Chrome OS does not report truncated console buffer any more. Change-Id: I016460f57c70dab4d603d4c5dbfc5ffbc6c3554f Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: bfa31684a1a9be87f39143cb6c07885a7b2e4843 Original-Change-Id: I2c3d198803e6f083ddd1d8447aa377ebf85484ce Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/358125 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15607 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-13gru: Enable TPM2Vadim Bendebury
Gru and derivative boards use TPM2 to support Chrome OS verified boot. BRANCH=none BUG=chrome-os-partner:50645 TEST=re-built Kevin firmware, verified that TPM2 support over SPI is enabled, and that with appropriate vboot and depthcharge patches applied the device can boot into chrome os properly verifying RW firmware and kernel key indices. Change-Id: Id14a51cea49517bd2cc090ba05d71385aad5b54c Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 60e229d93d7e219e261b851f654e459eb2cf4f41 Original-Change-Id: Ic6f3c15aa23e4972bf175b2629728a338c45e44c Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/354781 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: https://review.coreboot.org/15606 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-13oak/gru: Fix derivative KconfigsJulius Werner
Add a few missing Kconfig defaults for derivatives of the Oak and Gru baseboards. Also group all Kconfigs that must change for derivatives together for easier updating. BRANCH=None BUG=None TEST=None Change-Id: I95ebb08b4f13f09f2539b451d7b96a826ddf98f8 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: ae3f13c1dc323f4c7c4a176a4f5e1285fec312ce Original-Change-Id: I658130e88daa2d113fd722b0527cf0e7ab66c7ef Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/357922 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15605 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-13soc/intel/apollolake: add offset of GPIO_TIER1_SCI_EN bitShaunak Saha
This patch adds the support for gpio_tier1_sci_en bit which needs to be set before going to sleep so that when gpio_tier1_sci_sts bit gets set platform can wake from S3. BUG = chrome-os-partner:53992 TEST = Platform wakes from S3 on lidopen,key press. Tested on Amenia and Reef boards. Change-Id: I3ba79fa53ca8817149d585fa795a8f427c128dcb Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15612 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-13soc/intel/apollolake: work around FSP for gpio interrupt polarityAaron Durbin
FSP is currently setting a hard-coded policy for the interrupt polarity settings. When the mainboard has already set the GPIO settings up prior to SiliconInit being called that results in the previous settings being dropped. Work around FSP's default policy until FSP is fixed. BUG=chrome-os-partner:54955 Change-Id: Ibbd8c4894d8fbce479aeb73aa775b67df15dae85 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15649 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-13soc/intel/apollolake: set gpio interrupt polarity in ITSSAaron Durbin
For APIC routed gpios, set the corresponding interrupt polarity for the associated IRQ based on the gpio pad's invert setting. This allows for the APIC redirection entries to match the hardware active polarity once the double inversion takes place to meet apollolake interrupt triggering constraints. BUG=chrome-os-partner:54955 Change-Id: I69c395b6f861946d4774a4206cf8f5f721c6f5f4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15648 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-13soc/intel/apollolake: add initial ITSS supportAaron Durbin
The interrupt and timer subsystem (ITSS) sits between the APIC and the other logic blocks. It only supports positive polarity events, but there's a polarity inversion setting for each IRQ such that it can pass the signal on to the APIC according to the expected APIC redirection entry values. This support is needed in order for the platform/board to set the expected interrupt polarity into the APIC for gpio signals. BUG=chrome-os-partner:54955 Change-Id: I50ea1b7c4a7601e760878af515518cc0e808c0d1 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15647 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-13mainboard/intel/amenia: use new gpio interrupt macrosAaron Durbin
Utilize the new interrupt macros in order to specify correct polarity of the gpio interupts. Some of the interrupts were working by catching the opposite edge of the asserted interrupt. BUG=chrome-os-partner:54977 Change-Id: I55bee2c4363cfdbf340a4d5b3574b34152e0069c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15646 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-13mainboard/google/reef: use new gpio interrupt macrosAaron Durbin
Utilize the new interrupt macros in order to specify correct polarity of the gpio interupts. Some of the interrupts were working by catching the opposite edge of the asserted interrupt. BUG=chrome-os-partner:54977 Change-Id: Iee33c0a949be0a11147afad8a10a0caf6590ff7b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15645 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-13soc/intel/apollolake: provide gpio _HIGH/_LOW macrosAaron Durbin
Internally, apollolake routes its interrupts as active high. This includes SCI, SMI, and ACPI. Therefore, provide helper macros such that the user can describe an interrupt's active high/low polarity more easily. It helps for readability when one is comparing gpio configuration next to APIC configuration in different files. Additionally, the gpio APIC macros always use a LEVEL trigger in order to let the APIC handle the filtering of the IRQ on its own end. BUG=chrome-os-partner:54977 Change-Id: Id8fdcd98f0920936cd2b1a687fd8fa07bce9a614 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15644 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-13intel/amenia: Disable unused PCIe portsJagadish Krishnamoorthy
Disable PCIe A0, A1, A2, A3, B1 ports. Enable B0 port which is used for wifi. BUG=chrome-os-partner:54288 BRANCH=None TEST=lspci should show only PCIe B0 device Change-Id: I266d6eb7ddd56888f6b07b59681c2d9f0a6c0a9e Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/15599 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-13FSP1_0 does not support HAVE_ACPI_RESUMEKyösti Mälkki
FSP1_0 places romstage ram stack at fixed location of RAMTOP in low memory before returning to coreboot proper. There is no possibility of making a complete backup of RAMBASE..RAMTOP region and currently such backup is not even attempted. As a conclusion, S3 resume would always cause OS memory corruption. Change-Id: I5b9dd4069082e022b01b0d6a9ad5dec28a06e8b0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15576 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-12lib/selfboot: clear BSS segmentsAaron Durbin
For some reason the self loader wasn't clearing segments marked as BSS type. Other segments which weren't fully written by the file-backed content were being cleared up to the indicated memsize. Treat segments marked BSS similarly by clearing their content. Change-Id: I9296c11a89455a02e5dd18bba13d4911517c04f6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15603 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-12lib/selfboot: remove duplicate prog_set_area()Aaron Durbin
There were two successive calls to prog_set_area() which duplicated the same logic. Remove the unnecessary redundancy. Change-Id: I594577f8e7e78d403e7a5656f78e784e98c2c859 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15602 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-12lib/selfboot: don't open code linked list operationsAaron Durbin
The list insertion operations were open coded at each location. Add helper functions which provide the semantics needed by the selfboot code in a single place. Change-Id: Ic757255e01934b499def839131c257bde9d0cc93 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15601 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-12Documentation: Fix doxygen errorsMartin Roth
Change-Id: I195fd3a9c7fc07c35913342d2041e1ffef110466 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15549 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-12spike-riscv: Remove HTIF related codeJonathan Neuschäfer
The HTIF is deprecated and the newest RISC-V binutils don't know the mtohost/mfromhost CSRs anymore. The SBI implementation still needs to be restructured. Change-Id: I13f01e45b714f1bd919e27b84aff8db772504b1f Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15289 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2016-07-12google/reef: Add GPE routing settingsShaunak Saha
This patch sets the devicetree for gpe0_dw configuration and also configures the GPIO lines for SCI. EC_SCI_GPI is configured to proper value. BUG = chrome-os-partner:53438 TEST = Toggle pch_sci_l from ec console using gpioset command and see that the sci counter increases in /sys/firmware/acpi/interrupt and also 9 in /proc/interrupt Change-Id: If258bece12768edb1e612c982514ce95c756c438 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15556 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-12intel/amenia: Add GPE routing settingsShaunak Saha
This patch sets the devicetree for gpe0_dw configuration and also configures the GPIO lines for SCI. EC_SCI_GPI is configured to proper value. BUG = chrome-os-partner:53438 TEST = Toggle pch_sci_l from ec console using gpioset command and see that the sci counter increases in /sys/firmware/acpi/interrupt and also 9 in /proc/interrupt Change-Id: I3ae9ef7c6a3c8688bcb6cb4c73f5618e7cde342c Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15325 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-12soc/intel/apollolake: Add handler for SCIShaunak Saha
This patch adds the handler to enable bit for gpio_tier1_sci_en. gpio_tier1_sci_en enables the setting of the GPIO_TIER1_SCI_STS bit to generate a wake event and/or an SCI or SMI#. We are setting the bit for gpio_tier1_sci_en from the ASL code as OS clears this bit if set from BIOS. As per ACPI spec _GPE is defined as the Named Object that evaluates to either an integer or a package. If _GPE evaluates to an integer, the value is the bit assignment of the SCI interrupt within the GPEx_STS register of a GPE block described in the FADT that the embedded controller will trigger. FADT right now has no mechanism to acheive the same. Change-Id: I1e1bd3f5c89a5e6bea2d1858569a9d30e6da78fe Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15578 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-12soc/intel/quark: Set CBMEM top from HW registerLee Leahy
Properly obtain the top of memory address from the hardware registers set by FSP. TEST=Build and run on Galileo Gen2 Change-Id: I7681d32112408b8358b4dad67f8d69581c7dde2e Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15594 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-12soc/intel/quark: Add host bridge access supportLee Leahy
Add host bridge register access routines and macros. TEST=Build and run on Galileo Gen2 Change-Id: I52eb6a68e99533fbb69c0ae1e6d581e4c4fab9d2 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15593 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-12SPD: Add CAS latency 2Elyes HAOUAS
CAS latency = 2 support added for DDR2. Change-Id: I08d72a61c27ff0eab19e500a2f547a5e946de2f0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15439 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-12rockchip/rk3399: Fix pinctrl pull bias settingsShunqian Zheng
The pull bias settings for GPIO0_A, GPIO0_B, GPIO2_C and GPIO2_D are different from the other GPIO banks. This patch adds a callback function to get the GPIO pull value of each SoC(rk3288 and rk3399) so we can still use the common GPIO driver. BRANCH=none BUG=chrome-os-partner:53251 TEST=Jerry and Gru still boot Change-Id: I2a00b7ffd2699190582f5f50a1e21b61c500bf4f Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 46d5fa7297693216a2da9bcf15ccce4af796e80e Original-Change-Id: If53f47181bdc235a1ccfefeeb2a77e0eb0e3b1ca Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/358110 Original-Commit-Ready: Julius Werner <jwerner@chromium.org> Original-Tested-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/15587 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-12google/gru: Read RAM & board ids from the ADCShelley Chen
- Update so that the RAM id is read from ADC instead of hard-coded from the config array. - Update the boardid readings so that they are bucketed instead of within an error margin. BRANCH=None BUG=chrome-os-partner:54566,chrome-os-partner:53988 TEST=hexdump /proc/device-tree/firmware/coreboot/ram-code and boardid when OS boots up. Also verified that voltage read in debug output returns correct id. Change-Id: I963406d8c440cd90c3024c814c0de61d35ebe2fd Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 068705a38734d2604f71c8a7b5bf2cc15b0f7045 Original-Change-Id: I1c847558d54a0f7f9427904eeda853074ebb0e2e Original-Signed-off-by: Shelley Chen <shchen@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/356584 Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/15586 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-12google/gru: Enable coreboot read recovery eventShelley Chen
Enable reading of keyboard recovery host event from coreboot. BUG=None BRANCH=None TEST=esc+refresh+power combo and make sure you see recovery fw screen. Change-Id: I166619d6202e23569395434e9dc1adb2a6a53296 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: f9279c8c06abb170589b1b11bf5287fbf38c9905 Original-Change-Id: Id980c77c8d7695b2c1b3343d968ad2a302d42aaa Original-Signed-off-by: Shelley Chen <shchen@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/357841 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: https://review.coreboot.org/15585 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-12google/gru: enable EC software syncShelley Chen
Enable CONFIG_EC_SOFTWARE_SYNC. Crossystem needs this to get ec RW/RO info. BUG=chrome-os-partner:54566 BRANCH=None TEST=1. apreset from ec console. Check for "VbEcSoftwareSync() check for RW update" string in ap console. 2. Run "ectool version" from OS to check that RO/RW version are different and that we're in RW: RO version: kevin_v1.1.4818-8243672 RW version: kevin_v1.1.4762-1957187 Firmware copy: RW 3. Run crossystem ecfw_act. check for RW return value. Change-Id: If6524f2cca4a6223ab9704d0af827e8c1072670f Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 0deb0e1c69d6bf21acf7640bf76f9196e14437d7 Original-Change-Id: I0db8235cf7d472f0aa642eea1998282d010d3433 Original-Signed-off-by: Shelley Chen <shchen@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/357811 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15584 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-12rockchip/rk3399: initialize apll_bLin Huang
coreboot boots from the little core, and doesn't use the big core for now, but if apll_b is set to the default 24MHz, it will take a long time to enable the big core. This will cause a watchdog crash, so apll_b initialization to 600MHz needs to be done in coreboot. BRANCH=none BUG=chrome-os-partner:54817 TEST=Pick CL:353762 and see big CPU clocks look right TEST=Boot from Gru and see no cpufreq warnings Change-Id: Ie45cd2271555942e4321e9a9e523dc10f63d8107 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: Original-Change-Id: I20b8b591db3171e27740d85edce11f9e8797d849 Original-Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Original-Commit-Id: 16bc916174042620bebe19ae73d241002491aecc Original-Original-Change-Id: Id3487138b383b6643ba7e3ce1eae501a6622da10 Original-Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Original-Reviewed-on: https://chromium-review.googlesource.com/356399 Original-Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15583 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-12rockchip/rk3399: Use apll instead of apll_l defineLin Huang
Use the apll define instead of the apll_l define so it can be reused when setting apll_b. BRANCH=None BUG=None TEST=Boot from Gru Change-Id: Iebc4ce3b66a86c33653292340b9855265ac4fc07 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: eb578110d19a35ef04f8749fdc202055abd50fd1 Original-Change-Id: I63966e98af48eaf49837eb0b781eea001a376ef4 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/356398 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Original-Tested-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/15582 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-12vboot2: tpm2 factory initialization.Vadim Bendebury
This patch adds a TPM2 specific path in the vboot2 initialization sequence when the device is turned on in the factory for the first time, namely two secure NVRAM spaces are created, with different access privileges. The higher privilege space can be modified only be the RO firmware, and the lower privilege space can be modified by both RO and RW firmware. The API is being modified to hide the TPM implementation details from the caller. Some functions previously exported as global are in fact not used anywhere else, they are being defined static. BRANCH=none BUG=chrome-os-partner:50645 TEST=when this code is enabled the two secure spaces are successfully created during factory initialization. Original-Commit-Id: 5f082d6a9b095c3efc283b7a49eac9b4f2bcb6ec Original-Change-Id: I917b2f74dfdbd214d7f651ce3d4b80f4a18def20 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/353916 Original-Reviewed-by: Bill Richardson <wfrichar@chromium.org> Original-Reviewed-by: Darren Krahn <dkrahn@chromium.org> squashed: mock tpm: drop unused functions safe_write() and safe_define_space() functions are defined in secdata_mock.c, but not used in mocked TPM mode. The actual functions have been redefined as static recently and their declarations were removed from src/include/antirollback.h, which now causes compilation problems when CONFIG_VBOOT2_MOCK_SECDATA is defined. Dropping the functions from secdata_mock.c solves the problem. BRANCH=none BUG=none TEST=compilation in mock secdata mode does not fail any more. Original-Commit-Id: c6d7824f52534ecd3b02172cb9078f03e318cb2b Original-Change-Id: Ia781ce99630d759469d2bded40952ed21830e611 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/356291 Original-Tested-by: Caesar Wang <wxt@rock-chips.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Change-Id: Icb686c5f9129067eb4bb3ea10bbb85a075b29955 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/15571 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-12rockchip/rk3399: calculate clocks based on parent clock speedLin Huang
Currently aclkm pclkdbg atclk clocks use apll_l as a parent, but the apll_l frequency may change in firmware, so we need to caculate the div value based on the apll_l frequency. BRANCH=None BUG=chrome-os-partner:54376 TEST=Boot from Gru Change-Id: I2bd8886168453ce98efec58b5490c2430762769b Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 116ae863a504630e2aff056564836d84198fcae2 Original-Change-Id: I7e3a5d9e3f608ddf15592d893117c92767fcd015 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/356397 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15581 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-12rockchip/rk3399: Clean up comments in sdram.cDerek Basehore
Cleans up the comments in sdram.c to make them consistent. BRANCH=none BUG=none TEST=make sure gru/kevin build and boot also, run "stressapptest -M 1024 -s 3600" to make sure it passes Change-Id: I1daf72b847374d549389bacd2fa0a9f8f231b190 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 63a224d6f4b0e4d13bc372c05c4b9196895d553f Original-Change-Id: Iaf8a32cfe2b22c4ccff71952f90d162ad8c2d3e7 Original-Signed-off-by: Derek Basehore <dbasehore@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/355665 Original-Reviewed-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/15579 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-12tpm: report firmware versionVadim Bendebury
Some devices allow to retrieve firmware version by reading the same 4 byte register repeatedly until the entire version string is read. Let's print out TPM firmware version when available. Just in case something goes wrong limit the version string length to 200 bytes. CQ-DEPEND=CL:355701 BRANCH=none BUG=chrome-os-partner:54723 TEST=built the new firmware and ran it on Gru, observed the following in the coreboot console log: Connected to device vid:did:rid of 1ae0:0028:00 Firmware version: cr50_v1.1.4792-7a44484 Original-Commit-Id: 1f54a30cebe808abf1b09478b47924bb722a0ca6 Original-Change-Id: Idb069dabb80d34a0efdf04c3c40a42ab0c8a3f94 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/355704 Original-Reviewed-by: Scott Collyer <scollyer@chromium.org> Squashed with: tpm: use 4 byte quantities when retrieving firmware version The CR50 device is capable of reporting its firmware version in 4 byte quantities, but the recently introduced code retrieves the version one byte at a time. With this fix the version is retrieved in 4 byte chunks. BRANCH=none BUG=none TEST=the version is still reported properly, as reported by the AP firmware console log: localhost ~ # grep cr50 /sys/firmware/log Firmware version: cr50_v1.1.4804-c64cf24 localhost ~ # Original-Commit-Id: 3111537e7b66d8507b6608ef665e4cde76403818 Original-Change-Id: I04116881a30001e35e989e51ec1567263f9149a6 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/356542 Original-Reviewed-by: Andrey Pronin <apronin@chromium.org> Change-Id: Ia9f13a5bf1c34292b866f57c0d14470fe6ca9853 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/15573 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-12Gale: Add LED support.Suresh Rajashekara
Reusing the LED patterns as it was defined for Storm/WW/Platform. BUG=b:29051518 TEST=After about 3 seconds of powering on the device different colors should be seen at the LED ring, depending on the state of the device. Alternatively, move the device to different states manually by appropriate actions (like dev mode, rec mode etc) and observe the colors. BRANCH=None Change-Id: I6f1b23fee15747a402e209a2d06f8794bbc2c5a1 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: be1194b095d9a5cf269710c43a27a5afb3e87b29 Original-Change-Id: Ie82d4e148025c0040cdb26f53f028d9b4cbe2332 Original-Signed-off-by: Suresh Rajashekara <sureshraj@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/355200 Original-Commit-Ready: Suresh Rajashekara <sureshraj@chromium.org> Original-Tested-by: Suresh Rajashekara <sureshraj@chromium.org> Original-Reviewed-by: Suresh Rajashekara <sureshraj@chromium.org> Reviewed-on: https://review.coreboot.org/15572 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-11tpm2: add marshaling/unmarshaling layerVadim Bendebury
TPM commands need to be serialized (marshaled) to be sent to the device, and the responses need to be de-serialized (unmarshaled) to be properly interpreted by upper layers. This layer does not exist in TPM1.2 coreboot implementation, all TPM commands used there were hardcoded as binary arrays. Availability of the marshaling/unmarshaling layer makes it much easier to add new TPM commands to the code. Command and response structures used in these functions are defined in Parts 2 and 3 of the TCG issued document Trusted Platform Module Library Family "2.0" Level 00 Revision 01.16 October 30, 2014 BRANCH=none BUG=chrome-os-partner:50645 TEST=with the rest of the patches applied it is possible to successfully initialize firmware and kernel TPM spaces. Change-Id: I80b3f971e347bb30ea08f820ec3dd27e1656c060 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 0782d9d452efb732e85d1503fccfcb4bf9f69a68 Original-Change-Id: I202276ef9a43c28b5f304f901ac5b91048878b76 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/353915 Original-Reviewed-by: Bill Richardson <wfrichar@chromium.org> Original-Reviewed-by: Darren Krahn <dkrahn@chromium.org> Reviewed-on: https://review.coreboot.org/15570 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-07-11tpm2: implement tlcl layerVadim Bendebury
This is the first approximation of implementing TPM2 support in coreboot. It is very clearly incomplete, some of the larger missing pieces being: - PCR(s) modification - protection NVRAM spaces from unauthorized deletion/modification. - resume handling - cr50 specific factory initialization The existing TPM1.2 firmware API is being implemented for TPM2. Some functions are not required at all, some do not map fully, but the API is not yet being changed, many functions are just stubs. An addition to the API is the new tlcl_define_space() function. It abstracts TMP internals allowing the caller to specify the privilege level of the space to be defined. Two privilege levels are defined, higher for the RO firmware and lower for RW firmware, they determine who can write into the spaces. BRANCH=none BUG=chrome-os-partner:50645 TEST=with the rest of the patches applied Kevin/Gru devices can initialize and use firmware and kernel spaces Change-Id: Ife3301cf161ce38d61f11e4b60f1b43cab9a4eba Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: bcc8e62604c705798ca106e7995a0960b92b3f35 Original-Change-Id: Ib340fa8e7db51c10e5080973c16a19b0ebbb61e6 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/353914 Original-Commit-Ready: Martin Roth <martinroth@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15569 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-07-11tpm: use proper locality zero SPI bus addressesVadim Bendebury
The "PC Client Protection Profile for TPM 2.0" document defines SPI bus addresses for different localities. That definition is not honored in the cr50 implementation, this patch fixes it: locality zero register file is based off 0xd40000. BRANCH=none BUG=chrome-os-partner:54720 TEST=with the fixed cr50 image and the rest of TPM2 initialization patches applied factory initialization sequence on Gru succeeds. Change-Id: I49b7ed55f0360448b9a6602ebd31a3a531608da3 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 43344fff5d58ec235e50030413fc38c98dd0a9a1 Original-Change-Id: I2de6fa6c05d3eca989d6785228d5adde1f2a7ab7 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/355620 Original-Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://review.coreboot.org/15568 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-07-10intel post-car: Consolidate choose_top_of_stack()Kyösti Mälkki
Change-Id: I2c49d68ea9a8f52737b6064bc4fa703bdb1af1df Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15463 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-10AMD k8 fam10: Drop excessive spinlock initializationKyösti Mälkki
If CAR migration operations unintentionally set the lock, BSP would have got stuck on printk() calls above already. Change-Id: I35155ebcb00475a0964fc639ee74ad2755127740 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15589 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-07-10Romstage spinlocks require EARLY_CBMEM_INITKyösti Mälkki
The lock stores need to migrate from CAR to CBMEM. Change-Id: I3cffd14bdfc57d5588d0f24afe00e0f9891bfe5a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15588 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-10AMD k8 fam10: Fix romstage handoffKyösti Mälkki
It is not possible for cbmem_add() to complete succesfully before cbmem_recovery() is called. Adding more tables on S3 resume path is also not possible. Change-Id: Ic14857eeef2932562acee4a36f59c22ff4ca1a84 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15472 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-10google/chromeec: Update EC command headerGwendal Grignou
In particular, update host_event the original value for MKBP was not set in ToT. CQ-DEPEND=CL:353634 BUG=b:27849483 BRANCH=none TEST=Compile on Samus. Tested in Cyan branch. Change-Id: I0184e4f0e45c3321742d3138ae0178c159cbdd0a Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: cc6750b705300f5b94bf23fe5485d6e7a5f9e327 Original-Change-Id: I60df65bfd4053207fa90b1c2a8609eec09f3c475 Original-Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/354040 Reviewed-on: https://review.coreboot.org/15567 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-10gru: include ram_code in coreboot tableVadim Bendebury
This is needed to ensure that the ram-code node is included in the device tree by depthcharge. BRANCH=none BUG=chrome-os-partner:54566 TEST=built updated firmware, booted on kevin into Linux shell, checked the device tree contents: localhost ~ # od -tx1 /proc/device-tree/firmware/coreboot/ram-code 0000000 00 00 00 01 0000004 localhost # Change-Id: Ibe96e3bc8fc0106013241738f5726783d74bd78b Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 53c002114f7044b88728c9e17150cd3a2cf1f80f Original-Change-Id: Iba573fba9f9b88b87867c6963e48215e254319ed Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/354705 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15566 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-09nb/intel/x4x: Fix underclocking of 800MHz DDR2 RAMDamien Zammit
Previously, any 800MHz DIMMs were being slowed to 667MHz for no reason other than there was a bug in the maximum frequency detection code for the MCH. Change-Id: Id6c6c88c4a40631f6caf52f536a939a43cb3faf1 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/15257 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-08soc/intel/quark: Pass in the memory initialization parametersLee Leahy
Specify the memory initialization parameters in mainboard/intel/galileo/devicetree.cb. Pass these values into FSP to initialize memory. TEST=Build and run on Galileo Gen2 Change-Id: I83ee196f5fb825118a3a74b61f73f3728a1a1dc6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15260 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-08mainboard/intel/galileo: Gen1 - Set correct I2C scriptsLee Leahy
Switch the I2C scripts to properly match the I2C address selection for the Galileo Gen1 board. TEST=Build an run on Galileo Gen1 Change-Id: I9fc8b59a3a719abb474c99a83e0d538794626da9 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15258 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-08soc/intel/quark: Remove use of PDAT.bin fileLee Leahy
Remove the unused Kconfig values which specify the PDAT file, its location and inclusion into the coreboot file system. Remove the code in romstage which locates the pdat.bin file. TEST=Build and run on Galileo Gen2 Change-Id: I397aa22ada6c073c60485a735d6e2cb42bfd40ab Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15205 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-08soc/intel/apollolake: Include gpio_defs headerHarsha Priya
Add the gpio_defs.h reference in chip.h to enable reef and amenia devicetree.cb to use the definitions from gpio_defs.h. Change-Id: I333d4e810e42309ac76dd90c19f05cf3e3a517b1 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/15550 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-08mainboard/google/reef: Use device driver for DA7219 configurationDuncan Laurie
Use the device driver for DA7219 device configuration in the SSDT and remove the static copy in the DSDT. Tested on reef to ensure that the generated SSDT contents are equivalent to the current DSDT contents. Change-Id: I288eb05d0cb3f5310c4dca4aa1eab5a029f216af Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15539 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-08drivers/i2c/da7219: Add driver for generating device in SSDTDuncan Laurie
Add a device driver to generate the device and required properties into the SSDT. This driver uses the ACPI Device Property interface to generate the required parameters into the _DSD table format expected by the kernel. This was tested on the reef mainboard to ensure that the SSDT contained the equivalent parameters that are provided by the current DSDT object. Change-Id: Ia809e953932a7e127352a7ef193974d95e511565 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15538 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-08acpi: Change device properties to work as a treeDuncan Laurie
There is a second ACPI _DSD document from the UEFI Forum that details how _DSD style tables can be nested, creating a tree of similarly formatted tables. This document is linked from acpi_device.h. In order to support this the device property interface needs to be more flexible and build up a tree of properties to write all entries at once instead of writing each entry as it is generated. In the end this is a more flexible solution that can support drivers that need child tables like the DA7219 codec, while only requiring minor changes to the existing drivers that use the device property interface. This was tested on reef (apollolake) and chell (skylake) boards to ensure that there was no change in the generated SSDT AML. Change-Id: Ia22e3a5fd3982ffa7c324bee1a8d190d49f853dd Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15537 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-08google/reef: Add Maxim98357a supportHarsha Priya
Adds Maxim98357a support for reef using the generic driver in drivers/generic/max98357 Change-Id: I333d4e810e42309ac76dd90c19f05cf3e3a517e0 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/15435 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-08siemens/mc_bdx1: Move SCI to IRQ 10Werner Zeh
IRQ 9 is used for different purpose on this board so move SCI away to IRQ10. Change-Id: I107bfb5ec8cd05f844ee75550779be7746e77a88 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15563 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-07mainboard/google/reef: apply EVT board changesAaron Durbin
Based on the board revision apply the correct GPIO changes. The only differences are the addition of 2 peripheral wake signals and a dedicated peripheral reset line. BUG=chrome-os-partner:54959,chrome-os-partner:54960,chrome-os-partner:54961 BRANCH=None TEST=Built and tested on reef. Change-Id: I9cac82158e70e0af1b454ec4581c2e4622b95b4b Signed-off-by: Aaron Durbin <adurbin@chromuim.org> Reviewed-on: https://review.coreboot.org/15562 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-07mainboard/google/reef: add board_id() supportAaron Durbin
The board build version is provided by the EC on reef. Provide the necessary functional support for coreboot to differentiate the board versions. BUG=chrome-os-partner:54959,chrome-os-partner:54960,chrome-os-partner:54961 BRANCH=None TEST=Built and tested on reef. Change-Id: I1b7e8b2f4142753cde736148ca9495bcc625f318 Signed-off-by: Aaron Durbin <adurbin@chromuim.org> Reviewed-on: https://review.coreboot.org/15561 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-07mainboard/google/reef: add memory SKU id supportAaron Durbin
While the proto boards didn't have a memory SKU notion the EVT boards do. Therefore, provide support for selecting the proper memory SKU information based on the memory id straps. This works on EVT boards because the pins used for the strapping weren't used on proto. However, internal pullups need to be enabled so that proto boards read the correct id. BUG=chrome-os-partner:54949 BRANCH=None TEST=Built and used on reef for memory config. Change-Id: I8653260e5d1b9adc83b78ea2770c683b72535e11 Signed-off-by: Aaron Durbin <adurbin@chromuim.org> Reviewed-on: https://review.coreboot.org/15560 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-07soc/intel/apollolake: add LPDDR4 sku selection supportAaron Durbin
Instead of having all the mainboards put similar logic into their own code provide common mechanism for memory SKU selection. A function, meminit_lpddr4_by_sku(), is added that selects the proper configuration based on the SKU id and configuration passed in. LPDDR4 speed as well as DRAM device density configuration is associated for each logical channel per SKU id. BUG=chrome-os-partner:54949 BRANCH=None TEST=Built and used on reef for memory config. Change-Id: Ifc6a734040bb61a58bc3d4c128a6420a71245c6c Signed-off-by: Aaron Durbin <adurbin@chromuim.org> Reviewed-on: https://review.coreboot.org/15559 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-07soc/intel/apollolake: make internal pulls weak for gpio inputsAaron Durbin
The internal pulls for gpio_input_pullup() and gpio_input_pulldown() were using fairly strong pulls. Weaken them so that external pulls can override the internal ones. This matches the current assumptions of lib/gpio.c. BUG=chrome-os-partner:54949 BRANCH=None TEST=Built and used on reef for memory config. Change-Id: Ifda1d04d40141325f78db277eb0bd55574994abf Signed-off-by: Aaron Durbin <adurbin@chromuim.org> Reviewed-on: https://review.coreboot.org/15558 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-07lib/gpio: add pullup & pulldown gpio_base2_value() variantsAaron Durbin
Provide common implementations for gpio_base2_value() variants which configure the gpio for internal pullups and pulldowns. BUG=chrome-os-partner:54949 BRANCH=None TEST=Built and used on reef for memory config. Change-Id: I9be8813328e99d28eb4145501450caab25d51f37 Signed-off-by: Aaron Durbin <adurbin@chromuim.org> Reviewed-on: https://review.coreboot.org/15557 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-07acpigen_write_package: Return pointer to package element counterDuncan Laurie
Have acpigen_write_package() return a pointer to the package element counter so it can be used for dynamic package generation where needed. Change-Id: Id7f6dd03511069211ba3ee3eb29a6ca1742de847 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15536 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-07soc: Remove newline from `CHIP_NAME`Paul Menzel
The name must not terminated with a newline character `\n` as it would make it hard to use it strings. So, remove the newline from the two SoCs with it. Change-Id: I7570442b38a455e7c497d7f461c208fb0a88296d Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/15540 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-07lenovo/t530: Don't enforce native gfx initAlexander Couzens
Change-Id: I6d51f46240c62fcd6089411e8681e0b6e7d5bfe4 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/15222 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-07lenovo/t530: add VGA device ID 8086,0106Alexander Couzens
Change-Id: I3cffe9d832edbbea79cabca639d9d920b7ffcf9a Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/8178 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-07-07nyan: Avoid running early_mainboard_init twice in vboot contextPaul Kocialkowski
A call to early_mainboard_init is already present in verstage, thus it is only necessary to call it from romstage when not in vboot context. Change-Id: I2e0b5a369c5fb24efae4ac40d83a31f5cf4a078d Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/15450 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-07tegra124: Build verstage when CHROMEOS is selectedPaul Kocialkowski
This includes the proper Kconfig options (based on the chromium os coreboot configuration) for setting up verstage on tegra124 devices. Change-Id: I4a1976ff684a417cae6fa718ef53cad763cee47d Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/15451 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-07-07intel/sandybridge: read correct leaf for cpu familyRyan Salsamendi
Reading cpuid leaf 0 is incorrect for testing cpu family. Use leaf 1 instead. See Intel SDM 2a Table 3-17. Change-Id: Ib2c95cdd1fb93db06a08ecd7266f6b88700caf83 Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-on: https://review.coreboot.org/15346 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-07-07board/intel/amenia: Enable LPSS S0ixHannah Williams
This setting will enable S0ix for LPSS Change-Id: Ie07cb8437d0cee61a03638aa980fd3322fef0c4e Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15056 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-07siemens/mc_bdx1: Set up opcode menu for SPI controllerWerner Zeh
Since SPI controller opcode registers are locked by FSP, they need to be initialized to a known good state before ReadyToBoot event and after every SPI flash access (e.g. for MRC cache) has been finished in order to enable the OS to use SPI controller without constraints. Change-Id: I0a66344cd44e036c3999ae98d539072299cf5112 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15547 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-07-07intel/fsp_broadwell_de: Do not use hard coded SCI IRQ for ACPIWerner Zeh
The SCI interrupt can be routed to different IRQs using ACPI control register. Instead of using hard coded IRQ9 for ACPI table generation read back the register and return the used IRQ number. This way SCI IRQ can be modified (e.g. for a given mainboard) and ACPI tables will remain consistent. Change-Id: I534fc69eb1df28cd8d733d1ac6b2081d2dcf7511 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15548 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: York Yang <york.yang@intel.com>
2016-07-06siemens/mc_bdx1: Add usage of Siemens NC FPGA driverWerner Zeh
Enable NC FPGA driver for this mainboard. Change-Id: I87b6b10038f3d161a25b2008b7ea44b5627cca43 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15545 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-06siemens/nc_fpga: Add driver for Siemens NC FPGAWerner Zeh
Add driver code to initialize Siemens NC FPGA as PCI device. Beside some glue logic it contains a FAN controller and temperature monitor. Change-Id: I2cb722a60081028ee5a8251f51125f12ed38d824 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15543 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-06PCI: Use PCI_DEVFN macro instead of DEV_FUNCWerner Zeh
There are several different macros available to convert a PCI device and function to a single 8 bit value. One is PCI_DEVFN and is defined in device/pci_def.h. The other is DEV_FUNC and is defined in several intel fsp based chipset implementations. In fsp_broadwell_de DEV_FUNC is even used without being defined at all. This patch unifies the situation so that only PCI_DEVFN is used. Change-Id: Ia1c6d7f3683badc66d15053846936d88aa836632 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15546 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-07-05siemens/mc_bdx1: Set up MAC address for available i210 MACsWerner Zeh
Enable the usage of DRIVER_INTEL_I210 and provide a function to search for a valid MAC address for all i210 devices using hwilib. Change-Id: Ic0f4f1579364cf5b0111334a05a8a0926785318b Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15517 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-05intel/i210: Change API for function mainboard_get_mac_address()Werner Zeh
The function mainboard_get_mac_address() is used to get a MAC address for a given i210 PCI device. Instead of passing pure numbers for PCI bus, device and function pass the device pointer to this function. In this way the function can retrieve the needed values itself as well as have the pointer to the device tree so that PCI path can be evaluated there. Change-Id: I2335d995651baa5e23a0448f5f32310dcd394f9b Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15516 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>