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2015-04-22nvidia/tegra*: check bus number for i2c driver APIsYen Lin
BRANCH=None BUG=None TEST=emerge-foster coreboot Change-Id: I383d2b5f269ed348065a9f270f80514a2ff45742 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fba6973c304e1612a9869c2e78a08650b6e5fe66 Original-Change-Id: I6d5d0098db8dbfb21529bf112a04b97779a0f381 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/264027 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9913 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22arch/armv7: Add API to disable MMU pages.Deepa Dinamani
Disables 4K regions in the MMU table. Assumes that the region is already accounted for by the first level page table entry. BRANCH=storm BUG=chrome-os-partner:24786 TEST=verified mmu.pagetable.list output for Storm: _______address___________|_physical________________|sec|_d_|_size____|_permissions____________________|_glb|_shr|_pageflags______________________| C:00000000--00000FFF| | | | | | | | | C:00001000--000FFFFF| A:00:00001000--000FFFFF| ns| 00| 00001000| P:readwrite U:readwrite notexec| yes| no | strongly ordered | C:00100000--29FFFFFF| A:00:00100000--29FFFFFF| ns| 00| 00100000| P:readwrite U:readwrite notexec| yes| no | strongly ordered | C:2A000000--2A05FFFF| A:00:2A000000--2A05FFFF| ns| 00| 00001000| P:readwrite U:readwrite exec | yes| no | write-back/no write alloc | C:2A060000--2A0FFFFF| A:00:2A060000--2A0FFFFF| ns| 00| 00001000| P:readwrite U:readwrite notexec| yes| no | strongly ordered | C:2A100000--3FFFFFFF| A:00:2A100000--3FFFFFFF| ns| 00| 00100000| P:readwrite U:readwrite notexec| yes| no | strongly ordered | C:40000000--59FFFFFF| A:00:40000000--59FFFFFF| ns| 00| 00100000| P:readwrite U:readwrite exec | yes| no | write-back/no write alloc | C:5A000000--5A1FFFFF| A:00:5A000000--5A1FFFFF| ns| 00| 00100000| P:readwrite U:readwrite notexec| yes| no | strongly ordered | C:5A200000--7FFFFFFF| A:00:5A200000--7FFFFFFF| ns| 00| 00100000| P:readwrite U:readwrite exec | yes| no | write-back/no write alloc | C:80000000--FFFFFFFF| | | | | | | | | Change-Id: Ib603da91966cc4c70ea9d5fee04f1e9890d0bb93 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 67db80e6476d8ed35f0a9d1e0d3ca03612b9d9be Original-Change-Id: I6b149c7edbd975231b783cc53ddb63cf2e94052c Original-Signed-off-by: Vikas Das <vdas@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/253800 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Tested-by: Deepa Dinamani <deepad@codeaurora.org> Original-Commit-Queue: Deepa Dinamani <deepad@codeaurora.org> Reviewed-on: http://review.coreboot.org/9912 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22rockchip/rk3288: Fix operator precedence error in LPDDR initJulius Werner
Upstream coreboot regularly runs Coverity over the code base. Turns out that's a good idea since it's really easy to screw yourself over with a missing parenthesis and some unfortunately deceptive line breaking. This patch fixes a bug in LPDDR3 initialization due to an incorrect operator precedence assumption ( ?: does not bind stronger than | ). In effect, instead of setting MR11[1:0] to 0b11 or 0b00 based on ODT, we're unconditionally setting MR0[1:0] to 0b11. Thankfully, MR0[1:0] seems to contain read-only bits so this might have not been a problem when ODT is off (which is currently true for all LPDDR boards). Also adding a redundant LPDDR_OP() around the 0 to make the intent clearer and changing 3 and 0 to 0x3 and 0x0 to make it more obvious that these are bit masks (right?). BRANCH=veyron BUG=None TEST=Running reboot loop on a Minnie, looks good so far... Change-Id: I06464aaa57e693b1973846a5771162244f7a1c57 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan Original-Commit-Id: 5bd9eba39fb7b0f940fead963bbc1878b031b2cb Original-Change-Id: I701ce059472078b5de09a45dd31f54b65a51e641 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/264135 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Jinkun Hong <jinkun.hong@rock-chips.com> Original-Tested-by: Jinkun Hong <jinkun.hong@rock-chips.com> Reviewed-on: http://review.coreboot.org/9911 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22chromeec: lpc: Add variant MEC IOShawn Nematbakhsh
MEC cannot access memmap-range data directly though LPC and instead must access through its EMI unit. BUG=chrome-os-partner:38224 TEST=Verify host command functionality on glower. BRANCH=None Change-Id: If98d425014a894ddeafad4268f92af5860878522 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 58ed3c50ab97ca1e172d5cdc00f4cd8e069e565c Original-Change-Id: I32b897836d28ef4f3b3aa5f81b9023f2ceb629c8 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/263611 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9910 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22chromeec: lpc: Read / write IO ports through common functionsShawn Nematbakhsh
Rather than calling inb + outb directly, access the ports through common functions. This is in preparation for alternative access modes required by certain new embedded controllers. BUG=chrome-os-partner:38224 TEST=Manual on Samus. Verify system boots cleanly in normal mode. BRANCH=None Change-Id: I98783ff67a37d970019683bb589825bc5d68c033 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 25afa3f95183d8cf2e9a35272c77e92fbc6ee030 Original-Change-Id: Ic9d8f7f5c5d392212e39db28ebceea461d46f796 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/263571 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9909 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22broadcom/cygnus: Implement I2C driverAnatol Pomazau
BUG=chrome-os-partner:35810 BRANCH=purin TEST=Enable I2C1, reset devboard codec, read a register. Here is the code that demonstrates how I2C works: i2c_init(1, 100*KHz); mdelay(50); int rc = i2c_writeb(1, 0x18, 1, 0x80); // reset codec printk(BIOS_INFO, "I2C reset rc=%d\n", rc); mdelay(50); uint8_t data = 0; rc = i2c_readb(1, 0x18, 43, &data); printk(BIOS_INFO, "I2C read rc=%d data=%x\n", rc, data); // data == 0x80 Change-Id: I0d202f8b0375b5ccd9f71b23fb0cadd5a70ae779 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6bbe9afe3dccd104f39c2c286d3765a28ea20141 Original-Signed-off-by: Anatol Pomazau <anatol@google.com> Original-Reviewed-on: https://chrome-internal-review.googlesource.com/195706 Original-Reviewed-by: Daisuke Nojiri <dnojiri@google.com> Original-Reviewed-by: Anatol Pomazau <anatol@google.com> Original-Commit-Queue: Anatol Pomazau <anatol@google.com> Original-Tested-by: Anatol Pomazau <anatol@google.com> Original-Change-Id: I178acef9de18fa854983294edcd2c05886795e2a Original-Reviewed-on: https://chromium-review.googlesource.com/263496 Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Trybot-Ready: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: http://review.coreboot.org/9908 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22broadcom/cygnus: Enable gpio on romstageIcarus Chau
BUG=chrome-os-partner:35936 BRANCH=broadcom-firmware TEST=When enable configuration CYGNUS_GPIO_TEST, print on console: Start gpio test... [gpio_crmu] gpio:0 set input [gpio_crmu] gpio:0 set pullup:0 GPIO get 170=0 gpio request enable pin=64 offset=0x1c .... GPIO set 69=1 [gpio_asiu] gpio:45 set, value:0 GPIO set 69=0 Gpio test completed... Additional test: Measure on GPIO 69 to confirm the voltage change. Apply voltage on AON_GPIO0 to check reading. Change-Id: I634cffccc7f0fa198317a92e3f1670ae6828892e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4784e5d88b9f7acb70bd6f6b12b1096f092f34b8 Original-Signed-off-by: Icarus Chau <ichau@broadcom.com> Original-Reviewed-on: https://chrome-internal-review.googlesource.com/204537 Original-Reviewed-by: Daisuke Nojiri <dnojiri@google.com> Original-Change-Id: Ia4f833be80d7844c2d014c9ffcf587d385e7766c Original-Reviewed-on: https://chromium-review.googlesource.com/263495 Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Trybot-Ready: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: http://review.coreboot.org/9907 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22switch mainboards over to use BOARD_ID_AUTOStefan Reinauer
This patch switches the mainboards with board id straps to use BOARD_ID_AUTO instead of BOARD_ID_SUPPORT. On urara, which does not have those straps, the option is removed. (And re-added for urara derivatives through setting the config option BOARD_ID_MANUAL BRANCH=none BUG=chrome-os-partner:37593 TEST=emerg-nyan_big coreboot, emerge-urara coreboot, emerge-buranku coreboot Change-Id: I5ac4024c6f1f9b9d7a5179d88722c69b23b82bbd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 22a470698f9c9ed275aa8150a5bb8d8cf368b050 Original-Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Change-Id: I48c291ad6f255a28c833bebc2638bfafa2782e74 Original-Reviewed-on: https://chromium-review.googlesource.com/262935 Original-Reviewed-by: Vadim Bendebury <vbendeb@google.com> Reviewed-on: http://review.coreboot.org/9906 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22build system: add manual board id supportStefan Reinauer
This patch adds manual board id support to coreboot and selects manual board ids vs automatic (ie strap based) where appropriate in the mainboards. CQ-DEPEND=CL:262935 BRANCH=none BUG=chrome-os-partner:37593 TEST=emerge-urara coreboot, see no board_id file emerge-buranku coreboot, see board_id file Change-Id: Ia04e5498a01f35c5418698ecaf3197f56415e789 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3bdb1fa092005be24de9fc68998053982648da85 Original-Change-Id: I4f0820233a485bf92598a739b81be2076d4e6ae7 Original-Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/262745 Original-Reviewed-by: Vadim Bendebury <vbendeb@google.com> Reviewed-on: http://review.coreboot.org/9905 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22device: Add class and subclass name supportLee Leahy
Add support to display class and subclass names for PCI devices. BRANCH=none BUG=None TEST=Build and run on strago/cyan. Change-Id: I5136fae45b8a1cd02541f233d29a246cdfcd8331 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a7c9b0d7201b09a06ea32f0db84187d15f767c80 Original-Change-Id: Ibf2ee89dd84040ca6ab0e52857a69f7ed0c28f37 Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/263342 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/9901 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22Kconfig: Don't select GENERIC_GPIO_LIB in BOARD_ID_SUPPORTStefan Reinauer
The code guarded by BOARD_ID_SUPPORT does not use this library. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> BRANCH=none BUG=none TEST=emerge-storm coreboot succeeds in building an image. Change-Id: If8c5c326265441f0c10999e3882706432139fd89 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f49b89e0b03f482a30dc652e5956494fb994cc70 Original-Change-Id: Ie2cd2cd049fdb20fa5cc368bee08babd3f7a551c Original-Reviewed-on: https://chromium-review.googlesource.com/262744 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Original-Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/9900 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22soc: select generic gpio lib on (almost) all non-x86 SOCsStefan Reinauer
BOARD_ID functionality is not what requires the GPIO lib, but it is the mainboard specific implementations that do. The option essentially says whether the SoC provides <soc/gpio.h> (with the interface required by the common GPIO code). Right now, x86 and Samsung's Exynos SOCs don't have support for this interface. So this should be selected by the SOC, not by BOARD_ID_SUPPORT. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> BUG=none BRANCH=none TEST=emerge-storm coreboot still successfully compiled an image Change-Id: I0ce2bd7ce023f22791d31a6245833b61135504b3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0dd4dea521372194eedf11b077d95fd3b15ad9f7 Original-Change-Id: I3dea6c2fb42a23fcb9d384c3bbfa7fc8e217be2d Original-Reviewed-on: https://chromium-review.googlesource.com/262743 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9899 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22arm64: Correct shareability option for normal memoryFurquan Shaikh
In order to allow proper working of caches, set the correct shareability option for normal memory. BUG=chrome-os-partner:38222 BRANCH=None TEST=Compiles successfully for foster and SMP works. Change-Id: I5462cb0a2ff94a854f71f58709d7b2e8297ccc44 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e092916780716ac80c3608c1bd8ca2901fbb3bd1 Original-Change-Id: Idd3c096a004d76a8fd75df2a884fcb97130d0006 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/262992 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9898 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22google/urara: retrieve network device information from VPDVadim Bendebury
Invoke the function which copies MAC addresses from VPD into the coreboot table and calibration data into CBMEM. BRANCH=none BUG=chrome-os-partner:36584 TEST=with the rest of the patches applied observed that the MAC addresses from VPD get copied into the appropriate kernel device tree nodes. Change-Id: I68e2b73520853ef2d3249ca12ee87669fd01f442 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 12f935098c50e2df345748d3b71cee2152acd422 Original-Change-Id: I6e1483d33480d13380ade2dddae6c92fd3f1f881 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/262844 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9897 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22vpd: process WiFi MACs along with ethernet MACsVadim Bendebury
coreboot is expected to read all MAC addresses from the VPD and put them in the coreboot table entry, depthcharge is expected to associate different MAC addresses with different kernel device tree nodes. This patch adds processing of wifi_macX keys. The order of MAC addresses in the coreboot table is such that the wifi_macX entries follow ethrnet_macX entries, ordered by X. BRANCH=none BUG=chrome-os-partner:36584 TEST=with the rest patches applied verified the contents of the kernel device tree on an urara board. Change-Id: I6523e168d2fea201a4956bc2a2d605b07ddac452 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 36c12ee1d3ce9d2797902f0e098651067c2283ed Original-Change-Id: Ib87e4815243f34ab258325839cbc12d16120bf89 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/262843 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9896 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22vpd: decode calibration data into binaryVadim Bendebury
The preferred way of communicating WiFi calibration data to the kernel is binary blob. But this data is stored in the VPD, and must be in ASCII, so it is encoded using base64. With the recent addition of the bas64 decoder it is possible to convert the VPD representation to the form preferred by the kernel. BRANCH=none BUG=chromium:450169 TEST=with the rest of the patches applied verified that on both storm and urara the device tree contains the required binary data. Change-Id: I89da94bb425767eedc5e2d576e507663afad65ed Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c2ae38ded24394e0640b5d077e2231cf956397c5 Original-Change-Id: If8a7d0883ea8bb21a13bf203b25ee9f8a08903a9 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/262842 Reviewed-on: http://review.coreboot.org/9895 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22imgtec/pistachio: increase RAM CBFS cache sizeVadim Bendebury
CBFS cache use is very close to the limit, does not allow to read much more from CBFS. BRANCH=none BUG=chrome-os-partner:36586 TEST=the upcoming patches do not fail due to the lack of room in CBFS cache any more Change-Id: I8e784891e59ca284b3bd82557c2114a2f450d8a3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c94d55c8042db81c1eb0c10d5f24883e00cdc19a Original-Change-Id: Ic09dbd5b4a0e165ccef396ff8a9e21b12c49b705 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/263268 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9894 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22chromeec: Access ID + flags through ACPI I/O portsShawn Nematbakhsh
If CONFIG_EC_GOOGLE_CHROMEEC_ACPI_MEMMAP is set, access to memmap data should go through the ACPI CMD / DATA ports. BUG=chrome-os-partner:38224 TEST=Manual on Samus. Define EC_GOOGLE_CHROMEEC_ACPI_MEMMAP. Verify system boots cleanly. BRANCH=None Change-Id: I9d19704df259f5a25e04a9b07b23968e93fe6302 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d0b59b040a7889d2d1bd6eeaf57dd960bd29927d Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Change-Id: I405e28828457a1fd83a7ece7192a7e7d0a37be95 Original-Reviewed-on: https://chromium-review.googlesource.com/262932 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9893 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22lib: add base64 decoderVadim Bendebury
It became necessary to decode base64 data retrieved from VPD and convert it into binary for inclusion in the device tree. The patch introduces the decoder function based on the description found in http://en.wikipedia.org/wiki/Base64. An open source implementation from http://base64.sourceforge.net was considered, in the end the only thing borrowed from it is the table to translate base64 ascii characters into numbers in 0..63 range. BRANCH=none BUG=chromium:450169 TEST=created a test harness generating random contents of random size (in 8 to 32766 bytes range), then converting the contents into base64 using the Linux utility, and then converting it back to binary using this function and comparing the results. It succeeded 1700 iterations before it was stopped. Change-Id: I502f2c9494c99ba95ece37a7220c0c70c4755be2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6609f76e1559d3cdd402276055c99e0de7da27c8 Original-Change-Id: I5ed68af3a4daead50c44ae0f0c63d836f4b66851 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/262945 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9892 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22google/veyron_*: Increase SPI flash frequency to 24.75MHzJulius Werner
This patch increases the SPI clock for the ROM to 24.75MHz on all rk3288 (veyron) boards. This increases flash read speeds (and thereby decreases boot time) significantly, but we don't seem to get any more increases by going even higher. We have also seen occasional read failures at higher speeds in certain configurations, so this frequency seems to be the best option. BRANCH=veyron BUG=chrome-os-partner:38352 TEST=Booted on Jerry with Servo attached. Change-Id: I9bdb62eff169fe2be33558caafe9891668589372 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a1d07da4266f2922b076dfae8396c24c6a84252b Original-Change-Id: If3fd96c8cb5648d12fc4ee56fb6b6d5f3a0bf720 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/262645 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9889 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22google/urara: use board ID information to set up hardwareIonela Voinescu
The hardware initialization is now split in basic initialization (MIPS and system PLL, system clock, SPIM, UART), and initialization of other hardware blocks (USB, I2C, ETH). The second part uses board ID information to select setup that is board specific (currently only I2C interface is selected through board ID). BRANCH=none BUG=chrome-os-partner:37593 TEST=tested on bring up board for both Urara and Concerto; to simulate the use of Concerto (I2C3) DIP SW17 was set to 0. it works with default settings on Urara Change-Id: Ic5bbf28ab42545a4fb2aa6fd30592a02ecc15cb5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f2b3db2e7f9fa898214f974ca34ea427196d2e4e Original-Change-Id: Iac9a082ad84444af1d9d9785a2d0cc3205140d15 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/257401 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9888 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22rockchip/rk3288: Fix SPI clock divisor calculationJulius Werner
The code to calculate the RK3288 SPI controller's internal clock divisor is wrong: it assumes that the divisor register was an "n-1" divisor when it actually isn't (due to some misleading kernel code that was copied in here). This means that all SPI clocks are currently running lower than expected. This patch fixes the calculation and changes all callers such that the effective speeds stay the same. BRANCH=veyron BUG=chrome-os-partner:38352 TEST=Booted Jerry with and without the patch, dumping the divisor for flash and EC clocks. Made sure it stays the same. Change-Id: I2336e2b81c2384b5076175fcf32717a3ab2ba0c5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1fd5b990f937019a9bee7bd693c91d6e2fca1adb Original-Change-Id: I094d57a5933c8b849f5c66194e6cc2952ab68b90 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/262269 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9887 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22chromeec: Support accessing memmap data over port 62/66Shawn Nematbakhsh
Some platforms cannot access the 900h-9ffh region over the LPC bus, so it's necessary to access memmap data over the ACPI cmd / data ports. BUG=chrome-os-partner:38224 TEST=Manual on Samus. Define EC_GOOGLE_CHROMEEC_ACPI_MEMMAP. Verify system boots cleanly and battery status is updated immediately on plug / unplug. BRANCH=None Change-Id: Ifbed938668d3770750a44105e40fccb9babf62ed Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 14762261a6a32b2e96ee835e852b2c9537436ae3 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Change-Id: Idb516ff60b973d8833a41c45eac5765dafb8ec6d Original-Reviewed-on: https://chromium-review.googlesource.com/262314 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: http://review.coreboot.org/9886 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22chromeec: Update ec_commands.h from EC repositoryShawn Nematbakhsh
BUG=chrome-os-partner:38224 TEST=Compile for Samus BRANCH=None Change-Id: I9bb7ed100b876cbd50d39f5c5ad599e4bd7be6b4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ca8fbf8ed91d95486f0c8db680e8ceabca597a3a Original-Change-Id: I250fcce67f6103cf3037b416b8e74dd4a2cea780 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/262313 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9885 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22arch/arm64: allow floating-point registers accessYen Lin
BRANCH=None BUG=None TEST=build coreboot, make sure there are fmov instructions generated by the compiler, and boot to kernel Change-Id: Ia99c710be77d5baec7a743a726257ef3ec782635 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f770a436a0692c8e57a8c80860a180330b71e82c Original-Change-Id: Iab4ba979b483d19fe92b8a75d9b881a57985eed7 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/262242 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9884 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22google/rush_ryu: add serialno from vpdStephen Barber
Add the serial number from VPD on ryu. BRANCH=none BUG=chrome-os-partner:37813 TEST=devicetree is populated with "compatible", "hardware", and "serialno" properties Change-Id: I1e84933a01a34028a062d31aad026f91c3bd29e1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 18cefb655651c9097ff7f2ef3cb735efbbe32370 Original-Change-Id: I14439c37df0fde7f2328c7caae1adf6a122e8f5f Original-Signed-off-by: Stephen Barber <smbarber@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/260646 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9883 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22vpd: populate coreboot table with serialnoStephen Barber
BRANCH=none BUG=chrome-os-partner:37813 TEST=devicetree is populated with with "compatible", "hardware", and "serialno" properties Change-Id: Ibe84aa05702d2a33456c6c33d15a4c7d4a6d45d7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 61408d969f5d6e1e40f919b3defd5f1622391c9e Original-Change-Id: I02f360f4e5385042f56eb2b2f29072e393a24fc9 Original-Signed-off-by: Stephen Barber <smbarber@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/259141 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9882 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22vboot2: provide config option to clear dev mode state on recoveryVadim Bendebury
On embedded devices with limited input capabilities it is necessary to clear the developer mode condition when entering recovery. The new configuration option will enable such behavior using the new vboot2 flag. CQ-DEPEND=CL:261630 BRANCH=storm BUG=chrome-os-partner:36059 TEST=with the rest of the patches applies observed desired behavior on SP5 Change-Id: I99c3d1330bea9980a2af3b9fd99e29ab96f2cf07 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4c0a6315d6b4ede8d43e736ee6c82f1023f4716d Original-Change-Id: I8e4a521e574b53a670daf692f7b45dc21635f272 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/261620 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9878 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22vboot2: ignore physical dev switch in case virtual mode is configuredVadim Bendebury
It is better to explicitly disable the call to read the physical switch setting than to leave it up to implementation. In fact no implementation would be even required. BRANCH=none BUG=none TEST=verified that storm works as expected Change-Id: I4b39827dba34ec0124960d0634e45d4554252d9b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c9fd014f1bfec6570b20ed8fed16d14d7e4e11b9 Original-Change-Id: I5d6d223f0c684e105a5e3d0b407e0fb181c7a7df Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/261588 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9876 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22google/veyron_*: add ELPIDA F8132A3MA and FA232A2MA sdramjinkun.hong
BRANCH=None TEST=Boot from veyron BUG=None Change-Id: Ie154d233f144bde2625cf069b9b754e9518a1768 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0ddd03f8757b5122f6ca87baffdf95c46e356e53 Original-Change-Id: I725cfb04ff46f7e6493e0e12a464c45b1362bc1a Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/261083 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9874 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22arm64: provide icache_invalidate_all()Aaron Durbin
In order to not duplicate the instruction cache invalidation sequence provide a common routine to perform the necessary actions. Also, use it in the appropriate places. BUG=None BRANCH=None TEST=Built on ryu. Change-Id: I29ea2371d034c0193949ebb10beb840e7215281a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d5ab28b5d73c03adcdc0fd4e530b39a7a8989dae Original-Change-Id: I8d5f648c995534294e3222e2dc2091a075dd6beb Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/260949 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9871 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22elog: Eliminate CONFIG_ELOG_FULL_THRESHOLD and CONFIG_ELOG_SHRINK_SIZESol Boucher
These Kconfig options provided a level of configurability that is almost never necessary, so they are being moved into ordinary preprocessor defines in elog_internal.h. The new threshold to trigger shrinking is relative to the number of additional (maximum-size) events that can fit, and the new target post-shrink size is a percentage of the total ELOG area size. BUG=chromium:467820 TEST=Add loop at the end of elog_init() that fills the ELOG area to just below full_threshold with dummy events. Observe successful shrinkage when the next event is logged. BRANCH=None Change-Id: I414c4955a2d819d112ae4f0c7d3571576f732336 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ce439361e3954a2bf5186292f96936329171cf56 Original-Change-Id: I926097f86262888dcdd47d73fba474bb2e19856a Original-Signed-off-by: Sol Boucher <solb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/260501 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/9869 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22google/veyron_*: update sdram-ddr3-samsung-4GB.incjinkun.hong
The old parameters are wrong. K4B8G1646Q: rank = 2, row = 15 is right. BUG=None TEST=Boot from veyron BRANCH=None Change-Id: I41848c158f3ea028035cc8c0d969a4a449390a54 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 601ba06c636ff0f0779e6ef9357b53060a1ec19b Original-Change-Id: I5bc6798890b3ba0f5134d048ae6bbf2bfd696676 Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/260483 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Tested-by: Paul Ma <magf@bitland.com.cn> Reviewed-on: http://review.coreboot.org/9866 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22rockchip/rk3288: use bl_en instead lcd_bl to fill_lb_gpiohuang lin
in depthcharge we will use "backlight" gpio which in lb_gpio table to control backlight, we use lcd_bl before, but it will not meet the backlight power sequence, so we change it to bl_en. BUG=chrome-os-partner:37348 TEST=Boot from speedy, and backlight work well BRANCH=None Change-Id: I19e488c7d3f1fe5cb91f8a93fae6b848f58b36b7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cb594ce612e1cedeabced4531fbd954f3698da98 Original-Change-Id: Ib0dac7c48bce7d0b28ec287b32d8c5bad575893f Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/259900 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9864 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22vboot: when configured, pass the wipeout request to vbootVadim Bendebury
It has become necessary to be able to "factory reset" certain devices on firmware request. The vboot package has been modified to provide the necessary API, this patch introduces a configuration option and uses the API when enabled. CQ-DEPEND=CL:259857 BRANCH=storm BUG=chrome-os-partner:37219 TEST=with all the patches applied, on storm, holding the recovery button at startup for 10 seconds, causes 'crossystem wipeout_request' to report '1'. Change-Id: I5e57bc05af3753f451626021ba30c7726badb7b4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f70e03e9a8c55bf3c45b075ae4fecfd25da4f446 Original-Change-Id: I4c2192da4fabfdef34d527e5b80d137634eb6987 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/259843 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9862 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22qualcomm/ipq806x: report versions of RPM and DDR init componentsVadim Bendebury
DDR init blob version string can be found at a fixed location in memory once the blob is loaded. Maximum size of the string is 48 bytes. The RPM RW version is defined in a 32 bit version stored at yet another fixed address once RPM RW has started. BRANCH=storm BUG=chrome-os-partner:30623 TEST=ran this command on the booted system: localhost ~ # egrep '(DDR|RPM)' /sys/firmware/log Loaded DDR init blob version 99ce41d@-AAABANAZA DDR initialized Starting RPM Started RPM version 1.0.128 localhost ~ # Change-Id: If3c3c8368845b978605ccfda7e09c21ae2e5ab9a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 328c9c57cf93110bc0fdd267134d72e386d70834 Original-Change-Id: If411f6f7bca53ea20390b7e851cb3d120681eade Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/256738 Original-Reviewed-by: Varadarajan Narayanan <varada@qti.qualcomm.com> Reviewed-on: http://review.coreboot.org/9860 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22qualcomm/ipq806x: add board id value for SP5Vadim Bendebury
SP5 whirlwind is the earliest hardware version equipped with the LED ring. BRANCH=storm BUG=chrome-os-partner:36059 TEST=none Change-Id: I4c90a75911350bafd8ccb8755b2491e9447f285b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3dfee90457295668a2b60d5a1e913caf52557877 Original-Change-Id: I6bffdcc47fe9c72796e3bac44d211f907538ef0b Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/258270 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9857 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22google/urara: retrieve board ID from a CBFS fileVadim Bendebury
Concerto board does not have the means of detecting the identity of the device it is controlling. But it is very beneficial to be able to use the same firmware image on Concerto boards running different devices. The suggested solution is to keep the device identity as a string in a raw CBFS file called 'board_id'. With this patch coreboot maintains a table of possible board name strings and their matching board IDs. BRANCH=none BUG=chrome-os-partner:37593 TEST=verified that without the board id file addition the default Board ID of zero is used. Adding the file as follows: echo -n 'concerto' > /tmp/bid cbfstool /build/urara/firmware/image.serial.bin add -f /tmp/bid \ -t raw -n 'board_id' results in firmware reporting board ID setting of 1. board_id: failed to locate CBFS file board_id board_id: name urara, ID 0 Change-Id: I5a02192740dc94b1ea8090092cc325fe0ac42aa6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f41f9b07f155f0c719c36e0cd93081205624557e Original-Change-Id: I8341782005b101be78f5c9a6b375c8f73179c1ad Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/257170 Reviewed-on: http://review.coreboot.org/9856 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22broadcom/cygnus: add timestamps in pre-ram stagesDaisuke Nojiri
BUG=none BRANCH=broadcom-firmware TEST=timestamp table: 0501: 31858 0005: 106680 0503: 132098 0504: 135573 0006: 168656 0013: 168660 0014: 240487 0502: 240491 0001: 240515 0002: 247544 0003: 537158 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chrome-internal-review.googlesource.com/204758 Reviewed-by: Julius Werner <jwerner@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@google.com> Tested-by: Daisuke Nojiri <dnojiri@google.com> Change-Id: I5b4608152e97d53e35d28aa7bed2bfd158409df9 Reviewed-on: https://chromium-review.googlesource.com/256418 Reviewed-on: http://review.coreboot.org/9855 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22google/purin: add DMA coherent regionDaisuke Nojiri
BUG=none BRANCH=broadcom-firmware TEST=boot to depthcharge Change-Id: Id10437c12e219e07121395abd442d53b3b56c7be Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f33e9218ca8df1d149761c09253c30837b607433 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chrome-internal-review.googlesource.com/204757 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@google.com> Original-Tested-by: Daisuke Nojiri <dnojiri@google.com> Original-Change-Id: I93def9c326cc8b4fea69078987bddf09d9f2a797 Original-Reviewed-on: https://chromium-review.googlesource.com/256417 Reviewed-on: http://review.coreboot.org/9854 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22broadcom/cygnus: Initialize dram in romstage.Icarus Chau
BUG=chrome-os-partner:36456 BRANCH=broadcom-firmware TEST=When enable configuration CYGNUS_SDRAM_TEST_DDR, print on console: sdram initialization is completed. test ddr start from 0x60000000 to 0x80000000 ... test ddr end: fail=0 Translation table is @ 02004000 Mapping address range [0x00000000:0x00000000) as uncached Change-Id: I88dc2f0c504e2a152133edd442c3d776dd73d37e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 376471751d6980f99bbe47faad193c79a05fa69f Original-Signed-off-by: Icarus Chau <ichau@broadcom.com> Original-Reviewed-on: https://chrome-internal-review.googlesource.com/199775 Original-Commit-Queue: <ichau@broadcom.com> Original-Tested-by: <ichau@broadcom.com> Original-Reviewed-by: Scott Branden <sbranden@broadcom.com> Original-Change-Id: I47bc5d9ec147cc8bfbd893e8c0d7e5fc5e401771 Original-Reviewed-on: https://chromium-review.googlesource.com/256416 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: http://review.coreboot.org/9853 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21broadcom/cygnus: Fix missing writel->write32 transformationPatrick Georgi
cygnus' serial driver wasn't part of the tree when the big transformation was done, so follow up. Change-Id: Ic1a53bea9bcaf1e568b50b9c2ad7782e65e36328 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9852 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21cygnus: add QSPI driverCorneliu Doban
The driver uses the MSPI controller to read/write to/from SPI flash BUG=chrome-os-partner:35811 BRANCH=boradcom-firmware TEST=bootblock loads and executes verstage Change-Id: I34c7882170e4f89bee1b6001563c09b16dfea8ca Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8c3b156019df429e9d12728224ed4eec8436f415 Original-Signed-off-by: Corneliu Doban <cdoban@broadcom.com> Original-Reviewed-on: https://chrome-internal-review.googlesource.com/199776 Original-Reviewed-by: Scott Branden <sbranden@broadcom.com> Original-Tested-by: Corneliu Doban <cdoban@broadcom.com> Original-Commit-Queue: Corneliu Doban <cdoban@broadcom.com> Original-Change-Id: Ice798ec76011ee47e13174b4c5534b0d0bc8b4ad Original-Reviewed-on: https://chromium-review.googlesource.com/256414 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: http://review.coreboot.org/9849 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21veyron: add new SDRAM configuration with ram-code 1101bZhengShunQian
This add hynix-2GB SDRAM(H5TC4G63AFR-PBA), whose timing is the same as H5TC4G63CFR-PBA, to veyron boards. BUG=None BRANCH=veyron TEST=build on mighty and boot on mighty board with ram-id reworked Change-Id: I3ae5e65e60e18414cf4de6fbcc5bed736b1492de Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b22029f9b05ebb9a775266a7e3aae38b50c1883a Original-Change-Id: If17fb002f2816990e1706833b37ac6be345e540b Original-Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/256307 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Lin Huang <hl@rock-chips.com> Original-Tested-by: Lin Huang <hl@rock-chips.com> Reviewed-on: http://review.coreboot.org/9848 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21pistachio: Remove 50% DDR bandwidth restrictionIonela Voinescu
The existing DDR setup configures the burst length to be 8. However the DDR controller can only be given sufficient data per clock to satisfy a burst length of 4, hence the bursts are only half populated. This results in a 50% drop of efficiency. Fix this by configuring the burst size to 4. BUG=chrome-os-partner:31438, chrome-os-partner:37087 TEST=tested on Pistachio bring up board -> DDR initialized properly and ramstage executed correctly BRANCH=none Change-Id: I761ba73a04688841ca39a370b7cb99b6e0b22964 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0e590ab8387dbbccef45dc84d1eeafee2abc9e2e Original-Change-Id: I585385b65e330624ad70292349e50c6695eeeb6c Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/256305 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9847 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21pistachio: Decrease DDR ODT from 75R to 50RIonela Voinescu
The DDR On Die Termination was incorrectly configured at 75R, where as the data sheet suggests for DDR2-800 it should be set to 50R. Correct this by adjusting the ODT setting in the EMR register. BUG=chrome-os-partner:31438, chrome-os-partner:37087 TEST=tested on Pistachio bring up board -> DDR initialized properly and ramstage executed correctly BRANCH=none Change-Id: I2f0242c422b1cb3d1f64ce3dd17b62fef5e7e155 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ac081ac59c0dc3d16a7b540cd379fb870b6cfe40 Original-Change-Id: If7951812033c4e88f4be3c143fb49526eddba142 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/256304 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9846 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21pistachio: clean DDR2 initialization codeIonela Voinescu
The proper way to initialize DDR2 is for the PHY to automatically establish precise timing configuration through the training process. The alternative (used initially for testing) is no longer needed. This change determined the removal of some local variables as they ended up being used in one location only. BUG=chrome-os-partner:31438, chrome-os-partner:37087 TEST=tested on Pistachio bring up board -> DDR initialized properly and ramstage executed correctly. BRANCH=none Change-Id: I31e9a8975d176a04061f9c84fe06cce850bb53b9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e28f3ef9a22436bb0fa949df6f5a5c6a67002dfd Original-Change-Id: Ifb9c1bb6e0b71af72340381bd2349850d1b4af2d Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/256303 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9845 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21storm: print uber-sbl informationVadim Bendebury
Process information reported by uber-sbl: print out its version and RPM and KRAIT log contents. BRANCH=storm BUG=chrome-os-partner:30623 TEST=rebooted a storm device, checked out /sys/firmware/log after booting up Chrome OS: localhost ~ # head -29 /sys/firmware/log | tail -15 Uber-sbl version: @vbendeb-AAABANAZA Section 0 log: 0 :00:SBL1, Start 0 :00:SBL-RO Krait 2623 :00:SBL-RO Krait 0 :00:BB 4666 :00:BB 0 :00:sbl1_hw_init, Start 6130 :00:sbl1_hw_init, Delta 0 :00:SBL1, End 15372:00:SBL1, Delta Section 1 log: 0 :00:SBL-RO Krait, Start 0 :00:SBL-RO Krait, End 336 :00:SBL-RO Krait, Delta localhost ~ # Change-Id: I524dbb49f676046a43bfba26b31b2834c8d2769c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: dcabca6eb87dcead0c9c33749ed76ac939d843c1 Original-Change-Id: Ic037f936ff2d09b0346fb5239094e7928dfd7620 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/252830 Original-Reviewed-by: Varadarajan Narayanan <varada@qti.qualcomm.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@gmail.com> Reviewed-on: http://review.coreboot.org/9843 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21armv7: preserve bootblock invocation parameterVadim Bendebury
Some platforms may pass as a parameter the maskrom or vendor startup code information when calling the bootblock. Make sure the bootblock startup code saves this parameter for use by coreboot. As we don't want to touch memory before caches are initialized, save the passed in parameter in r10 for the duration of cache initialization. Added warning comments to help enforcing that cache initialization code does not touch r10. BRANCH=storm BUG=chrome-os-partner:30623 TEST=with the rest of the patches applied see the QCA uber-sbl report in the coreboot console output. Change-Id: Ic6a09e8c3cf13ac4f2d12ee91c7ab41bc9aa95da Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e41584f769eb042604883275b0d0bdfbf5b0d358 Original-Change-Id: I517a79dc95040326f46f0b80ee4e74bdddde8bf4 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/255144 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@gmail.com> Reviewed-on: http://review.coreboot.org/9842 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21ipq808x: add uber sbl parameter definitionsVadim Bendebury
This describes the structure of the information passed through a pointer by uber-sbl to be processed by the coreboot bootblock. BRANCH=storm BUG=chrome-os-partner:30623 TEST=with the rest of the patches applied observed uber-sbl information added to the coreboot console log. Change-Id: If04c4ee0ccfda3df45bd22eb576aaa5b51f1c4b5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ed39e2bcd793fd490416b407f627b5a9a86b8f78 Original-Change-Id: I1dffbf4559853a818e81ca5fdeff013cf008dd6a Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/255143 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@gmail.com> Reviewed-on: http://review.coreboot.org/9841 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21urara: I2C clock and MFIO setup function for all interfacesIonela Voinescu
The I2C MFIO setup function now supports all interfaces. Also, the API for the clock setup function changed to support all interfaces. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; all I2C interfaces were tested with the TPM and they all work properly. BRANCH=none Change-Id: I6dfd1c4647335878402cabb2ae512d6e3737a433 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f8a7ffb54e3f5092c9844b9b502949d3cfc053d1 Original-Change-Id: Ibd67c07acf3d1d9c594faa8ced5ab56d9abb2e40 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/256362 Original-Reviewed-by: Chris Lane <chris.lane@frontier-silicon.com> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9840 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21pistachio: add clock setup for all I2C interfacesIonela Voinescu
BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; all I2C interfaces were tested with the TPM and they all work properly. BRANCH=none Change-Id: I02202585140beb818212c02800f6b7e4966a922a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 33b2adecc4939ac73fffba47adf1c8306a888b8d Original-Change-Id: Ida7eaa72d4d6e6b034319086410de5baa63788bc Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/256361 Original-Reviewed-by: Chris Lane <chris.lane@frontier-silicon.com> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9839 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21Unify byte order macros and clrsetbitsJulius Werner
This patch removes quite a bit of code duplication between cpu_to_le32() and clrsetbits_le32() style macros on the different architectures. This also syncs those macros back up to the new write32(a, v) style IO accessor macros that are now used on ARM and ARM64. CQ-DEPEND=CL:254862 BRANCH=none BUG=chromium:444723 TEST=Compiled Cosmos, Daisy, Blaze, Falco, Pinky, Pit, Rambi, Ryu, Storm and Urara. Booted on Jerry. Tried to compare binary images... unfortunately something about the new macro notation makes the compiler evaluate it more efficiently (not recalculating the address between the read and the write), so this was of limited value. Change-Id: If8ab62912c952d68a67a0f71e82b038732cd1317 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fd43bf446581bfb84bec4f2ebb56b5de95971c3b Original-Change-Id: I7d301b5bb5ac0db7f5ff39e3adc2b28a1f402a72 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254866 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9838 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21arm(64): Manually clean up the mess left by write32() transitionJulius Werner
This patch is a manual cleanup of all the rubble left by coccinelle waltzing through our code base. It's generally not very good with line breaks and sometimes even eats comments, so this patch is my best attempt at putting it all back together. Also finally remove those hated writel()-style macros from the headers. BRANCH=none BUG=chromium:444723 TEST=None (depends on next patch) Change-Id: Id572f69c420c35577701feb154faa5aaf79cd13e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 817402a80ab77083728b55aed74b3b4202ba7f1d Original-Change-Id: I3b0dcd6fe09fc4e3b83ee491625d6dced98e3047 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254865 Reviewed-on: http://review.coreboot.org/9837 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21arm(64): Globally replace writel(v, a) with write32(a, v)Julius Werner
This patch is a raw application of the following spatch to src/: @@ expression A, V; @@ - writel(V, A) + write32(A, V) @@ expression A, V; @@ - writew(V, A) + write16(A, V) @@ expression A, V; @@ - writeb(V, A) + write8(A, V) @@ expression A; @@ - readl(A) + read32(A) @@ expression A; @@ - readb(A) + read8(A) BRANCH=none BUG=chromium:444723 TEST=None (depends on next patch) Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6 Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254864 Reviewed-on: http://review.coreboot.org/9836 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21arm(64): Change write32() argument order to match x86Julius Werner
This patch changes the argument order for the (now temporarily unused) write32() accessor macro (and equivalents for other lengths) from (value, address) to (address, value) in order to conform with the equivalent on x86. Also removes one remaining use of write32() on ARM that slipped through since coccinelle doesn't inspect header files. BRANCH=none BUG=chromium:444723 TEST=Compiled Cosmos, Daisy, Blaze, Pit, Ryu, Storm and Pinky. Change-Id: Id5739b144f6a5cfd40958ea68510dcf0b89fbfa9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f02cae8b04f2042530bafc91346d11bb666aa42d Original-Change-Id: Ia91c2c19d8444e853a2fc12590a52c2b6447a1b9 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254863 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9835 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21arm(64): Replace write32() and friends with writel()Julius Werner
This patch is a raw application of the following spatch to the directories src/arch/arm(64)?, src/mainboard/<arm(64)-board>, src/soc/<arm(64)-soc> and src/drivers/gic: @@ expression A, V; @@ - write32(V, A) + writel(V, A) @@ expression A, V; @@ - write16(V, A) + writew(V, A) @@ expression A, V; @@ - write8(V, A) + writeb(V, A) This replaces all uses of write{32,16,8}() with write{l,w,b}() which is currently equivalent and much more common. This is a preparatory step that will allow us to easier flip them all at once to the new write32(a,v) model. BRANCH=none BUG=chromium:451388 TEST=Compiled Cosmos, Daisy, Blaze, Pit, Ryu, Storm and Pinky. Change-Id: I16016cd77780e7cadbabe7d8aa7ab465b95b8f09 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 93f0ada19b429b4e30d67335b4e61d0f43597b24 Original-Change-Id: I1ac01c67efef4656607663253ed298ff4d0ef89d Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254862 Reviewed-on: http://review.coreboot.org/9834 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21romstage_handoff: Fix for changing CBMEM structureDuncan Laurie
Adding a new field to a CBMEM structure does not work if there are systems with older RO that do not have this new field as it means romstage did not prepare the field and ramstage is using it uninitialized. To deal with this instead of adding a new field split the existing s3_resume variable into bytes, using the first byte for the existing s3_resume variable (which is always just 0 or 1) and the second byte for the new varible, which will always be 0 for the old RO and can be set by new RO. BUG=chrome-os-partner:37108 BRANCH=samus TEST=manual testing on samus: 1) ensure that if vboot requests reboot after TPM setup that it still works and the reboot happens after reference code execution. 2) ensure that if RO is older without this change that it does not cause a continuous reboot if newer ramstage is added 3) test that suspend resume still works as expected Reviewed-on: https://chromium-review.googlesource.com/253550 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org> (cherry picked from commit 1ccb7ee5fc6980ca0f26fa52b385d2cc52f396c9) Change-Id: I6e206b4a3b33b8a31d102d64bd37d34657cf49ac Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fe85678ee788ff939bc8c084829a1b04232c4c6c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Change-Id: If69d0ff9cc3bf596eee8c3a8d6e04951820a26fe Original-Reviewed-on: https://chromium-review.googlesource.com/256114 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9833 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21veyron_{brain,danger}: Specify vboot romstage and ramstage indicesDavid Hendricks
This applies the same hack to Danger and Brain as on Rialto which allows us to remove the EC-related sections from their respective flashmaps. BUG=none BRANCH=veyron CQ-DEPEND=CL:255669 TEST=built and booted on Brain w/ depthcharge and mosys changes, was able to read vbnv data from userspace Change-Id: I95715d59a21cd081ac4a3a2216576ede5620f1a5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4de4273be9ac80ca77a34bc076d1f265fbb94e9f Original-Change-Id: I6c2041e8c17ab157599255a505aaef5e2447a241 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/255780 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9832 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21rk3288: disable rk808 DCDC_UV_ACT_REG restart converter functionhuang lin
if DCDC_UV_ACT_REG setted, when the buck voltage drop to 85%, rk808 will reset this buck, but now when the current consumption large, rk808 may miscarriage of justice this status, so we must disable this function BUG=chrome-os-partner:34834 TEST=Boot from jerry, and do RUNIN test sucess BRANCH=None Change-Id: I08cef73b88d6c2722b389c632c7db29605f4545d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 858c8abc11a824fc3d991a39a49710243f4b1473 Original-Change-Id: I46ebe332c576eebd3386b5042b146a8b57a5c194 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/254496 Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Original-Tested-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9831 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21veyron: The ODT function is disabled for LPDDR3jinkun.hong
We found that we should better keep ODT off for LPDDR3 on our boards. BRANCH=veyron BUG=chrome-os-partner:37346 TEST=Boot veyron_speedy normal Change-Id: Id158c88769cf7ed1a5127cd09bad679a2f5e6a01 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0d85725a6faedb5bdbe8731991c225c31f138599 Original-Change-Id: Iebb8e74706756508dd56b85ad87baad48893c619 Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/255381 Reviewed-on: http://review.coreboot.org/9830 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21veyron: Sync up SDRAM configurationsJulius Werner
This patch adds all SDRAM configurations currently in use for any Veyron board to all boards. In the future we might decide that we want to reuse known good memory from one board on another, and having all of these in there already might help us avoid a firmware rev. We can still differentiate them later if the need ever arises. Not touching Rialto since it already decided to go its own way and replace an existing RAM code with it's own 1GB configuration. Also adjusting the names of the recently added DDR3 4GB configs to fit the existing scheme. Includes changes from "veyron: The ODT function is disabled LPDDR3". BRANCH=veyron BUG=None TEST=Compiled all Veyron boards, booted on Jerry. Change-Id: I817efd4b467a5a9587475a82df207048173e7bd5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 36d3fe138b154a16700e3c7adbb33834ff1c5284 Original-Change-Id: I4d037967dcb5cbd6b2b82f347f6b19541559b61a Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/255665 Reviewed-on: http://review.coreboot.org/9829 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21rockchip: configure lpddr odt properlyDerek Basehore
The wrong offsets were being used for the GRF_SOC_CON2 register. This also configures odt based on the value of odt in the sdram_params for lpddr systems. BUG=chrome-os-partner:37346 TEST=boot veyron_speedy and veyron_jerry BRANCH=None Change-Id: I13ec3d0df162fe73fabf8af40dd5472e15d6f6af Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 403ab13de17290dc3766bd6f1a03b6effbe58b41 Original-Change-Id: Ic0c18cc7ccf861ef8749e6c950fab9a2802e5f26 Original-Signed-off-by: Derek Basehore <dbasehore@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/255584 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9828 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21cbfs: Print absolute offsets of loaded filesVadim Bendebury
Add the absolute offset value to the CBFS log, to make it easier to understand which particular CBFS section the file is loaded from. BRANCH=storm BUG=none TEST=rebooted a Whirlwind device, observed an empty line before the ramstage section of the log and absolute offsets reported by CBFS. Change-Id: Ifcb79ab386629446b98625a5416dfa5850a105f6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ecc4d1df7c51a263230c45ecac5981d53bdd44b1 Original-Change-Id: I5cc727127374d6e55b8ff6f45b250ef97125a8ec Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/255120 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9827 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21veyron_jerry: support K4B8G1646Q-4GB and H5TC8G63XXX-4GB ddr3jinkun.hong
add the K4B8G1646Q-4GB and H5TC8G63XXX-4GB ddr3 inf file, and use ram_id 1110 correspond to K4B8G1646Q-4GB ddr3 use ram_id 1111 correspond to H5TC8G63XXX-4GB ddr3 BUG=None TEST=Boot veyron_jerry normal BRANCH=None Change-Id: I3398516a9f2c2e44c9f5d08d0a3ab6e76b5c6f5f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b8dfc455bb93c2daf567e3b6e39c0a715e44311c Original-Change-Id: I90250cb84eb140f93c4fc655fb3b90584dd515c0 Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/255010 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9826 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21x86: Allow builds without ACPI tablesLee Leahy
Fix build bug that is referencing vboot_data from vendorcode/google/chromeos/gnvs.c when CONFIG_HAVE_ACPI_TABLES is not set. BRANCH=none BUG=None TEST=Build and run on Glados 1. Checkout updated patches for config, skylake and glados through FspNotify1 2. Verify that mainboard/intel/glados/Kconfig does not select HAVE_ACPI_TABLES 3. emerge-glados coreboot 4. Test passes if build completes successfully Change-Id: Ida5ab8b8dafe30b11dc80dab935e3223d4c760d3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1908079360aa065a36956d487eb93142e9c012a1 Original-Change-Id: Icac3845f7e2d1ddffa5f787a640033fba286c13e Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/254360 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/9825 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21ipq806x: i2c: stop transfer as soon as an error is reportedSourabh Banerjee
I2c transfer may consist of multiple segments (for instance write segment to set the register address and then a read segment to read the register value). Transfer should be stopped as soon as a segment processing error has been reported. BRANCH=master BUG=chrome-os-partner:35328 TEST=transfer shall not process the read segment when the write segment fails Change-Id: I85b7b59b376ce33ba3f6d2526be86e9f6585d97b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 50cd4d40851b3cea99183c549c47b4486a3deb4a Original-Change-Id: Id65f995d860dd670b289fbdd9eb0ca19a50d7007 Original-Signed-off-by: Sourabh Banerjee <sbanerje@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254494 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9824 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21ipq806x: i2c: write function fixed to avoid spurious successSourabh Banerjee
The qup_i2c_write_fifo() made to query QUP_I2C_MASTER_STATUS after QUP transitions into PAUSE state to ensure that it captures the correct status. Handled more error bits. BRANCH=chromeos-2013.04 BUG=chrome-os-partner:35328 TEST=Booted up storm P0.2, verified that the TPM on GSBI1 works. Verified that SUCCESS is not reported when the write FIFO has failed. Change-Id: Ia91638d37b3fa8449630aa2cf932114363b2db78 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 75e0d59d2e6ba03182003f22944dbf99ce3eb412 Original-Change-Id: Ic4e8e85686499ce71ad3258b52e687ceff36a1f8 Original-Signed-off-by: Sourabh Banerjee <sbanerje@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254495 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9823 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21arch/mips: simplify cache operationsIonela Voinescu
Cache operations are simplified by removing assembly implementation and replacing it with simpler C code. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; caches are properly invalidated; BRANCH=none Change-Id: I0f092660549c368e98c208ae0c991fe6f5a428d7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bf99849e75813cba865b15af9e110687816e61e4 Original-Change-Id: I965e7929718424f92f3556369d36a18ef67aa0d0 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/250792 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9820 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21rk3288: support single channel ddrjinkun.hong
When using single-channel ddr, DMC channel 1 need to reset dll, otherwise it will lead to pmdomain idle request fails. BUG=chrome-os-partner:35654 BRANCH=veyron TEST=boot rialto Change-Id: Id6b673187c688d238e9a391b3d98720c783e3af4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 927e8426104f8869e139c3f60a04cd49bf726e61 Original-Change-Id: I8be1567040ddb5f2a2b0d06568e517d794ead87a Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/250060 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9819 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21urara: Identity map DRAM/SRAMAndrew Bresticker
Using identity_map(), map the DRAM/SRAM regions to themselves (which happens to be using KUSEG on urara). The bootblock (which still runs in KSEG0) sets up the identity mapping in bootblock_mmu_init() so that ROM/RAM stages can be loaded into the KUSEG address range. The stack and pre-RAM CBMEM console also remain in KSEG0 since we don't really care about their physical addresses. Also splitting CBFS cache to pre and post RAM, to allow for larger rambase images. BUG=chrome-os-partner:36258 BRANCH=none TEST=With the rest of coreboot and depthcharge patches applied: - booted urara into the kernel login prompt - from depthcharge CLI tried accessing memory below 0x100000 - observed the exception. Change-Id: If78f1c5c54d3587fe83e25c79698b2e9e41d3309 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9668b440b35805e8ce442be62f67053cedcb205e Original-Change-Id: I187d02fa2ace08b9fb7a333c928e92c54465abc2 Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/246694 Reviewed-on: http://review.coreboot.org/9816 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21mips: Allow memory to be identity mapped in the TLBAndrew Bresticker
Introduce identity_map() function. It takes a memory range and identity maps it entirely in the TLB table, if possible. As a result the virtual and physical address ranges are the same. The function attempts to use as large of a page size as possible for each region in order to conserve TLB entries. BUG=chrome-os-partner:36258 BRANCH=none TEST=Build and boot on Pistachio with the rest of the patches applied. Change-Id: I4d781b04699e069a71c49a0c6ca15c7a6b42a468 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 234d32edfd201019b7a723316a79c932c62ce87e Original-Change-Id: If3e2392b19555cb6dbae8b5559c1b1e53a313637 Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/246693 Reviewed-on: http://review.coreboot.org/9815 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21broadwell: Clear USB3.0 PORTSC status bits in sleep_prepare.Todd Broch
Found that any non-USB3.0 devices connected to type-C ports (displayPort dongles) cause XHCI port to see connection which in turn leads us to enter USB compliance mode. That in turn causes the port to wake the system for a yet-to-be determined reason. Clearing the PORTSC status bits (actually just CSC) seems to remedy the wake. Signed-off-by: Todd Broch <tbroch@chromium.org> BRANCH=samus BUG=chrome-os-partner:35320 TEST=manual, 1. Plug hoho into type-C port on samus and remove 2. powerd_dbus_suspend Device stays asleep. Change-Id: Id3a291579ffca0152a7ef32e37ecae80ca08a82b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0be5cba4916681dceb0372e76d9643e6c7175db5 Original-Change-Id: I1396b9f8013dbbb31286c1d8958af592b3da7475 Original-Reviewed-on: https://chromium-review.googlesource.com/247410 Original-Commit-Queue: Todd Broch <tbroch@chromium.org> Original-Tested-by: Todd Broch <tbroch@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9814 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21broadwell: indent xhci codePatrick Georgi
Change-Id: I97920e7eb64c05034184f9a4e1c8f2dfa44d3fdd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9813 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21broadwell: Skip pre-graphics delay in resume pathDuncan Laurie
If the board is configured with a pre-graphics delay it should be skipped in the resume path. BUG=chrome-os-partner:28234 BRANCH=broadwell TEST=measure resume time in dev mode to be same as normal mode Change-Id: I5a4ad5bba9e5316c89f7935d8811759b041429d9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b44a7167532410fc44ca9df1c91c91aaf541ae49 Original-Change-Id: Ic9f2cda71d8a567f57e863409f0f3fb98ab68bcf Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/245116 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9812 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21broadwell: Implement Recovery ButtonRyan Lin
This patch fixes the use of the recovery button, and the value is stored in a SATA controller scratch register. BUG=chrome-os-partner:35241 BRANCH=none TEST=Use recovery button and run firmware_RecoveryButton Change-Id: Ia06f147c7e44d6c4eea2c2e4f502c233c956ee9b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 34c7ee922a9602b3448a72cd669fd68feeed1bba Original-Change-Id: I1667c7f188b0f87c4bc7caa82f9c977b2b4c0611 Original-Signed-off-by: Ryan Lin <ryan.lin@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241772 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9811 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21Arrange CBMEM table entries' IDs alphanumericallyVadim Bendebury
This is a no-op change just sorting the CBMEM entries' definitions for easy look up and comparison. BRANCH=storm BUG=none TEST=Booted a storm device, observed the expected CBMEM entries present in the console output. Change-Id: I26365285f20ecb256918277b60e178cd61dc8213 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f140fd8d85ded30d1b89f5d4c64f8b9f31d6b27b Original-Change-Id: Ibcd4f184ef1bade10ad677384f61243da7e3c713 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225259 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9810 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-04-21urara: add config of SPI bus and correct selection of winbond flashIonela Voinescu
Urara uses SPFI interface 1 and Winbond SPI NOR flash. BRANCH=none BUG=chrome-os-partner:31438 TEST=with the fix of the Winbond driver (next patch) the bootblock successfully probes the Windbond device on the FPGA board. Console log below: coreboot-4.0 bootblock Tue Nov 11 07:05:48 PST 2014 starting... SF: Detected W25Q16 with page size 1000, total 200000 Change-Id: Ia848eac5b4a94bf95297c928b5447463c90d89eb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 38386715c52526edbe9ad356945849e21799fd94 Original-Change-Id: Ic27b60adc26bf244e7a15b5257e94df4b9d88249 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229030 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9809 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21imgtec/pistachio: Add spi_crop_chunk()Patrick Georgi
This was added in upstream but not in Chromium OS where pistachio support was developed. Change-Id: I54f883776f19aa7bd357841731166e92d03145d8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9808 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-20gigabyte/ga-b75m-d3v: Add GIGABYTE GA-B75M-D3V mainboardDamien Zammit
Board boots to linux. VGA works with rom. Change-Id: I96b73a90c3d88672f0d238f4b735cd2f96ef99bd Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/9803 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-04-20southbridge/intel/bd82x6x: Add LPC id 0x1e49 for B75 chipsetDamien Zammit
Change-Id: I3375c21d5d4aed30d5641629c44d6a5885efee11 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/9807 Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Tested-by: build bot (Jenkins)
2015-04-20mainboard/lenovo/t430s,t530,x230:enable usb3, set xhci overcurrent mappingNicolas Reinecke
Tested on T530, T430s. Verified with lspci dump. Change-Id: I45acadb0c55534a67f7ad3e7bd84f4482a4344d7 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/9451 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-04-20southbrige/intel/bd82x6x: add XHCI overcurrent map configNicolas Reinecke
Change-Id: I9a40e5a1028c7674e6dd54742e6646ba48ce7696 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/9449 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-20Kconfig: rename CONSOLE_SERIAL_UART to DRIVERS_UARTPatrick Georgi
Some upstreaming patches missed that, so follow up. Change-Id: I28665c97ac777d8b0b0f909e64b32681ed2b98f7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9771 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-04-20purin: add ns16550 driverDaisuke Nojiri
BUG=chrome-os-partner:35807 BRANCH=broadcom-firmware TEST=booted b0 board. messages printed on console: coreboot-bcf5dc0-dirty bootblock Mon Feb 9 13:33:55 PST 2015 starting... Exception handlers installed. Change-Id: I271ead2f4fe48b809fd311acd5a27a675dce549e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ddff8fb170e775a121150fce065410d2925ad18c Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Ia6e82fa89547d61745c1473f723897dc3c1296ef Original-Reviewed-on: https://chromium-review.googlesource.com/251301 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9765 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-04-20console: copy ns16550 driver from u-bootDaisuke Nojiri
BUG=chrome-os-partner:35807 BRANCH=broadcom-firmware TEST=none Change-Id: I40623e92f290e5c584a451d99071316b6fc35431 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 505720f734da7a4cdfaff8b2531385644141ba83 Original-Change-Id: I655c7065047971ab05a13e90ab911d7464a37552 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/251300 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9764 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-04-20chromeos: vboot2: Add TPM PCR extension supportJulius Werner
ChromeOS/vboot devices expect the TPM PCRs 0 and 1 to be extended with digests that attest the chosen boot mode (developer/recovery) and the HWID in a secure way. This patch uses the newly added vboot2 support functions to fetch these digests and store them in the TPM. CQ-DEPEND=CL:244542 BRANCH=veyron BUG=chromium:451609 TEST=Booted Jerry. Confirmed that PCR0 contains the same value as on my vboot1 Blaze and Falco (and PCR1 contains some non-zero hash). Original-Change-Id: I7037b8198c09fccee5440c4c85f0821166784cec Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/245119 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 8b44e13098cb7493091f2ce6c4ab423f2cbf0177) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I549de8c07353683633fbf73e4ee62ba0ed72ff89 Reviewed-on: http://review.coreboot.org/9706 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-20vboot2 workbuf alignment is now 16 bytes, not 8Bill Richardson
BUG=chromium:452179 BRANCH=ToT CQ-DEPEND=CL:243362 TEST=manual emerge-veyron_pinky coreboot Original-Change-Id: Ibcbaea2990e5e06ea7cfaaa5412ef7c1477f5fcc Original-Signed-off-by: Bill Richardson <wfrichar@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/243380 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> (cherry picked from commit 8e5c18eeb21944bdcb064b4491c6781d16ef5608) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I26f6fb67655cb1dfbdcdc48530ef6bfeb1aa692a Reviewed-on: http://review.coreboot.org/9705 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-20rk3288: Disable ramstage compression by defaultJulius Werner
The ramstage is loaded from romstage, so the LZMA scratchpad buffer used to decompress it is part of the romstage BSS in SRAM. On RK3288, SRAM cannot be cached which makes the decompression so slow that it's faster to just load an uncompressed image from SPI. Disable ramstage compression on this SoC to account for that. [pg: implementation avoids restructuring all of Kconfig] BRANCH=None BUG=None TEST=Built for Pinky and Falco, confirmed that the former didn't have COMPRESS_RAMSTAGE in its .config and the latter still did. Measured a speed-up of about 35ms on Pinky. (For some weird reason, the decompression of the payload also takes way longer than on other platforms, although not as long as the ramstage. I have no explanation for that and can't really think of a good way to figure it out... maybe the Cortex-A12 is just terrible at some operation that LZMA uses a lot?) Change-Id: I9f67f7537696ec09496483b16b59a8b73f4cb11b Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/234192 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9792 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-19southbrige/intel/bd82x6x: XHCI replace magic valuesNicolas Reinecke
Change-Id: I62674ccfb836fb0b02ac562f678cdfa44be98ae3 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/9779 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-18riscv: use new-style CBFS header lookupPatrick Georgi
We recently restructured where the CBFS header is stored and how it is looked up, with less magic. The RISC-V port didn't get the memo, so have it follow the pack now. Change-Id: Ic27e3e7f9acd55027e357f2c4beddf960ea02c4d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/9795 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-04-18vboot2: provide path for booting using alternative CBFS instancesVadim Bendebury
When CONFIG_MULTIPLE_CBFS_INSTANCES is enabled, the image is expected to have CBFS instances in rw-a and rw-b sections of the bootrom. This patch adds code which makes sure that CBFS header points at the proper bootrpom section as determined by vboot, and the RW stages load from that section. BRANCH=storm BUG=chrome-os-partner:34161, chromium:445938 TEST=with the rest of the patches in, STORM boots all the way into Linux login prompt. Original-Change-Id: I187e3d3e65d548c672fdf3b42419544d3bd11ea1 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/237662 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 71ad0bb41b183374a84a5b9fb92c3afd813ceace) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ia05cb713981c44da8cb379b72dfbe17fe1f6c5ff Reviewed-on: http://review.coreboot.org/9704 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-18vboot2: Implement new vb2ex_hwcrypto APIJulius Werner
This patch aligns our verstage code to the new API addition in vboot2. The hardware crypto functions are stubbed out by default and just pretend that all algorithms are unsupported, causing vboot to fall back to the normal software hashing code. These weak symbols can be overridden by individual platform code to provide actual hardware crypto engine support. CQ-DEPEND=CL:236453 BRANCH=None BUG=chrome-os-partner:32987 TEST=Booted Pinky, confirmed vboot falls back to software crypto. Original-Change-Id: Idf6a38febd163aa2bff6e9a0e207213f01ca8324 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/236435 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> (cherry picked from commit 9b5ee7f575f1aa3b0eb6ef78947ca93a4818f57b) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I6f0e19255a9bc5c5cd1767db76f1e47897ef0798 Reviewed-on: http://review.coreboot.org/9703 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-18vboot: make vboot2_verify_firmware returnDaisuke Nojiri
this allows each board to decide what to do after firmware verification is done. some board needs to return back to the previous stage and let the previous stage kick off the verified stage. this also makes it more visible what is going to happen in the verstage since stage_exit now resides in main(). BUG=none BRANCH=tot TEST=booted cosmos dev board. booted blaze in normal and recovery mode. built for all current boards. Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I3cb466cedf2a9c2b0d48fc4b0f73f76d0714c0c7 Original-Reviewed-on: https://chromium-review.googlesource.com/232517 (cherry picked from commit 495704f36aa54ba12231d396376f01289d083f58) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ic20dfd3fa93849befc2b37012a5e0907fe83e8e2 Reviewed-on: http://review.coreboot.org/9702 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-18ipq806x: initialize UART even when console is not enabledVadim Bendebury
The ipq806x UART is based on the same universal serial port which can be also configured as i2c or SPI. Configuring it is not a trivial task, so in case the kernel wants to use earlyprintk() the port needs to be configured by the firmware. Invoking uart_init() when the console is not enabled causes include file collisions, which would require changes to more than 100 files. Leaving this to another day, rearranging the ipq806x driver to be able to invoke UART initialization function even when serial console is not configured. Also add a check to avoid initialization if UART has been already set up. BRANCH=storm BUG=chrome-os-partner:35364 TEST=verified that storm console is still fully operational when enabled, and that the kernel boots fine to the serial console login prompt even if the firmware console is disabled. Change-Id: Ibbbab875449f2ac2f0d6c504c18faf0da8251ffa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c512d6c1d0c0868137d1213ea84cd4bca58872db Original-Change-Id: I421acba3edf398d960b5058f15d1abb80ebc7660 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/240516 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9794 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-18ipq806x: uart: replace hardware accessorsVadim Bendebury
Originally ported QCA UART driver used hardware accessor macros where both address and data were represented by 32 bit integers. Coreboot uses macros where addresses are represented by pointers, this make the code more robust, as accidental swap between address and data does not go unnoticed. This patch converts ipq806x UART driver to use coreboot accessors. It relies on gcc void pointer arithmetic considering objects pointed at by void pointers to be one byte in size. Also replacing spaces with hard tabs where appropriate. BRANCH=storm BUG=chrome-os-partner:34790 TEST=new code still boots fine on Storm with console output present. Change-Id: I3ded9c338ff241bb1d839994f7296756aad8772d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 10616351704ebbcfcf25793ae974b256bc5bd6b0 Original-Change-Id: Ie15e09f9f3ea10a8566b6845219c2e09fed39218 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/240514 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org> Reviewed-on: http://review.coreboot.org/9793 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-18broadwell: Set C9/C10 vccminDuncan Laurie
This is done via a PCODE mailbox write. BUG=chrome-os-partner:37043 BRANCH=broadwell TEST=build and boot on samus Change-Id: I95e8fe3e28eec76d6b5b488a0c770c04f408700e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b90bef7f708b1ce83f6e124f4b38ae51ec6b0597 Original-Change-Id: I95cd4c17db672a53ba05f85ba5fa7bc866af1543 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/252862 Original-Reviewed-by: Alec Berg <alecaberg@chromium.org> Original-Reviewed-by: Shawn N <shawnn@chromium.org> (cherry picked from commit ab6b4bddf3365713aa40d194c2dbd3e59985f00d) Original-Reviewed-on: https://chromium-review.googlesource.com/252883 Reviewed-on: http://review.coreboot.org/9783 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-18broadwell: Disable XHCI compliance mode entryDuncan Laurie
To avoid entries with Type-C alternate mode devices disable compliance mode entry. This needs to be set on both boot and resume. BUG=chrome-os-partner:35320 BRANCH=samus TEST=manual: 1) boot on samus with USB keyboard plugged in -> controller in D0 at boot 2) iotools mmio_read32 0xe12080ec == 0x18010c01 3) suspend and resume 4) iotools mmio_read32 0xe12080ec == 0x18010c01 5) remove USB keyboard -> controller in D3 6) iotools mmio_read32 0xe12080ec == 0xffffffff 7) plug in USB keyboard -> controller in D0 8) iotools mmio_read32 0xe12080ec == 0x18010c01 9) boot with no external USB devices -> controller in D3 at boot 10) iotools mmio_read32 0xe12080ec == 0xffffffff 11) plug in USB keyboard -> controller in D0 12) iotools mmio_read32 0xe12080ec == 0x18010c01 Change-Id: I4d566112b3c188bafdf9a4bbd92944c89500e3e8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: db8c8ab8ff25f6a39cd50dcc91b5ba9fd7d05059 Original-Change-Id: I8b68ba75e254a7e236c869f4470207eb5290053d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/251361 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9782 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-18panther: Fix pointer related errors in LAN codeFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles and boots to "starting kernel" on panther Change-Id: Ic71aea6d8939a4fa3cd890e2048fff22ea25d186 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4b5515bd00b76332748e4181cdf984c98a83993a Original-Change-Id: I2f890871ad7cddaf132a0fa59a93f05c51d0c00e Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/234982 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9781 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-18soc/intel/common: Add common reset codeLee Leahy
Move reset support into the Intel common branch. Prevent breaking of existing platforms by using a Kconfig value to select use of the common reset code. BRANCH=none BUG=None TEST=Build and run on Glados Change-Id: I5ba86ef585dde3ef4ecdcc198ab615b5c056d985 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 85d8a6d9628a66cc8d73176d460cd6c5bf6bd6b2 Original-Change-Id: I5048ccf3eb593d59301ad8e808c4e281b9a0aa98 Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/248301 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/9505 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-26 02:11:37 +0000