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2019-01-25mb/google/octopus: Override emmc DLL values for AmptonKane Chen
New emmc DLL values for Ampton BUG=b:122307153 TEST=Boot to OS on 5 systems Change-Id: Iadd58d254f4bb384f483c2c3e5615f7569d5211c Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/31048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-01-25mb/google/sarien: Force power on after cr50 updateDuncan Laurie
By default this board is configured to not power up after an EC reset. However in the case of a cr50 firmware update that will reset the EC it will end up powered off. In order to have it stay powered up configure the board to power up. This will get reset to the configured default when it boots again. BUG=b:121380403 TEST=update cr50 firmware and reboot to ensure system boots and does not end up powered off. Change-Id: I85beae24b1bc56bb0813f1fd1305218f04b0c1c8 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31058 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-25vendorcode/google/chromeos: Add mainboard hook before cr50 updateDuncan Laurie
In order to allow the mainboard to configure the system before a cr50 initiated update reset add a weak function that the mainboard can override if necessary. This will allow a board that would otherwise be configured to stay off after an EC reset to instead power up after the reset and not end up in a shut down state after a cr50 update. BUG=b:121380403 TEST=update cr50 firmware on sarien and reboot Change-Id: I11f9e8c9bfe810f69b4eaa2c633252c25004cbd0 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31057 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-25soc/intel/cannonlake: Export function to set After G3 stateDuncan Laurie
Export the SOC level function to set the After G3 state so it can be changed by the mainboard. The setting will be restored by a normal boot but in some circumstances coreboot wants to ensure that it will be powered up again after a reset. BUG=b:121380403 TEST=update cr50 firmware on sarien and reboot and ensure the host does not power off after the cr50 initiated reset. Change-Id: I6cd572ac91229584b9907f87bb4b340963203c32 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31056 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-25soc/intel/cannonlake: Disable CpuRatio and SaGv in recoveryDuncan Laurie
Disabling CpuRatio UPD for FSP will ensure it does not force a hard reset to set the CPU Flex Ratio at boot. This is important in a recovery mode boot where the SOC will lose power and need to set the flex ratio again. Disabling SaGv makes recovery mode training faster and mirrors the setting that was done on Skylake. BUG=b:123305400 TEST=reliably enter recovery mode on sarien Change-Id: Ie9664493a980af9acce82faff81f4c4b1355be73 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-01-25mb/google/sarien: Increse BIOS region size to 28MBLijian Zhao
Increase BIOS region(SI_BIOS) from 16MB to 28MB to make more spaces for upcoming payloads. BUG=b:121169122 TEST=Build and boot up fine into OS on sarien and arcada platform. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I4b03e20a485cb819b468c00e68f1539e92731237 Reviewed-on: https://review.coreboot.org/c/31054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-25soc/intel/apollolake: Override GLK usb clock gating registerJohn Zhao
It was observed system suspend/resume failure while running RunInDozingStress. Apply correct GLK usb clock gating register value to mitigate the failure. BRANCH=octopus BUG=b:120526309 TEST=Verified GLK clock gating register value after booting to kernel. Change-Id: I50fb16f5ab0e28e79f71c7f0f8e75ac8791c0747 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-25mb/google/kahlee/variants/aleena: Add support Synaptics touch padLucas Chen
Add support Synaptics touch pad for Aleena/Kasumi. BUG=b:122549449 BRANCH=master TEST= Check if synaptics touch pad working in ChromeOS. Change-Id: Icab1b312f1943b27037ef458044ce9e7172919ee Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/31064 Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-25sb/intel/common: Show "Add gigabit ethernet firmware" only for boards that ↵Jan Tatje
need it Hide "Add gigabit ethernet firmware" option for boards that do not use GbE firmware in GbE section. The option is now hidden by default and can be reenabled on a per-board basis by selecting MAINBOARD_USES_IFD_GBE_REGION in the mainboards Kconfig. The following boards seem to use this: mb/roda/rv11 mb/ocp/wedge100s mb/ocp/monolake mb/lenovo/x230 mb/lenovo/x220 mb/lenovo/x201 mb/lenovo/x200 mb/lenovo/t530 mb/lenovo/t520 mb/lenovo/t430s mb/lenovo/t430 mb/lenovo/t420s mb/lenovo/t420 mb/lenovo/t400 mb/kontron/ktqm77 mb/intel/saddlebrook mb/intel/kblrvp mb/intel/dg43gt mb/intel/dcp847ske mb/intel/coffeelake_rvp mb/intel/camelbackmountain_fsp mb/hp/revolve_810_g1 mb/hp/folio_9470m mb/hp/compaq_8200_elite_sff mb/hp/8770w mb/hp/8470p mb/hp/8460p mb/hp/2760p mb/hp/2570p mb/google/sarien mb/facebook/watson mb/compulab/intense_pc mb/asus/maximus_iv_gene-z The boards were identified by looking at devicetree.cb, but this list is possibly still incomplete. Change-Id: Ibfb07902ad93fe5ff2bd4f869abcf6579f7b5a79 Signed-off-by: Jan Tatje <jan@jnt.io> Reviewed-on: https://review.coreboot.org/c/30790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-25mb/{kontron,supermicro}: Use pcidev_on_root()Elyes HAOUAS
Change-Id: I61b3e5c92830f02d61a108dadde25ff261099e57 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2019-01-25nb/intel/sandybridge/acpi: Add RMRR entry for iGPUNico Huber
The iGPU always needs access to its stolen memory. For proper IOMMU support, we have to make the OS aware of that. Directly below TOLUD lies the data stolen memory (BDSM) followed by the GTT stolen memory (BGSM), the iGPU needs access to both. Change-Id: I391d0a5f1ea14bc90fbacabce41dddfa12b5bb0d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/29668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-01-24src/mb/asrock/../g41m-s3: Remove spurious devicesAngel Pons
This fixes errors regarding "PCI: Leftover static devices" Change-Id: Ie45fe6934df4a9dad4c8f6b1af665034853c4c5a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/31020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-24ec/google/wilco: Turn on wake up from lidLijian Zhao
Send required EC command to enable ACPI S3 wake up from lid switch. BUG=b:120748824 TEST=Put Sarien system into S3 and then wake up from lid switch successful. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I13f3469847b0886147b8b624311a1ece796f847b Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-24mb/*/*/devicetree.cb: Move the ioapic device under the LPC bridgeArthur Heymans
This fixes spurious lines "child IOAPIC: 02 not a PCI device" and IOAPIC as leftover device. Change-Id: Id8010c84c45f0859508e7564c0eaa501904b7043 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/31041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-24Revert "soc/intel/denverton_ns: Rewrite pmutil using pmclib"Patrick Georgi
This reverts commit ab1227226ebd78b40783cb200e60711b900352f0. There were significant changes around soc_reset_tco_status() that this code needs to be adapted to. Change-Id: I563c9ddb3c7931c2b02f5c97a3be5e44fa873889 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/31071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-24mb/google/sarien/variants: Set tcc offset valueSumeet Pawnikar
Set tcc offset value to 5 degree celsius for Sarien system. BRANCH=None BUG=b:122636962 TEST=Built and tested on Sarien system Change-Id: I06fbf6a0810028458bdd28d0d8a4e3b645f279ca Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/31037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2019-01-24riscv: ARCH_RISCV_RV{32,64} selects ARCH_RISCVRonald G. Minnich
ARCH_RISCV_RV{32,64} will now select ARCH_RISCV. Change-Id: Ia7a1a8f0bfab20e91b8429dd6dd3e9a4180a0a5b Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/c/31042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx>
2019-01-24soc/intel/denverton_ns: Configure MCAJulien Viard de Galbert
Change-Id: I101eb4f008a13af92bac5ed738a8d1f1f8c65eba Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/c/25433 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24soc/intel/denverton_ns: Use cpulib in cpu.cJulien Viard de Galbert
Also remove duplicate code Change-Id: I45da6363a35cf6f5855906bb97ed023681d36df7 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/c/25432 Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Guckian Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24soc/intel/denverton_ns: Enable Fast StringsJulien Viard de Galbert
Change-Id: I7cee3c40299abf14a24128b1ac14f1823f87a0e1 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/c/25431 Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Guckian Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24soc/intel/denverton_ns: Rewrite pmutil using pmclibJulien Viard de Galbert
Change-Id: If31e7102bf1b47c7ae94b86d981b762eda0a19e5 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/c/25427 Reviewed-by: David Guckian Reviewed-by: King Sumo <kingsumos@gmail.com> Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24soc/intel/common/block/acpi: fix P-States extra entryJulien Viard de Galbert
The ratio_max step is appearing twice when (ratio_max - ratio_min) is evenly divisible by the ratio step. This is because in this case there are no rounding down of ratio_max in the for loop. Thanks Jay Talbott for the step calculation algorithm. Change-Id: I91090b4d87eb82b57055c24271d679d1cbb3b7a7 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/c/25429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-24ec/kontron: Add support for Kontron kempldNico Huber
A programmable logic device used by Kontron as EC on their COM express modules. The name `kempld` is taken from Linux kernel sources, as is the I2C driver. The meaning of the acronym is unclear, probably: Kontron Embedded Module PLD. Change-Id: If9a0826c4a8f5c8cd573610c2d10561334258b36 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/29476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-01-24mb/google/sarien: Fix recovery mode detectionDuncan Laurie
In order to support the physical recovery GPIO on sarien it needs to enable the option VBOOT_PHYSICAL_REC_SWITCH and set the GPIO number in the coreboot table appropriately so that depthcharge can correctly determine the GPIO number. The same is done for the write protect GPIO in this table. Additionally since we are reading a recovery request from H1 it needs to cache the result since H1 will only return true on the first request. All subsequent queries to H1 will not indicate recovery. Add a CAR global here to keep track of the state and only read it from H1 the first time. BUG=b:121380403 TEST=test_that DUT firmware_DevMode Change-Id: Ia816a2e285d3c2c3769b25fc5d20147abbc71421 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31043 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24mb/google/octopus/bobba: Add support to handle PEN_EJECT eventKarthikeyan Ramasubramanian
Enable gpio_keys driver for bobba and add required configuration in the device tree to handle the pen eject event. BRANCH=octopus BUG=b:117953118 TEST=Ensure that the system boots to ChromeOS. Ensure that the stylus tools open on pen eject. Ensure that the system wakes on Pen Eject. Ensure that the system enters S0ix and S3 states after the pen is ejected. Ensure that the system enters S0ix and S3 states when the pen remains inserted in its holder. Ensured that the system does not wake when the pen is inserted. Ensure that the suspend_stress_test runs successfully for 25 iterations with the pen placed in its holder. Change-Id: I768b89d2b45f4dcab6d235b11ce00544a827f22d Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/30108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-24drivers/generic/gpio_keys: Add trigger for wakeup event actionKarthikeyan Ramasubramanian
Currently without any trigger the wakeup event is generated on both the rising and falling edges of the GPIO input. Add support to specify the trigger explicitly so that the configuration can be passed to the kernel. BRANCH=octopus BUG=b:117953118 TEST=Ensure that the system boots to ChromeOS. Ensure that the stylus tools open on pen eject. Ensure that the system wakes on Pen Eject. Ensure that the system enters S0ix and S3 states after the pen is ejected. Ensure that the system enters S0ix and S3 states when the pen remains inserted in its holder. Ensured that the system does not wake when the pen is inserted. Ensure that the suspend_stress_test runs successfully for 25 iterations with the pen placed in its holder and ejected from its holder. Change-Id: Ifb08ba01106031aa2655c1ae2faab284926f1ceb Signed-off-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-on: https://review.coreboot.org/c/30451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-24soc/intel/gpio: Enable configuring GPIO debounce durationKarthikeyan Ramasubramanian
Add new helper macros to enable configuring debounce duration for a GPIO input. Also ensure that the debounce configuration is not masked out. BRANCH=octopus BUG=b:117953118 TEST=Ensure that the system boots to ChromeOS. Ensure that the debounce duration is configured as expected. Change-Id: I4e3cd7744867bcfbaed7d3d96fed4e561afb2cec Signed-off-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-on: https://review.coreboot.org/c/30450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-24soc/intel/common/gpio_defs: Enable configuring GPIO_DW2 pad registerKarthikeyan Ramasubramanian
Currently all the helpers support configuring GPIO_DW0/1 registers. In some architectures there is an additional configuration GPIO_DW2 register that can be used to configure debounce duration etc. Add a helper macro to enable configuring GPIO_DW2 pad register. BRANCH=octopus BUG=b:117953118 TEST=Ensure that the system boots to ChromeOS. Ensure that the current configuration is not disturbed by turning on the GPIO_DEBUG option and verifying the debug output before and after the change. Change-Id: I3e5d259d007fdc83940a43cc4cd4a2b8a547d334 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-on: https://review.coreboot.org/c/30449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-24cbmem_top: Fix comment and remove upper limitPatrick Rudolph
There's no such limit on 64 Bit coreboot builds. * Fix comment in cbmem.h * Remove 4 GiB limit on Cavium SoCs Tested on opencellular/elgon. Still boots Linux as payload. Change-Id: I8c9c6a5ff81bee48311e8bf8e383d1a032ea3a6d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/30609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-01-24soc/cavium/cn81xx: Replace uses of dev_find_slot()Kyösti Mälkki
Change-Id: I9f176caff3b6423121676eb895f5f68a5b926de4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-24mediatek/mt8183: Move some initialization into mt8183_early_initYou-Cheng Syu
MT8183 only allows booting from eMMC, so we have to do eMMC emulation from an external source, for example EC, which makes the size of bootblock very important. This CL adds a new function mt8183_early_init, which includes all initializations that should be done in early stages. All mainboards using MT8183 should manually call it in either bootblock or verstage. BRANCH=none BUG=b:120588396 TEST=manually boot into kernel Change-Id: I35d7ab875395da913b967ae1f7b72359be3e744a Signed-off-by: You-Cheng Syu <youcheng@google.com> Reviewed-on: https://review.coreboot.org/c/31024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-01-24cr50: Add probe command to poll Cr50 until DID VID is validKeith Short
Added new routine cr50_i2c_probe() which ensures that communication with the Cr50 over I2C is good prior to attempting other initialization of the Cr50 and TPM state. This avoids a race condition when the Cr50 is first booting that it may reset it's I2C slave interface during the first few I2C transactions initiated from coreboot. BUG=b:120009037 BRANCH=none TEST=Run the Cr50 factory update against Careena board. Confirm that I2C reads are retried until the DID VID is valid. Tested against debug Cr50 firmware that forced failure of cr50_i2c_probe() and verfied that coreboot shows recovery screen. Change-Id: I47c59a32378ad00336277e111e81ba8d2d63e69a Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/30295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2019-01-24mb/google/hatch: Enable support for WWANMaulik V Vaghela
This patch enables relevant GPIOs to enable WWAN. WWAN also requires to enable USB 2 port 6 and USB3 port 5 which is already enabled in device tree related changes. BUG=b:120914069 BRANCH=none TEST=check if code compiles with changes. Change-Id: I1559bbc6168aec1a369bf3291d2c1e2f9a2fbe07 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/30678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-24mb/google/hatch: Enable PCIe WLAN and BTMaulik V Vaghela
Enable PCIe WLAN for hatch 1. Enable PCI port 14 for PCIe WLAN 2. Enable CLKREQ, CLK SRC 3 for PCI port 14 3. GPIO pad config for WLAN and BT USB port for BT has already been enabled so not included in this patch BUG=b:120914069 BRANCH=none TEST=check if code compiles correctly and verify GPIO configuration with schematics Change-Id: I4f2a6eb37a467ad8b8cdde8fe6b657fabb383b04 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/30467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2019-01-24nb/intel/x4x: Put stage cache in TSEGArthur Heymans
TSEG is not accessible in ring 0 after it is locked in ramstage, in contrast with cbmem which remains accessible. Assuming SMM does not touch the cache this is a good region to cache stages. Tested on Intel DG41WV, the stage cache gets properly created and used on S3 resume. Change-Id: Ie46c1416f8042d5571339b36e1253c0cae0684b8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25606 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24nb/intel/pineview: Put stage cache in TSEGArthur Heymans
TSEG is not accessible in ring 0 after it is locked in ramstage, in contrast with cbmem which remains accessible. Assuming SMM does not touch the cache this is a good region to cache stages. Tested on Foxconn D41S. Change-Id: I3d163e8ff328ba01425b524a673f34a96fb93ea7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25605 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24nb/intel/gm45: Put stage cache in TSEGArthur Heymans
TSEG is not accessible in ring 0 after it is locked in ramstage, in contrast with cbmem which remains accessible. Assuming SMM does not touch the cache this is a good region to cache stages. Tested on Lenovo thinkpad X200: on cold boot the external stage cache gets created and the cached ramstage gets successfully used on the S3 resume path. Change-Id: I642f7d6ae5523a35904c8e1f029027565a364d26 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25604 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24nb/intel/i945: Put stage cache in TSEGArthur Heymans
TSEG is not accessible in ring 0 after it is locked in ramstage, in contrast with cbmem which remains accessible. Assuming SMM does not touch the cache this is a good region to cache stages. Tested on Intel D945GCLF and Lenovo Thinkpad X60, on cold boot the external stage cache gets created and the stage cache gets properly used on S3 resume. Change-Id: I447815bb0acf5f8e53834b74785d496f9d4df1da Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25603 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24cpu/intel: Configure IA32_FEATURE_CONTROL for alternative SMRRArthur Heymans
Some CPUs, (Intel core2 and pineview) have slightly different SMRR MTRR mechanism. The MSR_SMRR_PHYSBASE/MASK MSRs are at a different location, have slightly different semantics and need SMRR enable in a locked down IA32_FEATURE_CONTROL MSR. This change takes away the possibility to (not) lock IA32_FEATURE_CONTROL on these CPUs, as this is needed for SMRR MSR to work. Since sockets cover multiple CPUs of which only some support SMRR, the Kconfig option CONFIG_SET_IA32_FC_LOCK_BIT is kept in place, even though it gets meaningless on those CPUs. Locking that bit was the default anyway. With this patch Intel Netburst CPUs also configure IA32_FEATURE_CONTROL. According to Intel 64 and IA-32 Architectures Software Developer's Manual those CPUs support that MSR so issues are not to be expected. Change-Id: Ia85602e75385e24ebded75e6e6dd38ccc969a76b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/27586 Tested-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2019-01-24Kconfig: Remove symbol names for choicesNico Huber
These are completely throwing Kconfig off, resulting in duplicate entries. Change-Id: I401467da686d5011a456b661a10170492a919c81 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/30582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-01-24cpu/intel/model_406dx: Remove the notion of CPU socketsArthur Heymans
Change-Id: I5e8fb2e7331d02224a4199c4d05f92c603c57f78 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/31032 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24cpu/intel/model_206ax: Remove the notion of socketsArthur Heymans
With the memory controller the separate sockets becomes a useless distinction. They all used the same code anyway. UNTESTED: This also updates autoport. Change-Id: I044d434a5b8fca75db9eb193c7ffc60f3c78212b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/31031 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24sb/intel/common: More SMBus block_cmd_loop()Kyösti Mälkki
Setup to different block transactions are similar enough to have common place to call execute_command() in. Change-Id: I671fed280f47e6bc673eb7506f09ed6ed36d2804 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/26763 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24sb/intel/common: SMBus block_cmd_loop()Kyösti Mälkki
For debugging prints, report the number of loop spent polling instead. Change-Id: I61865aaafc9f41acd85c5dc98817d12642965ba4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/21121 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24sb/intel/common: SMBus complete_command()Kyösti Mälkki
Adds helper to test for SMBHSTSTAT flags for hardware having finished or failed a transaction. Change-Id: Idea15e03edde7aeedf198c1529f09c24a5bc0b06 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/21120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-24sb/intel/common: SMBus execute_command()Kyösti Mälkki
Implement the common start of transaction. Fixes a problem where smbus_wait_until_active() can miss SMBHSTSTS_HOST_BUSY being set, if transaction completes very fast. Or if we are single-stepping or executing under SerialIce emulation. Change-Id: Icb27d7d6a1c54968950ca292dbae05415f97e461 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/21119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-24sb/intel/common: SMBus setup_command()Kyösti Mälkki
Implements the common parts of any SMBus transaction with a stub to log and recover (TBD) from timeout errors. Bits in SMBHSTCTL register are no longer preserved between transactions. Change-Id: I7ce14d3e895c30d595a94ce29ce0dc8cf51eb453 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/21118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-24mb/ocp/wedge100s: Add SuperIO supportPatrick Rudolph
* Enable COM1, COM2, PMC1 and PMC2 TODO: Look at additional configuration and EC space. Tested on wedge100s. The serial works without CONFIG_CONSOLE_SERIAL. Change-Id: Id139bf243c7e7ac3e51a0ddb19d2396452341e29 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/30961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-24superio/ite: Add it8528ePatrick Rudolph
* Add support for the SuperIO part of IT8528E * Based on the IT8528E datasheet and tests on vendor firmware TODO: Add support for accessing EC space, which should be implemented in src/ec/ instead, as it's a separate logical unit. No datasheet is publicy available. Tested on wedge100s. The serial works under the OS without CONFIG_CONSOLE_SERIAL. Change-Id: I72aa756e123d6f99d9ef4fe955c4b7f1be25d547 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/30957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-24AGESA fam12/fam14: Drop amdfamX.c file includeKyösti Mälkki
Quick and ugly approach, just paste the file in place, dropping any __PRE_RAM__ parts. That's the way it was previously done for fam15tn already, refactoring common parts will happen on a later date. Change-Id: I29fd421fb4aef984d117912ac836dee71d3d73ea Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-01-24superio/it8716f: fix pnp_dev_infoFelix Held
Change-Id: If6a4b6f52425a795af34264ab839968b36a117eb Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/30960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-01-24superio/wpcm450: fix keyboard IO masksFelix Held
The two IO regions of the keyboard controller are 1 byte long, not 8. Change-Id: I7319ce9f84181759f4dc7b59c0020f3a5dd5dc03 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/30958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-01-23mb/google/sarien: Replace B0D4 with TCPUSumeet Pawnikar
Replace B0D4 with TCPU for DPTF thermal sensor. This helps to maintain consistency between coreboot and UEFI BIOS. Change-Id: I024068c19160e1c08badef3d304ada14455c045f Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/31028 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23soc/intel/cannonlake: Replace device name B0D4 with TCPUSumeet Pawnikar
Replace device name from B0D4 with TCPU for DPTF sensor. This helps to maintain consistency between coreboot and UEFI BIOS. Change-Id: I962d74fc1baa07581d065734aaabb4dcd5e3d247 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/31029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-23mb/*/*/devicetree.cb: Make sandybridge devicetree uniformArthur Heymans
This is a merely cosmetic change. Change-Id: If36419fbee9628b591116604bf32fe00a4f08c17 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/31030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2019-01-23i945,ICH7: Write on RPFN only onceElyes HAOUAS
RPFN is a R/WO register we write on it in i945/early_init.c and i82801gx/pcie.c Drop the romstage write. Change-Id: If9a131ad12530876a650b7a38daa9c9fc52aefb7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-01-23soc/amd/stoneyridge/gpio: Allow specifying 0 value for debounce timeoutDaniel Kurtz
It is possible to configure debounce, but leave it disabled by specifying a 0 value for the timeout. Add a define for allowing to do so via the PAD_DEBOUNCE() macro. Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> BUG=b:113880780 BRANCH=none TEST=compile Change-Id: I9de61297b0677cc904535a51c16970eecb52021d Reviewed-on: https://review.coreboot.org/c/30998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2019-01-23mb/intel/icelake_rvp: Enable dptf functionalitySumeet Pawnikar
Enable dptf functionality for IceLake based U and Y systems. Change-Id: I8ef396f9df8e39300d5870fd9a147ecdd6f0ba90 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/29686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-23mb/intel/glkrvp: Fix termination for dual voltage pinsShamile Khan
These pins should not have pull downs configured in standby state as that can cause contention on the termination circuitry and lead to incorrect behavior as per Doc# 572688 Gemini Lake Processor GPIO Termination Configuration. BUG=b:79982669 TEST=Checked that code compiles with changes. Change-Id: I8156c67df152555ecf9e7be9e4851468538bcff1 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/c/30867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: John Zhao <john.zhao@intel.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-23google/kukui: Revise FMAP layout for larger CBFSHung-Te Lin
Kukui with vboot enabled will build with `detachable_ui`, which needs larger space in CBFS for more complicated assets. So we need to revise FMAP sections: - BOOTBLOCK (not really used) only needs <= 32K. - GBB can be much smaller since assets moved from GBB to CBFS. - FMAP is re-ordered (with the cost of less efficient in bsearch) so CBFS can get larger continuous space. - COREBOOT(CBFS) should take all space left. Since FMAP and COREBOOT have changed location, the system will need to reflash EC (which contains the new bootblock) as well. BUG=b:123202015 TEST=Builds and boots on Kukui P1 Change-Id: I22cff99dca8c396c5897c3f6631721af40f3ffbd Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/31035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: You-Cheng Syu <youcheng@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-01-23mb/google/poppy/variant/nami: disable unused usb2 portsRen Kuo
disable unused usb2 ports of bard and ekko skus BUG=120874946 TEST=build a test firmware and run lsusb to check usb ports Change-Id: I2ef3cd17ada8b65c96bc80675650905949f235e1 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30986 Reviewed-by: Vincent Wang <vwang@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23mb/google/arcada: Add settings for noise mitgationCasper Chang
Enable acoustic noise mitgation for arcada platform, the slow slew rates are fast time dived by 2. BUG=none BRANCH=none TEST=none Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: Ia838818a76a7f638b24146f3eb48493a4091c9cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/31034 Reviewed-on: https://review.coreboot.org/c/31034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-23mb/lenovo/x131e: add VBTJames Ye
VBT was extracted from VBIOS ROM. Tested with libgfxinit, booting SeaBIOS into Linux. Change-Id: Ibedb43852dc9b846850e1070b84f708c847b7dbf Signed-off-by: James Ye <jye836@gmail.com> Reviewed-on: https://review.coreboot.org/c/31003 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23nb/intel/pineview: Use parallel MP initArthur Heymans
Remove guards around CPU code on which all platforms use parallel MP init code. This removes the option to disable HT siblings. Tested on Foxconn D41S. Change-Id: I89f7d514d75fe933c3a8858da37004419189674b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25602 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23nb/intel/x4x: Use parallel MP initArthur Heymans
Use parallel MP init code to initialize all AP's. Also remove guards around CPU code where all platforms now use parallel MP init. This also removes the code required on lapic init path for model_6fx, model_1017x and model_f4x as all platforms now use the parallel MP code. Tested on Intel DG41WV, shaves off about 90ms on a quad core. Change-Id: Id5a2729f5bf6b525abad577e63d7953ae6640921 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25601 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23nb/intel/i945: Use parallel MP initArthur Heymans
Use the parallel mp init path to initialize AP's. This should result in a moderate speedup. Tested on Intel D945GCLF (1 core 2 threads), still boots fine and is 26ms faster compared to lapic_cpu_init. This removes the option to disable HT siblings. Change-Id: I955551b99e9cbc397f99c2a6bd355c6070390bcb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-01-23nb/intel/gm45: Use parallel MP initArthur Heymans
This places the parallel mp ops up in the model_1067x dir and is included from other Intel core2 CPU dirs that can use the same code. Tested on Thinkpad X200 on which boot time is reduced by ~35ms. Change-Id: Iac416f671407246ee223075eee1aff511e612889 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/23434 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23mediatek/mt8183: Add Micron 4GB LPDDR4X DDR supportHuayang Duan
BUG=b:80501386 BRANCH=none TEST=Boots correctly and stress test pass on Kukui. Change-Id: I985c5061ce4ed4d88a17619aa5cde7d0121dd3a3 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/31033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-01-23soc/intel/baytrail/romstage: Remove unneeded white spaceElyes HAOUAS
Change-Id: I6725d1130a40d3c458a3cd5a116d6e91354ec41b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-23src/drivers: Remove needless '&' on function pointersElyes HAOUAS
Change-Id: I7a99d0dcbc8ea1362a12a68fa519c49058d30a05 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-23soc/{amd,intel}: Remove needless '&' on function pointersElyes HAOUAS
Change-Id: I7a59fd2f370d2b0d830ca83be9a9bc1abe2750f5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
2019-01-23mb/purism/librem_skl: add 13v3 variantMatt DeVillier
The 13v3 is just a 13v2 with TPM added, so duplicate 13v2 config and change strings where needed. Leave MAINBOARD_PART_NUMBER unchanged since boards were initially shipped with 13v2 firmware, and changing it now would cause flashrom to throw a board mismatch error. Change-Id: I1a5e4c84cc9444bb9731b6dcc4de2ce7427dbbb1 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/31010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-23mb/purism/librem_skl: add support for 13v4/15v4 boardsMatt DeVillier
Add support for Kabylake Librem 13v4/15v4 boards, reusing existing 13v2/15v3 variants since board design unchanged (only SoC). Adjust identification strings, add Kabylake VGA PCI ID. Change-Id: Ia795b9c7373ea2e2acd3bef309320b58e9e8449d Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/31009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-23mb/purism/librem_skl: adjust CBFS_SIZEMatt DeVillier
Adjust default CBFS_SIZE to match that used in configs for building Change-Id: Ibe1312560a923dcdefb8af52a721ab76c0b08a2e Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/31008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-23mb/google/poppy/variants/nami: close the FP power in S5Ren Kuo
close the FP module power in power off (s5) BUG=122887366 BRANCH=Nami TEST= build test firmware and measure the fp power enable pin Change-Id: I80ddfbf1edf7c6435d263d5f5e0edb8b8701817d Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30910 Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Vincent Wang <vwang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23mb/google/hatch: Enable SD card support for hatchMaulik V Vaghela
Enable support for SD card support for hatch 1. Enable PCI device for SD and also configure SD detect GPIO 2. Configure SD card related GPIOs in gpio.c BUG=b:120914069 BRANCH=none TEST=Verify GPIO configuration with schematics Change-Id: I8ccaa28323b1e1fcc192e245347a96309227660b Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/30545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-01-23arch/x86: Align _start16bit with C_ENVIRONMENT_BOOBLOCKKyösti Mälkki
Followup removes SIPI_VECTOR_IN_ROM and it seems reasonable enough to force the alignment unconditionally to page size. Reason for the conditionals is the alignment is not possible with romcc bootblocks having total size less than 4 kiB. Change-Id: I0ff2786f80a319ebb3215d4fd696cda3e15c3012 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30855 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23Drop leftover debug function declarationsKyösti Mälkki
Change-Id: Ib93b816e7ab3146f6f70ad4089327cd6b7bc7c24 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: David Guckian Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-23mb/google/octopus: Override emmc DLL values for MeepKane Chen
New emmc DLL values for Meep. BUG=b:122308271 TEST=Boot to OS on 13 Meep system Change-Id: I4247114ed69ff3aa283f0f72d5531ad0f37309ad Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/31021 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-22mb/asus/kgpe-d16: Add BMC KCS to ACPITimothy Pearson
The BMC KCS interface must be advertised to the host OS in order for automatic load of the ipmi module to work. Expose the KCS interface via ACPI. Change-Id: Ia251334ae44668c2260d8d2e816f85f1f62faac7 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/c/19822 Reviewed-by: Piotr Kubaj <pkubaj@anongoth.pl> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-22mb/asus/kgpe-d16: Enable IPMI KCS accessTimothy Pearson
The on-board BMC contains a hardware KCS interface. Allow access to it over LPC. Change-Id: Ia251334ae44668c2260d8d2e816f85f1f62faac6 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/c/19821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-22Revert "UPSTREAM: mainboard/google/kahlee: Also configure GPIO_9 in RAM stage"Daniel Kurtz
This reverts commit 3278f859c3dd97a6d6d885a91dfd33d44e95d58b. Reason for revert: It turns out all we want to set in RAM stage is GPIO's DEBOUNCE config, not its SCI configuration. Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> BUG=b:113880780 BRANCH=none TEST=Boot grunt, does not go to recovery screen Change-Id: I500934f3e03e66c97873accd4a979a23d4509675 Reviewed-on: https://review.coreboot.org/c/30997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2019-01-22AGESA/binaryPI: Add NULL pointers checkKyösti Mälkki
Fix regression after commits 4ad7f5b AGESA: Use pcidev_on_root() 33ff44c binaryPI: Use pcidev_on_root() Previously used call dev_find_slot() returned pointers to PCI device nodes that were actually not present in the hardware at all. Register reads would come back with invalid (0xff) values and writes would be ignored. After change to pcidev_on_root(), attempting to do register operations with non-present PCI hardware immediately halts with error get_pbus: dev is NULL! Change-Id: I785350c171a642207c5fab884a953d45a3bfe592 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-22cpu/intel/model_206ax: Use parallel MP initArthur Heymans
This patch adds a few southbridge calls needed for parallel MP init. Moves the smm_relocate() function to smm/gen1/smi.h, since that is where this function is defined now. Tested on Thinkpad X220, shaves off ~30ms on a 2 core, 4 threads CPU. Change-Id: Ia1d547ed4a3cb6746a0222c3e54e94e5848b0dd7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25618 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-22cpu/intel/smm/gen1: Add pineview to the check for alt SMRR MSR'sArthur Heymans
Intel pineview has the same alternative SMRR MSR and IA32_FEATURE_CONTROL enable bit as core2 CPUs so properly check for that before enabling this feature. This also exposes a function to fetch whether alternative SMRR MSR's ought to be used. Change-Id: Iccaabfa95b8dc4366b8e7e2c2a526081d4af0efa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30868 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-22mb/google/hatch: Remove MAINBOARD_USES_IFD_EC_REGION selectionSubrata Banik
hatch shouldn't make use of internal ec.bin through IFD tool. Change-Id: Ib1a324291b1c8ac90a7d790b63427b2e85c74fd1 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/31022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2019-01-21Revert "soc/amd/stoneyridge/gpio: Configure debounce for irq gpios"Raul Rangel
This reverts commit b82afce18aff24b6e5e3b73a67a6533cc4865a26. Reason for revert: This causes depthcharge to not boot due to TPM timeout errors. Because there is no wait after setting the debounce register, we lose data because the read-modify-write loses the interrupt status bit. e.g., GPIO 5 sets debounce, without a wait. Then GPIO 9 has it's debounce set. Because the interrupt controller is masking the interrupt enable status bit, the read-modify-write for GPIO9 loses the interrupt enable status bit and it never gets set again. This causes the interrupt to never latch. We should possibly make depthcharge set the interrupt enable status bit for latched GPIOs. Change-Id: Idd7259b14b24c441529d64e173be9faec03f4fc8 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/30981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2019-01-21lib/boot_device: Add API for write protect a regionRizwan Qureshi
Add API that should be implemented by the boot media drivers for write-protecting a subregion. Change-Id: I4c9376e2c2c7a4852f13c65824c6cd64a1c6ac0a Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/28724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-01-21drivers/spi: Add controller protection typeRizwan Qureshi
Some SPI controllers support both READ and WRITE protection add a variable to the protect API for the callers to specify the kind of protection they want (Read/Write/Both). Also, update the callers and protect API implementation. BUG=None BRANCH=None TEST=test that the mrc cache is protected as expected on soraka. Also tried if the read protection is applied correctly. Change-Id: I093884c4768b08a378f21242ac82e430ac013d15 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/30559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-01-20mb/google/octopus/variants: Disable xHCI compliance mode for FleexAmanda Huang
Some usb devices exhibits signal loss which causes xHCI entering compliance mode. The resolution is to disable xHCI compliance mode. BRANCH=octopus BUG=b:120009029 TEST=Verified usb operation successfully. Change-Id: Ic7fa08c894397598dee3c4ff9a764e43383a0627 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-01-20mb/google/octopus/variants/meep: Disable xHCI compliance modeWisley Chen
Some usb devices exhibit signal loss which causes xHCI entering compliance mode. The resolution is to disable xHCI compliance mode. BUG=b:122671995 TEST=check "Disable Link Compliance Mode" bit of "SuperSpeed Port Link control" register and usb operation successfully. Change-Id: Ia2ae7e52391fadc8ed23b8b76c45d410757d22ec Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/30948 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-20src/soc/intel/braswell: Use DEVICE_NOOPElyes HAOUAS
Use already defined DEVICE_NOOP instead. Change-Id: Ie6182f273cba3073c84a502c34a002dee6122c2f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29857 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-18soc/intel/denverton_ns: Select CPU_INTEL_FIRMWARE_INTERFACE_TABLEVanessa Eusebio
* Add CPU_INTEL_FIRMWARE_INTERFACE_TABLE Change-Id: I9d4901ea56d5bf5225a8f3a6015d2ea80a9e46b5 Signed-off-by: Vanessa Eusebio <vanessa.f.eusebio@intel.com> Reviewed-on: https://review.coreboot.org/c/26928 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-18mb/google/sarien/variants: Add Thermal Sensors informationSumeet Pawnikar
Add available thermal sensors information for CPU throttling action. BRANCH=None BUG=b:120058043 TEST=Built and tested on Arcada system Change-Id: I748ca0ce43915c96d71e63fb03fc3d1a02adc56c Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/30919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-18drivers/spi/winbond.c: Add the rest of >=1MB Winbond W25 chipsMike Banon
Required for ACPI S3 suspend support at some motherboards. Synchronizing with flashchips.c/h flashrom source code. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I4d15d5acf0e2044e5128ce809c282fbcb35f24f0 Reviewed-on: https://review.coreboot.org/c/30746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-01-18mb/google/sarien/variants/sarien: Adjust TP/TS/H1 I2C CLK to meet specDtrain Hsu
After adjustment on Sarien EVT TouchScreen: 380.7 KHz TouchPad: 379.3 KHz H1: 392.2 KHz BUG=b:122657195 BRANCH=master TEST=emerge-sarien coreboot chromeos-bootimage measure by scope Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I0dd92b054d934b38a17898dc8ce9cc18bda1633f Reviewed-on: https://review.coreboot.org/c/30949 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-17mb/lenovo/x220: Add x1 as a variantBill XIE
ThinkPad X1 ( https://www.thinkwiki.org/wiki/Category:X1 ) is nearly a clone of X220, with additional USB3 controller on pci-e (as i7 variant of x220), and a powered ESATA port wired to ata4 (Linux' annotation). Documentation added. Tested: - CPU i5-2520M - Slotted DIMM 8GiB - Camera - Mini pci-e on wlan slot - Msata on wwan slot - On board SDHCI connected to pci-e - USB3 controller connected to pci-e - NVRAM options for North and South bridges - S3 - TPM1 on LPC - Linux 4.9.110-3 within Debian GNU/Linux stable, loaded from SeaBIOS, or Linux payload (Heads) Not tested: - Fingerprint reader on USB2 - Onboard USB2 interfaces (wlan slot, wwan slot) Change-Id: Ibbc45f22c63b77ac95c188db825d0d7e2b03d2d1 Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/c/29434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-17mb/kontron/986lcd-m: Implement disabling ethernet NIC in ramstageArthur Heymans
With the i82801gx code automatically disabling devices ethernet NICs attached to the southbridge PCIe ports can now be disabled during the ramstage. Change-Id: If4163f8101d37cc09c0b51b1be20bf8388ed2b89 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30245 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-17sb/intel/i82801gx: Implement PCIe coalescingArthur Heymans
The implementation is a simplified version of the haswell/broadwell code. This also adds a chip option to enable coalescing from the devicetree. Change-Id: I6d7ddef96e4f45e163f7017175398a0938a18273 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-17vendorcode/{amd,cavium,intel}: Remove trailing whitespacePeter Lemenkov
find src -type f "!" -regex ".*\.\(vbt\|bin\)" -exec sed -i -e "s,\s\+$,,g" {} \; Change-Id: Ic70cf8524dcd0a0f5700f91b704b3c545dd8a01a Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/30959 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 07:42:58 +0000