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2018-12-05google/sarien: Increase BIOS region to 28MBLijian Zhao
Platform have a 32MB SPI chip, so we can increase the bios region from 16MB to 28MB. BUG=b:119267832 TEST=Build and boot fine on sarien platform. Change-Id: I9bc0fa0f662e5ec64e77f2005dbb2e7edb8b2524 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/29945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-05soc/amd/stoneyridge: Name IO061 in ASL appropriatelyMarshall Dawson
AMD traditionally claims the resource at I/O port 61 for the onboard PC-AT speaker. In later designs, the speaker may be omitted in favor of routing the SPKR signal to the codec. Some systems implement neither, and for those it is not correct to identify the resource as a speaker. Modify the EISAID reported to the OS depending on the system design. The default is that port 61 is reported as reserved. In order to report a speaker, add #define in mainboard//dsdt.asl. TEST=check /proc/ioports and iasl -d for both ways using a Grunt BUG=b:117818432 Change-Id: I33aafb187f9fea7b38aae43c399292c7521fcfc4 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/30037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-12-05src/(device/lib/soc): Remove unused variablesRichard Spiegel
When building grunt with flags set to detect variables that get a value but then are unused, there are 5 instances that causes error (unused variable). In most cases it's enough to simply remove the variable. Other instances, is better to simply use the variables (one instance it's a return value, on the other instance using the variables makes code more readable). BUG=b:120260448 TEST=Build and boot grunt. Change-Id: I0d00fb6a42db20afb34c76b9445a741a57096ead Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/29985 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-05mb/lenovo/x201/dsdt: Remove duplicated includePeter Lemenkov
Change-Id: Ifb08c903e19ef4e93bdc9cbc9844cb1888a8d2fa Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/29811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-12-05mb/lenovo/*/dsdt: Rearrange definesPeter Lemenkov
Sort mainboard-specific defines in the same order as in all other Lenovo boards. This is a purely cosmetic change which just makes diff between boards smaller. Change-Id: I4e379bb727b356fc6010e93de492f6d73f97a750 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/29544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-12-05mb/lenovo/*/dsdt: Move mainboard-specific defines out of ec.aslPeter Lemenkov
Most Lenovo mainboards define their own specific defines in dsdt.asl. Let's make it consistent across all Lenovo mainboards. Tested - builds fine. Change-Id: I03fbeb09b25e42af2dfbb220c0f726e6abb73673 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/29543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-12-05sb/intel/i82801{g,j}x: Remove unused smi.c filesArthur Heymans
Now that all targets featuring these southbridges use SMM_TSEG these files are unused. Change-Id: Ic3a1d790f3595e98a8d33e6e8274cb72ad356a89 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30018 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-05soc/sifive/fu540: Add helper function to get tlclk frequencyJonathan Neuschäfer
tlclk is not specific to the UART block in the FU540, so let's calculate its frequency in clock.c. Change-Id: I270920027f1132253e413a1bf9feb4fe279b651a Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/29335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Hug <philipp@hug.cx>
2018-12-05mb/emulation/spike-riscv: Implement mtime_initJonathan Neuschäfer
This patch lets spike boot to "Payload not loaded" again. Because soc/ucb/riscv/ does not represent a real SoC, but is a dummy directory for emulators, and different emulators might have different memory maps, I moved mtime_init to the mainboard-specific directories for Spike and QEMU. Change-Id: I080f7f81df752e25478bd277637bf894bbee4cb2 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/28873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx>
2018-12-05google/kukui: Support TPMTristan Shieh
Init SPI bus 0 to connect TPM, configure interrupt type of GPIO CR50_IRQ, implement tis_plat_irq_status(), and set up chromeos GPIO table for TPM interrupt. BUG=b:80501386 BRANCH=none Test=Boots correctly on Kukui. Change-Id: Ieaa6ae65fbfb5ab6323e226e8171dd7a992c3a39 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/29192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-12-05mediatek: Share GPIO external interrupts (EINT) code among similar SoCsChuanjia Liu
Refactor GPIO EINT code which can be reused among similar SoCs. BUG=b:80501386 BRANCH=none TEST=emerge-elm coreboot; emerge-kukui coreboot Change-Id: Ib01b43cf1aa4082d7d968fe1ef82f75e8cf05b8b Signed-off-by: Chuanjia Liu <Chuanjia.Liu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/29837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-12-05soc/intel/baytrail: Implement POSTCAR stageArthur Heymans
Use common code to tear down CAR. Change-Id: I62a70ae35fe92808f180f2b5f21c5899a96c2c16 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-05soc/intel/baytrail: Use postcar_frame functions to set up frameArthur Heymans
Change-Id: I77e375a2ff2fbf1be4ded922195b80b49ffa4cc5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29929 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-05soc/intel/baytrail: Improve CAR setupArthur Heymans
This patch does the following: - improve the style by removing tabs in front of jmp addresses - Make the code for zeroing variable MTRR more readable (copied from cpu/intel/car) - Fetch PHYSMASK high from cpuid instead of Kconfig Change-Id: I6ba67bb8b049c3f25b856f6ebb1399d275764f54 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-05soc/intel/broadwell: Implement postcar stageArthur Heymans
This does the following: - Reuse the cpu/intel/car/non-evict CAR setup and exit. - Use postcar_frame functions to set up the postcar frame Change-Id: I428832a2d7e46ce61a7f9bd498b609feb4518eb0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-05smmstore: make smmstore's SMM handler code follow everything elsePatrick Georgi
Instead of SMMSTORE_APM_CNT use APM_CNT_SMMSTORE and define it in cpu/x86/smm.h Change-Id: Iabc0c9662284ed3ac2933001e64524011a5bf420 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/30023 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-05elog: make elog's SMM handler code follow everything elsePatrick Georgi
Instead of ELOG_GSMI_APM_CNT use APM_CNT_ELOG_GSMI and define it in cpu/x86/smm.h Change-Id: I3a3e2f823c91b475d1e15b8c20e9cf5f3fd9de83 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/30022 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-05drivers/smmstore: Allow using raw FMAP regionsArthur Heymans
Use a raw fmap region SMMSTORE for the SMMSTORE mechanism, while keeping the initial option to use a cbfsfile. TESTED on Asus P5QC, (although it looks like the tianocore patches using it might need some love as they can't seem to save properly). Change-Id: I8c2b9b3a0ed16b2d37e6a97e33c671fb54df8de0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-05soc/intel/common/lpc_lib: Add function to disable LPC Clock RunNico Huber
Needed to fix up FSP-S bug on Apollo Lake. Change-Id: If09fee07debb1f0de840b0c0bd7a65d338665f7c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/29898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-05arch/x86/include/stdint: Fix PRIu64Patrick Rudolph
We alwas define uint64_t as unsigned long long, even on x86_64. Fix PRIu64 to match the definition of the datatype, to prevent compilation errors when compiling for x86_64. Change-Id: I7b10a18eab492f02d39fc2074b47f5fdc7209f3d Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/30002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-04mb/google/sarien: Enable WWAN detection on ArcadaLijian Zhao
Set GPIO D22 low to get WWAN_PERST#_R asserted. BUG=N/A TEST=Boot up with Arcada board, check WWAN get detected as USB devices through lsusb command. Change-Id: Ie848cd19fdf3b6c4b6abeb5fa3f566e5e4e7e928 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30030 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-04soc/intel/common: Limit BIOS region cache to 16MBLijian Zhao
Cache BIOS region can boost boot performance, however it can't be over 16MB, according to processor EDS vol1(Apollolake/Skylake/WhiskeyLake), FLASH+APIC LT will be less than 20MB under 4G. Set the maxiam to 16GB to save numbers of mtrr entries. BUG=b:119267832 TEST=Build and boot up fine on whiskeylake rvp platform. Change-Id: I46a47c8bf66b14fb2fcb7b6b1d30d02886c450a4 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/29944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-04mb/google/poppy/variant/nocturne: adjust RcompTarget to fix DRAM corruptionNick Vaccaro
BUG=b:111812662 TEST=flash to nocturne, boot nocturne, run "memtester 1g" and verify it passes. Change-Id: Iefc3957f915a39a47ad6018459e65b70d1b34091 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/29361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-04mb/google/sarien: Define USB devices for ACPIDuncan Laurie
Add the USB device information for the sarien/arcada variants. This includes the ACPI _PLD group definitions for the external ports that indicate which USB2 and USB3 ports share the same physical interface. Change-Id: I0b936127954ba09c61ccb871bfc62ee7d99da263 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/30000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-04mb/google/eve: Define USB port peersDuncan Laurie
Add ACPI _PLD group definitions for the external ports that indicate which USB2 and USB3 ports share the same physical interface. Change-Id: I7f85720a878a3774d453a9adb82518722f7ba23d Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-04acpi_pld: Make it easier to define the ACPI USB device groupsDuncan Laurie
The Linux kernel can use the ACPI _PLD group information to determine peer ports. Currently to define the group information the devicetree must provide a complete _PLD structure. This change pulls the group information into a separate structure that can be defined in devicetree. This makes it easier to set for USB devices in devicetree that do not need a full custom PLD. This was tested on a sarien board with the USB devices defined by verifying that the USB 2/3 ports are correctly identified with their peer in sysfs. Change-Id: Ifd4cadf0f6c901eb3832ad4e1395904f99c2f5a0 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-04soc/intel/cannonlake: Add USB device namesDuncan Laurie
Add the ACPI device names for the USB ports to match what is in the DSDT so USB ports can be defined in the SSDT. Change-Id: Ibb323bbd324811fa3178b0cba3d7f0a315169486 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-04soc/intel/cannonlake: Increase bootblock sizeDuncan Laurie
Increase the bootblock size to 48K to match skylake. With UART enabled we are very near the 32K limit, and with upcoming changes to add USB devices in devicetree for a cannonlake board it is over the current 32K limit. Change-Id: I155cb0a6af1746af6833fa9f35c2ea6fe0bc709f Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-04ec/google/wilco: Turn camera power onDuncan Laurie
Send the EC command required to turn the camera power on and verify that it shows up on the USB bus. Change-Id: I9e9ba712a11cef85cde91ac21a4b6b5090ef58dc Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-04mb/google/sarien: Enable DPTFDuncan Laurie
Enable DPTF support for sarien/arcada boards. This is currently using placeholder values that are identical that will be updated after thermal tuning is done. Change-Id: I7d51c3b38068fc25927c8dafc0bd9069b29d77f5 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-04ec/google/wilco: Guard DTPF with ifdefDuncan Laurie
There is a dependency issue with the EC DPTF code accessing methods that are external, but once the mainboard includes the relevant code they become internal and the current version of IASL used by jenkins will fail to compile it. Until the new IASL is deployed everywhere wrap the EC DPTF code and expect that the mainboard will explicitly enable it. Change-Id: I612ad8f86d424060ca0303d267d7c2915c760173 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/30036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-04ec/google/wilco/acpi: Add DPTF supportDuncan Laurie
Add the support needed for DPTF. This includes the methods to write trip point values, read temperatures, and handle events. This was tested on a sarien board by inspecting AML debug output with the kernel while monitoring temperatures and trip points in sysfs and controlling temperatures with a fan to ensure that when a trip point is crossed an SCI is generated and the event is handled properly. Change-Id: I8d8570d176c0896fa709a6c782b319f58d3c1e52 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29761 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-04ec/google/wilco/acpi: Fix issues and clean upDuncan Laurie
- Disable debug output from read/write methods by default - Use argument to _REG to disable SCI when EC is unregistered - Change read/write macros to sync level 2 so they can be called when a mutex is already held - Define some missing events Change-Id: Ic65ebbb6a6151444c47b4aeff7429e186856c49a Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29760 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-04soc/intel/cannonlake: Add DPTF ACPI codeDuncan Laurie
Define the constants that DPTF expects from the SOC in order to use the common DPTF ACPI code. For cannonlake this indicates the CPU device is called B0D4 and is at PCI address 00:04.0. Change-Id: I43c2f8dd7281d3e9f791ab01478ee7823fd6b128 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29759 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-04soc/intel/common/dptf: Add method for temp conversionDuncan Laurie
Add a method to convert from 1/10 Kelvin to Celsius. This is useful for EC devices where the sensor temperature are stored in Celsius instead of Kelvin. Change-Id: I6b1154f5ba13416131a029966d6d5c1598904881 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29758 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-04soc/intel/common/dptf: Make CPU address a defineDuncan Laurie
In order to support using the common ACPI code on more platforms than just Apollo Lake the DPTF code needs to be told what the PCI address is for the CPU thermal device. Change-Id: I638f2387330bbc42f64eb0fb676ee32c5df6572e Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29757 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-04ec/google/wilco: Fix extended event handlingDuncan Laurie
Extended events will be handled by the OS kernel driver, but that driver needs a method exposed by ACPI to read the event data from the EC and into a buffer. Tested by generating a hotkey event and reading the buffer from the Linux kernel driver with acpi_evaluate_object(). Change-Id: Ic8510e38d777a5dd31a5237867313efefeb2b48e Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29674 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-04ec/google/wilco: Enable WiFi radioDuncan Laurie
Add EC command to enable WiFi radio and send that command at startup. Tested to ensure WiFi is functional on a sarien board. Change-Id: Iac46895c7118567e1eb55ea33051a1662103b563 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29673 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-04ec/google/wilco: Enable COM1 ACPI deviceDuncan Laurie
Enable the COM1 ACPI device based on the existing Kconfig option CONFIG_DRIVERS_UART_8250IO instead of expecting the mainboard to also define another value for ACPI. Change-Id: I69361cc2c245cfcad3e4f57567bf56d5a26f0b06 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29672 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-04mb/google/sarien: Enable WWAN detectionAmanda Huang
Set WWAN_GPIO_PERST#(GPP_D22) to low at bootblock stage to meet the logic output for WWAN_PERST#_R to high. BUG=120004153 TEST=Boot up Sarien board, check WWAN get detected as USB devices through lsusb. Change-Id: I16f1101c64dfd4dcb5e8342fdb925951f6f2f90b Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-04soc/sifive/fu540: Load PLL settings from a structJonathan Neuschäfer
The different PLLs in the fu540 use the same register layout, so use one function (configure_pll) to program a PLL and wait for it to lock. This also makes it possible to dynamically calculate the PLL settings later. TEST=Boot until "Payload not loaded" on HiFive Unleashed Change-Id: I5c0cee886bad5758c70f967d2bb998c1e1a736ab Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/29356 Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-04drivers/intel/fsp1_1/romstage.c: Fix typoFrans Hendriks
Correct typo of 'Initialize' BUG=N/A TEST=N/A Change-Id: I94cfd9c41bb5f9751ef4a18beaeba05108220bc8 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/30016 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-04mb/opencellular/elgon: Enable write protectionPatrick Rudolph
* Verify the flash write protection on each boot * Program non-volatile write protection on first boot Tested using I715791b8ae5d1db1ef587321ae5c9daa10eb7dbc. The bootblock is write-protected as long as the #WP pin is asserted low: * Reprogramming of the status register fails. * Trying to write to WP_RO region fails. Programming the WP_RO is only possible if #WP pin is high. Change-Id: I6a940c69ecb1dfd9704b2101c263570bebc5540e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/29532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-12-04drivers/spi/winbond: Fix TB bitPatrick Rudolph
The TB has to be inverted to actually protected the correct region. Tested on elgon using I67eb4ee8e0ad297a8d1984d55102146688c291fc. Change-Id: I715791b8ae5d1db1ef587321ae5c9daa10eb7dbc Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/30014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-12-04mb/google/poppy/variants/nami: update bard/ekko sku idsRen Kuo
update the new sku ids of bard/ekko BUG=b:120257865 BRANCH=Nami TEST=emerge-nami coreboot chromeos-bootimage write the new sku id in cbi and verify the fw to check it can get the correct settings by the sku id Change-Id: I3579d3d8042a270d8ea8e2f7b5612ff8e2cdfa7b Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30031 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-03mb/google/octopus: Enable mode change as wake source from S3/S0ixFurquan Shaikh
This change enables mode change as a wake source from S3 and S0ix. Thus, any time the device switches between clamshell and tablet mode while it is suspended, it will be treated as a valid user event and hence wake source. BUG=b:120349473 BRANCH=octopus TEST=Verified that octopus wakes up on mode transitions. Change-Id: Ib224df434730f873ce5514303e5d043cbc85a9a4 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/30001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2018-12-03soc/intel/apl: Enable graphics with libgfxinitNico Huber
Backlight control of internal panels likely won't work as configuration for that seems absent in coreboot. Also, libgfxinit doesn't support any MIPI/DSI connections, yet, and neither Gemini Lake. TEST=Booted work-in-progress port kontron/mal10 with VGA text and linear framebuffer modes. DP display came up. Change-Id: I7b111f1cdac4d18f2fc3089f57aebf3ad1739e5d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/29903 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-03cpu/intel/fsp_model_406dx: Drop dead microcode referenceNico Huber
The referenced Kconfig symbols don't exist (anymore?). Change-Id: Ia724262a526fe960c17ae4b248acfa42fc342331 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/29931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Guckian Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-03sb/intel/i82801jx: Fix the x_pm2_cnt_blk addrlArthur Heymans
Removes a warning in Linux about FACP. Change-Id: Ia12302a4dcd34eacdcc8ae16bd39e951e616c6ea Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-12-03soc/intel/apollolake: Add support to print ME versionFurquan Shaikh
This change adds support to print ME version if UART_DEBUG is enabled. Check for UART_DEBUG is necessary because talking to ME to get the firmware version adds ~0.6 seconds to boot time. TEST=Verified on octopus that ME version printed is correct. Change-Id: I41217371558da1af694a2705e005429155d62838 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/29989 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-03smmstore: update smm store filename to use an underscoreJoel Kitching
Rename "smm store" to "smm_store". BUG=b:120060878 TEST=None Signed-off-by: Joel Kitching <kitching@google.com> Change-Id: If70772e17cc1668a28b376eeccfde0424e637b1a Reviewed-on: https://review.coreboot.org/c/29854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-03soc/amd/stoneyridge: Use new ACPI MMIO functionsRichard Spiegel
Replace IO access to ACPI registers with the new MMIO access functions. BUG=b:118049037 TEST=Build and boot grunt. Test ACPI related functionality. Change-Id: I7544169bb21982fcf7b1c07ab7c19c6f5e65ad56 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/29296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-12-03soc/amd/stoneyridge: Create MMIO offsets for ACPIRichard Spiegel
ACPI registers can be accessed through IO or through MMIO. However, the offset relationship is not one to one. Therefore, definitions with the correct offset for MMIO access are needed. BUG=b:118049037 TEST=Use Chrome OS IOTOOLS io_readxx and mem_readxx to find the correct relationship between ACPI IO and ACPI MMIO. Change-Id: Id20754c0fc0af35bc9eb1a4b40c62fbf9ed6304d Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/29294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-12-03mb/asus/am1i-a: add missing GPIO IO portsKevin Cody-Little
This makes the mainboard able to boot again. Change-Id: Id96fbfd5c815431dba2f030fca62a5ea16b97393 Signed-off-by: Kevin Cody-Little <kcodyjr@gmail.com> Reviewed-on: https://review.coreboot.org/c/29994 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-03mb/sifive/hifive-unleashed: Use if (IS_ENABLED(...))Jonathan Neuschäfer
"if" is preferable over "#if", because it lets the compiler perform syntax and type checks even if CONFIG_CONSOLE_SERIAL is disabled. Change-Id: I45a763f2d854fbe9082795bc74de7a9d0fded3c9 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/29336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-03soc/sifive/fu540: Simplify UART refclk calculationJonathan Neuschäfer
clock_get_coreclk_khz() already detects whether the PLL or the input clock (hfclk) is used. Tested on HiFive Unleashed. Change-Id: I264977b0de0b81ef74a014984b6d33638ab33f4b Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/29334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-12-03sb/intel/lynxpoint: Move `HAVE_SMI_HANDLER` to southbridge KconfigTristan Corrick
All Lynx Point board select this, and none build without it. Change-Id: I4b59b10ee985cff5a8e1442677d36b0be88cf437 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/29992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-12-03sb/intel/common: Create a common PCH finalise implementationTristan Corrick
The common finalise code is used by bd82x6x, Lynx Point, and Ibex Peak. Lynx Point now benefits from being able to write-protect the flash chip. For Lynx Point, writing the SPI OPMENU now happens in ramstage, as done in bd82x6x. Tested on an ASRock H81M-HDS (Lynx Point). When write-protection is configured, flashrom reports all flash regions as read-only, and does not manage to alter the contents of the flash chip. Also tested on an ASUS P8H61-M LX (Cougar Point). Everything seems to work as before. Change-Id: I781082b1ed507b00815d1e85aec3e56ae5a4bef2 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/29977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-12-03sb/intel/lynxpoint: Ensure the finalise handler is calledTristan Corrick
The finalise handler is not called during S3 resume when using the `BS_PAYLOAD_BOOT` approach. So, adopt the `lpc_final` approach used by bd82x6x and others. Tested on an ASRock H81M-HDS. The finalise handler is now called on the normal boot path, and during S3 resume. Change-Id: I9766a8dcbcb38420e937c810d252fef071851e92 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/29976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-12-03sb/intel/lynxpoint: Make the finalise handler commonTristan Corrick
The ASRock H81M-HDS doesn't implement a finalise handler. To fix this, and reduce code duplication in the process, make a common implementation. There should be no functional change to boards with existing finalise handlers, since the code is identical among them and the new, common implementation. Tested on an ASRock H81M-HDS. The finalise handler works. Change-Id: I13b581a2219288019a4e0c9e618db3ac7c3c15ab Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/29975 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-12-03mb/google/poppy/variant/nocturne: increase touch panel power-on delayNick Vaccaro
The WACOM 5C01 touch panel power-up delay of 10mS is too aggressive and causes "failed to change power setting" errors in the kernel, so this change increases the power-up delay to 20mS which allows enough time for the WACOM device's i2c controller to wake up. BUG=b:120090384 BRANCH=none TEST=flash and boot nocturne, log into kernel, execute the following command and make sure the string is not found : dmesg | grep "failed to change power setting" Change-Id: I1db0b3f5ce666b79d8ada2939ec865233ce52a56 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/29988 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-03mb/poppy/variant/nami: Move FPMCU_INT_L gpios to B groupShelley Chen
We discovered that the gpios previously used for FPMCU_INT_L were in two different groups with two different voltages (C group was at 3.3V and D group was at 1.8V). Moving both to B group which is at 3.3V. BUG=b:119447525 BRANCH=Nami TEST=unlock OS with fingerprint register fingerprint run powerd_dbus_suspend and see if it goes int s0ix Change-Id: I2332b0eb7a2f74e8178b95a23c8ac2091027a071 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/29872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-03mb/google/fizz/variants/karma: Update USB port infoDavid Wu
Update USB port info according to the schematic file. BUG=none BRANCH=master TEST=Compiles successfully and boot on DUT. Change-Id: I7383b3d676fd7c775a6d749c70af65b28cf941eb Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/29912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-03mb/google/fizz/variants/karma: Disable native SD card controllerDavid Wu
This change selects Kconfig option to disable native SD card controller in ACPI tables. BUG=b:119798840 BRANCH=master TEST=Compiles successfully and boot on DUT. Change-Id: I68dc9be511a370d882e4656c165efbe5dc6ee52e Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/29918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-03soc/intel/cannonlake: Load FSP teardown optionallyLijian Zhao
Make build still pass in case of no FsptUpd.h available. BUG=N/A TEST=Delete FsptUpd.h and build pass wihtout FSP_CAR set. Change-Id: I3936d3deb8b079bd4db11e444f6bb7f9605520dc Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/29907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-03soc/amd/stoneyridge: Create MMIO ACPI access functionsRichard Spiegel
Now that the relationship between IO access and MMIO access has been established, create read/write functions to access ACPI standard registers through MMIO. BUG=b:118049037 TEST=Build grunt Change-Id: I32c26f342885c0d99b082be98730edcf16ab5dfc Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/29295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-12-03src/mb/pcengines/apu2/mainboard.c: Fix retrieving serial numberMichał Żygowski
Handle situation when first NIC is not BDF 1:0.0. The PCI enumeration is different when a external PCIe device is connected to mPCIe2 slot which is routed to first PCIe bridge. The first NIC is then assigned BDF 2:0.0, because it is connected to the second PCIe bridge. Read the secondary bus number from the NIC PCIe bridge before attempting to read MAC adress and calculating serial number. Change-Id: I9f89a6f3cd0c23a2d2924e587338f69c260b12f8 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/29842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-12-03nb/intel/gm45: Make fetching the blc_pwm freq globalArthur Heymans
This can be used to select the proper VBT. Change-Id: Id3f6ba3ae31a5ab47f44d207678c1c4a6a43b7ec Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-12-03nb/intel/gm45: Make fetching the blc_pwm freq its own functionArthur Heymans
Also check the EDID string using strcmp instead of strncmp. Change-Id: I9ad364f84f3658be98ce7ad3a6f0f0fe3247fc41 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-12-03sb/intel/lynxpoint/usb_{e,x}hci.c: Don't use device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: Ie75450c844e2317ded157465eb0fc6a9ec1b3ab0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29932 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-03mb/google/dragonegg: Don't use device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: Ief858f6612d1c7b4b0c286cf5938f8c29055f1b5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-12-03include/device/smbus.h: Don't use device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: I2c88642133d3cbf33015e3e1e855fb2c786878d6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-03sb/intel/i82801gx: Clean up unneeded smi setup codeArthur Heymans
All i82801gx targets now use SMM_TSEG. Change-Id: Ib4e6974088a685290ed1dddf5228a99918744124 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-03nb/intel/pineview: Use common code for SMM in TSEGArthur Heymans
This also caches the TSEG region and therefore increases MTRR usage a little in some cases. Change-Id: I5f947cfae730b67bc76a581bc90cb10e5a2a4a52 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25598 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-03nb/intel/x4x: Use common code for SMM in TSEGArthur Heymans
This also caches the TSEG region and therefore increases MTRR usage a little in some cases. Currently SMRR msr's are not set on model_1067x and model_6fx since this needs the MSRR enable bit and lock set in IA32_FEATURE_CONTROL. This will be handled properly in the subsequent parallel mp init patchset. Tested on Intel DG41WV, resume from S3 still works fine. Change-Id: I317c5ca34bd38c3d42bf0d4e929b2a225a8a82dc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25597 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-03nb/intel/i945: Use common SMM_TSEG codeArthur Heymans
Use the common SMM_TSEG code to relocate the smihandler to TSEG. This also caches the TSEG region and therefore increases MTRR usage a little in some cases. This fixes S3 resume being broken introduced by CB:25594 "sb/intel/i82801gx: Use common Intel SMM code". Currently SMRR msr's are not set on model_1067x and model_6fx since this needs the MSRR enable bit and lock set in IA32_FEATURE_CONTROL. This will be handled properly in the subsequent parallel mp init patchset. Tested on Intel d945gclf and Lenovo Thinkpad X60. Change-Id: I0e6374746c3df96ce16f1c4a177af12747d6c1a9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25595 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-03sb/intel/i82801jx: Use common Intel SMM codeArthur Heymans
Use the common Intel code to set up smm and the smihandler. This is expected to break S3 resume and other smihandler related functionality as this code is meant to be used with CONFIG_SMM_TSEG. The platform (x4x) using this southbridge will adapt the CONFIG_SMM_TSEG codepath in subsequent patches. Change-Id: Id3b3b3abbb3920d68d77fd7db996a1dc3c6b85a3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25596 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-03nb/intel/gm45: Correctly cache TSEGArthur Heymans
Change-Id: I6a8752da9f92b90a2cb2cca5ebf28e2bc5a9c9a8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29866 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-03soc/intel/apl: Configure LPC serial IRQ modeNico Huber
Sync the FSP settings with what coreboot does. Why both FSP and coreboot configure this redundantly stays a secret. TEST=Set SERIRQ_CONTINUOUS on kontron/mal10. A CPLD connected to LPC works correctly now, but was confused by the wrong settings before because the FSP defaults allowed to disable the LPC clock. Change-Id: Id1c7180f460678bf0f9458228591050dd628c052 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/29901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-30cpu/intel/common: Use a common acpi/cpu.asl fileArthur Heymans
Change-Id: Ifa5a3a22771ff2e0efa14fb765603fd5e0440d59 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: David Guckian
2018-11-30soc/intel/fsp_baytrail: Rework acpi/cpu.aslArthur Heymans
Use acpigen_write_processor_cnot to implement notifications to the CPU. Change-Id: I01e4397b9a1c15eff4b856cbc697fa2b4bc9761f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-11-30soc/intel/denverton_ns: Rework acpi/cpu.aslArthur Heymans
Use acpigen_write_processor_cnot to implement notifications to the CPU. Change-Id: If482c64e7133cc6d82472d121ac138fc1b60a183 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: David Guckian
2018-11-30soc/intel/common: Rework acpi/cpu.aslArthur Heymans
Use acpigen_write_processor_cnot to implement notifications to the CPU. Change-Id: Id64f9857bbd7db520c94de949db8f823f71d6dae Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-11-30soc/intel/broadwell: Rework acpi/cpu.aslArthur Heymans
Use acpigen_write_processor_cnot to implement notifications to the CPU. Automatically generate \PPKG in SSDT. Change-Id: I79d2eed9b89b420554ce10d1fc0f151b1872afe2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-11-30soc/intel/braswell: Rework acpi/cpu.aslArthur Heymans
Use acpigen_write_processor_cnot to implement notifications to the CPU. Change-Id: I93c11e89da34c5432c6ce0415998b47bad339763 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29889 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-30soc/intel/baytrail: Rework acpi/cpu.aslArthur Heymans
Use acpigen_write_processor_cnot to implement notifications to the CPU. Change-Id: Ifb5a5c1255f9a922063293bf430e849909468eaf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29888 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-30cpu/intel/fsp_model_406dx: Rework acpi/cpu.aslArthur Heymans
Use acpigen_write_processor_cnot to implement notifications to the CPU. Change-Id: I00d15d0640a37f89ffd5cc87b89d5ba11fecb9ed Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29887 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-30cpu/intel/model_206{5,a}x: Rework acpi/cpu.aslArthur Heymans
Use acpigen_write_processor_cnot to implement notifications to the CPU. Automatically generate \PPKG in SSDT. Change-Id: Iecc54e94484f5f11e0ba8ef6d1d844276e484b4d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29886 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-30cpu/intel/haswell: Rework acpi/cpu.aslArthur Heymans
Use acpigen_write_processor_cnot to implement notifications the CPU. Generate PPKG in SSDT. Change-Id: I126989e8737720f55f7ce113ff4e32bfe0f22620 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29885 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-30soc/intel/skylake: Rework acpi/cpu.aslArthur Heymans
Use acpigen_write_processor_cnot to implement notifications to the CPU. Change-Id: I182585fd09e4ce848c860d00eb612e8f5fdde35e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29884 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-30sdm845: Add clock supportDavid Dai
This sets up initial clock configuration for QUP and QSPI, and includes configuration of Root Clock Generators(RCG) and clock branches enablement. TEST=build & run Change-Id: I0b1d7f6daa179c0b24a97d42b66c1a9ee596b0a3 Signed-off-by: David Dai <daidavid1@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/25454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-11-30arch/power8: Rename to ppc64Jonathan Neuschäfer
POWER8 is a specific implementation of ppc64, which is by now outdated (POWER9 has been on the market for a while). Rename arch/power8/ to potentially cover a wider range of hardware. TEST=Toolchains built before/after this commit can build coreboot for emulation/qemu-power8 from before/after this commit. Change-Id: I2d6f08b12a9ffc8a652ddcd6f24ad85ecb33ca52 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/29943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
2018-11-30security/vboot: Fix remaining measured boot issuesPhilipp Deppenwiese
Makes vboot measured boot mode available for all boards. * Increase Tegra210 and Rockchip3228 SRAM for romstage/verstage. * Add missing files for Intel apollolake and AMD stoneyridge as TPM driver target. Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/29840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-11-30broadcom: Remove SoC and board supportPhilipp Deppenwiese
The reason for this code cleanup is the legacy Google Purin board which isn't available anymore and AFAIK never made it into the stores. * Remove broadcom cygnus SoC support * Remove /util/broadcom tool * Remove Google Purin mainboard * Remove MAINTAINERS entries Change-Id: I148dd7eb0192d396cb69bc26c4062f88a764771a Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/29905 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-29google/kahlee/variants/aleena: Set STAPM values.Lucas Chen
According to aleena thermal testing to set STAPM values. skin scalar for 80%. time constant for 2500s. power limit for 7.8w. BUG=b:72979852 TEST=test build for thermal check. Change-Id: I09f1c1052dd317969546ac7d2bbde14cc563c160 Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/29795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-11-29google/grunt: Update hynix-H5ANAG6NAMR-UH.spd.hex SPD file Module Part NumberLucas Chen
Correct Ram_ID=0b0001 SPD Module Part Number to "H5ANAG6NAMR-UH" from "HMAA51S6AMR6N-UH". BUG=b:120000816 BRANCH=master TEST=mosys memory spd print all Change-Id: I59d920498ff6b73e9e7b2887771ad6bc6c6c0b66 Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/29873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-11-29mb/google/octopus: Create Casta variantKarthikeyan Ramasubramanian
This commit create a casta variant for Octopus. The initial settings override the baseboard GPIO configuration for Touchscreen, LTE, Pen and Trace modules. BUG=b:119056117 BRANCH=None TEST=None Change-Id: I5d3f7df66981d84fb47a6aa248480ef53dfd90d0 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/29763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-29mediatek/mt8183: Add DDR driver of rx dqs gating calibration partHuayang Duan
BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui, and inits DRAM successfully with related patches. Change-Id: I504d6d5c9ea01b11a9f2a05b5ee4b5f1af87e23f Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/28841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: You-Cheng Syu <youcheng@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-11-29arch/acpi.h: Add some update to version 6.2aElyes HAOUAS
Some tables updated to comply with ACPI version 6.2a. Change-Id: I91291c8202d1562b720b9922791c6282e572601f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-11-29mb/google/sarien: Add HD Audio verb tableLijian Zhao
Implement HD Audio verb table for RealTek ALC 3204/3254 codec on google sarien and arcada board. BUG=b:119058355,119054586 TEST=Confirm audio play back is working on Sarien and Arcada board. Change-Id: Icedbb510c7668d96c99c657091fc865f03bf7783 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/29484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>