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2018-07-16mainboard/google/kahlee: Add support for Dediprog em100Simon Glass
This device claims to run at 75MHz with dual read, but it is not always reliable. Add an option to change the SPI flash speed to 16MHz, to avoid any problems. BUG=b:111363976 TEST=manually try to get my em100 running (it doesn't yet) Change-Id: I78d3d32c467aac82c72d31c773bfb0f69808aed4 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/27466 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-16Kconfig: Make the EM100 config option commonSimon Glass
This applied to AMD devices as well as Intel, although the mechanism is different. Move the option to a common place. BUG=b:111363976 TEST=USE=em100-mode emerge-reef coreboot See that a message appears: * Enabling em100 mode (slow SPI flash) Change-Id: Iea437bdf42e7bc49b1d28c812bfc6128e3eb68bd Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/27467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-13mb/google/poppy/variants/nami: Use Pantheon VBTIvy Jian
Add new Pantheon sku-id for loading vbt-pantheon.bin BUG=b:78663963 BRANCH=firmware-nami-10775.B TEST=Boots to OS and display comes up. Check the board specific vbt binary loaded. Change-Id: I1ee156372754ac0e77caae5959a9ca9884de95f4 Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27432 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-13intel/wifi: Add WGDS ACPI method for Geo Aware SARPratik Prajapati
To comply with all relevant bodies throughout the world, SAR settings take into account the lowest common denominator Tx power settings. This setup may lead to non-optimal performance when the user location is in a country that may allow higher power setting. The purpose of Wireless Geo Delta Settings (WGDS) is to provide offset settings for FCC, Europe, Japan and Rest of the world. These offsets would be added (by Intel wifi driver) to the base SAR Tx Power as defined in WRDS and EWRD BUG=b:65155728 BRANCH=none TEST=WGDS ACPI table gets created as expected. Change-Id: I4f602e3f95ff3545db6cc6e428beb9a36abd9296 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-13mainboard/google/kahlee: Add more 3 SPD filesMartin Roth
BUG=b:111195311 TEST=Build grunt, verify SPDs are present Change-Id: Ief5ed5c3ca1d96b36926f1fc84c344a8d66dcda5 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/27437 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-12mainboard/google/nocturne: Update GPIO_FCAM_PWR_ENRicky Liang
The FCAM_PWR_EN gpio should be GPP_B4 according to the latest board schematics. Change-Id: Id926bd224b3392d8a61b6d8ae0509053afaa5b9e Signed-off-by: Ricky Liang <jcliang@chromium.org> Reviewed-on: https://review.coreboot.org/27433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tomasz Figa <tfiga@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-07-12Coverity: Fix CID1393976Patrick Rudolph
Cast to u64 to prevent possible integer overflow. Change-Id: I5c7d25278db54523242314cba6c85ac2f7a6c1f3 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-07-12Coverity: Fix CID1393978Patrick Rudolph
Fix a typo. Only memcpy into target buffer if pointer is not NULL. Change-Id: I1aa4b2ce1843e53ab6ed2224eaa928fc79ea3b83 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-07-12Coverity: Fix CID1393979Patrick Rudolph
Fix resource leak in dt_set_bin_prop_by_path(). Change-Id: I1c4d7e01b25847a2091ad90d2d70711beae55905 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-07-12riscv: add include/arch/smp/ directoryXiang Wang
Replicate directory layout from x86 for SMP. Change-Id: I27aee55f24d96ba9e7d8f2e6653f6c9c5e85c66a Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/27355 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-12soc/intel/skylake: add a space in printing ME FPF statusPratik Prajapati
This is cosmetic change Before: ME: Power Management Event : Clean global reset ME: Progress Phase State : Unknown phase: 0x08 state: 0x10 ME: Power Down Mitigation : NO ME: FPF status : fused After: ME: Power Management Event : Clean Moff->Mx wake ME: Progress Phase State : Unknown phase: 0x08 state: 0x10 ME: Power Down Mitigation : NO ME: FPF status : fused Change-Id: I15c02045d0f94fdb3f4a028585cad488d4ac9aa6 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/27246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-12nb/i945/raminit: Correct C0DRAMW & C1DRAMW for 4 DIMMsElyes HAOUAS
Change-Id: Ib1f999447b37a1524d589552ea2eec640c2a2c7e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/18387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-12soc/intel/braswell/acpi/dptf/thermal.asl: Make Thermal event optionalFrans Hendriks
Currently thermal event support can not be disabled at board level. Define and dependent code are placed in same file. Move define of HAVE_THERM_EVENT_HANDLER to mainboard file. Change-Id: Icb532e5bc7fd171ee2921f9a4b9b2150ba9f05c5 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/27415 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-12mb/google/octopus/variants/yorp: Enable TBMC deviceFurquan Shaikh
This change enables tablet mode ACPI device for yorp. BUG=b:111264961 CQ-DEPEND=CL:1132686 Change-Id: I81140b84a1adb5b21f1656fd89d953331e538f01 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-07-12mb/google/octopus: Enable TBMC device only for phaserFurquan Shaikh
Enabling of TBMC device on AP side requires corresponding support on the EC side as well. Since not all octopus variants have tablet mode support enabled, this change enables TBMC device only for phaser. BUG=b:111264961 Change-Id: I1ce181baa8ebaff0a9d767e97ddc256eef9789e8 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-07-12mb/google/octopus/variants/bip: Enable EC SW syncFurquan Shaikh
This change enables EC SW sync for bip by removing GBB flag selection for disabling SW sync. BUG=b:110523189 TEST=Verified that EC SW sync works fine on bip. Change-Id: Iff8ee67fd682530a4fa82643cd1d00a645b347a3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-07-11skylake: Remove "IshEnable"li feng
Remove "IshEnable" from soc_intel_skylake_config since it's not used anymore. Enable/disable ISH by checking if ISH device is turned on or not. Refer to https://review.coreboot.org/#/c/coreboot/+/26485/. BUG=b:79244403 BRANCH=none TEST=Built. Change-Id: I4d2889af118659852431c87cb516fd19b577efc5 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://review.coreboot.org/26521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-11mainboard/google/poppy/variants/atlas: config ISH in mainboard sideli feng
To enable ISH device on atlas board, change "device pci 13.0 off end" to "device pci 13.0 on end" in file mainboard/google/poppy/variants/atlas/devicetree.cb. "IshEnable" is not needed. Config atlas board specific ISH setting in devicetree.cb. Dynamically load gpio setting for ISH enabled/disabled cases. BUG=b:79244403 BRANCH=none TEST=Verified on Atlas board with ISH rework. ISH log showed on console. Change-Id: I8269a85cd2ab7917bfc0e7d63d988e0e678d0bf2 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://review.coreboot.org/26486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-11mediatek/mt8183: add PLL and clock init supportWeiyi Lu
Add PLL and clock init code. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui. Checked with frequency meter in SOC. Change-Id: I1f561f66bcf12de6a95c2f64eecd9508bd9bb26c Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Reviewed-on: https://review.coreboot.org/27031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-11mediatek: Share PLL code among similar SOCsTristan Shieh
Refactor PLL code which will be reused among similar SOCs. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: I11f044fbef93d4f5f4388368c510958d2b0ae66c Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27305 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-11google/kukui: Update MMU table in romstage and ramstageTristan Shieh
In order to get better performance, map dram as cached after dram ready in romstage. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui. Need a futher check after dram calibration code ready. Change-Id: Ie541fe08ee1d5b260abbabc0a5c18fb04e602b9c Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27304 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-11mediatek/mt8183: Add MMU operation supportTristan Shieh
Enable MMU in bootblock for performance, link common code to provide mtk_mmu_after_dram() to update MMU table in romstage after dram ready, implement mtk_soc_disable_l2c_sram(), and call mtk_mmu_disable_l2c_sram() to turn off L2C sram in ramstage. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui. Change-Id: I4e35f8276ca23de7fd13da3515b9f48d944ead32 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-11mediatek: Share MMU operation code among similar SOCsTristan Shieh
Refactor MMU operation code which will be reused among similar SOCs. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: Id8173da0a02e57e863263fcd89c91a9c089e8a0f Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-11mainboard/google/kahlee: Update existing SPD filesMartin Roth
Add an extra space after 8th value on each line to make it easier to count the values. Update the empty spd to remove two random 0x80 values. BUG=None TEST=None Change-Id: If330dbf0c133f65aedddc58ecb351a80b0e45a05 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/27423 Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-11mainboard/google/kahlee: Add additional SPDs for variantsMartin Roth
BUG=b:111079089, b:80375243 TEST=Build grunt, verify that SPDs are included. Change-Id: Idb03a3fa0842f7f89bb8c66dedbb8a0b293569be Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/27422 Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-11riscv: add support to check ISA extensionXiang Wang
Add support to check ISA extension for RISC-V. Change-Id: I5982fb32ed1dd435059edc6aa0373bffa899e160 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/27410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Philipp Hug <philipp@hug.cx>
2018-07-10src/sb/amd/pi/hudson/sd.c: disable SDR50 tuning and set correct clock freq ↵Michał Żygowski
in SD2.0 mode According to BKDG for AMD Family 16h Models 30h-3Fh Processors SDR50 tuning should be disabled in 0xA8 register. Also fix clock frequency setting in 0xA4 for stepping >= A1 which caused reduced performance of SD cards transfer speed even by half. Change-Id: I80ca754b0c89e08aa90ff885467c7486a3efb999 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-on: https://review.coreboot.org/27359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-10soc/cavium: Add secondary CPU supportPatrick Rudolph
Change-Id: I07428161615bcd3d03a3eea0df2dd813e08c8f66 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-10soc/cavium/cn81xx: Set cntfrq_el0Patrick Rudolph
Set cntfrq_el0 to provide correct timer frequency. Change-Id: I4b6d0b0cf646a066fc5a51552a1891eccbd91e5e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25450 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-10mb/cavium/cn8100_sff_evb: Be verbosePatrick Rudolph
Print some useful information about the board. Change-Id: I0acac7a29290bc2eb9f4283317165fa0cf1b24e1 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25449 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-10soc/cavium: Clean uart codePatrick Rudolph
* Only init UART_FOR_CONSOLE * Allow UART init with zero baudrate. * Init UART0..3 on Cavium's cn8100_sff_evb to fix kernel panic. Tested on CN8100_SFF_EVB. Change-Id: I1043b30318ec6210e2dd6b7ac313a41171d37f55 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-10soc/cavium: Enable MMUPatrick Rudolph
* Configure and enable MMU. * Cover the whole I/O space. * A minimum of 512KB TTB space is required. * Use secure mem attribute as firmware is running in ARM TZ region. Tested on Cavium SoC. Change-Id: I969446da62b4cc7adf9393fab69ff84ebf49220d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-10cavium: Add CN81xx SoC and eval board supportDavid Hendricks
This adds Cavium CN81xx SoC and SFF EVB files. Code is based off of Cavium's Octeon-TX SDK: https://github.com/Cavium-Open-Source-Distributions/OCTEON-TX-SDK BDK coreboot differences: bootblock: - Get rid of BDK header - Add Kconfig for link address - Move CAR setup code into assembly - Move unaligned memory access enable into assembly - Implement custom bootblock entry function - Add CLIB and CSIB blobs romstage: - Use minimal DRAM init only devicetree: - Convert FTD to static C file containing key value pairs Tested on CN81xx: - Boots to payload - Tested with GNU/Linux 4.16.3 - All hardware is usable (after applying additional commits) Implemented in future commits: - Vboot integration - MMU suuport - L2 Cache handling - ATF from external repo - Devicetree patching - Extended DRAM testing - UART init Not working: - Booting a payload - Booting upstream ATF TODO: - Configuration straps Change-Id: I47b4412d29203b45aee49bfa026c1d86ef7ce688 Signed-off-by: David Hendricks <dhendricks@fb.com> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/23037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-09src/southbridge: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: I72d50615d77b91529810e8f590fa56f3c6f7546c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-09src/soc: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: I21680354f33916b7b4d913f51a842b5d6c2ecef3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-09src/northbridge: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: Iaf86a0c91da089b486bd39518e5c8216163bf8ec Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-09src/mb: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: Iedc2e48349e40e94863c8080d11e11dbe6084c9d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-09src/{ec,include,lib}: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: I447aaa1850b7e8b514a8c4c04bf5b426d3d1cd0a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-09src/{device,drivers}: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: Ic1c9b1edd8d3206a68854107ddcbc5c51cb487c3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-09src/{arch,commonlib,cpu}: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: I8e4118c5c5d70719ad7dc5f9ff9f86d93fa498ac Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-09soc/intel/skylake: config ISH in SOC sideli feng
Config ISH in SOC side by checking if ISH device is turned on. "IshEnable" is not needed anymore since ISH device on/off will tell if ISH should be enabled or not. "IshEnable" will be removed from chip.h in separate CL. Atlas board specific ISH setting is needed, which is committed in separate CL. BUG=b:79244403 BRANCH=none TEST=Verified on Atlas board with ISH rework. ISH log showed on console. Change-Id: I3fc8648b3e6551497617ef1ebd2889245cdd31c3 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://review.coreboot.org/26485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-09ec/lenovo/h8/acpi: Add BDC interfacePatrick Rudolph
* Add SSDT generator to add dynamic ACPI code. * Implement GBDC and SBDC for thinkpad_acpi kernel module. Required for BDC power control from userspace. Tested on Lenovo T430: The bluetooth module is detected and can be powercycled using network manager. Change-Id: Ida825196650966194a883945896a038b0790fe45 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-06superio: move files to match the common naming schemeFelix Held
Change-Id: I1a8fc34aaaf42514c8af97ab155ff2712e7a5448 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/23009 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-06src: Add missing license headersMartin Roth
These two files were added before I was able to get the updated linter committed. Updated/Add the headers so the stable header lint check can be updated. Change-Id: I464ddecb5eebe8c5b907f3dcfeab1b06501af6ab Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/27362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-06riscv: use __riscv_atomic to check support A extensionXiang Wang
GCC pre-defined some macros for detecting ISA extensions. We should use these macros to detect ISA features. Change-Id: I5782cdd1bf64b0161c58d789f46389dccfe44475 Signed-off-by: XiangWang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/27300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-07-06google/grunt: Update Raydium TS device ACPI nodesKevin Chiu
change I2C irq to EDGE trigger BUG=b:110962003 BRANCH=master TEST=emerge-grunt coreboot Raydium TS is working. Change-Id: Iff3acf4199d23b29dff209ec1c03a731679c6cbe Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/27327 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-06mb/google/octopus: Enable tablet modeJustin TerAvest
This change configures ACPI to properly route notifications from the EC for tablet mode events to userspace. Relevant EC config changes are at: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1125261 BUG=b:111078678 TEST=With EC change, tablet mode detected by evtest and powerd Change-Id: Ifbc318186b195534f647f062544de4968aa87401 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/27346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jett Rink <jettrink@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-06ec/lenovo/h8/acpi: Move ACPI HKEY device to new filePatrick Rudolph
Move the APCI HKEY device to a new file and include it. The follow-up commits will extend it and this way it remains readable. Change-Id: Ie59b59e5a4148807125c71a362161026f685a97e Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2018-07-06mb/google/poppy/variants/nocturne: fix FPMCU IRQ sensitivityVincent Palatin
the FPMCU_INT_L on GPP_C11 is active low but the kernel irq handler is defined as IRQF_TRIGGER_LOW, so do not invert it twice. BRANCH=poppy BUG=b:78613978 TEST=On Nocturne, the 'cros_ec' IRQ count in /proc/interrupts does not increment wildly. Change-Id: I56c13c797b133dd22669a2299bcd16ef14eed335 Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://review.coreboot.org/27221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-06mb/intel/d945gclf/romstage.c: Remove unneeded includesElyes HAOUAS
Change-Id: I3bdb93e51cabbfc14fe992ccdb6556e344e03c2f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-06mb/ibase/mb899: Remove unneeded includesElyes HAOUAS
Change-Id: Iee237206f309409be64307d2daee044da52a05e1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-06google: Use proper ACPI ID for Semtech chips: STHGwendal Grignou
Change-Id: I85cd567a923cccd2504f351aae276b5f0d9db4de Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://review.coreboot.org/27347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt Delco <delco@google.com> Reviewed-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-03soc/cavium: Integrate BDK files into corebootDavid Hendricks
* Make it compile. * Fix whitespace errors. * Fix printf formats. * Add missing headers includes * Guard headers with ifdefs Compile DRAM init code in romstage. Compile QLM, PCIe, RNG, PHY, GPIO, MDIO init code in ramstage. Change-Id: I0a93219a14bfb6ebe41103a825d5032b11e7f2c6 Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/25089 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-03soc/amd/stoneyridge: correct GPIO emission error in ACPIKevin Chiu
It can not emit byte data without BytePrefix. design to: Or (Local5, GPIO_PIN_OUT, Local5) error due to GPIO_PIN_OUT is 0x40 but 0x40 encoding means nothing in AML spec. so it will include next emitted string in Or: Or (Local5, Local5, \_SB.GPW2) fix: Store (0x40, Local0) Or (Local5, Local0, Local5) BUG=b:110962003 BRANCH=master TEST=emerge-grunt coreboot extract SSDT then check ACPI syntax is correct Change-Id: I7a0704112b77105826de87b14a38ed2f665224d5 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/27306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-03mb/pcengines/apu1: use generic SPDMichał Żygowski
Clean up leftovers of old SPD generation and utilize common procedure to produce SPD binary. Change-Id: I4e48817c03b4372887bc0ea14209736ae2b4e48f Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/27301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-03drivers/pc80/vga: Fix coding styleElyes HAOUAS
Change-Id: I0452407d1346ca8ead2638e2a31269931ea5d12e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-03mb/intel/dg43gt: Expose some SIO devices via ACPIArthur Heymans
Change-Id: I0df578b98c5b346caa6f6df5fdabda28788e6b66 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-03mb/intel/dg41wv: Expose some SIO devices via ACPIArthur Heymans
Change-Id: Ia658c117434c3fae45bbbe6c472ca58ba4f1a117 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-03ec/google/chromeec: Remove keyboard initializationFurquan Shaikh
Since none of the boards using chromeec select DRIVERS_PS2_KEYBOARD now, there is no need to call pc_keyboard_init anymore. This change gets rid of the call and adds an error message in case any mainboard using chromeec tries to select this config. BUG=b:110024487 Change-Id: Ia0b56abe0a5990e527277eaf3397e00dccda3e50 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-03mb/intel/glkrvp: Get rid of DRIVERS_PS2_KEYBOARD selectionFurquan Shaikh
Until now, chromeec was doing keyboard initialization for the boards that have DRIVERS_PS2_KEYBOARD selected. However, coreboot does not leave the keyboard controller in a default reset state. This could result in payloads or OS failing to probe the controller as there could be stale data buffered in the controller during the handoff. Since the boards using chromeec already perform keyboard initialization in payload, there is no need to initialize the keyboard in coreboot too. This change gets rid of DRIVERS_PS2_KEYBOARD selection from all google mainboards using chromeec. BUG=b:110024487 Change-Id: I9af48e648231c18f98d0cc1ddd178b8d00082b0a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-03mb/google/*: Remove selection of DRIVERS_PS2_KEYBOARDFurquan Shaikh
Until now, chromeec was doing keyboard initialization for the boards that have DRIVERS_PS2_KEYBOARD selected. However, coreboot does not leave the keyboard controller in a default reset state. This could result in payloads or OS failing to probe the controller as there could be stale data buffered in the controller during the handoff. Since the boards using chromeec already perform keyboard initialization in payload, there is no need to initialize the keyboard in coreboot too. This change gets rid of DRIVERS_PS2_KEYBOARD selection from all google mainboards using chromeec. BUG=b:110024487 TEST=Keyboard works fine after booting to OS even if user hits keys during BIOS to OS handoff. Change-Id: I1f49b060eb005c0f2b86f9d68d6758954eeb3cf0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27291 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-02arch/x86: add SMM callerPatrick Georgi
Useful for debugging or for cases where we need to enter SMM. Probably should be moved to commonlib or libpayload. Change-Id: I7a9cc626dae9a7751034615ef409eebc6035f5c3 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/25193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-02src: Get rid of unneeded whitespaceElyes HAOUAS
Change-Id: I3873cc8ff82cb043e4867a6fe8c1f253ab18714a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-02src/nb: Fix non-local header treated as localElyes HAOUAS
Change-Id: I8174d7b40008cfe4fba10fde4670682aac0ad078 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-02src/sb: Fix non-local header treated as localElyes HAOUAS
Remove some unneeded includes. Change-Id: I4b9bcb74b6441db9e44fe471b9cd789e42e7093a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-02src/mb: Fix non-local header treated as localElyes HAOUAS
Also remove some unnedded includes. Change-Id: I036208a111d009620d8354fa9c97688eb4e872ad Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-02mb/lenovo/t400: Change CMOS value name to Dual GraphicsNico Rikken
To uniform the naming of the 'Dual Graphics' mode amongst the ThinkPads that support it, the T400 CMOS value needs a change. This was the outcome of a discussion on another patch: https://review.coreboot.org/#/c/coreboot/+/23040/ This might cause breakage for automated NVRAM configuration scripts, and manuals. I only found one manual using the previous 'Switchable' option: https://libreboot.org/docs/install/r400_external.html#a-note-about-gpus Change-Id: I2e4d8bafbae5de97c78dab118f75fdefff1d7c37 Signed-off-by: Nico Rikken <nico@nicorikken.eu> Reviewed-on: https://review.coreboot.org/27158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-02stoneyridge: Enable legacy IORaul E Rangel
Legacy IO enables access to RTC IO 0x70-0x73. This is needed for CMOS to function correctly. BUG=b:110817463 TEST=ran firmware_CorruptFwSigB on grunt Change-Id: I533226ba764f567e348577d7fcf6ebe43336609a Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-02stoneyridge: Enable IO CF9 in bootblockRaul E Rangel
If IO CF9 is not enabled, hard_reset() won't do anything in bootblock or verstage. BUG=b:110817463 TEST=built on grunt and made sure that hard_reset() reboots. Change-Id: I5f091077a17db3dfe5b8e8367163312db6828360 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27267 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-02ec/google/chromeec: Remove notify for power buttonFurquan Shaikh
None of the mainboards using Chrome EC set SCI mask for power button. Thus, the EC will never generate SCI for power button events. This change removes the Notify call for power button as part of clean up for getting rid of the power button device in coreboot. BUG=b:110913245 Change-Id: I86c72fd82f1a0e6d5693ebbcd58e2aea808f8817 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-02mediatek/mt8183: Add mtcmos init supportTristan Shieh
Using common mtcmos code to power on audio and display modules in SOC. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui. Passes the status check at the end of mtcmos_power_on() Change-Id: I41f16ba36432a8bbc47793cec2979753c9f84b43 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-02mediatek: Move mtcmos code to a common directoryTristan Shieh
Move mtcmos code which can be reused into a common directory under soc/mediatek. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: I92b138890424b4f4a68cdb00bf2326eef9cd87b7 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27029 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-02mediatek: Share mtcmos code among similar SOCsTristan Shieh
Refactor mtcmos code which will be reused among similar SOCs. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: Ibfd0a90f6eba3ed2e74a3fd54279c7645aa41774 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-02soc/amd/common: Change create_struct return valueKyösti Mälkki
Old return value was not used, and function body has die() in case of errors in allocation. Change-Id: I89b0e9c927d395ac6d27201e0b3a8658e9585187 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/27261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-02soc/amd/common: Fix agesawrapper CreateStruct callsKyösti Mälkki
When AllocationMethod == ByHost, buffer has to be provided by caller. Improve code symmetry, the named parameter is now always pointer to the struct. Change-Id: I2085f7d5d63ef96f4bd9d5194af099634c402820 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/27112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-07-02mainboard/google/nocturne: Enable IPU3Lijian Zhao
Enable Image Processing Unit and CIO2 device that constitute IPU3. BUG=None TEST=Build and boot up into Nocturne platform and check with lspci. Change-Id: Ic2edf5ec7bde5c55ce1b13cf7b680094a9fffc6a Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Signed-off-by: Tomasz Figa <tfiga@chromium.org> Reviewed-on: https://review.coreboot.org/27124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-02mainboard/google/nocturne: Set camera power sequenceLijian Zhao
To make image sensor working, the intended power sequence need to applied. BUG=NONE TEST=NONE Change-Id: I4833c0e303174b297c1d193495e08e55d294a717 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Signed-off-by: Rajmohan Mani <rajmohan.mani@intel.com> Signed-off-by: Tomasz Figa <tfiga@chromium.org> Reviewed-on: https://review.coreboot.org/27094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-02mainboard/google/nocturne: Enable camera sensorsLijian Zhao
Sensors and CSI2 receiver configuration for Nocturne platform. IMX355 module has VCM, NVM and is on the second port of receiver. IMX319 module has NVM and is on the first port of receiver. Change-Id: I37c877df8062d5c79e25ed27775ab58e977555db Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com> Signed-off-by: Rajmohan Mani <rajmohan.mani@intel.com> Signed-off-by: Tomasz Figa <tfiga@chromium.org> Reviewed-on: https://review.coreboot.org/26283 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-02commonlib/storage: Make sd_mmc_go_idle an apiBora Guvendik
change sd_mmc_go_idle to be accessible from other files so that we have an api to send CMD0 and reset the card. BUG=b:78106689 TEST=Boot to OS Change-Id: I064a9bded347be5d500047df92d1c448c3392016 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/25066 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-02nocturne: Do not set 4 LSB of SX9310 CRTL0Gwendal Grignou
These bits start the acquisition process. They should only be set by the driver. BUG=b:74363445 TEST=compile Change-Id: I9e10f5570ac82124f7f4b5cc7aaad27da0c578be Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://review.coreboot.org/27265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-02nocturne: Fix casing for register definitionGwendal Grignou
Use lower case for hex values. BUG=b:74363445 TEST=compile Change-Id: I24afea58b1a791fac3c87ad397a696f7f6e0d127 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://review.coreboot.org/27264 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-02mb/google/poppy/variants/nami: Perform PL2 setting for sonaJohn Su
According to sona thermal table, PL2 need to check cpu id. And then set PL2 value. BUG=b:110867809 TEST=The thermal team verify OK Change-Id: I5759fb3c685e3d4eef1be054541f950843d19874 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-06-30soc/intel/skylake: Generate ACPI RMRR tableMatt DeVillier
An ACPI RMRR table is requried for IOMMU to work properly with an iGPU (without using passthrough mode), so create one along with the DRHD DMAR table if the iGPU is present and enabled. Test: build/boot google/chell and purism/librem13v2 with kernel parameter 'intel_iommu=on' but without 'iommu=pt;' observe integrated graphics functional without corruption. Change-Id: I202fb3eb8618f99d41f3d1c5bbb83b2ec982aca4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2018-06-30arch/x86/acpi: Add DMAR RMRR helper functionsMatt DeVillier
Add DMAR RMRR table entry and helper functions, using the existing DRHD functions as a model. As the DRHD device scope (DS) functions aren't DRHD-specific, genericize them to be used with RMRR tables as well. Correct DRHD bar size to match table entry in creator function, as noted in comments from patchset below. Adapted from/supersedes https://review.coreboot.org/25445 Change-Id: I912b1d7244ca4dd911bb6629533d453b1b4a06be Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27269 Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-29mb/google/poppy: Fix bytes 145-146 in nayna_dimm_NT6CL256T32CM SPDT.H. Lin
nayna/NT6CL256T32CM-H1 file change byte 145/146 to be"20" for JEDEC spec BUG=b:79443146,b:109708239 BRANCH=nami TEST=emerge-nami coreboot chromeos-bootimage Test on R69.10825 with mosys Change-Id: Iadc820111f0aed34e5b46d7e23dff44cb5bb811d Signed-off-by: T.H. Lin <t.h_lin@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27275 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-29src/device: Add check for existence and validity of PCIE base address configAamir Bohra
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Change-Id: I89b0e9c927d395ac6d27201e0b3a8658e958518d Reviewed-on: https://review.coreboot.org/27263 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-29soc/intel/baytrail: Fix Kconfig for mrc.bin inclusionArthur Heymans
It used the sandybridge systemagent binary and mentioned that in the help text which is simply wrong and won't work. This copies the nb/intel/haswell/Kconfig to not include an mrc.bin by default. Change-Id: I2e151a66abc6dab710abdbb92c0c28884d88912e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27140 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-29sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tablesArthur Heymans
Both southbridges need to be done at once since this southbridge code is used for different northbridges, which fails to compile when done separately. This needs an acpi_name functions in the northbridge code to be defined. TESTED on Intel DG43GT: show correct PIRQ ACPI entries in /sys/firmware/acpi/tables/SSDT. Change-Id: I286d251ddf8fcae27dd07011a1cd62d8f4847683 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-29sb/intel/i82801ix: Use the common ACPI pirq generatorArthur Heymans
For this to work the northbridge and lpc bridge device need acpi_name functions. TESTED on Thinkpad X200, a valid PIRQ routing in SSDT in /sys/firmware/acpi/tables/SSDT Change-Id: I62e520f53fa3f928a8e6f3b3cf33af2acdd53ed9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-28drivers/intel/fsp2_0: Fix uncountable "information"Elyes HAOUAS
Change-Id: I91e13a786b12328f1d9200f76788faa19847bbe7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26593 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-28nocturne: Fix uid and desc for sx9310Enrico Granata
This commit changes the uid and desc fields for the sx9310 entries in the devicetree to be unique, and correctly identify the position of the respective sensors. Change-Id: I501df7d3349fdebc9673c9815f5b1b2458abac6e Signed-off-by: Enrico Granata <egranata@chromium.org> Reviewed-on: https://review.coreboot.org/27248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
2018-06-28amd/common/pi: Remove AGESA support files from bootblockMarshall Dawson
The stoneyridge bootblock no longer makes AGESA calls. Remove the support files from the bootblock build. TEST=boot Grunt Change-Id: I14d2336d5fb766a1acf5e812337ae0ab3ca4a6c1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-28amd/common/pi: Remove obsolete heapmanager workaroundMarshall Dawson
Remove residual code that allowed successful building of the heapmanager code. Now that stoneyridge no longer makes AGESA calls in bootblock, it is safe to elimate the workaround. BUG=b:74518368 TEST=boot Grunt Change-Id: Ie169a691a177bcd8283c31c8188ce28bcbce82af Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-28mb/*/*/cmos.layout: Fix coding styleElyes HAOUAS
Change-Id: I4f82482595b0e6c6159c6e1c66158bc18b061f04 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-28fsp_broadwell_de: Add ability to set PCIe completion timeoutDavid Hendricks
This enables the user to set the completion timeout value in PCI Express Device Control 2 register via devicetree.cb. Based on corebootBDE-270-iou-complto.patch in Arista EOS 4.20 release. Change-Id: If0527899bc2047d0e57c11f7801768d07f9a5179 Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/26225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-06-28arch/x86: include verstage.c only when verstage is a separate stageArthur Heymans
Change-Id: Ia75205001f2443cb8221a0762f182aae01ee615e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26924 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-28soc/intel/skylake: clear MCA before booting to OSPratik Prajapati
mca_configure needs to be called for each core before booting to OS, else OS would keep dumping MCEs Change-Id: I95ca46fda7be65d74714bdb344e339922cbb6305 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/26392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-06-28intel/common: change mca_configure API's defPratik Prajapati
add an unused param so that mca_configure can be called by mp_run_on_all_cpus to run it on all cores. Change-Id: I2395ee7fbedc829f040959b0021967f800693eeb Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/26391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-06-28devicetree: Add method to delete property by namePatrick Rudolph
Will be used on Cavium SoC to delete devicetree entries that aren't available with the board/configuration. Change-Id: I7c58a2411206bca62d0e96fa627530e937383ac9 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-06-28smm: Add canary to end of stack and die() if a stack overflow occursRaul E Rangel
If CPU 0's stack grows to large, it will overflow into CPU 1's stack. If CPU 0 is handling the interrupt then CPU 1 should be in an idle loop. When the stack overflow occurs it will override the return pointer for CPU 1, so when CPU 0 unlocks the SMI lock, CPU 1 will attempt to return to a random address. This method is not foolproof. If code allocates some stack variables that overlap with the canary, and if the variables are never set, then the canary will not be overwritten, but it will have been skipped. We could mitigate this by adding a larger canary value if we wanted. I chose to use the stack bottom pointer value as the canary value because: * It will change per CPU stack. * Doesn't require hard coding a value that must be shared between the .S and .c. * Passing the expected canary value as a parameter felt like overkill. We can explore adding other methods of signaling that a stack overflow had occurred in a follow up. I limited die() to debug only because otherwise it would be very hard to track down. TEST=built on grunt with a small and large stack size. Then verified that one causes a stack overflow and the other does not. Stack overflow message: canary 0x0 != 0xcdeafc00 SMM Handler caused a stack overflow Change-Id: I0184de7e3bfb84e0f74e1fa6a307633541f55612 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27229 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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