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This change adds the SPI-DMI Destination ID for tigerlake
soc. This is needed for enabling support for extended
BIOS region. Also, implements a SOC helper function
soc_get_spi_dmi_destination_id() which returns SPI-DMI
Destination id.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I0b6a8af0c1e79fa668ef2f84b93f3bbece59eb6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This change enables support for configuration of extended BIOS
region decode window. This configuration needs to be performed
as early as possible in the boot flow. This is required to
ensure that any access to the SPI flash region below 16MiB in
coreboot is decoded correctly. The configuration for the extended
BIOS window if required is done as part of fast_spi_early_init().
Changes include:
1. Make a call to fast_spi_enable_ext_bios() before the bus master
and memory space is enabled for the fast SPI controller.
2. Added a helper function fast_spi_enable_ext_bios() which calls
fast_spi_get_ext_bios_window() to get details about the extended
BIOS window from the boot media map.
3. Depending upon the SPI flash device used by the mainboard and
the size of the BIOS region in the flashmap, this function will
have to perform this additional configuration only if the BIOS
region is greater than 16MiB
4. Adddditionally, set up the general purpose memory range
registers in DMI.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Idafd8be0261892122d0b5a95d9ce9d5604a10cf2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47990
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change allows configuring the General Purpose
Memory Range(GPMR) register in BIOS to set up the decoding in DMI.
This driver provides the following functionality:
1. Add a helper function dmi_enable_gpmr which takes as input base,
limit and destination ID to configure in general purpose memory range
registers and then set the GPMR registers in the next available
free GMPR and enable the decoding.
2. Add helper function get_available_gpmr which returns available free
GPMR.
3. This helper function can be utilized by the fast SPI driver to
configure the window for the extended BIOS region.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I34a894e295ecb98fbc4a81282361e851c436a403
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47988
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change adds details about the memory map windows to translate
addresses between SPI flash space and host address space to coreboot
tables. This is useful for payloads to setup the translation using the
decode windows already known to coreboot. Until now, there was a
single decode window at the top of 4G used by all x86
platforms. However, going forward, platforms might support more decode
windows and hence in order to avoid duplication in payloads this
information is filled in coreboot tables.
`lb_spi_flash()` is updated to fill in the details about these windows
by making a call to `spi_flash_get_mmap_windows()` which is
implemented by the driver providing the boot media mapping device.
BUG=b:171534504
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I00ae33d9b53fecd0a8eadd22531fdff8bde9ee94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48185
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change reserves the window used for extended BIOS decoding as a
fixed MMIO resource using read_resources callback in systemagent
driver. This ensures that the resource allocator does not allocate
from this window.
Additionally, this window is also marked as fixed memory region in
_CRS for PNP0C02 device.
BUG=b:171534504
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I42b5a0ebda2627f72b825551c566cd22dbc5cca7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This change enables support for a custom boot media device in fast SPI
controller driver if the platform supports additional decode window
for mapping BIOS regions greater than 16MiB. Following new Kconfigs
are added:
1. FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW: SoC can select this to indicate
support for extended BIOS window.
2. EXT_BIOS_WIN_BASE: If FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW is
selected, this provides the base address of the host space that is
reserved for mapping the extended window.
3. EXT_BIOS_WIN_SIZE: If FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW is
selected, this provides the size of the host space reserved for
mapping extended window.
If platform indicates support for extended BIOS decode window,
cbfstool add command is provided additional parameters for the decode
window using --ext-win-base and --ext-win-size.
It is the responsibility of the mainboard fmap author to ensure that
the sections in the BIOS region do not cross 16MiB boundary as the
host space windows are not contiguous. This change adds a build time
check to ensure no sections in FMAP cross the 16MiB boundary.
Even though the platform supports extended window, it depends upon the
size of BIOS region (which in turn depends on SPI flash size) whether
and how much of the additional window is utilized at runtime. This
change also provides helper functions for rest of the coreboot
components to query how much of the extended window is actually
utilized.
BUG=b:171534504
Change-Id: I1b564aed9809cf14b40a3b8e907622266fc782e2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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There have been a few issues with the new CBFS mcache code in stages
after romstage, where the mcache resides in CBMEM. In a few special
cases the stage may be doing a CBFS lookup before calling
cbmem_initialize(). To avoid breaking those cases, this patch makes the
CBFS code fall back to a lookup from flash if CBMEM hasn't been
reinitialized yet in those stages.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Icf6d1a1288cb243d0c4c893cc58251687e2873b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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cbmem_online() always returns 1 in stages after romstage. However, CBMEM
isn't actually immediately available in those stages -- instead, it will
only become available when cbmem_initialize() is called. That usually
happens very early in the stage, but there are still small amounts of
code running beforehand, so it is useful to reflect this distinction.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I623c0606a4f49ea98c4c7559436bf32ebb83b456
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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disabling DDI port 1 and 2 HPD.
This patch adds the PMC MUX and CONx devices for lindar. Device
specific method contains the port and orientation details used
to configure the mux.
BUG=b:172533907
BRANCH=firmware-volteer-13521.B
TEST=Built and booted into OS.
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: Id5ee78b7ece8421144086af9b95f5f0d849be56c
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains
identical.
Change-Id: I5fa1e7216f3e80de0da5a58b84f221af321e4753
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48396
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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SATA_AHCI is already the default mode for CNL based mainboards.
Therefore, remove its configuration from all related devicetrees.
Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains
identical.
Change-Id: I814e191243224a4b021cd7d4c1b611316f1fd1a4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Align the SATA mode names with soc/skl providing a consistent API.
Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains
identical.
Change-Id: I54b48462852d7fe0230dde0c272da3d12365d987
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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The PCI devices P2SB and PMC are hidden by the FSP and cannot be
unhidden, because the FSP locks their configuration. Thus, setting them
to `on` is not correct. Therefore, set their state to hidden.
Change-Id: Ib7c019cd7f389b2e487829e5550cc236ee5645b7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48388
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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SATA_AHCI is already the default mode for SKL/KBL based mainboards.
Therefore, remove its configuration from all related devicetrees.
Built clevo/n130wu with BUILD_TIMELESS=1, coreboot.rom remains
identical.
Change-Id: Ib5222c1b0314365b634f8585e8a97e0054127fe9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48378
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Skylake FSP isn't used by coreboot anymore. Therefore, drop the
misleading comment and the "KBLFSP" extension from the names of these
enums.
Also, drop the "MODE" extension to make their names shorter in general,
since it doesn't add any more value.
Built clevo/n130wu with BUILD_TIMELESS=1, coreboot.rom remains
identical.
Change-Id: If37d40e4e1dfd11e9315039acde7cafee0ac60f0
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48377
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Built clevo/n130wu with BUILD_TIMELESS=1, coreboot.rom remains
identical.
Change-Id: I6a5c694a9686a5435aa5c64647286a6017f9aa13
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48376
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I56a905980e5ae382c3488b9fddb9fab382efc1d6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48375
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I193aea7c92f340bd80a41a3777bcddc3f1339620
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Remove unnecessary device declarations and remove comments where SMBIOS
slot descriptions are used.
Change-Id: I3aa3f72de764889becdb0afeb2dac522385d70ef
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48373
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use proper indents in the devicetree and align `end` keywords.
Change-Id: Id6e6f4ad648a9bed35305b7a446744c6ed06a150
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48372
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The PCI devices P2SB and PMC are hidden by the FSP. So instead turning
them off, set their state to hidden being able to allocate ressources
for them.
Change-Id: Ie6e12f99b0a7ffb1c4831b3aa8705e911b677e88
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48371
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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remove TCC offset setting in overridetree.cb,
use default setting(# TCC of 90) in baseboard.
BUG=b:174547185
BRANCH=volteer
TEST=emerge-volteer coreboot
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Iaac1fae12ccaa8a623bc2dc3105262918523d440
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48264
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update lindar gpio settings for Synaptics trackpad no function issue.
Update I2C5 bus freq to 400kHz.
Improve Goodix Touchscreen power on sequence.
BUG=b:160013582
BRANCH=firmware-volteer-13521.B
TEST=emerge-volteer coreboot and check system dmesg and evtest can get
device. Verify trackpad function workable.
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I8c1ab6bab1f9de187e2a78ead7b5bbaf758f5fcf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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This change updates the translated region device (xlate_region_dev) to
support multiple translation windows from the 1st address space to
2nd address space. The address spaces described by the translation
windows can be non-contiguous in both spaces. This is required so that
newer x86 platforms can describe memory mapping of SPI flash into
multiple decode windows in order to support greater than 16MiB of
memory mapped space.
Since the windows can be non-contiguous, it introduces new
restrictions on the region device ops - any operation performed on the
translated region device is limited to only 1 window at a time. This
restriction is primarily because of the mmap operation. The caller
expects that the memory mapped space is contiguous, however, that is
not true anymore. Thus, even though the other operations (readat,
writeat, eraseat) can be updated to translate into multiple operations
one for each access device, all operations across multiple windows are
prohibited for the sake of consistency.
It is the responsibility of the platform to ensure that any section
that is operated on using the translated region device does not span
multiple windows in the fmap description.
One additional difference in behavior is xlate_region_device does not
perform any action in munmap call. This is because it does not keep
track of the access device that was used to service the mmap
request. Currently, xlate_region_device is used only by memory mapped
boot media on the backend. So, not doing unmap is fine. If this needs
to be changed in the future, xlate_region_device will have to accept a
pre-allocated space from the caller to keep track of all mapping
requests.
BUG=b:171534504
Change-Id: Id5b21ffca2c8d6a9dfc37a878429aed4a8301651
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47658
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Unique among the Volteer devices, the volteer2_ti50 variant connects to
the TPM via I2C. This CL introduces the proper devicestree declarations
for the Linux kernel to recognize that.
overridetree.cb is shared between "sub"-variants volteer2 and
volteer2_ti50, so both will have two TPM nodes, the I2C being disabled
by default. The odd _ti50 variant then has code in variant.c to enable
the I2C node and disable the SPI node.
BUG=b:173461736
TEST=abuild -t GOOGLE_VOLTEER2{_TI50,} -c max -x
Change-Id: I5576a595bbabc34c62b768f8b3439e35ff6bcf7b
Signed-off-by: Jes Bodi Klinke <jbk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48223
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update Power Limit2 (PL2) minimum value to the same as maximum value for
volteer variants like baseboard, delbin, eldrid, terrador and todor.
All other variants uses the DTT entries from baseboard devicetree since
there is no override present for those variants. DTT does not throttle PL2,
so this minimum value change here does not impact any existing behavior on
the system.
BUG=None
BRANCH=volteer
TEST=Build and test on volteer system
Change-Id: I568e87c87ef517e96eaab3ff144b1674d26ae1e6
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Probabilistic interrupt storm is observed while kernel is configuring
the GPIO for SD card CD pin. The root cause is that the macro
PAD_CFG_GPI_GPIO_DRIVER isn't configuring trigger as PAD_TRIG(OFF).
The way GPIO interrupts are handled is:
1. Pad is configured as input in coreboot.
2. Pad IRQ information is passed in ACPI tables to kernel.
3. Kernel configures the required pad trigger.
Therefore, PAD_TRIG(OFF) should be added in PAD_CFG_GPI_GPIO_DRIVER
to turn off the trigger while pad is configured as input in coreboot
and then let kernel to configure the required pad trigger.
BUG=b:174336541
TEST=Run 1500 reboot iterations successfully without any interrupts
storm.
Signed-off-by: Kaiyen Chang <kaiyen.chang@intel.corp-partner.google.com>
Change-Id: Icc805f5cfe45e5cc991fb0561f669907ac454a03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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DRIVER_I2C_TPM_ACPI is used to enable the "driver" needed for coreboot
to present a TPM node in the devicetree. It would usually only do so,
if coreboot itself is communicating with the TPM via I2C (I2C_TPM).
However, technically, there is no dependency.
In order to not show the ACPI option in menuconfig if the board is not
using I2C, a dependency was declared in Kconfig. However, the same can
be achieved without making it an error to manually declare
DRIVER_I2C_TPM_ACPI without I2C_TPM.
For Volteer, we have just such a need, since it has two "sub-variants"
sharing the same overridetree.cb, one having SPI TPM and another having
I2C TPM. The former will have a disabled ACPI node representing the I2C
TPM, while its Kconfig is such that coreboot itself does not have I2C
TPM support.
In order to export even a disabled ACPI node representing the I2C
connected TPM, coreboot needs DRIVER_I2C_TPM_ACPI. Hence, that will
have to be enabled in a case where coreboot does not have I2C_TPM (for
one of the two sub-variants, namely volteer2).
BUG=b:173461736
TEST=Tested as part of next CL in chain
Change-Id: I9717f6b68afd90fbc294fbbd2a5b8d0c6ee9ae55
Signed-off-by: Jes Bodi Klinke <jbk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48222
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Id014828d282350bcb1f4de295d5cfb72b6950634
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This patch removes 1 unnecessary whitespace and add 1 whitespace into IA
common car code block.
Change-Id: I3690b5f219f5326cfca7956f21132062aa89648e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Move all memory map definitions into a separate header.
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.
Change-Id: I1f37ad9cae39041f98871c613b308b5ac5da01b3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45379
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There's no need to wrap these macros with casts. Removing them allows
dropping more casts in `early_init.c`.
To avoid binary changes the casts are put into the
{MCH,DMI,EP}BAR{8,16,32} macros instead where they are needed to reach
the right memory locations.
Change-Id: Icff7919f7321a08338db2f0a765ebd605fd00ae2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Inspired by Idca25b2e4bf65abcb and Ib275f9ad8ca9ff move all memory map
definitions into a header with a common name.
Change-Id: I32a99f70f4d2eb52367c9edfc0aa6d5da2fec03f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Setting PegXEnable to 1, statically enables the PEG ports, which blocks
the SoC from going to deeper PC states. Instead, set the state to "auto"
(2), so the port gets disabled, when no device was detected.
Note: Currently, this only works with the AST PCI bridge disabled or the
VGA jumper set to disabled on coreboot, while it works on vendor
in any case. The reason for this is still unclear.
Test: powertop on X11SSM-F shows SoC in PC8 like on vendor firmware
instead of just PC3
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I3933a219b77d7234af273217df031cf627b4071f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The patch modifies KConfig behaviour if CSE Lite SKU is integrated into
the coreboot. When the CSE Lite SKU is integrated, the KConfig prevents
writing to ME region but keeps read access enabled. Since CSE Lite driver
checks the signature of RW partition to identify the interrupted CSE
firmware update, so host must have read access to the ME region. Also, the
patch modifies the KConfig's help text to reflect the change.
When CSE Lite SKU is integrated, master access permissions:
FLMSTR1: 0x002007ff (Host CPU/BIOS)
EC Region Write Access: disabled
Platform Data Region Write Access: disabled
GbE Region Write Access: disabled
Intel ME Region Write Access: disabled
Host CPU/BIOS Region Write Access: enabled
Flash Descriptor Write Access: disabled
EC Region Read Access: disabled
Platform Data Region Read Access: disabled
GbE Region Read Access: disabled
Intel ME Region Read Access: enabled
Host CPU/BIOS Region Read Access: enabled
Flash Descriptor Read Access: enabled
BUG=b:174118018
TEST=Built and verified the access permissions.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I2f6677ab7b59ddce827d3fcaae61508a30dc1b28
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
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refer to cb:45878
Now that soc_get_pmc_mux_device() is gone, the PMC MUX connector devices
can be hooked up together via devicetree aliases.
BUG=b:174735512
BRANCH=volteer
TEST=build and type-c display work
Change-Id: I0bf84e2691856c9760d8fa9b6d853b04be10390a
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48268
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch renames the cbfs_boot_load_file() to cbfs_load() to
avoid the build errors for cselite and align with the new changes
to API https://review.coreboot.org/c/coreboot/+/39304 .
Change-Id: I717f0a3291f781cc3cf60aae88e7479762ede9f9
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48291
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tested=On OCP Delta Lake, verify the memory map hob data are correct.
Change-Id: I7bb2e9f41daa4cbce49169535eadf7f0d4972716
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Remove the unused UART_BT_WAKE GPIO as BT is over USB.
Change-Id: I638b4528fa5c4c378a1e8ff7bb88546da1513df2
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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TEST=Timeless build of mb/amd/mandolin results in identical image.
Change-Id: Ib1337f64ea7057cf04ca92bdef66e35cc350625d
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Change-Id: I89f08c201bd7d9a11b186ef960abe9714a76fb97
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Change-Id: I39cf2d28749536cb7d9462fa4af412850677f2e3
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Change-Id: Idc0061e7b88134ab17cb65429133cffd16ca5651
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Now pci_domain_ops in chip.c can also be marked as static.
Change-Id: Ia92b778a5882d991b391dc29aeee0a5615677913
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48315
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I1456fe069c4b0cf859f769e0144ec62cff0f3987
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Now pci_domain_ops in chip.c can also be marked as static.
Change-Id: I5e481fe311c9db4aacfd94bbf671edf679528946
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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TEST=Identical timeless build for amd/gardenia.
Change-Id: I04952cdbbe7893f35a674a156a9bc22202fbdc2f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48311
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since config_of() calls die() if dev or dev->chip_info are NULL,
config_of_soc() will either return a non-NULL pointer or won't return.
Change-Id: I6de6bb1610e823af215436c94ff1a78ff6b86b78
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
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Since config.c also gets linked into verstage on PSP and not only into
the stages running on the x86 cores, use all-y instead of adding
config.c to all classes separately.
Change-Id: Icacb13e73e80e6f3d8c2141784702fb895daf7db
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Change-Id: I9bc82f1e64f2cf21bfa4bf1ac75d17247208686c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48306
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The corresponding MSRs of all AMD family 17h and 19h CPUs/APUs match the
code.
Change-Id: I29cfef5d8920c29e36c55fc46a90eb579a042b64
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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The next patch will add a tsc subfolder that might end up containing
code that is guarded with different Kconfig options, so move the guards
into the Makefiles in the subfolders instead of guarding the inclusion
of the Makefiles in the subdirectories with the corresponding Kconfig
option.
Change-Id: Iafc867eb9adcb23e9a4878cc381684db6f9692d5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Remove SOC_INTEL_COMMON_BLOCK_HDA from mainboards Kconfig since it is
selected by their SoC soc/intel/cannonlake.
Change-Id: I9597746a217575b42f6325998b948e16b452231a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48289
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move mainboard/gpio.h to variant/gpio.h and rename its methods to make
clear that these methods are implemented on variant level.
Change-Id: Ib4e7ec948ca4d019ad82ebc5abe39fc408281cf4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48299
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add variant_configure_early_gpios() configuring early GPIOs to make the
difference clear.
Change-Id: I6e7c8c32963c9eeab4399947dac511442987cb45
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48298
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move mainboard/gpio.h to variant/gpio.h and rename its methods to make
clear that these methods are implemented on variant level.
Change-Id: Ibcb6322067285984bad70761fce34cfcb6ed8e0f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48297
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move mainboard/gpio.h to variant/gpio.h and rename its methods to make
clear that these methods are implemented on variant level.
Change-Id: I1ae9b54ed683000f65323b11747ce3280a1c7f2a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48296
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TEST=Timeless build doesn't change for amd/gardenia.
Change-Id: I5f1873111c07f6dc823b06654e463830d83acc9e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Change-Id: I3e4b3cbed8abe3988d9f48c13d01400af75a4776
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48307
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Don't make the default paths to AMD blobs depend on USE_AMD_BLOBS. This
way we get error messages about the missing files when the blobs repos
aren't checked out.
Change-Id: I754fdc5e1414c8a3dc88b364bcfbea9a26b59eb0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Allow to specify which signature is to be checked.
Change-Id: Ica874b1c4283fdb8dbd702c34ccb3315a2cf160d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Create the storo variant of the waddledee reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.3.1).
BUG=b:174284884
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_STORO
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I5ad41e0b2bc95b44733a2ad3c543267f3f56f9e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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The CPU core clock divisor ID needs to be in the range from 8 to 0x30
including both numbers.
TEST=Compared with Picasso's PPR #55570
Change-Id: Ie5ee342d22294044a68d2f4b2484c50f9e345196
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Without the EC blob being present in the SPI flash, the board won't even
power up.
Change-Id: Ia3c50e86414bbc707bc33e28c636196c1be2f1e6
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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This is an adapted copy of mainboard/example/min86 that is currently
only used for Jenkins to test the SoC code in soc/amd/cezanne and isn't
expected to reach boot block at the moment. It will be extended in
future follow-up commits.
Change-Id: I6806955952fbfa3227294cfc44fdf9156140e933
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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This is based on the minimal example code in soc/example/min86 and was
adapted to use the AMD non-CAR boot block and the common AMD PCI MMCONF
support.
In its current state this won't even reach the boot block, but will pass
the build bot. The missing parts for that will be added in future
patches. This is an attempt to not go the usual route to create a copy
of a previous SoC generation and the make changes to the code to work
for the new SoC, but to start from a nearly empty directory and then add
the actual code stage by stage and component by component.
Change-Id: I70aeb9ae010e943abfa667a0ea95c6fa9f15b7f5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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1. Add VARIANT_HAS_MIPI_CAMERA to Kconfig.name
2. Add mipi_camera.asl
BUG=b:169356808,b:169551066
TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I63d133246dbdc6aff7bf97d98f95052edf53bac9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47668
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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DPTF paramerters form thermal team.
Set PL1 Min/Max 15/25W, PL2 Min/Max 40/49W.
BUG=b:174514010
BRANCH=puff
TEST=build image and verified by thermal team.
Change-Id: I9e6c4bae181e87f87f2e92337bb9d989f5b7d955
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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set APU_EDP_BL_DISABLE(GPIO_85) to low to avoid the VARY_BL fast than
APU_DP_BLON.
BUG=b:171954512
BRANCH=zork
TEST=validate the panel sequence with scope.
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ia6d3f4335583bb2d91a6bce96d89cff84247d0ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Create the copano variant of the volteer reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.3.1).
BUG=b:174413884
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_COPANO
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Ib06625f492f68a6a6f5c6b382772b68f1eb681ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
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Use a wrapper code that does nothing on x86_32, but drops to protected
mode to call into FSP when running on x86_64.
Tested on Intel Skylake when running in long mode. Successfully run the
FSP-M which is compiled for x86_32 and then continued booting in
long mode.
Change-Id: I9fb37019fb0d04f74d00733ce2e365f484d97d66
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48202
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This adds a helper function for long mode to call some code in protected
mode and return back to long mode.
The primary use case is to run binaries that have been compiled for
protected mode, like the FSP or MRC binaries.
Tested on Intel Skylake. The FSP-M runs and returns without error while
coreboot runs in long mode.
Change-Id: I22af2d224b546c0be9e7295330b4b6602df106d6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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According to the spec provided by Bayhub, the 3.3V power rail must be enabled at least 100ms before reset is released.
To ensure this, set the power enable signal in the bootblock GPIO table.
BUG=b:173676531
BRANCH=firmware-volteer-13521.B
TEST=Built and booted into OS, test USB function normally.
Change-Id: I0c536f36c138ace93766f3024f6ec5d47b38269f
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47799
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use a new driver for the SX9324 proximity detector device.
This is first draft settings, will modify it after fine tuning.
BUG=b:172397658
BRANCH=zork
TEST=run "i2cdump -y -f 0 0x28" and checked all registers are expected.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I869d0b6640247099ca489e96ed94e03811a04bf4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47867
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Export all registers that driver is looking for. And put in alphabetic order.
The missing registers for kernel v5.4 sx93xx are:
reg_irq_msk
reg_irq_cfg0
reg_irq_cfg2
reg_afe_ph0/1/2/3
BUG=b:172397658
BRANCH=zork
TEST=Build passed
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ic9d7a959b1769b6846bba302e3aeab9a3a1cedac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47866
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Latest HW schematic add LTE_RST pin to control module power sequence.
BUG=b:173490220
BRANCH=zork
TEST=measure the waveform is meet the LTE module spec.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I0f0a35a905d711dd8d17dea2ae82a8dfa1fa05ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Enable Acoustic noise mitigation for drawcia and set slew rate to 1/4
which is calibrated value for the board. Other values like PreWake,
Rampup and RampDown are 0 by default.
BUG=b:162192346
BRANCH=dedede
TEST=Correct value is passed to UPD and Acoustic noise test passes.
Change-Id: Iadcf332d59dac2ba191b82742a18a1ab326940d1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This patch exposes acoustic noise mitigation related UPDs/configuration
to be filled from devicetree.
For each variant, we might have different values for various parameters.
Filling it from devicetree will allow us to fill separate values for
each board/variant.
Note that since JasperLake only has one VR, we're only filling index 0
for slew rate and FastPkgCRampDisable.
BUG=b:162192346
BRANCH=dedede
TEST=code compilation is successful and values from devicetree are
getting reflected in UPDs
Change-Id: Id022f32acc3fd3fe62f78e3053bacdeb33727c02
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Don't use the common block acpi.h when we aren't using the
COMMON_ACPI config. Fixes a dependency build issue in an upcoming
commit.
Change-Id: I3b80f7bbdf81e594fdde5b750c666edd8ca7268d
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
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This patch adds the PCI device ID for Alderlake
CPU xHCI.
Change-Id: I4074a81aa9be2ef3a0956da08bece32a613415ab
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Add the PCI IDs for Alderlake TCSS,
* USB xHCI
* USB xDCI
* TBT DMA
* TBT PCIe
Change-Id: I28bb310c7b031d2766c9e03dbcbe1c79901a7d87
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48242
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The new CBFS stack will log messages for found files but leaves error
messages up to the caller. This patch adds appropriate generic error
messages to cbfs_lookup(), matching the behavior of the old CBFS stack
for not found files.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I8cf44026accc03c466105d06683027caf1693ff0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The GPIO controller on Picasso has 4 banks of GPIOs with a size of 256
bytes each, so increase the reserved size to match the hardware.
Also replace the base GPIO address with the corresponding define.
Change-Id: I453f1c531d612a0e82ee0d91762fec6cdb2b8556
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Initiate device tree based on latest schematic.
BUG=b:174266035
TEST=Build Test
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia94119cb6d7eff6ea13c7d6a7dfd6ce891f706fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Refer pci_devs.h naming to align chipset.cb.
Correct thc0, thc1 and add cnvi_bt.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Iac33983dc12ed4e5b9257c50d82adc8e4e728ad6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48153
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add implementation of EC smihandler
BUG=b:174266035
TEST=Build Test
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I211f5755ff44514ab7ab4083f684ddd88c23fe48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48115
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Perform EC initialization in bootblock and ramstages. Add associated
ACPI configuration.
BUG=b:174266035
TEST=Build Test
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ie1305706134ca7cc58b8a9941231d1ee14f80949
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Enable building for Chrome OS and add associated ACPI configuration.
BUG=b:174266035
TEST=Build Test
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I5311879a127a2c8da1bbb086449019d932d57b72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Follow latest schematic UART_PCH_DBG is UART 0.
BUG=b:174266035
TEST=Build Test
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I8e334fee1adcd79d058b7ab07127f8ecf1735202
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48070
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable ACPI configuration and add DSDT ACPI table.
BUG=b:174266035
TEST=Build Test
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I08513ec159b69535f742a1fd70cdec9ec845d414
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Coachz rev1 has changed EN_PP3300_DX_EDP from gpio52 to gpio67.
BRANCH=none
BUG=b:174123578
TEST=emerge-strongbad coreboot chromeos-bootimage.
flash coreboot and boot up normally.
Signed-off-by: yuanliding <yuanliding@huaqin.corp-partner.google.com>
Change-Id: I32a721d0d725bf217debe35a5cdc01aa8f5d5daf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Change-Id: I9288ede88f822ff78dd9cb91020451dc935203a0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
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The functionality in smi_util applies for all 3 AMD SoCs in tree. This
patch additionally drops the HAVE_SMI_HANDLER guards in the common
block's Makefile.inc, since all 3 SoCs unconditionally select
HAVE_SMI_HANDLER in their Kconfig and smi_util doesn't use any
functionality that is only present when that option is selected.
Change-Id: I2f930287840bf7aa958f19786c7f1146c683c93e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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To accommodate also `off`, two spaces are used after `on` to align
comments.
This unifies the devicetree files of the two variants.
Change-Id: I7908fe2313ddccb6a4448a6338d6cd4938264f62
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This reduces the difference with Cereme’s devicetree file.
Change-Id: I1e6ba5891245562d5132307eab224623031e11c8
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Since the FMD file isn't parsed any more by a shell script in the SoC's
Makefile.inc, we can use better human-readable numbers for the section
sizes.
TEST=Timeless build results in identical image.
Change-Id: I2117064a694f67767284f6fd4ac3604b254a2734
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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TEST=Timeless build results in identical image.
Change-Id: Ifa5c14add555b382f74ba1165131b1569bbef123
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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This makes it possible to select both the legacy LAPIC AP init or the
newer parallel MP init.
Tested on i440fx with -smp 32.
Change-Id: I007b052ccd3c34648cd172344d55768232acfd88
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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CONFIG_MAX_CPUS=4 is the maximum supported with SMM_ASEG.
TESTED: on q35 and i440fx -smp 4/32.
Change-Id: I696856870e34e7a7ad580bc83c6b38f1dfb4511d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Adapt the old lapic init code for x86_64.
Change-Id: I5128ed574323025e927137870fb10b23d06bc01d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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