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2011-08-04cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.Keith Hui
Bring from coreboot v1 support for initializing L2 cache on Slot 1 Pentium II/III CPUs, code names Klamath, Deschutes and Katmai. Build tested on ASUS P2B-LS and P3B-F. Boot tested on P2B-LS with Pentium III 600MHz, Katmai core. Also add missing include of model_68x in slot_1, to address a similar problem fixed for model_6bx by r5945. Also change Deschutes CPU init sequence to match Katmai. Change-Id: I502e8481d1a20f0a2504685e7be16b57f59c8257 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: http://review.coreboot.org/122 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-08-03Remove debugging code, or convert it to be selected by kconfigJonathan A. Kollasch
Change-Id: Ib6cd82badeb6401e065ee14c2a04c78f61a87dd4 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/130 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-03Use preferred style of fixed-width integer typesJonathan A. Kollasch
Change-Id: I1abaaa2af4de940584039f9b8c348bb57fb611e0 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/125 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Peter Stuge <peter@stuge.se>
2011-07-22Add xhcbios and ahcibios rom handlingefdesign98
This change adds xhci and ahci bios rom handling that is similar to the vgabios rom handling in the arch/x86 Makefile.inc to the Persimmon and Torpedo mainboards. It also adds the basis for AHCI BIOS rom handling to the Persimmon Kconfig. Change-Id: I527a906323ae483cfa2ca0785f3adb43e88fd84b Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/109 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-22Add the SuperMicro H8QGI platformefdesign98
This set adds support for the SuperMicro H8QGI mainboard. It is a publicly available 4 socket board using AMD Family 10 cpus and AMD SR5650 and SB700 bridges. Change-Id: I196704f79db4c45382559c5ee0619dc8d96ff140 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/108 Tested-by: build bot (Jenkins) Reviewed-by: Kerry She <shekairui@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-22Add SSE3 dependent codeefdesign98
This change separates out changes that were initially found in the commit for XHCI and AHCI changes to "arch/x86/Makefile. inc". It also corrects a comment. The SSE3 dependent code adds a pair of CR4 access functions and a blob of code that re-sets CR4.OSFXSR and CR4.OSXMMEXCPT. Change-Id: Id97256978da81589d97dcae97981a049101b5258 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/113 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-07-22Update AMD SR5650 and SB700efdesign98
This updates the code for the AMD SR5650 and SB700 southbridges. Among other things, it changes the romstage.c files by replacing a .C file include with a pair of .H file includes. The .C file is now added to the romstage in the SB700 or SR5650 Makefile.inc. file to the romstage and ramstage elements. This particular change affects all mainboards that use the SB700, and their changes are include herein. These mainboards are: Advansus a785e, AMD Mahogany, Mahogany-fam10, Tilapia-fam10, Asrock 939a785gmh, Asus m4a78-em, m4a785-m, Gigabyte ma785gm, Iei Kino-780am2-fam10 Jetway pa78vm5 Supermicro h8scm_fam10 The nuvoton/wpcm450 earlysetup interface is changed because the file is no longer included in the mainboard romstage.c files. Change-Id: I502c0b95a7b9e7bb5dd81d03902bbc2143257e33 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/107 Tested-by: build bot (Jenkins) Reviewed-by: Kerry She <shekairui@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-18Add AMD Family 10 support to cpu folderefdesign98
This change adds the AMD Family 10 cpu support to the cpu folder. It also updates the makefiles of the Families 12 and 14 to take advantage of a pair of shared files that are moved to the cpu/agesa folder. Change-Id: Ibd3a50ea7a3028bd6a2d2583f021506b73e2fce2 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/97 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-07-18Add AMD Family 10 cpu support to northbridge folderefdesign98
This change adds the AMD Family 10 cpu support to the northbridge folder. The northbridge/amd/agesa Kconfig and Makefile.inc are changed as well. Change-Id: Id76e9fa388c79ac469a673aaedaa4f1bfd7619d9 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/98 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-07-16Workaround the errata #181.Rudolf Marek
We use LDTSTOP# to trigger the FID/VID change on K8M890, because the FID/VID SMAF is blocked by not yet configured internal VGA. The memory controller is enabled later, nor the workaround makes any harm to non-affected CPUs. This update unbreaks compilation by declaring the tmp variable. Change-Id: Icf5d126b8c8cd9ece6af41d3129315a777c8cef2 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com> Reviewed-on: http://review.coreboot.org/69 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-07-15Add the AMD Family10 Agesa codeefdesign98
This change officially adds the Agesa code for the AMD Family 10 cpus. This code supports the G34 and C32 sockets. Change-Id: Idae50417e530ad40a29fb6fff5b427f6b138126c Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/95 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-07-14Move AMD SB800 early clock setup.Scott Duplichan
Move the AMD SB800 early clock setup code that is needed for early serial port operation from mainboard/romstage.c to sb800/bootblock.c. This prevents code duplication and simplifies porting. Change-Id: I615cfec96c9f202d9c154dc6674ec7cbcf4090c3 Signed-off-by: Scott Duplichan <scott@notabs.org> Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/96 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-07-14Set SB800 ROM decode size based on kconfig.Marc Jones
Change-Id: I46ea26b5534064fe1c7e2ce2b2f12cacf18a4d4d Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/94 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-07-13Enable SMI on M2V-MX SERudolf Marek
Finally the SMI routines are in good shape on AMD, lets enable this and later implement ACPI on/off SMI commands. Change-Id: I9848a7be908780353eead30c16fd2df8ea48f77e Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/83 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-07-13Make AMD SMM SMP awareRudolf Marek
Move the SMM MSR init to a code run per CPU. Introduce global SMM_BASE define, later all 0xa0000 could be changed to use it. Remove the unnecessary test if the smm_init routine is called once (it is called by BSP only) and also remove if lock bit is set becuase this bit is cleared by INIT it seems. Add the defines for fam10h and famfh to respective files, we do not have any shared AMD MSR header file. Tested on M2V-MX SE with dualcore CPU. Change-Id: I1b2bf157d1cc79c566c9089689a9bfd9310f5683 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/82 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-07-12Do full flush on uart8250 only at end of printk.Kevin O'Connor
The previous code does a full flush of the uart after every character. Unfortunately, this can cause transmission delays on some serial ports. This patch changes the code so that it does a flush at the end of every printk instead of at the end of every character. This reduces the time it takes to transmit serial messages (up to 9% on my Asrock e350m1 board). It also makes the transmission time more consistent which is important when performing timing tests via serial transmissions. Change-Id: I6b28488b905da68c6d68d7c517cc743cde567d70 Signed-off-by: Kevin O'Connor <kevin@koconnor.net> Reviewed-on: http://review.coreboot.org/90 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-by: Sven Schnelle <svens@stackframe.org>
2011-07-11T60: enable GPIO before using GPIO I/O port rangeSven Schnelle
Change-Id: I39369e6f8a39f53f58a4b7fbe357637a79f5b596 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/93 Tested-by: build bot (Jenkins)
2011-07-11T60: dont use X60 USB init flagSven Schnelle
ec byte 0x03, bit 2 seems to be only used on the X60s for USB switch initialization. Don't touch it on T60. Change-Id: Icb89a514757a0e06ccea200fde62a778fa8c268e Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/92 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2011-07-10ASRock E350M1: ACPI-related BSOD fixScott Duplichan
On installing/starting Windows (tested with Win7 Ultimate) the system crashes with a Blue Screen of Death, reporting an ACPI BIOS error. From Scott Duplichan: To avoid the Windows BSOD, the uninitialized value TOM1 in the SSDT must be corrected. The attached patch does this. It uses the older patching method, and not the (possibly preferred) AML generation method. To simplify the patching operation, I moved the AML item 'TOM1' to the start of the SSDT. The patch also includes code to confirm the AML variable TOM1 is at the expected offset before patching. Also tested & working with Linux. Change-Id: I59cedc366e09d98f690b093d6a21fc0c864559c3 Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marshall Buschman <mbuschman@lucidmachines.com> Reviewed-on: http://review.coreboot.org/91 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-07-09Fix memory size reporting on AMD family 14h systems for >= 4GBCristian Măgherușan-Stanciu
Applying Scott Duplichan's fix for memory >=4GB Adjusted it to the new directory structure (agesa_wrapper was renamed to just agesa). Boot-tested and confirmed to work, on my board Linux can now access the whole RAM. Change-Id: I31d66a488a7811d214d84653860b3e0116f67d19 Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marshall Buschman <mbuschman@lucidmachines.com> Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com> Reviewed-on: http://review.coreboot.org/48 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-07-07T60: handle EC events in SMM if ACPI is disabledSven Schnelle
Change-Id: I6f9e90015cafef3da896453ef8e3588434ae3554 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/89 Tested-by: build bot (Jenkins)
2011-07-04Small SMM fixupsRudolf Marek
Align the spinlock to the 4 byte boundary (CPU will guarantee atomicity of XCHG). While at it add the PAUSE instruction to spinlock loop to hint the CPU we are just spinlocking. The rep nop could not be used because "as" complains that rep is used without string instructions. Change-Id: I325cd83de3a6557b1bee6758bc151bc81e874f8c Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/81 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-07-02whitespace-only changes in acpi.c, replaced spaces with tabsCristian Măgherușan-Stanciu
Change-Id: Ibd598813bec0c93d77afbce8aee330498afbe5f6 Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com> Reviewed-on: http://review.coreboot.org/74 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2011-07-02added a config option for ACPI debuggingCristian Măgherușan-Stanciu
Change-Id: Ie6296f5652196c6258aa6902d84dd86c17e224cb Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com> Reviewed-on: http://review.coreboot.org/36 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2011-06-30Improve VIA K8M890 HT settings. Use recommended settings for ROMSIP andRudolf Marek
for the transmit clock driving control. Unfortunately this is not enough to make the HT1000 work reliably, therefore blacklist this for now in CPU HT code. If ever anyone figure out what is wrong, it could be removed. The downgrading now makes the board work on HT800, which is certainly better than not at all with a HT1000 CPU. Change-Id: I949bfd9b0b48ee12bd0234c2fb1deaaa773bd235 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/68 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-29Added support for Aaeon PFM-540I RevB PC104 SBCMark Norman
The Aaeon PFM-540I RevB SBC is a PC104 SBC using a AMD Geode LX800 CPU. More infomation about the board available at www.aaeon.com. Change-Id: Ia8a3caacdc9ff1820a6c0a13a9a7ee758b929dfd Signed-off-by: Mark Norman <mpnorman@gmail.com> Reviewed-on: http://review.coreboot.org/30 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-29i82801gx: read RTC status register to prevent IRQ stormSven Schnelle
My Thinkpad appeared dead. After investigation, it turned out that the RTC Alarm was triggering an RTC PM1 SMI, but the SMI handler didn't read the status register, so it was triggered again. This is a really nasty situation, as it means you have to dissemble your Notebook just to unplug the RTC battery. Change-Id: I5ac611e8a72deb5f38c86486dbe0693804935723 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/67 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-06-29amd southbirdge sb800 wrapper, pci bridge fixKerry She
sb800 pci bridge SHOULD enabled by default according to the chipset document, but actually not enabled on some mainboard. enable sb800 pci bridge when told to enable in devicetree.cb. tested on ibase persimmon mainboard. Change-Id: I42075907b4a003b2e58e5b19635a2e1b3fe094c3 Signed-off-by: Kerry She <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/63 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-28Add the AMD Torpedo mainboardefdesign98
The Torpedo mainboard is the reference platform for the AMD Family 12 cpus and the AMD Hudson-2 (SB900) southbridge. Change-Id: Ifbf82fc4e4375a108a9d6068876b8ff612cfa8e1 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/54 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-28Addition of Family12/SB900 wrapper codeefdesign98
This change adds the wrapper code for the AMD Family12 cpus and the AMD Hudson-2 (SB900) southbridge to the cpu, northbridge and southbridge folders respectively. Change-Id: I22b6efe0017d0af03eaa36a1db1615e5f38da06c Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/53 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-28SMM: add guard and include types.h in cpu/x86/smm.hSven Schnelle
Change-Id: I002845cf7a37cd6885456131826ae0ba681823ef Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/64 Tested-by: build bot (Jenkins)
2011-06-28X60: remove pci config register save/restoreSven Schnelle
SMM code already makes sure this register is saved and restored, so we don't have to do it. Change-Id: I078e1227de4436fba9c5fb3879a564c981cb0f9a Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/65 Tested-by: build bot (Jenkins)
2011-06-23T60: undock on external power lossSven Schnelle
If power is unplugged/lost, we should undock the docking station. The power loss can also be caused by the fact that the user removed the thinkpad from the docking station without pressing the Undock button/hotkey first. Without undocking it on this event, the thinkpad LPC switch will still connect the Docking connector, which causes crashes when docking it again. Change-Id: I9ed783e491827bde20264868eab2b3a79c232922 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/62 Tested-by: build bot (Jenkins)
2011-06-23T60: enable userspace EC eventsSven Schnelle
EC events 0x50-0x5f are never triggered by the EC. Instead they can be generated by writing the wanted events to register 0x2a. Change-Id: Ifd7ce991ee094cb16e8425ed670b6b45cffe3907 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/61 Tested-by: build bot (Jenkins)
2011-06-23T60: add additional EC eventsSven Schnelle
We missed a few bits, i.e the battery and some hotkey events. Change-Id: Ia5561532f421eb3b40225301f0af639112abc3cc Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/60 Tested-by: build bot (Jenkins)
2011-06-23Add ThinkPad modelsSven Schnelle
Change-Id: I4f1a5d99486929eb0be76a0ab3bf0158a23c7d36 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/59 Tested-by: build bot (Jenkins)
2011-06-23T60: add missing License HeaderSven Schnelle
Change-Id: I03636deac7b6d8e01654cf978b1aac79cba10641 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/58 Tested-by: build bot (Jenkins)
2011-06-22X60: add missing License HeaderSven Schnelle
Change-Id: I9d6e80a633990e86dd3adfa2a761d09f62978349 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/57 Tested-by: build bot (Jenkins)
2011-06-22H8: add missing License HeaderSven Schnelle
Change-Id: If472e1e8bb93d64cc52a9084ad33fb9abbf0fb33 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/56 Tested-by: build bot (Jenkins)
2011-06-22PMH7: add missing License HeaderSven Schnelle
Change-Id: I3468689408fce05142a0959d5d725bdbd03faea7 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/55 Tested-by: build bot (Jenkins)
2011-06-22Move SB800 clock init earlierScott Duplichan
Committing Scott's e350m1 changes (svn r6585): Move SB800 clock init earlier, Fixes problem where initial serial port output is garbled. Change-Id: If05aa37726b962e8994ee69bf1882fcfae56aa19 Signed-off-by: Scott Duplichan <scott@notabs.org> Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com> Reviewed-on: http://review.coreboot.org/32 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-22Add the coreboot config to CBFSCristian Măgherușan-Stanciu
The CBFS will contain a new file, named 'config' of type 'raw' that is a stripped-down version of the .config file that was used to build the current coreboot image. For space savings, all the comments and empty lines were removed from the original config, except for one that lists the coreboot git revision that's built into the image. This is done in order to easily reproduce the work of someone else when only having their ROM image. In theory the reproduce could even be automated by a new dedicated make target. This should work even with abuild now. Change-Id: I784989aac0227d3679d30314b06dadaec402749e Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com> Reviewed-on: http://review.coreboot.org/46 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-22Move existing AMD Ffamily14 code to f14 folderefdesign98
This change moves the AMD Family14 cpu Agesa code to the vendorcode/amd/agesa/f14 folder to complete the transition to the family oriented folder structure. Change-Id: I211e80ee04574cc713f38b4cc1b767dbb2bfaa59 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/52 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-22Rename {CPU|NB|SB}/amd/*_wrapper foldersefdesign98
This change renames the cpu/amd/agesa_wrapper, northbridge/ amd/agesa_wrapper, and southbridge/amd/cimx_wrapper folders to {cpu|NB}/amd/agesa and {SB}/amd/agesa to shorten and simplify the folder names. There is also a fix to vendorcode/amd/agesa/lib/amdlib.c to append "ull" to a trio of 64-bit hexadecimal constants to allow abuild to run successfully. Change-Id: I2455e0afb0361ad2e11da2b869ffacbd552cb715 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/51 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-21Add AMD SB900 CIMx codeefdesign98
This code is added to support the AMD SB900 southbridge. Change-Id: I7dc5e13a53ffd479dcea4e05e8c8631096e2ba91 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/41 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-21Add AMD Family 12 cpu Agesa codeefdesign98
This is the addition of the AMD Family 12 cpu code. Change-Id: I3febc81e192b4e86bbd3e8d6e1da62a28598fa8c Signed-off-by: Frank Vibrans<frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/40 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-20sb800: move spi prefetch and fast read mode to sb bootblock.Stefan Reinauer
So we don't waste time on the first cbfs scan. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> [adapt persimmon with the same change, and work around romcc bug in bootblock code: it doesn't like MEMACCESS[idx] |= value;] Change-Id: Ic4d0e53d3102be0de0bd18b1b8b29c500bd6d997 Reviewed-on: http://review.coreboot.org/9 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-20Introduced support for 8MB and 16MB flash sizesCristian Măgherușan-Stanciu
Change-Id: I217ff84be3575ec09781710f19ad272c88227663 Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com> Reviewed-on: http://review.coreboot.org/49 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-20ASRock E350M1: Enable USB3 supportMarshall Buschman
Requires Scott Duplichan's patch for NIC support. Enables required PCIe port for USB3 - does not interfere with normal operations on non-USB3 model. Change-Id: I451bb1b4f799d6485e75fa949933e25e821b65f9 Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com> Reviewed-on: http://review.coreboot.org/45 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-19ASRock E350M1: Configure SB800 GPP ports to support onboard pcie nicScott Duplichan
Scott Duplichan's patch from the mailing list: sb800 cimx wrapper: Run the complete sb800 cimx sbBeforePciInit() function once, after determining device 0x15 function enables. 1) Update the asrock e350m1 devicetree.cb to match the hardware. 2) Change the way the sb800 cimx wrapper code works. The original cimx code calls sb800 cimx function sbBeforePciInit() once. When ported to coreboot, the gpp component of this function was called once for each gpp port, as the gpp port's enable/disable state became known. A 05/15/2011 change makes the early gpp code run only once, triggered by processing the 4th gpp port. This method is not general enough because the 4th gpp port is not enabled on all boards. With the current change, the early gpp code runs when the first gpp port is processed. If any gpp ports are enabled, the first must be enabled. Tested with Win7 and linux on asrock e350m1. This change will also affect amd inagua, and has not been tested on that board. Change-Id: I93d44c216bfcab3c3a8fbb79d23dab43a65850e6 Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marshall Buschman <mbuschman@lucidmachines.com> Reviewed-on: http://review.coreboot.org/44 Tested-by: build bot (Jenkins) Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
2011-06-18SMM: flush caches after disabling cachingSven Schnelle
Fixes spurious SMI crashes i've seen, and ACPI/SMM interaction. For reference, the mail i've sent to ML with the bugreport: whenever i've docked/undocked the thinkpad from the docking station, i had to do that twice to get the action actually to happen. First i thought that would be some error in the ACPI code. Here's a short explanation how docking/undocking works: 1) ACPI EC Event 0x37 Handler is executed (EC sends event 0x37 on dock) 2) _Q37 does a Trap(SMI_DOCK_CONNECT). Trap is declared as follows: a) Store(Arg0, SMIF) // SMIF is in the GNVS Memory Range b) Store(0, 0x808) // Generates I/O Trap to SMM c) // SMM is executed d) Return (SMIF) // Return Result in SMIF I've verified that a) is really executed with ACPI debugging in the Linux Kernel. It writes the correct value to GNVS Memory. After that, i've logged the SMIF value in SMM, which contains some random (or former) value of SMIF. So i've added the GNVS area to /proc/mtrr which made things work. I've also tried a wbinvd() in SMM code, with the same result. After reading the src/cpu/x86/smm/smmhandler.S code, i've recognized that it starts with: movw $(smm_gdtptr16 - smm_handler_start + SMM_HANDLER_OFFSET), %bx data32 lgdt %cs:(%bx) movl %cr0, %eax andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */ orl $0x60000001, %eax /* CD, NW, PE = 1 */ movl %eax, %cr0 /* Enable protected mode */ data32 ljmp $0x08, $1f ...which disables caching in SMM code, but doesn't flush the cache. So the problem is: - the linux axpi write to the SMIF GNVS Area will be written to Cache, because GNVS is WB - the SMM code runs with cache disabled, and fetches SMIF directly from Memory, which is some other value Possible Solutions: - enable cache in SMM (yeah, cache poisoning...) - flush caches in SMM (really expensive) - mark GNVS as UC in Memory Map (will only work if OS really marks that Area as UC. Checked various vendor BIOSes, none of them are marking NVS as UC. So this seems rather uncommon.) - flush only the cache line which contains GNVS. Would fix this particular problem, but users/developers could see other Bugs like this. And not everyone likes to debug such problems. So i won't like this solution. Change-Id: Ie60bf91c5fd1491bc3452d5d9b7fc8eae39fd77a Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/39 Tested-by: build bot (Jenkins)
2011-06-18T60: set dock LED's in mainboard.cSven Schnelle
The docking takes place in romstage to have early serial I/O for debugging. But to keep romstage small and prevent linking the EC code to romstage, set the status LED's in ramstage. Change-Id: I89fadbd61b6bfd9aff8c22370e51c84325f24751 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/42 Tested-by: build bot (Jenkins)
2011-06-16X60/T60: disable USB power during suspendSven Schnelle
Change-Id: I11afba5d7531132a0274e55e8a478985a0ef956f Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/38 Tested-by: build bot (Jenkins)
2011-06-16Lenovo H8 EC: add usb_power_enable()Sven Schnelle
Can be used to disable/enable Power output on USB ports. Change-Id: I5eb52b33c9e3359b0e5874bda2c0c8d75c196bc2 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/37 Tested-by: build bot (Jenkins)
2011-06-15SMM: don't overwrite SMM memory on resumeSven Schnelle
Overwriting the SMM Area on resume leaves us with all variables cleared out, i.e., the GNVS pointer is no longer available, which makes SMIF function calls impossible. Change-Id: I08ab4ffd41df0922d63c017822de1f89a3ff254d Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/34 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-15i945 GMA: restore tft brightness from cmosSven Schnelle
Change-Id: Iaf10f125425a1abcf17ffca1d6e246f955f941cc Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/24 Tested-by: build bot (Jenkins)
2011-06-15Remove old ACPI codeSven Schnelle
it isn't used anywhere, and could be fetched from git/svn history if needed. Change-Id: Iaa2ba39af531d0389d7ab1110263ae7ecaa35c70 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/35 Tested-by: build bot (Jenkins)
2011-06-15i82801gx: replace cafed00d/cafebabe by definesSven Schnelle
We're using '0xcafed00d' all over the code as magic for ACPI S3 resume. Let's add a define for that. Also replace 0xcafebabe by a define. Change-Id: I5f5dc09561679d19f98771c4f81830a50202c69f Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/33 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-06-15X60: handle EC events in SMM if ACPI is disabledSven Schnelle
Change-Id: I0fee890bd2d667b54965201f5c90da3656d7af5c Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/27 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-15X60: trigger save cmos on volume/brightness changeSven Schnelle
Change-Id: I020e06bc311c4e4327c9d3cf2c379dc8fe070a7a Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/25 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-15CMOS: add set_option()Sven Schnelle
Change-Id: I584189d9fcf7c9b831d9c020ee7ed59bb5ae08e8 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/23 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-06-13X60/T60: set CMOS defaultsSven Schnelle
Change-Id: I5789a03898cdbade67887c0389aab5c773f867d9 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/26 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-12ASRock/E350M1: Skip memory clear for boot time reductionMarshall Buschman
Applying Scott's patches to e350m1, svn r6600: Memory clear is not required for non-ECC boards. Change-Id: Ia1a7c926611de72351434cbdc1795ed10bc56ed1 Signed-off-by: Scott Duplichan <scott@notabs.org> Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com> Reviewed-on: http://review.coreboot.org/20 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-06-12X60/T60: fix return value of mainboard_io_trap_handler()Sven Schnelle
The handler should return 1 if it handled the request. The current code returns 0, which causes 'Unknown function' logs. Change-Id: Ic296819a5f8c6f1f97b7d47148182226684882a0 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/29 Tested-by: build bot (Jenkins)
2011-06-12log ec data with DEBUG_SPEWSven Schnelle
Change-Id: I26424e80c776bfc134528f42e87fde42d6a13108 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/28 Tested-by: build bot (Jenkins)
2011-06-10Add ACPI automatic PIC/APIC interrupt routing logic for ck804Jonathan A. Kollasch
Change-Id: I2d462ca1220ea31af243c7a58a1dc33c39e9c840 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/13 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-09H8 EC: add volume CMOS settingSven Schnelle
Change-Id: I5332c8fa52556db34dfb5e772bf544f0323e823d Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/12 Tested-by: build bot (Jenkins)
2011-06-09Revert changes to set the sb800 to AHCI mode.Marc Jones
Seabios doesn't have this support included yet, which causes the generic Persimmon and other CIMx sb800 platforms to not boot. Change-Id: If07328b7c62d7fc314647adce8fab983ed327854 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/14 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-06-07T60/PMH7: move 'touchpad' option to pmh7Sven Schnelle
This option is PMH7 specific, and should be moved there, so all Notebook utilizing a PMH7 have this option. For Thinkpads without Touchpad (like the X60), simply don't add 'touchpad' to cmos.layout. Change-Id: Icdd0093670d565f1b16e2483aa286f4d63ccc52a Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/6 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-07i82801gx: enable ACPI during S3 resumeSven Schnelle
disabling ACPI during S3 wakeup breaks ACPI wakeup, as the Host OS is assuming that ACPI is enabled. Change-Id: I8ced72c4b553d41a57f26d64998118e8a77621f8 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/7 Tested-by: build bot (Jenkins)
2011-06-07SMM: add defines for APM_CNT registerSven Schnelle
in the current code, the defines for the APM_CNT (0xb2) register are duplicated in almost every place where it is used. define those values in cpu/x86/smm.h, and only include this file. And while at it, fixup whitespace. Change-Id: Iae712aff53322acd51e89986c2abf4c794e25484 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/4 Tested-by: build bot (Jenkins)
2011-06-07T60: fix touchpad optionSven Schnelle
Code used 'int' as return type, but the cmos option is only one bit. get_option returned with the value in bit 0-7, but all remaining bits were left unitialized by get_option(). fix this by using char as type. Change-Id: I60e609164277380f936f66c99ef9508fa6a6b67c Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/5 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-06-07re-indent, so files conform to coding guidelines.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: If840164fa0e2b6349ba920edf06386ba1fe08aab Reviewed-on: http://review.coreboot.org/8 Tested-by: build bot (Jenkins) Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
2011-06-06SMM: add mainboard_apm_cnt() callbackSven Schnelle
motherboards can use this hook to get notified if someone writes to the APM_CNT port (0xb2). If the hook returns 1, the chipset specific hook is also skipped. Change-Id: I05f1a27cebf9d25db8064f2adfd2a0f5759e48b5 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/3 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2011-06-04WARNINGS_ARE_ERRORS is y per default, don't set it twice.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6637 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04Port persimmon r6594 to e350m1: Cosmetic cleanupPeter Stuge
Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Marshall Buschman <mbuschman@lucidmachines.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6636 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04Port persimmon r6593 to e350m1: Remove unused Kconfig optionsPeter Stuge
Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Marshall Buschman <mbuschman@lucidmachines.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6635 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04Port persimmon r6592 to e350m1: Update GPP port configurationPeter Stuge
Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Marshall Buschman <mbuschman@lucidmachines.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6634 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04Port persimmon r6591 to e350m1: ROM cache earlyMarshall Buschman
Enable rom cache early to reduce boot time. Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6633 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04Port persimmon r6590 to e350m1: Work around memory allocation problemMarshall Buschman
Fix memory allocation problem in amdInitLate. Disabled until further debug. Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6632 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04Port persimmon r6589 to e350m1: Strip down AGESA optionsMarshall Buschman
Remove some non-essential agesa options to reduce boot time. Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6631 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04Port persimmon r6588 to e350m1: VGA framebufferMarshall Buschman
Declare legacy video frame buffer so that Windows generic VGA driver will work. Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6630 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04Port persimmon r6587 to e350m1: RTC is not PIIX4 compatibleMarshall Buschman
Declare RTC as not PIIX4 compatible to match AMD hardware. Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6629 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04Port persimmon r6586 to e350m1: FADT revisionMarshall Buschman
Make fadt revision match its length. Solves Windows 7 checked build assert. Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6628 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04Port persimmon r6584 and r6601 to e350m1: SPI prefetch earlyMarshall Buschman
Enable SPI cacheline prefetch early to reduce boot time. Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6627 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04Port persimmon r6583 to e350m1: pstate 0 earlyMarshall Buschman
Switch processor cores to pstate 0 early to reduce boot time. Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6626 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04Port persimmon r6582 to e350m1: 33 MHz SPI read earlyMarshall Buschman
Enable 33 MHz fast mode SPI read early to reduce boot time. Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6625 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04Port persimmon r6578 and r6596 to e350m1: MMCONF basePeter Stuge
Remove multiple mmconf settings and just use kconfig setting. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04Port persimmon r6574 to e350m1: MMCONF sizeMarshall Buschman
Size mmconf according to CONFIG_MMCONF_BUS_NUMBER. Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6623 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04Port persimmon r6573 to e350m1: VGA, PCI MMIO and SB800 legacyMarshall Buschman
1) Use D18F1xF4 VGA Enable to simplify legacy video I/O support. 2) Extend PCI MMIO limit from dfffffff to fecfffff. 3) Add AMD recommended non-posted mapping for SB800 legacy devices. Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6622 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04Port persimmon r6572 to e350m1: I/O APIC IDMarshall Buschman
1) Set I/O APIC ID according to BKDG recommendation 2) Correct I/O APIC ID reported by mptable Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6621 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04vt8237r: Simplify bootblock init to work around nested if() romcc problemPeter Stuge
During the hackathon in Prague we discovered that romcc has a problem compiling the previous nested if() statements correctly. This patch makes the code a little simpler, and indeed works around the romcc issue. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6620 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-03This patch sets max freq defaults for ddr2 and ddr3for fam10.Marc Jones
Signed-off-by: Marc Jones <marcj303@gmail.com> Acked-by: Scott Duplichan <scott@notabs.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6619 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-03Correct wrong PCI ID for VIA K8M890 Chrome.Alexandru Gagniuc
With the K8T800/M800 patch from r6367 the PCI IDs for the VIA chrome were moved to pci_ids.h. The PCI ID for K8M890 chrome was copied incorrectly. (3220 instead of 3230). This patch defines the correct PCI ID for this device. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6618 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-03advansus/a785e-i mainboard enable warning as errorKerry She
Signed-off-by: Kerry She <kerry.she@amd.com> Acked-by: Kerry She <kerry.she@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6617 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-01trivial remove blanks at the end of lineKerry She
Signed-off-by: Kerry She <kerry.she@amd.com> Acked-by: Kerry She <kerry.she@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6614 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-01This patch fix a AMD sb800 wrapper compile warning:Kerry She
src/southbridge/amd/cimx_wrapper/sb800/late call clear_ioapic but not include the prototype declare header file. Signed-off-by: Kerry She <kerry.she@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6613 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-23We don't have pausing versions of single-IO instructions.Stefan Reinauer
Hence remove the wrong comment. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6612 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-23AP_IN_SIPI_WAIT is already defined in the CPU Kconfig of those boards.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6611 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-23Correct implementation of r6608.Jonathan Kollasch
(.align actually takes its argument in bytes) Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net> Acked-by: Jonathan Kollasch <jakllsch@kollasch.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6610 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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