| Age | Commit message (Collapse) | Author |
|---|
|
This adds use of BROKEN_CAR_MIGRATE to include CBMEM symbols for the
build of romstage also for boards without HAVE_ACPI_RESUME.
These symbols got exposed as the use of preprocessor directives was
reduced.
We expect the linker to do a fair job and optimize away function
bodies that are on unreachable execution paths.
Change-Id: Ibf5181d3eecb87ce647abe0be01072594b05aa5f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6067
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
|
To be precise, wakeup from S3 does not involve SPI writing, while
preparing for it on cold power-ons currently does.
For S3DataTypeMtrr storage is changed such that the first 4 bytes
is the length of data stored like with the other two S3DataType.
Change-Id: Id920650474530d4191075da4ef70daa66c904c5b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6085
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
|
|
Use one common implementation for all AGESA platforms.
Change-Id: I410f8e0a9c75445882d67659cde00004eb7ad6b4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6084
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Prepare code to locate S3 backup from CBFS as a file. Follow-up will
replace remaining use of CONFIG_S3_DATA_POS with cbfs_get_file_content().
Change-Id: I693c41c90e61d1a7c7b10e43c9f264d099c9a400
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6083
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
|
|
Port the changes that were made in amd/cimx to amd/agesa
as were done in:
commit c93a75a5ab067f86104028b74d92fc54cb939cd5
Author: Mike Loptien <mike.loptien@se-eng.com>
Date: Fri Jun 6 15:16:29 2014 -0600
AMD/CIMx: Add functions for AMD PCI IRQ routing
This change also moves the PCI INT functions to
southbridge/amd so that they can be used by CIMX and
AGESA. The amd/persimmon board is updated for this
change.
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Change-Id: I525be90f9cf8e825e162d53a7ecd1e69c6e27637
Reviewed-on: http://review.coreboot.org/6065
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Change-Id: Ib2f6fad735e085d237a0d46e0586e123eef6e0e2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6161
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
|
Even with !defined(__ROMCC__) in the file, romcc chokes on these
parameter names after we declare common max() macro in stdlib.h.
Change-Id: Id4f2aa61d9c5b19f428452cd475b1b2ed9a70f52
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6165
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
|
Equality comparison with extraneous parenthese, spotted by Clang.
Change-Id: I8d532392a0365753583ed441958e06d5da784587
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6124
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
There is no guarantee reading a dereferenced null pointer will not be
optimised away. Qualify the integer storage type with volatile. Clang
enforces this explicitness.
Change-Id: I31524141d70632cade0490c820936a3a8b570346
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6148
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
It was never well-defined what value this function should return.
Change-Id: If84aff86e0b556591d7ad557842910a2dfcd3b46
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6166
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
|
Change-Id: I60ae6dcb8c3b280fe74f27f4d61de70cc1ba190b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6123
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
|
Missing "__attribute__((noreturn))" on halt function. This sync's the
implementation to be the same as that of amd/lx thereby avoiding
compiler warnings.
Change-Id: Iead16125805eb36ff875fba767cf8d4e5aa86715
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6157
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Clang complains these functions are unused since they find their way
into the bootblock of ROMCC boards by #including the .c file. These
static inlines should probably be moved into a header in reality.
Change-Id: I9d82a6befb0ac99afab6265f9d3649e419f2887d
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6122
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
|
|
Move some __SMM__ functions under the #if preprocessor condition to
avoid warnings about unused functions.
Change-Id: I7f6fbc6a577032bc4e4635d91e8e94aecb517bd3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6127
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Spotted by Clang.
Change-Id: I38832da7b93d4ee18b8de3e80dc39513a8910221
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6149
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Comparison of unsigned expression < 0 is always false.
Change-Id: Idf4e7846b50f4376a5d33515681efbd773d1caca
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6146
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Change-Id: Id630cc46b79a39e1786d42adbc21f3b9c3a051aa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6118
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
|
We now use the slightly more familiar CFLAGS_* and CPPFLAGS_*
for the same purpose.
Change-Id: Ifd2bd13f67f71fa0a15611a6d11a6a4c7994271b
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5875
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Change-Id: Ie1ec8dbcdbbe0f2b05fdb10b1dca43cfee2a58cb
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6120
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Sanitize the inclusion of mc146818rtc.h in bootblock_common.h
Change-Id: I37d9ffd1375aedbf1f3eaa4ddce27e16166ce0b9
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6119
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Embedding comments inside comments is illegal in the C specification,
Clang enforces this.
Change-Id: I0a468e4196034b00dfc5860fdbbab7788e4fef77
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6154
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
We don't need exception handlers and they waste space.
Change-Id: I98a34d1c9638e8c4168edbfb4b1cddde8a64623f
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6105
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
|
CPPFLAGS is only used as qualified variant
(like CPPFLAGS_armv7) now.
Change-Id: If8b570ace4ac92d1fdb38ca3f7fef6c79d513a95
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5874
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
|
|
On SVR4-derived platforms, the character `/' is treated as a comment
character, which means that it cannot be used in expressions. The
`--divide' option turns `/' into a normal character. This seems to be
needed with our local build of binutils since we don't yet use the
internal assembler/disassembler of the Clang tooling.
Change-Id: I344fc8670fd5d994f3b63308a513dd367aefc7f9
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5813
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
The libgcc runtime workarounds found in gcc.c are not needed for
compiler-rt used by the Clang toolchain. Stop gcc.c from sneaking into
Clang builds while processing boards that use SMM code.
Change-Id: I51e8d517784721d28b4d951bd0bebc8b52682a8e
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6121
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
|
|
Continuing on from the rational given in:
a173a62 Remove guarding #includes by CONFIG_FOO combinations
Change-Id: I524713b21684f6fa99355614a1ab38aee9975790
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6091
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
|
|
This header is incompatible with ROMCC and its inclusion leads to 'odd'
build failures.
Change-Id: If31d774385796dcafe2fd48151e424b4c872aec3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6103
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
|
|
Change-Id: I76f017b0919e301eeb84e73eff21170bbc921ae2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6113
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
|
Change-Id: I5df80e6445f390060372be8760c9b5e960e4a6e5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6117
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
|
Change-Id: If1dc4fd2204a2e4b6f84c75f385b8ff958d2251d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6112
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
|
Change-Id: I22180c3c2987396717864f04c59560029d088d53
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6111
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
|
Change-Id: I92f3877b58d9acaa9578337e66107e9cd9f46043
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6110
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
|
Change-Id: I090e98fbf28595d3917ef84e19bd6d6742f11b94
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6108
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
|
Change-Id: I4d8abe3841378e06515e1b3a8f22d78425d08449
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6109
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
|
- Disable the EHCI controller and enable the XHCI controller.
SeaBIOS has been tested on the board and boots an OS from a
flashdrive at SuperSpeed.
This also enables the top USB port on the 2-port stack, which goes
through a High Speed Inter-Chip port. The HSIC port is only enabled
through the XHCI device.
Change-Id: Ic3dfc55028fa5e081a30819fe9596b1a9f57fd9c
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/6106
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: build bot (Jenkins)
|
|
Change-Id: Id19d31a2d114bb796b31ad61802d40c8608e4020
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6038
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
|
|
Change-Id: Ie4df2199e746de58c926f35bc9000752d399aa37
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6037
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
|
|
Change-Id: I1bbcba086f841a90544b827ae807a3c351d19d21
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6036
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
|
|
Change-Id: I00055064003c814b86fd1400d50bfd02fdfdf475
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6035
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Martin Roth <gaumless@gmail.com>
|
|
Like with other more recent boards already using DYNAMIC_CBMEM,
the pointer to TOC is no longer stored in GNVS for ACPI.
Change-Id: If2e11294202c40793ec985e2c0c006bbfcd03d3d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6034
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
|
|
PC80 header components are winding up in ARM builds with static inline
X86 specific code.
Change-Id: Ib23e70a34c478dc099b84b59a5234539cc2482e3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6101
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
|
|
In theory we could run out of CBMEM space so check the entry was added.
There is no interest to support builds without EARLY_CBMEM_INIT.
Change-Id: I68dd7c20e3d3692331aaafa2a692c5c0dfce95d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6033
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
|
|
The variable 'wait' is used uninitialized whenever 'if' condition is false
if (val & DDI_BUF_CTL_ENABLE) {
^~~~~~~~~~~~~~~~~~~~~~~~
Leading to an uninitialized use occurs here:
if (wait)
^~~~
Change-Id: I7d96bf1e33b9c4312d4a0ba8276e83d17d6cd070
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6052
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Change-Id: I7640186702abac6fe116e3c750be08c958bc6cad
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6092
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <gaumless@gmail.com>
|
|
There is only one bit for memory width reporting, either x16 or
other. With x32 memory this code is reporting it as x8 so instead
report "x8 or x32" in this condition.
BUG=chrome-os-partner:23449
BRANCH=samus
TEST=emerge-samus chromeos-coreboot-samus
Change-Id: I2a7c49bcb8de19084947b9dc42b93140641886fc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174120
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/6008
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
BUG=chrome-os-partner:22254
BRANCH=falco
TEST=emerge-falco chromeos-coreboot-falco
Original-Change-Id: I493a8cbbfdd958b855f6b4c01e03ee524be74c6e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/167050
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 226a66772768bf3c2f69e585984e52c0c270821f)
Change-Id: I800b02b511f9d188dd7a8e8d83139a8181346916
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/167312
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/6014
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Change-Id: Ic4905d8a6908a30602382f5846f1dc2c0dbe2431
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6068
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Comment #endif /* FOO */ pairings.
Alphabetise headers and remove any #if CONFIG_ guards around them.
Background rational:
Remove guarding the inclusion of headers based on CONFIG_ options. This
*potentially* could hide issues such as functions being swapped from
under our feet, since different runtime behaviour could be declared with
the same function same name and type-signature. Hence, depending on the
header we happen to get may change runtime behaviour.
Change-Id: Ic61bdfb64d99f0e2998c6451ae6686915b7bb3d4
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6059
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Alphabetise headers and remove any #if CONFIG_ guards around them.
Use #if IS_ENABLED(CONFIG_FOO) over #if CONFIG_FOO where applicable.
Change-Id: I2a616bcfb8470a1fa21c9e26271e81cca835272a
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6057
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Change-Id: I6254f4ab767952cc8ff31bb462c7037b027442ba
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6079
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Missing header for the ramstage version of device_t which is a struct
ptr.
Change-Id: Ie2a30b75ee1d0513397276b81e8df1d995707f6f
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6080
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
After commit
2ca2afe ACPI S3 support: Add acpi_s3_resume_allowed()
ACPISCRATCH region in CBMEM was no longer allocated, causing
AGESA platforms to fail S3 resume.
IS_ENABLED() did not evaluate true here with non-zero parameter.
Also avoid multiple defined defaults for HIGH_SCRATCH_MEMORY_SIZE.
Change-Id: Id99e4bee91581b8ac3d1ec44763b2d792b721832
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6093
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Martin Roth <gaumless@gmail.com>
|
|
These parameters are not specific to the southbridge device, but
the implementation of S3 storage defined by CPU code.
Change-Id: Ic341cc2b7669cf8e3e920c48473826ec03fc7d8d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6081
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Change-Id: I5314d76168c40a6327d4a9ac3b4f4fb05497d6fc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4525
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
This code would not get enabled just by flipping the options in menuconfig,
also ramcheck() no longer test the range like the parameters would imply.
We should add non-destructive ram_check() on S3 resume path to verify
memory controller configuration has been properly recovered.
Change-Id: Ie4675c4770146c4312cdfbc81afa19f243f90ee4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6027
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Update the elements in the MP Spec structures with
appropriate types to more accurately reflect the
real sizes of the bit fields in the MP Tables.
Also add a function for PCI I/O interrupts since these are
handled slightly differently than the other I/O interrupt
entries. The src_bus_irq field is defined where
Bits 1-0: PIRQ pin: INT_A# = 0, INT_B# = 1, INT_C# = 2, INT_D# = 3
Bits 2-6: Originating PCI Device Number
Bit 7: Reserved
Change-Id: I693407beaa0ee454f49464e43ed45d8cba3b18fc
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/6050
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
The override value in the mainboard that was removed was correct.
Change-Id: Ie820df0d6b7a713488173240f0c0ca4a9e108f71
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/6095
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
|
|
- remove the Kconfig text when setting the default for the FSP location.
The text was showing up twice in the config menu.
- Remove an extra 'the' in the help text.
Change-Id: I3777833bf32e19bbe5a8493578a9346d6ab062a4
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/6090
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
This just adds some additional comments for the EMMC / SD / SDIO PCI
devices in devicetree.
The documentation states that the EMMC 4.1 device shouldn't be used,
but it's available to enable in the FSP. Because it can be enabled,
I've included it in the devicetree even though its use is discouraged.
Change-Id: I64633fe1908368f69a8d4031aa900b0bceb2189e
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/6089
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
First of many to remove guarding the inclusion of headers based on
CONFIG_ options. This *potentially* could hide issues such as functions
being swapped from under our feet, since different runtime behaviour
could be declared with the function same name and type-signature. Hence,
depending on the header we happen to get may change runtime behaviour.
Change-Id: Ife56801c783c44e1882abef711e09b85b7f295a4
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6055
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Change test to return true on S2 wakeup too. In S2 CPU would
have been powered down so MTRR recovery is required.
Change-Id: I6ad5fb7e32c59be7d84f28461c238c3975e1e04e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6078
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Change-Id: If237c2fcd52f50d5fa0cad5a02a941386b085f2e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6077
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Change-Id: Ia6f5b0454e7fbbf36baa2372dfeec51b5f5e8f67
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6076
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Change-Id: I6f9c992f1a68025ed18de57c5856b3bf9a673bfb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6075
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Change-Id: Idc4c47f3802019c2853ec71f8e9c057c3ab8d3ee
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6074
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Change-Id: I812cc40e50a1e7e13caed48a1693feb8658b645c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6073
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Change-Id: I46906e6d68775edc5cfe199cfeb465db4da2691f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6072
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Change-Id: Icab0aeb2d5bf19b4029ca29b8a1e7564ef59a538
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6071
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Alphabetise headers and a few trivial cleanups.
Change-Id: Ib8c8362962297cb59671d8274df8e4945373f94b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6042
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
|
|
Change-Id: I08b9eef9d6b0f120c17c3293f1f90b847742dc06
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/6064
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
|
|
Pins 41-48 default to being GPIs. This switches the internal
mux to connect them to UARTD.
Change-Id: I61393b8c35cbc664f6520f60eed09ba4bbede0dc
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/5963
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Silence unused function warnings, spotted by Clang.
Change-Id: I5127893e9605ca490ff450faa92af5e9eafe8940
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6054
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
|
|
Change-Id: Iaf5db7153b08ac81b233f967c7a604ed08af91ca
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6040
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
|
|
No need for these.
Change-Id: I1df6e2ef06bd5546a66ee05a15fa2f7c3daf8853
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6039
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
|
|
Change-Id: I8ddd46a573b61eba685efcc15456f288645d214d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5936
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
|
|
Port to recent reference board (AMD Persimmon) changes in commits:
c93a75a AMD/CIMx: Add functions for AMD PCI IRQ routing
Change-Id: I307709bfee554bc64788a973da6d9313ca7c0de2
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5882
Tested-by: build bot (Jenkins)
Reviewed-by: Mike Loptien <mike.loptien@se-eng.com>
|
|
Test explicitly for S3 resume.
Also switch to use IS_ENABLED().
Change-Id: I17ea729f51f99ea8d6135f2c7a807623f1286238
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6070
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
|
|
Change-Id: I8e0d43293e095c1c76c3cfef1f426737624ea37f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6063
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
|
|
Also update packardbell/ms2290 to match lenovo/x201.
Change-Id: I6bda740cadd81ebe47e57742c507bff322a9fb0e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6062
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
|
|
Change-Id: I7811ee695f35c708144c4af5d43935deb22dd4df
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6061
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
|
|
Add this to reduce the amount of preprocessor conditionals used in the source,
compiler currently resolves this to a constant.
Once we have gone through all #if CONFIG_HAVE_ACPI_RESUME cases, we may change
the implementation to enable/disable S3 support runtime.
Change-Id: I0e2d9f81e2ab87c2376a04fab38a7c951cac7a07
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6060
Tested-by: build bot (Jenkins)
|
|
Change-Id: I6b37cf945db12d2cf8096c9f49fff9e0bec139d6
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6058
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
|
|
Spotted by Clang.
Change-Id: I3e612c0fa050a09fa7e5b1cb643935b84eb2b957
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6053
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
|
|
Change-Id: I0ecc3c5a26251f248234244bf305d3e13e41b9e9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6069
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
|
|
This is implied from DYNAMIC_CBMEM from soc/.
Change-Id: I8cd8c2dff723950377998750377a3168f1f5fc5b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6029
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Martin Roth <gaumless@gmail.com>
|
|
The default FSP location needs to be in the chipset, not the mainboard.
This was removed from the Bayley Bay mainboard in patch 41ea7230f7
reviewed at http://review.coreboot.org/#/c/5982/
Change-Id: Ia26ed34e1401cbd2303166628e7a4e357d79c874
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5985
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: build bot (Jenkins)
|
|
- Add the Bay Trail B0/B1 microcode. These versions of the SOC were
released as a "Super SKU" which had features of all the different
SKUS (M/D/T/I), and identified as a Bay Trail T as noted by the
number 2 in the third character from the left in the microcode name.
- Update the size of the microcode blob. We should be pushing a patch
to eliminate the need for this shortly.
Change-Id: I57ba51eabe9ea0609ab809f18b95e3bc9d5cb191
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5986
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
|
|
Push back any board specific values back into romstage.c #defines and
drop any remaining fragments of CONFIG_SIO_PORT in-tree.
Change-Id: Ieb63fb0c2ab1a82b53bafd86686de7b21ac226c3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6045
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
CONFIG_SIO_PORT is not used anywhere and should not be here any way.
Change-Id: I39eb2d668f1da9f89b7ff6eb219af1a48cb29232
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6044
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
CONFIG_SIO_PORT is not used anywhere and should not be here any way.
Change-Id: I2e7be4337f7f46298b9ca5bd613c58deec2cb01a
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6043
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
This existed for ChromeOS but was no longer used with DYNAMIC_CBMEM.
Change-Id: I558a7ae333e5874670206e20a147dd6598a3a5e7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6032
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
|
|
We implement get_top_of_ram() on these chipset to resolve CBMEM
location early in romstage. Call to set_top_ram() is not required.
Change-Id: I492e436b0c32d2c24677265b35afd05f29dcd0f8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6031
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
|
Needed to resolve CBMEM location early in ramstage. With DYNAMIC_CBMEM
set_top_of_ram() will no longer be available.
Change-Id: If50f1c5455a587b096348ffedadbe1dd2350a714
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6030
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
|
|
S3 resume detection not implemented in romstage.c.
Change-Id: I98277cb483825af2e6c5c8eefa4598b117613478
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6028
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
|
Clang complains about a unused debug function, so remove dead code.
We have copy of dump_smbus_registers() in amdk8/debug.c.
Change-Id: Ibf46deb1de1589d81760841b1d4ba319707915aa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5942
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
|
|
Use the value from hardware for uma_memory_base.
Change-Id: I70351166db6634ef3bca2bf12051ccc3730cab8e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5893
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
|
|
Change-Id: I2a46806a3f0a57497edebd49e69b97f90948adb9
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5117
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
|
|
With the addition of the mainboard PCI IRQ routing tables
for AMD Persimmon, the MPTables can be set to use this
information to accurately reflect the real hardware settings
of the system. Additionally, the IOAPIC gets defined before
the MPTable gets generated so the settings can be read
directly from the IOAPIC registers instead of 'guessing' at
them as was done before.
Change-Id: I96ec046a2208eddf4b5e442214ff43d2a349ca4d
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/5878
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
|
|
Virtual Wire mode is set by writing 0 to the the MPTable
Feature2 bit field 'IMCR'. The virtualwire variable was
initially defined as writing a 1 to this bit field which
would actually set PIC mode instead of Virtual Wire mode.
However, nearly every mainboard called the MPTables with
virtualwire = 0, which actually had the effect of setting
Virtual Wire mode. I am correcting the definition but
leaving the call to write the MPTables with virtualwire = 0,
which is how most mainboards are already setting the tables
up.
See the MP Spec table 4-1 for more details:
Bit 7: IMCRP. When the IMCR presence bit is
set, the IMCR is present and PIC Mode is
implemented; otherwise, Virtual Wire Mode is
implemented.
http://download.intel.com/design/archives/processors/pro/docs/24201606.pdf
Change-Id: I039d88134aabd55166c2b68aa842bacbfcc0f42b
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/5977
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
|
Adding the copyright header to the MP Spec files because
they were not included before.
Change-Id: Ifcd217a53bf8df19b28e251a7cac8b92be68d1fc
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/5981
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
|
