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2008-09-26Add IRQ12 to the dbm690t mptable for mouse interrupt support.Marc Jones
Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3603 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-24Support for the memory controller and PCIe interface of the IntelEd Swierk
EP80579 Integrated Processor (codename "Tolapai"). The memory controller code supports only 64-bit-wide DIMMs with x8 devices and ECC. It has been tested on a development board using a single Micron MT9HTF6472PY-667D2 DIMM. Your mileage will definitely vary with other DIMMs. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3600 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-23This patch adds support for watchdog kill and adds it to Asus M2V-MX SE.Rudolf Marek
Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3595 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-23The AMD dbm690t mainboard uses the it8712f SIO with theMarc Jones
default 48MHz clock input. The Asus a8n_e uses the it8712f with a 24MHz clock input. The it8712f early init code was setting a 24MHz input clock(to support the a8n_e). Since 48Mhz is the default I added a function to set 24MHz input clock to the a8n_e. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3594 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-23Attached patch removes HPET info from ACPI tables. HPET does not work fine onRudolf Marek
VT8237R (random keyboard/mouse lockups). Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Jordan Crouse <jordan.crouse@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3593 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-23Following patch adds support for Asus M2V-E SE. Works pretty well, the onlyRudolf Marek
problem left is with CPU scaling setup. No VGA - may work with the Xorg drivers recently released, maybe with OpenChrome too. It wont work with the little patch which will hop in soon Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3591 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-22Patch for AMD DBM690T board.Michael Xie
Signed-off-by: Michael Xie <Michael.Xie@amd.com> Reviewed-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3590 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-22Patch for AMD SB600 chipset.Michael Xie
Most of the functions in SB600 are enabled except power management. Signed-off-by: Michael Xie <Michael.Xie@amd.com> Reviewed-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3589 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-22Patch for AMD RS690 chipset.Michael Xie
All the PCIe slots are enabled in this patch except power management. Signed-off-by: Michael Xie <Michael.Xie@amd.com> Reviewed-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3588 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-19Attached patch fixes at least one issue ;) During the PCI BAR sizing must ↵Rudolf Marek
be the D1F0 bridge without activated I/O and MEM resources, otherwise it will hang whole PCI bus. U-boot is also disabling the IO/MEM decode when sizing the BARs, dont know why does we not. Second small change just changes a bit which controls the PSTATECTL logic. Third change deals with the integrated VGA, which needs to be enabled early, so the VGA_EN is set along the bridges, and PCI K8 resource maps are set correctly. Finally the CPU accessible framebuffer is now disabled as it is not needed. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3587 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-19Whitespace and style cleanup. (trivial)Marc Jones
Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3586 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-19Add AMD K8 S1G1 socket support.Michael Xie Michael.Xie
Signed-off-by: Michael Xie Michael.Xie@amd.com Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3585 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-18ck804 whitespace fixesMyles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3584 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-18Fix whitespace in tyan s289{1,2,5} files. Also removes some #if 0 and #if 1Myles Watson
that don't seem to clarify anything. Abuild tested. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3583 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-12For the jetway jf2/4 series of mainboards:Alex Mauer
* change the comment for device f.0 from "IDE" to "SATA" * turn on firewire device a.0 * turn on pata device f.1 * don't turn on the unusable device 10.5 (built-in vt8237 ethernet?) Signed-off-by: Alex Mauer <hawke@hawkesnest.net> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3577 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-11From Vincent Legoll:Stefan Reinauer
Use dev_path() to have nice debug output patch is run-time tested Trivial, thus: Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3572 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-10Add the "jetway j7f[24]*" mainboard. As compared to the Via Epia CN, thisAlex Mauer
changes the superio to a Fintek F71805F as described at http://www.coreboot.org/Jetway_J7F2_Build_Tutorial It also creates the mainboard tree for this series of motherboards (Jetway J7F2 and J7F4). I've tested it with one motherboard (J7F2WE1G3), and I believe it works with the others, as the differences among them are mostly trivial (processor speed, chipset and quantity of LAN cards, audio chipset, etc.). A list of the relevant motherboards with specs can be found at http://www.jetway.com.tw/jw/ipcboard_socket.asp?platid=16 The irq_tables.c is copied directly from the epia-cn, because the one generated by getpir with the factory BIOS did not work properly while the EPIA-CN one did. Minor changes on checkin to cope with moved romcc in latest revision. NOTE: This board is broken until the issue introduced in r3567 is resolved. Signed-off-by: Alex Mauer <hawke@hawkesnest.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3571 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-05This patch adds support for the VIA VT8237S south bridge. The VT8237R ↵Rudolf Marek
programming remains unchanged (tested on mine desktop) except of reverting the small change introduced by Bari (gpio/inta setup reg 0x5b). This should go for some board specific file. The change would broke at least mine board. But seems to be needed for jakllsch. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Bari Ari <bari@onelabs.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3567 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-04This changes the python generated makefilesCarl-Daniel Hailfinger
targets/*/*/Makefile targets/*/*/normal/Makefile targets/*/*/fallback/Makefile to use a common copy of romcc, and to leave this compiler untouched by 'make clean' in targets/*/*/fallback/ and targets/*/*/normal/ . 'make clean' in targets/*/*/ will clean romcc. Thanks to Mats for the initial idea and implementation of a tool to do this. This patch has almost the same behaviour as the original tool without having to run the tool each time. Tested for abuild-friendliness. The patch saves ~10-12 seconds for every target using romcc. For a full abuild run, this is ~20% time saved. For the first 38 abuild targets, total build time is down to 13m24s instead of 16m22s on my machine. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Mats Erik Andersson <mats.andersson@gisladisker.se> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3564 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-03Tidy up identifiers, per Uwe's suggestion. Trivial.Ed Swierk
Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Ed Swierk <eswierk@arastra.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3563 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-01This patch gets the Epia-CN working without ACPI or APIC.Bari Ari
All devices work, no irq storms. Enjoy. Signed-off-by: Bari Ari <bari@onelabs.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3556 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-28Add definitions for DDR2 SPD registers.Ed Swierk
Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3547 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-28Eric Biederman believes that he and Tom Zimmerman of the defunctEd Swierk
LinuxNetworx own the copyright for the Intel e7520, e7525 and 3100 raminit code. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3546 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-27If you haveWard Vandewege
option CONFIG_COMPRESSED_PAYLOAD_LZMA=1 option CONFIG_PRECOMPRESSED_PAYLOAD=1 set in Config.lb but accidentally use an uncompressed payload, coreboot (v2) bombs out like this: elfboot: Attempting to load payload. rom_stream: 0xfffc0000 - 0xfffdefff Uncompressing to RAM 0x01000000 Decoder scratchpad too small! Decoding error = 1 Unexpected Exception: 6 @ 10:04000408 - Halting Code: 0 eflags: 00010057 eax: 00000101 ebx: 04000400 ecx: 000003d4 edx: fffc0000 edi: 04000400 esi: 04000401 ebp: 04000400 esp: 0013dfb4 The attached patch modifies v2's lzma code so that it assumes an uncompressed payload if it fails to find a properly compressed payload. Compare with the fatal error above: elfboot: Attempting to load payload. rom_stream: 0xfffc0000 - 0xfffdefff Uncompressing to RAM 0x01000000 Decoder scratchpad too small! olen = 0x00000000 done. Decompression failed. Assuming payload is uncompressed... Found ELF candidate at offset 0 header_offset is 0 Try to load at offset 0x0 If you don't have CONFIG_COMPRESSED_PAYLOAD_LZMA and CONFIG_PRECOMPRESSED_PAYLOAD set and use an uncompressed payload, things are as before: elfboot: Attempting to load payload. rom_stream: 0xfffc0000 - 0xfffdefff Found ELF candidate at offset 0 header_offset is 0 Try to load at offset 0x0 One can argue that this is a case of 'builder beware', but my counter argument is that anything that causes unexpected runtime breakage is really, really, really bad, and should be avoided where possible. This patch also fixes one erroneous comment. Signed-off-by: Ward Vandewege <ward@gnu.org> Acked-by: Myles Watson <mylesgw@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3542 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-25This patch adds PCI device IDs for the Intel EP80579 Integrated Processor,Ed Swierk
and renames some existing macros for clarity. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-25This patch modifies the Intel 3100 southbridge code to recognize theEd Swierk
integrated LPC, SMBus, USB and SATA devices of the Intel EP80579 Integrated Processor. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3535 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-25This patch implements support for the CPU core of the Intel EP80579Ed Swierk
Integrated Processor. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-19Add Tyan S2912 platform with AMD Family 10 support. Arne Georg Gleditsch
Thanks Arne. Good job. Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3526 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-13Fix outb to 0x80 delay functions to use inb instead (fixes excessive post codesStefan Reinauer
in a couple of occurences) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3509 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-12License updated to GPL v2.Marc Jones
Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3504 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-08Enable both IDE ports for our qemu target.Ward Vandewege
Signed-off-by: Ward Vandewege <ward@gnu.org> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3481 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-07Clean up whitespace and comments style. (trivial)Marc Jones
Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3480 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-04Initial support for the ASI MB-5BLGP (Neoware Eon 4000s).Uwe Hermann
This works fine in Linux if you use the 'irqpoll' kernel command line option. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3469 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-03Remove welcome message from elfboot. None of the other subsystems have theirStefan Reinauer
own welcome message. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3468 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-03fix lots of warnings for cache as ram builds (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3467 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-02adapt Uncompressing.. patch for AMD code. Also replace "linxbios" by "coreboot"Stefan Reinauer
in a number of places. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3466 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-02Go back to SIPI WAIT state for those CPUS defining the newly introducedStefan Reinauer
CONFIG_AP_IN_SIPI_WAIT flag. Newer Intel CPUs need this to operate with multiple cores. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3465 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-02This patch Stefan Reinauer
* fixes a warning * puts some debug messages to spew because they're only useful to debug CAR * print an explicit message "Uncompressing..." instad of "Copying..." when coreboot_ram.rom is compressed. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3463 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01oops, forgot these in the cleanup.. (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3461 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01a heuristics is something different Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3460 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01Typo, thanks to Idwer for spotting this. (trivial patch)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3459 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01clarify in the printks what function is actually called. This little smart magicStefan Reinauer
drove me crazy during debugging. Fix Typos. Add a warning because the on-chipset devices are hardcoded. For newer machines, a lot more memory space will have special meanings, and we can't hardcode them all in an ifdef desert. (trivial) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3458 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01clean out obsoleted config.lb rules and output, fix indenting (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3457 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01use printk, when possible. (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3456 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01match against all steppings of a CPU model, because these are _model_ drivers.Stefan Reinauer
(trivial) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3455 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01serial.inc is not used anywhere. drop it (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3454 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01same spelling in all mtrr output.. (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3453 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01drop unused code (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3452 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01coding style fixes (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3451 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01fix compile warnings of rom_stream.c (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3450 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01add some SPD values from specs. (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3449 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01function prototypes don't need extern. (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3448 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01fix warning in vga console code (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3447 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01fix typo in coreboot_ram.ld comment (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3446 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01fix typo in commend of generic_sdram.c (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3445 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01clean up comment in onboard.c (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3444 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01clean up Config.lb in lib/ (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3443 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01fix warnings, make mptable struct members explicitly packed, as they'reStefan Reinauer
supposed to be. rename LXBIOS to CORE in ACPI table identifiers. (trivial) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3442 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01fix typos and warnings in the device tree code (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3441 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-23This patch fixes the kernel EBDA mislocation problem. Thank you, Yinghai.Roman Kononov
The change in tables.c protects the legacy x86 BIOS data segment (0x400-0x4ff) from being used for storing coreboot tables. Some bytes from the segment are used by the kernel and should not be garbled. The change in coreboot_table.c is not strictly necessary. It removes some redundancy and confusion. Signed-off-by: Roman Kononov <kononov@dls.net> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3437 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-23Fix r3434 check-in. Added missing end to Options.lb. Not entirely sure how itMarc Jones
went missing.... Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3436 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-23Add AMD Fam10 B3 default settings to match AMD example code.Marc Jones
Includes setting for most recent errata. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-23Update to the latest AMD Fam10 microcode patches.Marc Jones
Add platform option for patch file name. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3434 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-23Memory initialization support for AMD Fam10 B3 (B0-B2 already supported).Marc Jones
Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3433 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-21Missed a const in my previous checkin, r3426 (trivial).Marc Jones
Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3432 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-21Add support for the Winbond W83697HF Super I/O.Sean Nelson
Signed-off-by: Sean Nelson <snelson@nmt.edu> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3430 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-17Add manual HT BUID fixup to detect previously set BUIDs in early init. This ↵Marc Jones
fixes the non-coherent(sb) link running at default speed. Fix HT event notify to output useful information. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3426 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-17Clean up AMD FAM10 HT variable initialization. The structure init is ↵Marc Jones
cleaner, avoid compiler warnings, and matches the AMD example code more closely. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3425 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-17Add Fam10 Gart table walk enable for MCA reporting to match AMD example code.Marc Jones
Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3424 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-16Clean up comments, whitespace, and copyright date in the AMD HT code.Marc Jones
Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3423 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-15Add missing Intel CPU (trivial).Uwe Hermann
Tested by me on actual hardware. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3422 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-12There was a programming error which made most USB port4 setup wrong. This ↵Marc Jones
patch uses byte pointer and the MMIO read and write functions. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3421 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-29Adds a field to the serial port descriptor about the configured line speed.Patrick Georgi
Signed-Off-By: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3396 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-26Initial support for the A-Trend ATC-6240 board.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3391 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-22Enable hardware fan control for m57sli.Ronald Hoogenboom
Tested on v1 and v2 of the board. Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl> Signed-off-by: Ward Vandewege <ward@gnu.org> Acked-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-22This patch allows support for multiple so-dimms, single or double sided.Joseph Smith
Signed-off-by: Joseph Smith <joe@settoplinux.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3380 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-20Extend the VIA vt8237r southbridge decode range for the ROM to 1MB.Bari Ari
Signed-off-by: Bari Ari <bari@onelabs.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3369 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-21This is a simple patch which allows payloads to be placed in memory inMyles Watson
the range of 0xf0000-0x100000, where the Coreboot tables live in v2. As long as the payload doesn't need the tables, it seems harmless, so why not just print a warning? This allows v2 to load "legacybios" without having to have a separate loader. Signed-off-by: Myles Watson <mylesgw@gmail.com> It'll be fine for testing and doesn't really break anything that did work before... Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3343 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-20Add post-RAM init code for the Fintek F71805F Super I/O.Corey Osgood
Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Richard Stellingwerff <remenic@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3335 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-19Add support for the VIA EPIA-CN baord, which uses C7 + CN700 + VT8237R.Aaron Lwe
This also contains various improvements of the CN700 code in svn. Signed-off-by: Aaron Lwe <aaron.lwe@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3334 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-16Doesn't have to be executable (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3330 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-16Geode platforms that use a LPC Super I/O had the LPC serial IRQ set to allMarc Jones
the possible IRQs generated by the SIO. This included IRQ 7 as the default parallel port IRQ. This overlapped with the MFGPT driver setting IRQ7 for it's own use. This fix removes IRQ7 from the serial IRQ list for all the mainboards that were setting it to prevent the conflict and crash when the MFGPT driver loads. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3329 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-16New Target and initial support for the Thomson IP1000.Joseph Smith
Signed-off-by: Joseph Smith <joe@settoplinux.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3328 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-15This patch allows the RCA RM4100 to reboot. Upon rebooting in auto.c it ↵Joseph Smith
detects if the memory is already initialized, if so it issues a hard reset through the southbridge. Signed-off-by: Joseph Smith <joe@settoplinux.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3322 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-09coreboot-v2: Disable second serial port on NorwichJordan Crouse
There isn't really any good reason to have the second serial port enabled on Norwich, and this makes the X DDC code stop working. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3294 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-07Implement GPIO configuration routines for the Intel 3100 southbridge,Ed Swierk
allowing you to specify per-mainboard GPIO settings. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3290 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-06cs5536 IDE PWB flag was not getting set since it is 1<<14 and it was only ↵Marc Jones
doing a pci_write_config8. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3282 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-06This patch adds pc keyboard init function call for qemu in v2 since some ↵Aaron Lwe
payloads assume Coreboot initializes it. Coreboot v3 already does it. Signed-off-by: Aaron Lwe <aaron.lwe@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3280 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-06Fix various issues on MSI MS-7135 board.Jonathan A. Kollasch
- W83627THF is strapped to 0x4e, not 0x2e - there's no device 9 on PCI-E x1 bus, it should be device 0 - add mptable entries for AGR slot, based on info in user manual - enable floppy drive controller so that some legacy VGA ROMs will work Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3279 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-30By default, the Intel 3100 LPC interface enables only I/O range 0x3f8Ed Swierk
for both serial ports, making it challenging to use COM2 for the early console. Enable the traditional I/O ranges 0x3f8 for COM1 and 0x2f8 for COM2. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3276 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-25Remove inline from FAM10 CPU initialization functions.Marc Jones
This doesn't save any space for me but it is the right thing to allow GCC to optimize. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-25Fix so pci device memory allocation does not use memory base address at ↵Aaron Lwe
0xfec00000, this is reserved for APIC. Signed-off-by: Aaron Lwe <aaron.lwe@gmail.com> Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3265 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-24Add CPUID processor name string support for Fam10 CPUs.Marc Jones
Peter did a nice job cleaning up my initial patch. Thanks! Signed-off-by: Marc Jones <marc.jones@amd.com> Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3263 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-24On APs the ClLinesToNbDis was being left enabled from CAR setup.Marc Jones
Disabling it should help performance. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3262 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-24This board (http://www.ieiworld.com/en/product_IPC.asp?model=PCISA-LX)Nikolay Petukhov
is based on amd-lx800/cs5536. Tutorial: http://www.coreboot.org/IEI_LX_800_Build_Tutorial Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3261 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-23This is the sata irq patch for s2895 and ultra40. It also changes some brokenMyles Watson
white space in the s2892 and s2891 mptable.c files. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3256 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-23Fix irqs for secondary ports on both sata controllers.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3255 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-23This patch fixes the 3 broken sata ports on the Tyan s2891 (primary port onWard Vandewege
secondary controller was ok). There were two problems: the master sata controller was not being initialized, and the irqs for the secondary ports on both controllers were not being set in the mptable. Thanks for Jonathan Kollasch for all the help figuring out the IRQ problem. While all ports work reliably under a recent kernel (2.6.24), sata is about half as fast as under the proprietary bios, according to bonnie++. That still needs fixing... Signed-off-by: Ward Vandewege <ward@gnu.org> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3253 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-22Clean up and remove late initialization code that is no longer needed.Marc Jones
Pstate intialization has moved to early init because it requires a warm reset. Add CPUID setup and disable SMM access to late initialization. Much of this code is leftover from porting from K8. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3252 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-22Find matching settings for each CPUs FID, VID, and P-state registers and ↵Marc Jones
initialize them. Supports single and split plane systems. Set P0 on all cores for best performance. All APs will be in hlt(C1). The platform warm rest logic has been updated to alway reset for HT and FID/VID setup. It is not optional anymore. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3251 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-23 02:44:13 +0000