summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2019-04-02mb/google/hatch: Change GPIO_E1 settingJohn Su
For HW require to change GPIO_E1. Change GOIO_E1 setting from NF2(SATAGP1) to NF1(SATAPCIE1). BUG=b:123730924 TEST=flash BIOS and make sure hatch boots up properly Change-Id: I0f5569e13b17a2dc713be5031a63436e8f31f911 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32099 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-02mb/google/hatch: Re-configure GPP_A12 as GPO before entering sleepKrishna Prasad Bhat
GPP_A12 has a Native3 (SX_EXIT_HOLDOFF#) mode, which allows to delay resuming to S0. If this pad is not locked and platform was not initially designed for this functionality, malware could reconfigure this pads setting under OS (switch to Native3), which would make platform not able to resume until G3 is applied. To prevent misuse of this pad, re-configure this pad before entering S3 and S5 to guarantee that the pad configuration is correct. BUG=b:128686027 Change-Id: I1e7979baa491acf2c56d223afb4618f0f6429e37 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-02drivers/intel/fsp2_0: Use same stack with corebootSubrata Banik
This patch ensures to have same stack base for FSP and coreboot. Feature added in FSP2.1 - Remove stack swapping from FSP. - Stack will be shared between coreboot and FSP. TEST=Build and boot FSP2.1 enable platform like dragonegg, iclrvp. No car global variable corruption seen after enabling this feature. Change-Id: I673b4216d991d8ccad725c3931006a694184106c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32079 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-01mb/aopen/dxplplusu: Remove redundant use of ACPI offset operatorElyes HAOUAS
Change-Id: I790303a1fab64dbbe749563325394b9be2c109ad Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-04-01assert: Make dead_code() work at link-time instead of compile-timeJulius Werner
The dead_code() macro can be used to ensure that a certain code path is compile-time eliminated (e.g. if you want to make sure it's never executed for certain Kconfig combinations). Unfortunately, the current implementation via __attribute__((error)) hits only at the GCC level. This can catch code that can be compile-time eliminated based on state within the same file, but it cannot be used in cases where a certain library function is built but then garbage collected at link time. This patch improves the macro by relying solely on the linker finding an undefined reference. Unfortunately this makes the error message a little less expressive (can no longer pass a custom string), but it is still readable and one can add code comments next to the assertion to elaborate further if necessary Change-Id: I63399dc484e2150d8c027bc0256d9285e471f7cc Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32113 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-01vboot: Select CONFIG_VBOOT_OPROM_MATTERS in more casesJulius Werner
This patch enables CONFIG_VBOOT_OPROM_MATTERS in a few more cases where I think(?) it should be. Haswell, Broadwell and Baytrail Chromebooks have this enabled in their old depthcharge firmware branches -- we presumably just forgot to move it over when vboot2 migrated the option to coreboot. Braswell didn't, but it seems like this requirement was added when it was migrated to FSP 1.1...? (Not very sure about that one, but it does call load_vbt() right now which executes things based on display_init_required().) Additionally, it seems to make sense to enable it whenever the user explicitly selects VGA_ROM_RUN in menuconfig (like one of the Intel defconfigs does). Once we have all this, one could take a step back and ask whether this option still makes sense at all anymore. It's enabled for almost all devices (that work with vboot at all), it will presumably be enabled for all future devices, and it seems that most devices that don't enable it use libgfxinit, which as far as I can tell isn't gated on display_init_required() but probably should be. Realistically, whatever kind of display init a board needs to do (native or option ROM), it's probably expensive enough that it's worth skipping on a normal mode vboot boot, and we'd want to have this enabled by default on everything except boards that actually don't have a display. So maybe we should flip it around to CONFIG_VBOOT_OPROM_DOESNT_MATTER, but doing that would probably lead to nobody ever selecting it at all. Not sure what the best solution there is yet, but I think this patch at least moves things in the more correct direction. Change-Id: Id96a88296ddb9cfbb58ea67d93e1638d95570e2c Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-01mb/google/sarien: Enable Bluetooth RF killLijian Zhao
Add bluetooth Rfkill function to recover the Bluetooth controller in cases where itself has entered a bad state and needs to be recovered. Bug=b:129375810 TEST=Boot up into OS and dump SSDT table, check there's _DSD entry under Bluetooth devices with GPIO in. Also confirm bluetooth itself is functional. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I79a310a55d94d7d20d1705afc11fe47cbb81abc1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-04-01cpu/ti/am335x: Fix checkpatch warningsDaniel Lim Wee Soong
Replace occurences of 'unsigned' with 'unsigned int' to fix WARNING: Prefer 'unsigned int' to bare use of 'unsigned' Signed-off-by: Daniel Lim Wee Soong <weesoong.lim@gmail.com> Change-Id: I94665e8fcb4719521d143774aa84f630b10ee68a Reviewed-on: https://review.coreboot.org/c/coreboot/+/32119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2019-04-01mb/google/hatch: Unlock GPIO padsKrishna Prasad Bhat
GPP_A12 is being used as FPMCU_RST in hatch. This GPIO is being padlocked in FSP and cannot used in kernel. Hence unlock the GPIO pads to export this pin in kernel to be used as FPMCU_RST. BUG=b:128686027 BRANCH=None TEST=Read Pad Configuration Lock (PADCFGLOCK_GPP_A_0) register. localhost /sys/class/gpio # iotools mmio_read32 0xfd6e0080 0x00000000 localhost /sys/class/gpio # echo 212 > export Change-Id: Ie0439956e6c8e386435e535665ccaf2ab82adeb0 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32126 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-01soc/intel/cannonlake: Add FSP UPD to unlock GPIO pads in devicetreeKrishna Prasad Bhat
FSP has a UPD to unlock all GPIO pads. This parameter is disabled by default. Add a chip parameter so that GPIO pads can be unlocked on mainboard level in devicetree and therefore this feature can be used if needed. BUG=b:128686027 Change-Id: Iad9e8a209dc3f8ca0c994e8c1da329918409a1d4 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-31mainboard/asus/p8h61-m_pro : Support TPM moduleSimon Newton
Select support in Kconfig and configure device in devicetree Tested with ASUS addon TPM modules, v1.2 (ASUS TPM-L FW3.19 rev1.02H) and v2.0 (ASUS TPM-L R2.0 rev1.00) using SeaBIOS and Linux OS Change-Id: Icdad9a41b61221b536f2ac695f44319f6b0599e7 Signed-off-by: Simon Newton <simon.newton@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-03-29src: Use include <reset.h> when appropriateElyes HAOUAS
Change-Id: I3b852cae4ef84d257bf1e5486447583bdd16b441 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-29arch/x86/smbios(type4): Write processor_upgrade fieldElyes HAOUAS
Change-Id: I1bf5ac6c411720d349df8fd706015c6835758cd0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29529 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-29soc/intel/cannonlake: Ignore GBE LTRLijian Zhao
Ignore integrated GBE controller LTR setting to make it wake up from s0ix with 10/100M cable attached. BUG=b:122435844 TEST= Test on sarien platorm, after the changes sytem can wake by WOL, and also checked SLP_S0 residency can increase with 10/100M cable and battery connected. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Iec7dd197b8a456751f8e4dcb19e3e153f5888613 Reviewed-on: https://review.coreboot.org/c/coreboot/+/31888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-03-29mb/google/arcada: Make bluetooth reset_gpio active lowMike Hsieh
Follow b:129375810 to set bluetooth reset_gpio as ACPI_GPIO_OUTPUT_ACTIVE_LOW BUG=b:129375810 TEST=Verified BT function on Arcada DVT1 system. Signed-off-by: Mike Hsieh <mike_hsieh@wistron.corp-partner.google.com> Change-Id: I816eb2a76f642a2bb1702f38138bce7916334011 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-03-29mb/google/arcada: Make touchscreen IRQ level triggeredMike Hsieh
Touchscreen lost function after boot with stylus touching the screen BUG=b:128554235 Signed-off-by: Mike Hsieh <mike_hsieh@wistron.corp-partner.google.com> Change-Id: I692fc6f245b7fade67862da4986a83d11a2cd51f Reviewed-on: https://review.coreboot.org/c/coreboot/+/32100 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-29mb/google/hatch: Deassert EN_PP3300_WWAN during sleepMaulik V Vaghela
Deassert EN_PP3300_WWAN to turn the WWAN module completely off when entering S5. This is the same fix in commit eeb475c5c for coral board. BUG=none BRANCH=none TEST=On hatch, Perform a quick system power cycle, verify that the modem is powered cycle and the SIM with PIN lock enabled requests unlocking. Change-Id: I3ec8ccb7618189b9e8586f5571a68d3309597ee7 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-29lib/edid.c: Add missing break statementJacob Garber
This was flagged as CID 1229647 (MISSING_BREAK). It was originally fixed in e211bd9, but then reverted in 1c8ee21. Hopefully fix it for good now. Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: Ib25b07b633ed02c466391050df15eaf9c36a3199 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-03-29lib/edid.c: Log an error if unable to find edid or headerJacob Garber
Failure to find an edid or header is more serious than the spew log level and should be an error. Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I660218f8b5f5e7f0b01daef0739db79418941515 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32084 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-29soc/intel/icelake: Fix chipset_power_state structureSubrata Banik
This patch ports CB:30717 changes from CNL to ICL. This structure is declared as a static CAR_GLOBAL in the common PMC library code and in the SOC specific code. Remove the SOC specific version and instead get the chipset_power_state pointer from the PMC library. This fixes events that were recorded in chipset_power_state at boot but were reading as all zero when it was time to parse the structure when logging events to flash. Change-Id: I1152d0e882e1acf475072d1553b74f9161e2f485 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32095 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-28ec/google/wilco: Add ACPI _BIX method for batteryDuncan Laurie
I added a method to fill out the _BIX package structure but never hooked it up to the expected _BIX method that the OS uses. This change adds _BIX method and uses the existing method to fill it out. It also adds ^ before the _UID in _BIF to match _BIX as the _UID is one level above the method. Change-Id: I0de91369b6780fd9432990732c1078a73f6a3419 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-03-28mb/google/sarien: Call EC romstage init functionDuncan Laurie
When in romstage call into the EC init function so it can send a progress code to the EC before memory training starts. BUG=b:127875364 TEST=boot with FSP debug and ensure EC does not try to turn off the system while it is still booting. Change-Id: I5d99fb16bae250a82b652c530c13977e74c3378b Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-03-28ec/google/wilco: Add a romstage init function to send progress codeDuncan Laurie
When using FSP with debug enabled it takes too long to get to ramstage and send the first progress code to the EC. The same thing has been reported to happen when 2x16GB memory is installed. BUG=b:127875364 TEST=boot with FSP debug and ensure EC does not try to turn off the system while it is still booting. Change-Id: I5676354f5e53540273a9029411507f91864735a1 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-03-28drivers/intel/wifi: Add support for Harrison Peak (HrP) 9560 moduleSubrata Banik
Add HrP 9560 module device ID (0x06F0) into device/pci_ids.h file. TEST=HrP module is getting detected during PCI enumeration on CMLRVP Change-Id: I8f6d89b1c6d03e2497f6b345a520323f45247d7e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32096 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-28Mistral: Enable USB in romstageNitheesh Sekar
Enable USB support for mistral in romstage. TEST=build & run Change-Id: I5c2bbe16aa3601e014a2b77d192565402ed23794 Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-28qcs405: Add support for USB host modeVijayavardhan Vennapusa
Add required changes for USB host mode for USB disk enumeration. TEST=build & run Change-Id: I35ec549b49b9789389c80843f6103e7243d52aac Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Signed-off-by: Vijayavardhan Vennapusa <vvreddy@partner-android.googlesource.com> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-28chromeos: remove remaining dev switch referencesJoel Kitching
As part of chromium:942901, physical dev switch functionality is being deprecated. Remove remaining references as well as helper macros. BUG=chromium:942901 TEST=Build locally TEST=make clean && make test-abuild BRANCH=none Change-Id: Ib4eec083eb76d41b47685701f9394c684ddc6b37 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-03-28soc/intel/apollolake: Add support to log XHCI wake eventsKarthikeyan Ramasubramanian
Add support to identify and log the XHCI wake events for apollolake into event logs. BUG=b:123429132 BRANCH=None TEST=Ensure that the system boots to ChromeOS. Ensure that the wake up events due to USB are logged into the event logs. 6 | 2019-03-21 09:22:18 | S0ix Enter 7 | 2019-03-21 09:22:22 | S0ix Exit 8 | 2019-03-21 09:22:22 | Wake Source | PME - XHCI (USB 2.0 port) | 9 9 | 2019-03-21 09:22:22 | Wake Source | GPE # | 13 10 | 2019-03-21 09:23:20 | ACPI Enter | S3 11 | 2019-03-21 09:23:30 | Wake Source | PME - XHCI (USB 2.0 port) | 9 12 | 2019-03-21 09:23:30 | ACPI Wake | S3 13 | 2019-03-21 09:23:30 | Wake Source | GPE # | 13 Change-Id: I55b850646dda8acaa086a9012c2d8b611016f932 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32000 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-28soc/intel/common: Move support to log XHCI wake eventsKarthikeyan Ramasubramanian
The policy to identify and log the XHCI wake events is similar between skylake and apollolake. Hence move the similar parts to a common location. BUG=b:123429132 BRANCH=None TEST=Ensure that the system boots to ChromeOS. Ensure that the wake up events due to USB are logged into the event logs. 6 | 2019-03-21 09:22:18 | S0ix Enter 7 | 2019-03-21 09:22:22 | S0ix Exit 8 | 2019-03-21 09:22:22 | Wake Source | PME - XHCI (USB 2.0 port) | 9 9 | 2019-03-21 09:22:22 | Wake Source | GPE # | 13 10 | 2019-03-21 09:23:20 | ACPI Enter | S3 11 | 2019-03-21 09:23:30 | Wake Source | PME - XHCI (USB 2.0 port) | 9 12 | 2019-03-21 09:23:30 | ACPI Wake | S3 13 | 2019-03-21 09:23:30 | Wake Source | GPE # | 13 Change-Id: Ia6643342e3292984e422ff3c3fcd4bc0d99f947e Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-28mb/google/hatch/variants: Add DPTF based Fan controlSumeet Pawnikar
This adds DPTF based Fan speed control for CML based Hatch system. BUG=None BRANCH=None TEST=Built and tested fan speed with different temperatures Change-Id: I3c2a679dc67eecb17098ce0f0c9703c679473a2d Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-28google/oak: Delete rowanEvan Green
Rowan board is dead, dissect it out of Oak. Signed-off-by: Evan Green <evgreen@chromium.org> BUG=chromium:840888 BRANCH=none TEST=emerge-oak coreboot chromeos-bootimage CQ-DEPEND=CL:1538915,CL:*1087044 Change-Id: Ifb19fa0cd814853270847bc14fc21c841d905146 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32061 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-28mb/google/hatch: Initialize FPMCU_PCH_BOOT1Shelley Chen
In the latest hatch schematics, BOOT1 for the FP MCU is now connected to the AP. Configuring it to be the same as BOOT0. BUG=b:126455006 BRANCH=None TEST=./util/abuild/abuild -p none -t google/hatch -x -a -c max Change-Id: Ibb451983674a7d812dc562cb8addb1dc50fb155c Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-28soc/intel/cannonlake: Update CPU Ratio base on MSRLijian Zhao
The following is the FSP logic: as long as the Cpu Ratio input in coreboot is different with CpuStrapSet, system will force to follow input from coreboot. But CpuStrapsetting is floating, it will be 0 from the first cold boot before memory training and set to 0x1c (or max CPU ratio for the installed CPU) after first memory training. The previous fix was attempting to ensure settings were cleared when FSP was called in recovery mode, but only when coming from S5 which caused issues if recovery mode is requested by the OS and is only followed by a warm reset. BUG=b:129412691 TEST=Boot up sarien platform and force recovery, check there's no reset in the path of recovery. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I959188be46343bc6f2cb3cc149097b4d449802aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/32089 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-27mb/mainboard/google/hatch/variants: Set tcc_offset valueSumeet Pawnikar
Set tcc_offset value to 10C. It configures the Thermal Control Circuit (TCC) activation value to 90C. This prevents any abrupt thermal shutdown by taking early thermal throttling action when CPU temperature goes above 90C. Change-Id: Ifee0fcc326530622b04e60af0f3b9cb9e3aea7ea Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31984 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-27soc/intel/cannonlake: Configure voltage margining policiesKrzysztof Sywula
For systems that integrate GbE controllers, following parameters should be configured: SlpS0WithGbeSupport: enable PchPmSlpS0VmRuntimeControl: disable, PchPmSlpS0Vm070VSupport: disable, PchPmSlpS0Vm075VSupport: disable. TEST=boot on any GbE supported WHL platform Change-Id: I02aaf0b77b8fc1555a3a424c02acfada21707d0e Signed-off-by: Krzysztof Sywula <krzysztof.m.sywula@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-03-27drivers/intel/gma: Move gfxinit into sub packageNico Huber
Move the actual graphics init provided by libgfxinit into a sub package `GMA.GFX_Init`. This way it can be compiled in individually. Change-Id: Ib413a0d70c8dc305f4476c1d5aee6b81ff880bec Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31456 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-27drivers/intel/gma: Make libgfxinit available w/o gfxinitNico Huber
We might want to make use of libgfxinit functions without using it for actual graphics init. Change-Id: I29c3b19989acb678d0d447e83d38bad9d584caa9 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31455 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-27Revert "src/arch: An upgrade of SMBIOS to latest version 3.2"Nico Huber
This reverts commit b7daf7e8fa18de7bfb3cd102791bc6af89bac4b6. The review was spread across four different change-ids. Of course, not all comments were addressed, now coverity complains too. Change-Id: If5dbc1ae37120330ab192fb15eb4984afc84a7af Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-27lib/edid.c: Dump EDID breakdown after null checkJacob Garber
The edid variable was being dereferenced before the null check. Split off the null check to before dumping and update the error message. Fixes CID 1370576 (REVERSE_INULL) Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I8fe3d911df3a11a873056d3a5c05c5a3cbcfe2c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-03-27mb/google/poppy/variants/rammus: Support new onboard Micron memoryKane Chen
Add micron_dimm_MT52L256M32D1PF-107 for new onboard memory support. BUG=none BRANCH=firmware-rammus-11275.B TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure system boots up. Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Iaec4147a64313dcd461affb492805c0453e8703d Reviewed-on: https://review.coreboot.org/c/coreboot/+/32046 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-27Move calls to quick_ram_check() before CBMEM initKyösti Mälkki
After raminit completes, do a read-modify-write test just below CBMEM top address. If test fails, die(). Change-Id: I33d4153a5ce0908b8889517394afb46f1ca28f92 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-03-27mb/google/hatch: Add GPIO_A8 for Pen detect functionDtrain Hsu
Add GPIO_A8 for pen detect function. BUG=b:122765828 TEST=flash BIOS and using switch to verify GPIO_A8 value change. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ie7c888ea61dd61e60c1d184565bd95e6b03777be Reviewed-on: https://review.coreboot.org/c/coreboot/+/31815 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-27mb/google/octopus/variants: Remove bipEvan Green
Remove bip, as it is no longer actively developed, and its EC overflowed storage, so the EC build is no longer viable. BUG=b:129283539 BRANCH=none TEST=emerge-octopus coreboot chromeos-bootimage CQ-DEPEND=CL:1538819,CL:*1086038 Signed-off-by: Evan Green <evgreen@chromium.org> Change-Id: Ie9ffa704af3523908858d382e2c188422323550e Reviewed-on: https://review.coreboot.org/c/coreboot/+/32053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-27chromeos: update old boards to use lb_add_gpios notationJoel Kitching
Instead of manually filling out the lb_gpios struct, use the newer lb_add_gpios notation, which is more compact and less error-prone. BUG=b:124141368 TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x BRANCH=none Change-Id: I90795f32be5de881c94519933f36127098c184df Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32031 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-27vboot_handoff: do not set VBSD_HONOR_VIRT_DEV_SWITCHJoel Kitching
As part of chromium:942901, physical dev switch functionality is being deprecated. This flag is no longer read after CL:1526070, and thus does not need to be set here. coreboot's vboot subrepository needs to be updated to include CL:1526070 before this CL can be merged. BUG=b:124141368, b:124192753, chromium:942901 TEST=Build and deploy to eve TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=make clean && make test-abuild CQ-DEPEND=CL:1526070 BRANCH=none Change-Id: Ie5849f9e0fcb8e4e6d35d542a141bf635e751af4 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31952 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-27vboot: deprecate physical dev switchJoel Kitching
Currently only two devices make use of physical dev switch: stumpy, lumpy Deprecate this switch. If these devices are flashed to ToT, they may still make use of virtual dev switch, activated via recovery screen. BUG=b:124141368, b:124192753, chromium:942901 TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x TEST=make clean && make test-abuild BRANCH=none Change-Id: I87ec0db6148c1727b95475d94e3e3f6e7ec83193 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31943 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-27device/pciexp_device: Convert LTR non-snoop/snoop value into common macroSubrata Banik
Change-Id: I3d14a40b4ed0dcc216dcac883e33749b7808f00d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-03-26qcs405: clock: Adding the clock support for qcs405Pranav Agrawal
Add basic clock support and enable UART, SPI clocks. Change-Id: I991bdde5f69e1c0f6ec5d6961275a1c077bc5bae Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Signed-off-by: Pranav Agrawal <pranava@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-26qcs405: Add GPIO APINitheesh Sekar
Introduce new and required GPIO APIs, using common pinmux definitions for GPIO configuration. TEST=build & run Change-Id: I85ce9007c545b44371c4704a0456774d0eff12a8 Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-26vboot: remove VBOOT_EC_SOFTWARE_SYNC Kconfig optionJoel Kitching
This option is duplicated in depthcharge: https://crrev.com/c/1524811 BUG=b:124141368, b:124192753, b:128737909 TEST=Build and deploy to eve TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x TEST=make clean && make test-abuild CQ-DEPEND=CL:1524811 BRANCH=none Change-Id: Id8c207ec4ad5a476e24eee1ceb9e40f24d55e725 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31926 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-25vboot: remove VBOOT_EC_SLOW_UPDATE Kconfig optionJoel Kitching
This option has been relocated to depthcharge: https://crrev.com/c/1524806 BUG=b:124141368, b:124192753 TEST=Build and deploy to eve TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x TEST=make clean && make test-abuild CQ-DEPEND=CL:1524806 BRANCH=none Change-Id: Ib4a83af2ba143577a064fc0d72c9bc318db56adc Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31909 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-25soc/apollolake: Add UART0Felix Singer
In my case, on UPsquared board with Celeron N3350 CPU, I don't have UART2 but UART0. Change-Id: Id9a742144eba0f1d1544aafecf44d4730d055b4a Signed-off-by: Felix Singer <felix.singer@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-25Fix up remaining boolean uses of CONFIG_XXX to CONFIG(XXX)Julius Werner
This patch cleans up remaining uses of raw boolean Kconfig values I could find by wrapping them with CONFIG(). The remaining naked config value warnings in the code should all be false positives now (although the process was semi-manual and involved some eyeballing so I may have missed a few). Change-Id: Ifa0573a535addc3354a74e944c0920befb0666be Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-25soc/intel/cannonlake: Clear PMCON status bitsKrishna Prasad Bhat
The prev_sleep_state value was showing 5 even after warm reboot, once the SUS_PWR_FLR bit is being set. This bit was not being cleared. Hence clearing the PMCON status bits. BUG=b:128482282 BRANCH=None TEST=In cbmem logs, check for value of “prev_sleep_state” using command cbmem –c | grep “prev_sleep_state” For cold reboot, "prev_sleep_state 5" For warm reboot, "prev_sleep_state 0" Change-Id: If9863d52ed3c61b6a160df53f023b0787eaaed68 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2019-03-25mb/asus/{p5qc,p5q_pro}: Correct mapping of PCI-E 1x portsBill XIE
There are 3 PCI-E 1x ports on p5q_pro and p5qc, which correspond to the first three functions of 1c. Confirmed on a p5q_pro board. Change-Id: I779400494e27bf046996512d1f772311e6e4e091 Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-03-25gale: add dev switch back as physical presence GPIOJoel Kitching
gale has a button which is essentially used as a "physical presence" button. Its only use is to emulate ^D or ^U on boot when the button is pressed. (See depthcharge src/board/gale/board.c) Previously (and currently in CrOS firmware branch) this GPIO was defined as the physical developer switch, and read as such in depthcharge. It was removed in cleanup patch CB:18980. Add the GPIO back as physical presence ("presence"), which will be read by depthcharge in CL:1532492. BUG=b:124141368, b:124192753, chromium:942901 TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x TEST=make clean && make test-abuild BRANCH=none Change-Id: Ic144f839b7f9933d573db8f84c4bf5905eea96f6 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-03-25mainboard/google/sarien: skip tpm check when !verstageJett Rink
The TPM driver isn't loaded in other stages but verstage so when we try to communicate with the TPM it fails. We don't need to communicate with it anyway since the TPM won't continue to tell us that recovery was requested, only the first query responds with the recovery request. BRANCH=none BUG=b:129150074,b:123360379 TEST=1)boot arcada without recovery and notice that the "tpm transaction failed" log lines are no longer present. 2) boot into recovery using the ESC refresh power key combination and verify that the recovery reason was "recovery button pressed" Change-Id: I13284483d069ed50b0d16b36d0120d006485f7f4 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-03-25vendorcode/cavium/bdk/libdram: Add missing commaJacob Garber
Fixes Coverity CID 1393957 (Missing Comma) Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I63ee47f870081bcf081bcf6dcec764e830b4ab75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-03-25sb/intel/{i82801g/i/j,bd82x6x}: Make use of generic set_subsystem()Kyösti Mälkki
Change-Id: Ia7a3eb2e29eb245c0e70abc23c2139aebc07cbfe Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-03-24intel/apollolake: Add HDA to disable_dev functionNico Huber
Change-Id: Id4f5e1fad935645830782ba922f55f614c72cf06 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31353 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-24nb/intel/i945: Use DEBUG_RAM_SETUPKyösti Mälkki
Avoid preprocessor here, also we never set loglevel to value of >8 so the call would not be made. The calls to ram_check() were removed, for a long time that function has not tested start..stop region. Change-Id: Ib952b8905c29a5c5c289027071eb6ff59aaa330b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-03-24soc/intel/common: Remove common chip config use_fsp_mp_initSubrata Banik
This patch ensures to make use of common MP Init Kconfig to choose desire method to peform MP initialization for platform. Change-Id: I4ee51276026748e8daf154f89e57095e8fe50280 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-24soc/intel/common: Add Kconfig option to choose desired MP Init for platformSubrata Banik
mainboard users can select correct MP Init Kconfig in order to perform MP initialization. 1. Native coreboot MP Init. 2. FSP to do MP Init. 3. FSP to make use of coreboot MP service PPI to perform MP Initialization Change-Id: Ifbea463fdaf97d68c21a759c37f49492d58a056b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-23console/qemu_debugcon: Support additional stagesPatrick Rudolph
Add support for bootblock and postcar, which were introduced on qemu in the last few month. Fixes non-working debugcon in those stages. Change-Id: I553f12c2105237d81ae3f492ec85b17434d8334c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31833 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-22soc/intel/broadwell: Fix use of CONFIG_USBDEBUGKyösti Mälkki
Change-Id: I52c852fb449de5a6512aa2556592e6dfe7b0c573 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-03-22src/arch: An upgrade of SMBIOS to latest version 3.2Francois Toguo
This is the second of 2 patches upgrading the SMBIOS interface to the latest 3.2 First patch is in mosys. Newer required fields are added to various types definitions BUG=NONE TEST=Boot to OS on GLK Sparky Change-Id: Iab98e063874c9738e48a387cd91341d266391156 Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-03-22mb/google/poppy/variants/atlas: DPTF tuning v2Puthikorn Voravootivat
We have more test data now so update the DPTF accordingly. * Change passive temp to 50/57/55/52 C * Change critical temp to 75C * All interval to 20 secs BUG=b:113101335 TEST=temp/perf looks better in thermal chamber test. Change-Id: I872c3f1875d0cbac148c44c449954e6871c9d0b0 Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-22soc/intel/cannonlake: Enable power button smi in pre-OSKrzysztof Sywula
This change enables user to shutdown the system by shortly pressing power button (<10sec) before OS is loaded. Main use case is shutdown from recovery/broken screen. BUG=N/A TEST=Boot up into recovery screen on Sarien platform, press power button once, and system should shutdown immediatelly. Change-Id: I7655daf65ff058df7d9bad4567f74b4f4007acb4 Signed-off-by: Krzysztof Sywula <krzysztof.m.sywula@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-22mb/google/hatch: Enable FP MCUShelley Chen
AP communicates with FP MCU through gspi1. BUG=b:126455006 BRANCH=None TEST=ensure during bootup we see spi id spi-PRP0001:01 in dmesg FP MCU fw is not ready yet, so not much testing to be done yet. Signed-off-by: Shelley Chen <shchen@google.com> Change-Id: I2eba205d5e63664dca684fbd849454c5a2fe0d0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/32017 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-22mb/google/hatch: Add overridetree to hatch variantShelley Chen
Add serialio settings to hatch. Only applies to CML. BUG=b:128347800 BRANCH=None TEST=abuild Change-Id: I6a9ec778d74cd48a2e1c79f8e669a9a6a6a9477d Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32003 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-22mb/google/octopus: Add keyboard backlight support for bloogTony Huang
Bloog supports keyboard backlight feature, so enable the ASL code. BUG=b:127736039 BRANCH=octopus TEST=Build and boot bloog, verify that the string 'KBLT' is in the DSDT. Change-Id: Iba66aade090816ea2376cae4baf4aae019cc97f4 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-03-22soc/intel/{baytrail,braswell}: Make use of generic set_subsystem()Kyösti Mälkki
We missed some PCIe root ports with previous cleanup. Change-Id: I8bf8f8b2ca1836316f84fb7f01820a00d7194d51 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-22sb/{amd,broadcom,nvidia}: Make use of generic set_subsystem()Kyösti Mälkki
Change-Id: I99b87004ea74a1ad0ec1d6e0c500df11dae4997c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-22sb/amd8111: Drop unused codeKyösti Mälkki
Change-Id: I2b1f46865aa380c2a31e05e55418b27296c72136 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-22sb/broadcom/bcm5785: Consolidate PCI set_subsystem()Kyösti Mälkki
This one uses vendor-specific register for the write. Change-Id: Ie36a87314054d00daed6a63b495bd5f5eabef66e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-03-22lib/ramtest.c: Make it a bit more arch-agnosticKyösti Mälkki
Change-Id: I05734515c0bbd043d489c76cf9cf8b2dbe0ff515 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-22arch/mips: Fix <arch/mmio.h> prototypesKyösti Mälkki
These signatures need to be consistent across different architectures. Change-Id: Ide8502ee8cda8995828c77fe1674d8ba6f3aa15f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-03-22mb/google/hatch: Add SX9310 SAR0 sensorEvan Green
Add SAR0, which is an SX9310. The schematics and layout have a second SAR1 sensor provisioned on I2C4, with an interrupt of GPP_A6, but this is not populated. Signed-off-by: Evan Green <evgreen@chromium.org> BUG=b:128540461 BRANCH=none TEST=Boot kernel with sx9310 driver, see it come up happily Change-Id: I63943cc7da5ff56f6ef6dcbd99bb8f8f031e8bf7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/31998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Enrico Granata <egranata@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-22mb/google/hatch: Enable HUNG_TASK wake interruptEvan Green
Enable the HUNG_TASK as a wakeup host event, as it's used by S0ix failure detection to wake the system back up if a suspend to S0ix never asserted S0_SLP#. BUG=b:123716513 BRANCH=None TEST=Test S0ix on Hatch with appropriate EC and kernel changes. Signed-off-by: Evan Green <evgreen@chromium.org> Change-Id: I447211892df210af97e8df0380bab032b14cbee8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32004 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-21grunt: Mark RW_LEGACY as CBFSMathew King
Depthcharge is changing how the RW_LEGACY CBFS is handled for alternate bootloaders, see https://crrev.com/c/1528550 and https://crrev.com/c/1530303. This means that RW_LEGACY must be marked as CBFS in the fmap in order to work. All boards except for kahlee(grunt) have CBFS marked. BUG=b:128703316 TEST=Build and ran on grunt along with chromium patches on grunt and was able to list alternate bootloader with ctrl+l BRANCH=none Change-Id: I843d565a9503d27e666a34e59aba263ec490c81f Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32019 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-21vboot: remove VBOOT_EC_EFS Kconfig optionJoel Kitching
This option has been relocated to depthcharge: https://crrev.com/c/1523248 BUG=b:124141368, b:124192753, chromium:943511 TEST=Build and deploy to eve TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x TEST=make clean && make test-abuild CQ-DEPEND=CL:1523248, CL:1525647 BRANCH=none Change-Id: I8b3740c8301f9a193f4fce2c6492d9382730faa1 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31897 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-21vboot: standardize on working data sizeJoel Kitching
Previously, the size of memory made for vboot_working_data through the macro VBOOT2_WORK was always specified in each individual memlayout file. However, there is effectively no reason to provide this customizability -- the workbuf size required for verifying firmware has never been more than 12K. (This could potentially increase in the future if key sizes or algorithms are changed, but this could be applied globally rather than for each individual platform.) This CL binds the VBOOT2_WORK macro to directly use the VB2_WORKBUF_RECOMMENDED_DATA_SIZE constant as defined by vboot API. Since the constant needs to be used in a linker script, we may not include the full vboot API, and must instead directly include the vb2_constants.h header. BUG=b:124141368, b:124192753 TEST=Build locally for eve TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x TEST=make clean && make test-abuild BRANCH=none CQ-DEPEND=CL:1504490 Change-Id: Id71a8ab2401efcc0194d48c8af9017fc90513cb8 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-21soc/intel/cannonlake: Assign FSP UPDs for HPD and Data/CLK of DDI portsKrishna Prasad Bhat
Assign the FSP UPDs for HPD and DDC of DDI ports. FSP assumes that all DDI ports are enabled and hence configures the HPD and CLK for DDI ports. This patch initializes only the required UPDs to enable display ports. BUG=b:123907904 TEST=DP devices working correctly. Change-Id: Ic0c172cd3d087fc8f49b01ab23feffdababf7166 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-21sb/intel/lynxpoint: Remove PCI bridge functionKyösti Mälkki
Legacy PCI-to-PCI (parallel) bridge 0:1e.0 is no longer supported in these SKUs. Change-Id: I954ee9cf8228c6352743cae968a0dd665865496c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-03-21{northbridge, soc, southbridge}/intel: Make use of generic set_subsystem()Subrata Banik
This patch removes all local definitions of sub_system functions and make use of common generic pci_dev_set_subsystem() from PCI bridge and Cardbus devices as well. Change-Id: I5fbed39ed448baf11f0e0786ce0ee94741d57237 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-21device/pci_device: Add generic subsystem programming logicSubrata Banik
This patch adds generic log to perform subsystem programming based on header type. Type 0: subsystem offset 0x2C Type 2: subsystem offset 0x40 Type 1: Read CAP ID 0xD to know cap offset start, offset 4 to locate subsystem vendor id. Change-Id: Id8aed6dac24517e93cd55d6bb3b254b7b4d950d3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: David Guckian Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-21{northbridge, soc, southbridge}/intel: Make use of pci_dev_set_subsystem()Subrata Banik
This patch removes local definitions of sub_system function and make use of common function pci_dev_set_subsystem(). Change-Id: I91982597fdf586ab514bec3d8e4d09f2565fe56d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: David Guckian Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-21src/arch/mips: Fix checkpatch warnings and errorsAsami Doi
This patch will fix these checkpatch errors in src/arch/mips/. - src/arch/mips/ashldi3.c:22: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' - src/arch/mips/bootblock_simple.c:35: WARNING: braces {} are not necessary for any arm of this statement Change-Id: Ic859913b93dc8ed6ff64b551c8a6baf72d28c75a Signed-off-by: Asami Doi <d0iasm.pub@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-03-21nvidia/tegra{124,210}/lp0: Directly include `stdint.h`Nico Huber
Use the compiler's `-include` switch to include `stdint.h` instead of adding coreboot's include paths. This avoids leaking other coreboot header files into lp0. Change-Id: I321c0a2fc4a2b3941990804db4e1a691e1bed8c6 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-21arch/ppc64: Add <arch/mmio.h> stubsKyösti Mälkki
The work may be incomplete, we only have an emulation power8 at the moment in the tree. Change-Id: Icdaa0995c8610dcc636923cc79b8455dfaeaa057 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
2019-03-21mb/siemens/mc_apl1: use comment in Kconfig.nameThomas Heijligen
Change-Id: I3c8791a0ed7b3bc670cf1433fa58f9b3d68e0b97 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-03-21mb/*/chromeos.c: Be explicit about code for ramstageKyösti Mälkki
Motivation is to reduce use of !__PRE_RAM__, it does not mean ENV_RAMSTAGE but we also exclude ENV_SMM with the change. Change-Id: I1f96bb8c055a3da63274e1ab7f7d4bc70867cbf1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-03-21Revert "UPSTREAM: ec/google/wilco: Enable software sync for VBOOT"Duncan Laurie
This reverts commit 51169b7dda4a1978d622e329a1c40e384471c165. I was not ready to enable this option yet, until it is enabled in depthcharge it needs to stay off in coreboot or depthcharge will attempt to do software sync without a proper driver. Change-Id: I4840812d0541f822502cfc5c66bed27edf4d2ecc Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32007 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-21mb/google/sarien: Add SKU for boards with signed ECDuncan Laurie
To support both boards with the same firmware add a SKU for each variant that is used to include the proper EC firmware image to match what the EC is expecting. BUG=b:119490232 TEST=tested by faking the EC response to ensure that the OS and firmware update tools are able to determine the correct model based on the value returned by the EC. Change-Id: Iaa677975e0bccbee5ec8a39821fe1637f08270fa Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-21ec/google/wilco: Add function to indicate if EC uses signed FWDuncan Laurie
This will be used to distinguish the mainboard SKU so that the correct EC firmware can be bundled with the board. This is read from EC RAM so it can be used by an ACPI method in the future. BUG=b:119490232 Change-Id: I71b8017fc4b88e793dfe709e1cb1ab0f0bcdc4fa Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-20soc/nvidia/tegra{124,210}: Remove unneeded 'include <halt.h>'Elyes HAOUAS
Commit 74aa99a (src: Drop unused '#include <halt.h>') accidentally added '#include <halt.h>', however tegra_lp0 directory is not linked into the rest of coreboot. So we can't use generic halt() from halt.c file. Change-Id: I3a67abb77846172597b8ebde779878b9aa2ff8d7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31979 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-20src: Use 'include <string.h>' when appropriateElyes HAOUAS
Drop 'include <string.h>' when it is not used and add it when it is missing. Also extra lines removed, or added just before local includes. Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-20google/mistral: Implement board resetsanthosh hassan
Implement reset using PSHOLD. Change-Id: I472bf73cc7b227187b284a3730ec5dea5373695c Signed-off-by: Santhosh Hassan <sahassan@google.com> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-20mistral: qcs405: copy calibration data to CBMEMNitheesh Sekar
This patch adds support to copy the wifi calibration data to CBMEM so that the depthcharge can use it to populate the data into wifi dt node. Change-Id: Ia8184e48a7176bb3b52e4d43866b7d065952c13e Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-20soc/intel/cannonlake: Fix return values for get_param_valueFurquan Shaikh
Commit 41483c9 (soc/intel/cannonlake: Add required FSP UPD changes for CML) changed the enum values for PCH_SERIAL_IO_MODE so that 0 is invalid and valid values start from 1. However, get_param_value was not updated to correctly subtract 1 before returning any value. This change adds a macro PCH_SERIAL_IO_INDEX to apply the subtract 1 operation on any value that get_param_value needs to return. BUG=b:128946016 TEST=Verified that hatch boots successfully. Change-Id: I4e32fcd1efe4a535251f0ec58662a2dc5f70e8b0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 16:51:32 +0000