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2023-07-14vc/intel/fsp/mtl: Update the MemInfoHob header to FSP version 3251.81Subrata Banik
This patch updates the MemInfoHob header file as per Meteor Lake version 3251.81. Changes include: 1. Drop DimmDFE structure variable 2. Drop unused macro MAX_COPY_DIMM_DFE_TAPS BUG=b:290898626 TEST=Able to build and boot google/rex. w/o this patch: cbmem -c -1 | grep DIMM [ERROR] No DIMMs found w/ this patch: cbmem -c -1 | grep DIMM [DEBUG]  8 DIMMs found Change-Id: I8eed410831399bb4835244f48c14d5ed9e701e68 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76433 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-14soc/mediatek/common/dsi: Add actual values to the log messagesRuihai Zhou
Per the suggestion in CB:76218, print actual values to the error messages, which may be helpful for debugging. Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: Id3a7a8c76b6ad15e7cf71225d8529f3e034935ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/76442 Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-07-14vc/amd/phoenix/platform_descriptor: clarify link_compliance_mode commentFelix Held
When set to 1, the link_compliance_mode element of the DXIO port descriptor will cause the corresponding PCIe port to not be trained but to output a compliance testing pattern instead. Update the comment to point out that this is only a testing mode. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaabb16c51a0c08391cd2d63b8064c524a748ccb8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76441 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-07-13mb/google/rex/var/screebo: Configure CNVi GPIO IO Standby StateWentao Qin
This configures GPIO IO Standby State of GPP_F00 - GPP_F05 as masked for CNVi. Meteor Lake rex platform does not wake up from low power state by bluetooth keyboard and mouse properly. It is identified that IO Standby State needs to be configured as masked to function properly for CNVi. BUG=b:286803481 TEST=Make screebo suspend to s0ix state and press a key from bluetooth keyboard. Check the platform wakes up properly from s0ix. Change-Id: I7fd342e52fa0f9126eab4c857a5adc04c26e49c6 Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76406 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-13soc/intel: Rename pcr.asl to pch_pcr.aslSubrata Banik
The PCR (Private Configuration Register) is applicable to access the P2SB register space starting with the Intel SkyLake generation of SoC. Prior to Intel Meteor Lake SoC generation, the only P2SB existed inside the PCH die. Starting with Meteor Lake SoC, there are two P2SB, one in SoC die (same as PCH die for U/H SoC) and another in IOE die. This patch renames pcr.asl to pch_pcr.asl to reflect the actual source of the P2SB IP in the die (i.e., SoC die or PCH die). BUG=b:290856936 TEST=Able to build and boot google/rex. Change-Id: Idb66293eaab01e1d4bcd4e9482157575fb0adf04 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76407 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-13acpi: Reserve hardware IDs for custom Intel GMBus I2C driverCoolStar
GMBus is an I2C compatible link on Intel IGPUs. Most non-Linux OS's don't support accessing this ordinarily, so a custom driver is needed with a bit of ACPI hackery. Reserve 2 IDs from the coreboot namespace so that the 2 devices required can be populated in Windows device manager Change-Id: I389612441e96ce2fc5e006051e523661953eba6e Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-07-13soc/intel/braswell: Use newer function for resource declarationsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I4769f79c67c372e11bb267de3acec0920d7ab0d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-07-13soc/intel/baytrail: Use newer function for resource declarationsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I80c8a1b58e8102ed11e22b74f30750d5a6c4eae4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76283 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-13mb/google/nissa/var/pujjo: Add WWAN EM060 power on sequenceLeo Chou
Pujjo support WWAN EM060 device, use FW_CONFIG to handle the power on sequence. BUG=b:290709711 TEST=Build and check WWAN EM060 power on sequence. Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I66800c75274e8e1e55d4314c82b7fcdf2a4477bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/76403 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-13mb/siemens/mc_ehl4: Change GPIO GPP_B5 polarity for DRAM populationMario Scheithauer
With the latest hardware revision, the polarity of GPP_B5 has been changed. For a full-populated DRAM configuration, the input signal is now connected to 3.3 V and for a half-populated configuration it is connected to ground. BUG=none TEST=Use different populated mainboards and check coreboot log GPP_B5 = 0: [INFO ] meminit_channels: DRAM half-populated [DEBUG] 1 DIMMs found GPP_B5 = 1: [DEBUG] 2 DIMMs found Change-Id: Iaa3a63fa52c802d8f5d8c6cc11dd6edfac117e88 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76434 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-13mb/google/nissa/var/uldren: Modify reset_delay_ms for EKTH7D18Dtrain Hsu
Modify reset_delay_ms from 300ms to 6ms for ELAN EKTH7D18. BUG=b:285999032 BRANCH=firmware-nissa-15217.B TEST=boot uldren to ChromeOS and touchscreen is workable. Change-Id: Iffcddbe7735b7a837887dec68e1270c2af5f4556 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76417 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-13soc/intel/alderlake: Disable hwp scalibility trackingBora Guvendik
Disable scalability tracking for autonomous frequency control in order to improve power and performance. BUG=b:280021171 TEST=Boot to OS on brya0 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: If71ee5374c67611b32691bbec4effdf828b3e566 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74723 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-07-13soc/intel/alderlake: Hook up UPD EnableHwpScalabilityTrackingBora Guvendik
Hook the newly exposed EnableHwpScalabilityTracking UPD up so that boards can configure is via devicetree. BUG=b:280021171 TEST=Verified by enabling/disabling the UPD on google/brya Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I4c8845c445d46caa30a0245386ab9cd690d2623f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74722 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-07-13soc/intel/alderlake: Hook up UPD DisableSagvReorderBora Guvendik
Hook the newly exposed DisableSagvReorder UPD up so that boards can configure is via devicetree. BUG=b:268546941 TEST=Verified by enabling/disabling the UPD on google/brya Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I89235d9384b67f03e68425aadd3458e1c77ff555 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-07-13soc/intel/alderlake: Disable SaGV reorderingBora Guvendik
Disable re-ordering SaGv point on warm reset so that most performant SaGv point is picked after memory training and boot time is reduced. BUG=b:268546941 TEST=Observe boot time improvement with these two UPDs set Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I44a1c054d52bb8585a320bb8a52a8f137e639804 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74721 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-13soc/intel/alderlake: Reduce memory test sizeBora Guvendik
Enable upd to reduce size of the memory test. BUG=b:268546941 TEST=Observe boot time improvement with these two UPDs set Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I95c7d8503596c2712d7abe123ed1f911ac4abacf Reviewed-on: https://review.coreboot.org/c/coreboot/+/74719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-13soc/intel/alderlake: Hook up UPD LowerBasicMemTestSizeBora Guvendik
Hook the newly exposed LowerBasicMemTestSize UPD up so that boards can configure is via devicetree. BUG=b:268546941 TEST=Verified by enabling/disabling the UPD on google/brya Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ib813e9f3b7419a3cb54b4e176dcc5cc74a783dfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/74718 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-07-13vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP RPL.4221.00Bora Guvendik
The headers added are generated as per FSP v4221.00 BUG=b:290038558 TEST=Boot to OS Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I23f6e1e4baa39883475cd93fa6aabcec4e7152cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/76147 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-07-12soc/intel/common: Restore to page 0 before reading SPDCoolStar
test: Warm reboot from Windows 11 w/ Samsung 980 Pro on Banshee Verify memory type detected properly and following boot works Change-Id: Iad0a2024bd0ef39f6ab57ff7a6e6aa651d7882a6 Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-07-12mb/ibm/sbp1: Disable SIO UartsNaresh Solanki
Avoid enabling SIO UART to prevent conflicts with BMC console; utilize VUART0 instead. TEST=Build for sbp1 & make sure coreboot logs do not spill into BMC console. Also made sure coreboot logs are accessible via VUART. Change-Id: I2d4bbd74bb7d37b74378650dd569bca7fa13c29b Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76396 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2023-07-12mb/ibm/sbp1: Set coreboot ready GPIO in BS_PAYLOAD_BOOTNaresh Solanki
Set coreboot ready gpio. This gpio is used to indicate to BMC of BIOS completion. Change-Id: Iaed8bec12e593cf1687d973765b0117bdc115cb8 Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76404 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-12mb/{google, intel}: Enable PCH Energy Reporting for MTL platformsSukumar Ghorai
This patch enables PCH to CPU energy report feature which can be used by Intel Telemetry Driver. BUG=b:269563588 TEST=Able to build and boot google/rex and perform below check to ensure the energy reporting is correct w/o this cl: # lspci -s 00:14.2 -vvv | grep "Region 0" Region 0: Memory at 957f8000 (64-bit, non-prefetchable) [size=16K] # iotools mmio_read32 0x957f8068 #i.e., 104th offset 0xXXXX0000 w/ this cl: #lspci -s 00:14.2 -vvv | grep "Region 0" Region 0: Memory at 957f8000 (64-bit, non-prefetchable) [size=16K] # iotools mmio_read32 0x957f8068 #i.e., 104th offset 0xXXXXfc004 Change-Id: I9bd4625ea311a05071878aaec68433a1ba018c0d Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76353 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-07-12intelblocks/cpu/mp_init: Add missing ADL-S SKUs to CPU match tableMichał Żygowski
Only A step ADL-S CPUs were added to CPU table for MP init. Add the remaining ADL-S CPUs to the table. TEST=Boot MSI PRO Z690-A with C step i5-12600K and observe coreboot no longer uses generic CPU ops. Change-Id: I3692a3f089ca23af860bd1c8e3c29fee9d9234c9 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76204 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-12soc/intel: Replace number in RPL-S ESPI PCI IDs by chipset nameMichał Żygowski
Change-Id: I68416e1633c3d67070790a9db2cd9a13a8981042 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-12soc/intel: Fix W790 chipset nameMichał Żygowski
In newer ADL/RPL PCH EDS 619362 revision 2.1 the ESPI ID 0x7A8A belongs to the W790 chipset. Earlier revisions had the chipset with ID 0x7A8A named W685, which was probably just a temporary name. Change the naming throughout the tree to W790, which is the real existing chipset. Change-Id: I87603298d655e9bf898b34acdd5b403f5affaee3 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2023-07-12treewide: Drop the suffixes from ADL and RPL CPUID macros and stringsMichał Żygowski
CPUID is the same for Alder Lake and Raptor Lake S and HX variants. To reduce the confusion and concerns how to name the macros, remove the suffixes from macros and platform reporting strings. Thankfully the stepping names are unique across mobile (P suffixed) and desktop (S and HX suffixed) SKUs. Distinguishing the S from HX is possible via host bridge PCI ID. Change-Id: Ib08fb0923481541dd6f358cf60da44d90bd75ae2 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2023-07-12soc/intel/alderlake: Add support for Raptor Lake S CPUsMax Fritz
Add PCI IDs, default VR values and power limits for Raptor Lake S CPUs. Based on docs 639116 and 640555. TEST=Tested on a MSI PRO Z690-A (ms7d25) with i9-13900K with Ubuntu 22.10 and LinuxBoot (Linux + u-root). Also tested on MSI PRO Z790-P with i5-13600K (UEFI Payload) usign RPL-S IoT FSP and Ubuntu 22.04. Change-Id: I767dd08a169a6af59188d9ecd73520b916f69155 Signed-off-by: Max Fritz <antischmock@googlemail.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69798 Reviewed-by: Tim Crawford <tcrawford@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
2023-07-12security/vboot/secdata_tpm: Simplify antirollback_read_space_firmware()Yu-Ping Wu
The static function read_space_firmware() is used only once, so merge it into antirollback_read_space_firmware(). Also change a debug log to error. BUG=none TEST=emerge-geralt coreboot BRANCH=none Change-Id: I8abcb8b90e82c3e1b01a2144070a5fde6fe7157f Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-07-12mb/google/geralt: Initialize I2C bus for TPS65132 in mainboardRuihai Zhou
The CB:76219 removed mtk_i2c_bus_init() from tps65132s_setup(), so we should initialize I2C bus for TPS65132 in mainboard now. BUG=None TEST=./util/abuild/abuild -t google/geralt -a Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: Iacf78221d2416f41467c709402b7e02e03dc5fc7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-07-12soc/intel/adl: Reduce microcode redundancyNico Huber
Some of the microcode update files listed in the Makefile are redundant: * 06-97-02 is exactly the same as 06-97-05 * 06-9a-03 is completely contained in 06-9a-04 (at offset 0x1c400) So drop these files. This saves us about 200KiB CBFS space in each case. Change-Id: Idfcab1de26ea4712295c1d22790bab3a73c17f93 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-07-12cpu/amd/mtrr: Use newer function for resource declarationArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I62f34a12bc5c4807638ddcb39fa5e450d99511fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/76277 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-12soc/amd/common: Use newer function for resource declarationsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Iad8b7c705d5053700850065f90314444904b5b54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76289 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-07-12mb/emulation/*: Use newer function for resource declarationsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Idd623e99ee20ad94e493c8560cfdac9f7baaf890 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76281 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-12soc/intel/*/pmc.c: Use newer function for resource declarationsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I852d6daebdcb8461c18e7c0eaf1c54ad7c59c0c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-07-12soc/intel/common: Use newer function for resource declarationsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: If7fe96220ce5b13f5541e25935afd0c681ff40f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76286 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-12soc/intel/apl: Use newer function for resource declarationsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I5728dc144b0d04a92a1e0a4b9abbe17ef0a06e41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76282 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-12soc/intel/broadwell: Use newer function for resource declarationsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ie44518988e999794fba35f41075ff62e82663d70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76285 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-12pc80/tpm: Use newer function for resource declarationsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I40b8482f41e8fece55fd60fec7ec3f63f83bd030 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76280 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-12ast2050: Fix reserving VGA regionArthur Heymans
Reserving resources needs to have inclusive region ends. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I88a09d205ef9699de7f18e0a2f33c9ad3ce9fa36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76279 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-12nb/e7505: Rework nb resource readingArthur Heymans
- Use newer functions and avoid the * / KiB dance - Use existing functions for figuring out TSEG and UMA - Don't have resources overlap Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ia8562660cf69d188b0cab4869aa3190f014dbfdc Reviewed-on: https://review.coreboot.org/c/coreboot/+/76276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-07-12mb/google/rex: Disable DRIVERS_INTEL_DPTF_SUPPORTS_TPCHKane Chen
There is no PCH FIVR participant on MTL and we should remove it in Rex. TEST=compile ok and make sure there no TPCH device in acpi BUG=b:290322310 Change-Id: Icf4be86da3f3cb9b1f0a3f2586b029a533c3e6a9 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76402 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-12nb/intel/x4x: Rework nb resource readingArthur Heymans
- Use newer functions and avoid the * / KiB dance - Use existing functions for figuring out TSEG and UMA Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I5c6dcbc8ed79b79ee097c7a14fe14ed87af33c2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/76275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-07-12nb/intel/pineview: Rework nb resource readingArthur Heymans
- Use newer functions and avoid the * / KiB dance - Use existing functions for figuring out TSEG and UMA Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I502eeb39c05bd4d00b01976c96884636baf3030c Reviewed-on: https://review.coreboot.org/c/coreboot/+/76273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-07-12nb/i440bx: Use newer function for resource declarationsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I61ae378867f8c0d9e86092ebe8deec53800c4717 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-07-12cpu/intel/microcode: Drop unnecessary alignment for split microcodeSubrata Banik
This patch drops the unnecessary alignment of 64 bytes that was introduced when implementing the split Intel microcode packing logic into CBFS. - The 16-byte alignment that is already used for Intel microcode is sufficient. - Removes unnecessary alignment check of 64 bytes against an AMD platform specific config. TEST=Able to build and boot google/rex without any functional impact. Change-Id: Icc44e9511e321592de7ab8d1346103d0a9951c9b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76397 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-07-11soc/intel/xeon_sp: Clear reserved field in SRATNaresh Solanki
During the ACPI dump of the System Resource Affinity Table (SRAT), it was noticed that the reserved field within the Memory Affinity structure contained a non-zero value. This commit addresses the issue by performing a memset to zero on the reserved field, ensuring the avoidance of any potential problems arising from garbage values. TEST= Build for ibm/sbp1 & make sure SRAT Memory Affinity entries reserved fields read zeroes Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Change-Id: I4ba697a6bd59054e74c84b98f3d9b517d333a5d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75417 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2023-07-11mb/google/rex: LZ4 compress ramstage instead of LZMAWonkyu Kim
for saving boot time, change ramstage compression from LZMA to LZ4. Boot time saving is around 35ms (30-37ms) while SPI size impact is 230KB. For detail, refer below. Existing: LZMA(55.6 ms) 8:starting to load ramstage 894,519 (0) 15:starting LZMA decompress (ignore for x86) 903,556 (9,036) 16:finished LZMA decompress (ignore for x86) 949,997 (46,441) 9:finished loading ramstage 950,179 (182) Changed: LZ4(17.8ms) 8:starting to load ramstage 900,876 (0) 17:starting LZ4 decompress (ignore for x86) 917,650 (16,774) 18:finished LZ4 decompress (ignore for x86) 918,690 (1,040) 9:finished loading ramstage 918,849 (158) Size impact (73KB * 3 = 219KB) fallback/ramstage 0x62940 stage 240281 LZ4 (405524 decompressed) fallback/ramstage 0x62940 stage 165452 LZMA (405524 decompressed) BUG=b:286930648 TEST= Boot to OS and check boot time Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I6610f405d287bff2eb4eee6f09026e3361405ded Reviewed-on: https://review.coreboot.org/c/coreboot/+/75769 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-11mb/google/rex/var/ovis: Configure CNVi GPIO IO Standby StateJamie Ryu
This configures GPIO IO Standby State of GPP_F00 - GPP_F05 as masked for CNVi to function properly with the connected bluetooth devices and wake up from low power state. BUG=None TEST=None Change-Id: I977493fd95a99381279f5a3f5e679e4893369b8a Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
2023-07-11mb/google/rex/var/rex0: Configure CNVi GPIO IO Standby StateJamie Ryu
This configures GPIO IO Standby State of GPP_F00 - GPP_F05 as masked for CNVi. Meteor Lake rex platform does not wake up from low power state by bluetooth keyboard and mouse properly. It is identified that IO Standby State needs to be configured as masked to function properly for CNVi. BUG=None TEST=Make rex platform suspend to s0ix state and press a key from bluetooth keyboard. Check the platform wakes up properly from s0ix. Change-Id: Ia98abde584699fa01acba47a9df4ef6332ac16fd Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76338 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-11mb/google/rex/var/rex0: Reduce camera NVM size to 8KBJamie Ryu
The actual NVM size of camera module is 64KB; however, only 8KB is in use to store data. This reduces the size of both NVM0 and NVM1 to 8KB to minimize the time taken to read NVM and launch Camera preview. BUG=NONE TEST=Launch Chrome camera application and check the time taken to read eeprom from camera service log and show camera preview. It takes 2 to 3 seconds to show camera preview while it takes 4 to 5 seconds without the changes. Before the changes: 06:21:04.204944Z OpenDevice(): camera_id = 1 06:21:07.297584Z Read camera eeprom from eeprom 06:21:08.763491Z Read camera eeprom from nvmem After the changes: 21:37:23.923676Z OpenDevice(): camera_id = 1 21:37:24.386020Z Read camera eeprom from eeprom 21:37:24.574515Z Read camera eeprom from nvmem Change-Id: I0e2272b3307fea60ea7406fc6899ae2cb0134fa3 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76189 Reviewed-by: Kiran2 Kumar <kiran2.kumar@intel.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-11mb/google/nissa/var/gothrax: Update eMMC DLL tuning valuesSimon Yang
Update eMMC DLL tuning values for improved initialization reliability BUG=b:289763421 TEST=cold reboot stress test over 5000 cycles on Foresee and Kingston eMMC Change-Id: I63077b8717feecf3d50507abb188b7fadb5d6c79 Signed-off-by: Simon Yang <simon1.yang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76221 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-10nb/amd/pi/00730F01: Specify supported memory typeElyes Haouas
Change-Id: Iccaeb685ba66112b9e05ed72b57eb840543d7c6a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-07-10mb/google/rex/var/ovis: Enable both Memory Channels (MC0 and MC1)Subrata Banik
This patch skips reading the MEM_CH_SEL GPIO aka GPP_E13 to determine the memory channel configuration. The signal behavior is not proper, hence limiting the DIMM capacity to half (only MC0 is enabled). This patch always reports the full memory capacity as in dual channel (both MC0 and MC1 enabled). This change is necessary to ensure that the system reports the correct memory capacity, even if the MEM_CH_SEL GPIO is not working properly. BUG=b:290174538 TEST=Able to detect 32GB memory capacity while booting google/ovis. Without this patch: localhost ~ # cat /proc/meminfo MemTotal: 16183080 kB With this patch: localhost ~ # cat /proc/meminfo   MemTotal: 32673664 kB Change-Id: I6c3fa941abb044b79b13785f7b65d09957f0487d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76359 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-10mb/google/brya/var/redrix: Use just single GFX entryWon Chung
Since multiple GFX entry causes an ACPI error when trying to write _DOD method multiple times, combine the GFX entry into one so that _DOD method is written just once. BUG=b:289854155 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: I22ad70d50f1aecf8da70e8dd04a36a0a7c1c7609 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76329 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-10mb/google/rex/var/rex0: Change touch over spi interrupt trigger to edgeEran Mitrani
This CL corrects the trigger for HID over SPI from Level to Edge. BUG:None TEST:Tested with I2C and SPI Change-Id: I78937af22df22d80a702477b6790a7aa40d782a4 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76116 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-10mb/google/corsola: Add support for AW37503 Power ICRuihai Zhou
The AW37503 is designed to supply positive/negative supply for driving the MIPI panel. It doesn't integrate non-volatile memory(EEPROM), so we need to program the registers at boot. We program the target positive/negative output voltage via I2C and enable the power rails by pulling up ENP and ENN pins. On Starmie, we need +/-6V power supply for the MIPI panel. We program the AW37503 registers in coreboot so that kernel can control AW37503 via fixed regulators without additional settings(what we did for TPS65132). Since we distinguish AW37503 and TPS65132 by reading the vendor ID, we need to initialize I2C bus as early as possible. Therefore, we move mtk_i2c_bus_init() to mainboard_init(). BUG=b:289482828 TEST=emerge-staryu coreboot chromeos-bootimage TEST=Test the sequence the voltage Change-Id: I9ccd4db19c93a032226f006eab0427f78f7b6dc8 Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76219 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-10mb/google/corsola: Add new board 'ponyta'cengjianeng
Add a new kingler follower 'ponyta'. BUG=b:290259648 TEST=make # select ponyta Signed-off-by: cengjianeng <cengjianeng@huaqin.corp-partner.google.com> Change-Id: I74759441957e9901bd7e5a709a2ae7d97a7cd040 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76331 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
2023-07-10mb/google/brya/var/brya: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Ia756f842943b8e1f1877db7433641e6bbd05f45b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74407 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-10mb/google/brya/var/skolas: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: I889db739d6e006c1753eb8c0d208cf471d09f18d Reviewed-on: https://review.coreboot.org/c/coreboot/+/74368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-10mb/google/brya: put Bluetooth VPGIOs overridableMac Chiang
The BT VGPIOs pad config in variant of gpio.c won't be overwritten on board eventually because no matched gpios existed here. Put BT VGPIOs in gpio_table, ensure that these were able to be overwritten. The fix included crota and omnigul BT offload work successfully. BUG=b:264834572 TEST=test Bluetooth offload playback/capture in SCO profile. Change-Id: I62cecf26abd0411f7cbb0a56b8b8f0a25d370c69 Signed-off-by: Mac Chiang <mac.chiang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-07-10vboot: Fix S3 resume with stage_cacheKyösti Mälkki
In VBOOT_STARTS_IN_ROMSTAGE=y case, vboot_run_logic() did not get called when postcar was loaded from TSEG stage cache on ACPI S3 resume path. Resume failed as MP init attempts to access microcode update from unverified FW_MAIN_A/B section. In a similar fashion, for POSTCAR=n, loading ramstage from TSEG stage cache would bypass the call to vboot_run_logic(). TEST=samsung/lumpy with VBOOT_STARTS_IN_ROMSTAGE=y is able to complete S3 resume. Change-Id: I77fe86d5fd89d22b5ef6f43e65a85a4ccd3259d9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-07-10mb/google/brya/var/kuldax: Add fw_config and configurate AUX pinDavid Wu
Add fw_config and configurate AUX pin for MB USB Type-C. MB USB3 doesn't have re-timer, thus have to configurate the AUX pin. BUG=b:275335023 TEST=build pass Change-Id: I1334dcbaec6de1707c6892efbebaf8d460ba8648 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76348 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2023-07-08allocator_v4: Disable top-down allocation for EDK2Nico Huber
EDK2 seems to have problems at least with the resource allocation for Intel's IGD. While the investigation is ongoing, disable top-down allocation by default if the payload is known to be EDK2. Change-Id: I771d8a3b74b54a043624843a00498225d1f509ad Signed-off-by: Nico Huber <nico.h@gmx.de> Ticket: https://ticket.coreboot.org/issues/499 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76373 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-07-08cpu/x86/lapic: Fix regression with X2APIC_LATE_WORKAROUNDKyösti Mälkki
This patch fixes the boot hang due to commit 053a45bcdb3ccf8 ("cpu/x86/lapic: Fix X2APIC_ONLY regression") on platform which selects X2APIC_LATE_WORKAROUND config. [EMERG] Switching from X2APIC to XAPIC mode is not implemented. Without this patch: Boot gets stuck inside at BS_WRITE_TABLES when enable_lapic() gets called after X2APIC mode has been enabled. The fix is to change enable_lapic() to track when late enablement for X2APIC mode happens with X2APIC_LATE_WORKAROUND. TEST=Able to build and boot google/rex to chromeos. Change-Id: I41e72380e9cfb59721d0df607ad875d7b6546974 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76384 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-08cpu: Enable per-CPUID microcode loading in CBFSSubrata Banik
The current design of the `ucode-<variant>.bin` file combines all possible microcode per cpuid into a unified blob. This model increases the microcode loading time from RW CBFS due to higher CBFS verification time (the bigger the CBFS binary the longer the verification takes). This patch creates a provision to pack individual microcodes (per CPUID) into the CBFS (RO and RWs). Implementation logic introduces CPU_INTEL_MICROCODE_CBFS_SPLIT_BINS config which relies on converting Intel CPU microcode INC file into the binary file as per format specified as in `cpu_microcode_$(CPUID).bin`. For example: Intel CPU microcode `m506e3.inc` to convert into `cpu_microcode_506e3.bin` binary file for coreboot to integrate if CPU_INTEL_MICROCODE_CBFS_SPLIT_BINS config is enabled. Another config named CPU_INTEL_UCODE_SPLIT_BINARIES is used to specify the directory name (including path) that holds the split microcode binary files per CPUID for each coreboot variants. For example: if google/kunimitsu had built with Intel SkyLake processor with CPUID `506e3` and `506e4` then CPU_INTEL_UCODE_SPLIT_BINARIES refers to the directory path that holds the split microcode binary files aka cpu_microcode_506e3.bin and cpu_microcode_506e4.bin. Refer to the file representation below: |---3rdparty | |--- blobs | | |--- mainboard | | | |--- google | | | | |--- kunimitsu | | | | | |--- microcode_inputs | | | | | | |--- kunimitsu | | | | | | | |--- cpu_microcode_506e3.bin | | | | | | | |--- cpu_microcode_506e4.bin Users of this config option requires to manually place the microcode binary files per CPUIDs as per the given format (`cpu_microcode_$(CPUID).bin`) in a directory. Finally specify the microcode binary directory path using CPU_UCODE_SPLIT_BINARIES config. Additionally, modified the `find_cbfs_microcode()` logic to search microcode from CBFS by CPUID. This change will improve the microcode verification time from the CBFS, and will make it easier to update individual microcodes. BUG=b:242473942 TEST=emerge-rex sys-firmware/mtl-ucode-firmware-private coreboot-private-files-baseboard-rex coreboot Able to optimize ~10ms of boot time while loading microcode using below configuration. CONFIG_CPU_MICROCODE_CBFS_SPLIT_BINS=y CONFIG_CPU_UCODE_SPLIT_BINARIES="3rdparty/blobs/mainboard/ $(CONFIG_MAINBOARD_DIR)/microcode_inputs" Without this patch: 10:start of ramstage 1,005,139 (44) 971:loading FSP-S 1,026,619 (21,479) > RO/RW-A/RW-B CBFS contains unified cpu_microcode_blob.bin Name Offset Type Size Comp ... cpu_microcode_blob.bin 0x1f740 microcode 273408 none intel_fit 0x623c0 intel_fit 80 none ... ... bootblock 0x3ee200 bootblock 32192 none With this patch: 10:start of ramstage 997,495 (43) 971:loading FSP-S 1,010,148 (12,653) > RO/RW-A/B CBFS that stores split microcode files per CPUID FMAP REGION: FW_MAIN_A Name Offset Type Size Comp fallback/romstage 0x0 stage 127632 none cpu_microcode_a06a1.bin 0x1f340 microcode 137216 none cpu_microcode_a06a2.bin 0x40bc0 microcode 136192 none ... ... ecrw 0x181280 raw 327680 none fallback/payload 0x1d1300 simple elf 127443 none At reset, able to load the correct microcode using FIT table (RO CBFS) [NOTE ] coreboot-coreboot-unknown.9999.3ad3153 Sat May 20 12:29:19 UTC 2023 x86_32 bootblock starting (log level: 8)... [DEBUG] CPU: Genuine Intel(R) 0000 [DEBUG] CPU: ID a06a1, MeteorLake A0, ucode: 00000016 Able to find `cpu_microcode_a06a1.bin` on google/rex with ES1 CPU stepping (w/ CPUID 0xA06A1) (from RW CBFS) localhost ~ # cbmem -c -1 | grep microcode [DEBUG] microcode: sig=0xa06a1 pf=0x80 revision=0x16 [INFO ] CBFS: Found 'cpu_microcode_a06a1.bin' @0x407c0 size 0x21800 in mcache @0x75c0d0e0 [INFO ] microcode: Update skipped, already up-to-date Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic7db73335ffa25399869cfb0d59129ee118f1012 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-07-08cpu/intel/microcode: Avoid Pre-RAM microcode update if FIT enableSubrata Banik
This patch changes the default behaviour of the MICROCODE_UPDATE_PRE_RAM config for the platform with FIT (CPU_INTEL_FIRMWARE_INTERFACE_TABLE) enabled. If FIT is enabled then microcode update will be taken care of by FIT at pre-cpu reset hence, microcode update at pre-ram phase can be skipped. BUG=b:242473942 TEST=Able to build and boot google/rex with MICROCODE_UPDATE_PRE_RAM remains disabled. No functional impact. Without this patch: CONFIG_MICROCODE_UPDATE_PRE_RAM=y With this patch: CONFIG_MICROCODE_UPDATE_PRE_RAM is not set Change-Id: I603e064115869aba2bffa5589ffe47a44a90b848 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-07-07mb/google/skyrim/var/crystaldrift: Override SPI flash bus speedYunlong Jia
Add configuration to bump up the SPI flash bus speed from 66 MHz to 100 MHz for starting next phase. BUG=b:270500631 BRANCH=None TEST=emerge-skyrim coreboot Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I0915d9b10dbfae7fff4e8874011951d1690de870 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Chao Gui <chaogui@google.com>
2023-07-07soc/amd/*/globalnvs,nvs: remove deprecated & unused CBMC field from GNVSFelix Held
Commit cde4f3b2790d ("acpi/gnvs.c: Drop unused pointer to the cbmem console") removed writing the coreboot memory console pointer to the GNVS and kept the CBMC field as reserved. Since those fields aren't needed any more and there are no dependencies on the absolute position of the different fields in GNVS as long as both GNVS definitions on the C and the ASL side match, remove the deprecated and unused CBMC field from the GNVS structs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iadfaf5a4ec1401b027dbfb6a7c6ce74a1dcecdfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/76351 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-07-07lib: Adjust the log levels in ux_locales.cHsuan Ting Chen
The function ux_locales_get_text() should expect to have a correct preram_locales region to read, hence we need to adjust the log levels inside lib/ux_locales.c:ux_locales_get_text(): * If the region does not exist or is not in a correct format, we should print in BIOS_ERR * If the arguments are not correct but we have a good workaround (e.g. the lang_id from vboot API seems weird), we should print in BIOS_WARNING. Also change some minor syntax issues. BUG=b:264666392, b:289995591 BRANCH=brya TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: Ic8a8856c883f6ca78fed69542a7d388f57c5c508 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76316 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-07-07soc/intel/xeon_sp/spr: Fix upd_display.c build errorJohnny Lin
Fix below build error after DISPLAY_UPD_DATA is selected: src/soc/intel/xeon_sp/spr/upd_display.c:131:29: error: variable 'old' set but not used [-Werror=unused-but-set-variable] 131 | const FSP_S_CONFIG *old; | ^~~ src/soc/intel/xeon_sp/spr/upd_display.c:130:29: error: variable 'new' set but not used [-Werror=unused-but-set-variable] 130 | const FSP_S_CONFIG *new; Change-Id: I43ed5fadab58e0d4dc824457c7a1bdf48511198e Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76342 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-07drivers/intel/fsp2_0: Remove BUILD_TIME_STAMP_SIZE macroRonak Kanabar
Remove BUILD_TIME_STAMP_SIZE macro from coreboot because FSP 3223 version have BUILD_TIME_STAMP_SIZE macro defined as part of `FspProducerDataHeader.h`. Ref change: 9c28ab1d1a vc/intel/fsp/mtl: Update header files from 3194_81 to 3223.80 BUG=b:285110116 TEST=Able to build google/rex. Change-Id: I52707adf1aa6dadca8dcf82102f76916a0cfe346 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-07-07soc/amd/*/Makefile.inc: Use _tohex instead of printfFred Reitberger
Use the _tohex function to convert values to hex instead of 'shell printf' TEST=timeless builds identical for grunt,dalboz,guybrush,chausie,birman Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ic7f7d1b764479088cc0980b208d8d603bc712832 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76314 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-07-07mb/google/brya/var/constitution: Update overridetreeMorris Hsu
constitution only has one TBT port, remove tcss_dma1. BUG=None TEST=emerge-constitution coreboot Change-Id: Ia4eb4371eb20e75a0f464e2b087fd2fe59569537 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Pablo Ceballos <pceballos@google.com>
2023-07-06util/apcb: Add apcb edit tool for phoenixRob Barnes
Add a new apcb edit tool, apcb_v3a_edit.py, that injects SPDs into an APCB for phoenix platform. The tool makes several assumptions: * Each SPD only uses blocks 0, 1, 3 and 5. All other blocks are zero. * Each block is 64 bytes. * Dimm and socket are always 0 * Unused SPD entries are zero'd BUG=b:281983434 BRANCH=None TEST=build, flash, boot myst Change-Id: Ifb50287de77138170714a702ab87d56427aacfef Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76188 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-06drivers/tpm: Move tis_plat_irq_status to cr50 driverGrzegorz Bernacki
tis_plat_irq_status() function is used only by Google TPM. It should be moved to drivers/tpm/cr50.c. The name of the function was changed to cr50_plat_irq_status(). BUG=b:277787305 TEST=Build all affected platforms Change-Id: I78dc39f2c7b44232b06947d3dfe6afa52807ced8 Signed-off-by: Grzegorz Bernacki <bernacki@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75917 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-07-06acpi/acpi.c: Fix regression with DSDTKyösti Mälkki
Fix regression introduced with commit 01af0f8ac803 ("acpi/acpi.c: Reduce boilerplate"). DSDT table is not to be listed within RSDT/XSDT, ACPICA and/or OSPM may try load it twice raising conflicts in the namespace and effectively ignoring all or most of the AML. Change-Id: I0e6d07b35522f2bf9a51cef0a7e3181b15087d88 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-07-06mb/amd/birman/Kconfig: Select SPI_FLASH_EXIT_4_BYTE_ADDR_MODEFred Reitberger
Always exit 4-byte addressing mode to prevent errors when the spi flash is not left in 4-byte addressing mode. TEST=boot with PSP releases that leave the flash in both 4-byte and 3-byte mode and verify flash writes Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I9884b85bc3b0a9b654a2cb91fb314b0869abd622 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76094 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-06mb/siemens/mc_ehl4: Make DRAM population depending on GPIO GPP_B5Mario Scheithauer
GPIO GPP_B5 is used as input on this mainboard. For a full-populated DRAM configuration, the input signal is connected to ground and for a half-populated configuration it is connected to 3.3 V. BUG=none TEST=Use different HW configurations and check coreboot log GPP_B5 = 0: [DEBUG] 2 DIMMs found GPP_B5 = 1: [INFO ] meminit_channels: DRAM half-populated [DEBUG] 1 DIMMs found Change-Id: I48b4a3bea7f1ff804b78b7c648a7ea1925627b8a Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76245 Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-06mb/siemens/mc_ehl: Make DRAM population configurableMario Scheithauer
There can be mainboard variants, which are only equipped with half-populated DRAM. For this reason, the meminit parameter for populatation should be adjustable. The default setting remains at full-populated DRAM. At mainboard variant level a different selection via individual input paths can be made. Change-Id: I390bbfa680b5505bb2230fa0740720bd9dd1fafb Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76244 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-06emulation/qemu-q35: Enable ECAM earlierKyösti Mälkki
Align implementation with real hardwares, such that ECAM (PCI configuration via MMIO) is available for use when console is initialised. Change-Id: I288991f31d3f1678132aa4315168c09eabbbe98d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76206 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-07-06acpi/gnvs.c: Drop unused pointer to the cbmem consoleArthur Heymans
Change-Id: I7e2018dbccead15fcd84e34df8207120d3a0c57c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64303 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-07-06cpu/x86: Add some notes about XAPIC/X2APICKyösti Mälkki
At the time of writing SMM runtime does not make register accesses to LAPIC registers, but such breakage has been reported. S3 resume failure, where OS switched back from X2APIC to XAPIC mode, can be reproduced with a sandybridge SKU that has VT-d disabled. Change-Id: I300ba87c3d8fde548dbaf95703bd7e2fe54cff57 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-07-06cpu/x86/lapic: Fix X2APIC_ONLY regressionKyösti Mälkki
Some ancient CPUs may have had LAPIC disabled at power-up, so semantically enable_lapic() should always come before attempting to access the register banks. With X2APIC_ONLY option it is necessary to ensure enable_lapic() is called prior to any other lapic register space accesses, since the XAPIC mode MMIO accessors are optimised away build-time and CPU's do not yet initialise for X2APIC mode at reset. Change-Id: I96eaa5c43108c802375e184e0c68b5091ca0198f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76195 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-07-06emulation/{i440fx,q35}: Don't use PCI driver to set root PCI dev opsArthur Heymans
This devices is always present so hooking up the ops in devicetree makes more sense. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I369129e365ce8596cad25b97d12168bb08e3ed0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/76241 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-06mainboard/starlabs/*: Remove the power_on_after_fail optionSean Rhodes
None of these boards have an RTC battery, so this option has no effect. Remove it. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9a55227f74c0b9ae9b56bdef4b8f53b2425b331c Reviewed-on: https://review.coreboot.org/c/coreboot/+/75450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-06mainboard/starlabs/starbook: Unselect RESIZABLE_BARSSean Rhodes
It is not needed, so remove it. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I606d0a76926e90e4ce321163400aa50ea961c2a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75342 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-07-06vc/intel/fsp/mtl: Update header files from 3194_81 to 3223.80Kilari Raasi
Update header files for FSP for Meteor Lake platform to version 3223_80, previous version being 3194_81. FSPM: 1. Add 'ROWHAMMER','RhSelect','McRefreshRate','Lfsr0Mask','Lfsr1Mask' UPDs 2. Add 'TmeExcludeBase','TmeExcludeSize','GenerateNewTmeKey' UPDs 3. Address offset changes BUG=b:287890130 TEST=Able to build and boot google/rex to ChromeOS. Change-Id: I4b8d0a3a87be7dc0d899298eb8e4e48905090e71 Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75916 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-06mb/google/brya/var/mithrax: Generate SPD ID for supported partsJohn Su
Add new memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: 1. K4U6E3S4AB-MGCL (Samsung) 2. K4UBE3D4AB-MGCL (Samsung) BUG=b:289873670 BRANCH=brya TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I7a262ac62c24cfb43c0283c9730c177a242342e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76240 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-05soc/amd/phoenix/Makefile.inc: Refactor repeated lines to a variableFred Reitberger
Rather than repeat the same line multiple times, save it in a variable once and use that variable in the rest of the file. TEST=timeless birman build identical Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I4eb262adb3bbda04add79b2e2b8bee9a609a1e5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/76197 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-05soc/amd/phoenix/Makefile.inc: Pass APOB_NV address as offsetFred Reitberger
Pass the APOB NV address as a flash offset instead of x86 address. TEST=boot birman and verify APOB_NV is working Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I0f710f12cc5d933a75840dbce1c4bad0c2ea04cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/76162 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-05arch/x86: Ensure LAPIC mode for exception handlerKyösti Mälkki
Attempting to use X2APIC MSRs before the call to enable_lapic() is made raises exception and double-faults. Change-Id: Ib97889466af0fbe639bec2be730784acc015b525 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-07-05soc/intel/alderlake: Increase default CBFS size to 4MBFelix Singer
Updating some submodule pointers to their latest commit causes some builds with default configuration to fail since all required components don't fit into 2MB anymore. Specifically, this has been experienced with the microcode and FSP submodules. So, increase the default CBFS size to 4MB to make sure builds succeed with updated submodules. Change-Id: I2fc16240bef36c057608acadf3cb7c65e7f0d244 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-07-05mb/protectli/vault_ehl: Set DIMM_MAX to 1Michał Żygowski
VP2420 (vault_ehl) has only 1 DIMM slot present. Set the DIMM_MAX to 1 to optimize the common libraries to not attempt to read and parse more SPD than needed. TEST=Boot Protectli VP2420 (vault_ehl) with different DIMMs and see FSP is retraining the memory properly and fastboot is working. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I29a99f387ffe2df1060547e0818c5c5b66a27061 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73819 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-05soc/intel/meteorlake: Set TCC to 90°CSumeet Pawnikar
Set tcc_offset value to 20 in chipset for Thermal Control Circuit (TCC) activation feature for meteorlake silicon. Also, remove tcc_offset default value from rex baseboard and variants. BUG=b:270664854 BRANCH=None TEST=Build FW and test on rex board Change-Id: Ieec1b7e0873eef46a56e612ed1d9445019b1f4a9 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-05mb/google/rex/var/screebo: Update touchpad I2C timingZhongtian Wu
Change i2c[3] parameter to meet below timing: t-HIGH > 600ns; 900ns > Thd:dat > 300ns. BUG=b:286030723 BRANCH=none TEST=Test success by EE. Change-Id: I4b2d958a5a0d41e2cfa1087f5cb94cc83bbb1739 Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76169 Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-05mb/google/rex/var/ovis: Set TCC to 100°CSubrata Banik
Set tcc_offset value to 10 in devicetree for Thermal Control Circuit (TCC) activation feature for ovis. BUG=b:270664854 TEST=Build and boot google/ovis. Change-Id: I0ef626f6cc460f1b460297804b97038705efaf4c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-05soc/intel/meteorlake: add power limits for 28W SKUSumeet Pawnikar
Add power limit values for Meteor Lake 28W SKU. Reference: Intel MTL-UH_Power_Map_Rev1p2, doc: 640982 BRANCH=None BUG=b:289854108 TEST=Build FW Change-Id: I0b4741185278913d11d902d53345ae8ccebb18f8 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76239 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-05soc/intel/meteoerlake: add support for 28W SKUSumeet Pawnikar
Add power limits support for 28W SKU. BRANCH=None BUG=b:289854108 TEST=Build FW Change-Id: I83deb1e574990cb70f9aac5d5eb46fbb710a6170 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76238 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-05mb/google/rex/var/ovis: Add Power Limit for 28WSubrata Banik
This patch adds a power limit for Ovis with 28W Intel Meteor Lake silicon. Reference: Intel MTL-UH_Power_Map_Rev1p2, doc: 640982 BUG=b:289854108 TEST=Able to boot google/ovis with power limit being overridden as appropriate to 28W. Change-Id: I312c70720fd89261c53d5bd4f45236e829d6c790 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2023-07-05mb/google/rex: Temporarily disable the crashlogKapil Porwal
Currently, boards with ES2 silicon are unable to boot with crashlog enabled because crashlog driver is unable to handle invalid data. Temporarily disable the crashlog to unblock development until the issue is fixed. BUG=b:289749310 TEST=Able to boot to the OS on Screebo Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ic63cf9cf5bfa2c92d8f2c5b13df2f23dc118b389 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76231 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-05 02:58:59 +0000