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Add new memory parts in memory_parts_used.txt and generate SPD id for
these parts:
Samsung K4U6E3S4AA-MGCL
BUG=b:204014463
TEST=run part_id_gen to generate SPD id
Change-Id: Icb0f211508450b16b2e5d214ae6adc9852718a59
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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The 'at' part of the name refers to starting to read from a specific
offset, so it doesn't make sense for the 'full' version of the function.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I60d595f0cbd161df171eaa4a76c7a00b6377e2b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59820
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The build fails because smm_stub_size() tries to find a symbol that
won't be present.
Change-Id: I73fee3cf26c0e37cca03299c6730f7b4f1ef6685
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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The Hermes mainboard is used in different system configurations. The
current VBT for Poseidon systems is unsuitable for Avalanche systems
because display ports are connected differently.
Add a new field in the BMC config EEPROM layout and use it to choose
the correct VBT for every system configuration.
Change-Id: I2647f2ae3f496b9ad75980ba86beb7800fdb0668
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The original RCOMP resistor and target values only apply to ULT CPUs and
do not make sense for the CFL-S CPUs Hermes uses. Fix the RCOMP settings
and the associated comments.
Tested, still boots.
Change-Id: I015797c58c914c6581d472e6d70d2dd7bad2b14f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Define a new field in the board config EEPROM layout for port B Vref.
Write port B Vref settings to unused non-volatile NID 0x12 instead of
NID 0x18, the actual port B NID. Because per-port Vref settings don't
persist after codec resets, a custom Realtek driver (ab)uses NID 0x12
to restore port B Vref after resetting the codec.
Change-Id: Iaa11ba9c74f643e94046d4983fbce65dbedd1025
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update the pin configs for the front panel jacks.
Change-Id: I3760f0a25e964cf0eba99d180fd6f3e8488af868
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Use lowercase for hex numbers, sort includes alphabetically and avoid
relying on indirect inclusion. Include `<intelblocks/gpio.h>` instead
of `<intelblocks/gpio_defs.h>`, as the latter implcitly relies on one
definition from `<soc/gpio.h>`. Also drop useless dsdt.asl and fix up
the indentation of some includes.
Tested with BUILD_TIMELESS=1, Prodrive Hermes remains identical.
Change-Id: I3aeb9a644cf33cb4b1987174f40ef0fc7daccfa9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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There's no need to use a variant structure here. Only one variant is
used, and revision-specific differences are handled at run-time, and
it's unlikely that another variant will ever exist.
Reorganize the mainboard code to get rid of the variant structure.
Change-Id: I1543f5b76975b0e7183fbb759e9bae5c34151d06
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: I943d0e2a91778df306f323e2b889cd4e928e0c2b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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EN_SPKR GPIO is used as a multiplexer select signal between RAM_ID
straps and Developer Mode Beep signals. During boot up it is LOW and
selects RAM_ID straps. When the system enters OS, it is driven HIGH and
selects DEV BEEP signals. Since in some boards, the GPIO chosen is in S5
domain it does not reset until the system enters mechanical off (G3)
state. On scenarios where the power button is pressed when the system is
in S5, incorrect RAM_ID strap is being read because the EN_SPKR is still
selecting DEV BEEP signal. This causes boot up failures. Fix this by
configuring the EN_SPKR GPIO (in S5 domain) explicitly in PSP verstage.
BUG=b:204450368
TEST=Build and boot to OS in Guybrush. Perform suspend-resume cycle
followed by a S5 -> S0 boot cycle for 2 iterations successfully.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I9a52a167da9c7040731da5d355ec345fd9b13762
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59813
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Turn on the LAN device in devicetree and add Kconfig item
RT8168_GET_MAC_FROM_VPD to support programming MAC address.
BUG=b:193750191
BRANCH=None
TEST=Use 'vpd -s ethernet_mac0=...' to write MAC to VPD.
Use 'ifconfig' to check if the MAC written successfully.
Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com>
Change-Id: Ibb95b02fd6d61621ef46db4d63b48456a0a72732
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The Realtek RT8168 and RT8125 have a similar programming interface,
therefore add the PCI device ID for the RT8125 into driver for support.
BUG=b:193750191
TEST=emerge-brask coreboot chromeos-bootimage. Test on brask whose NIC
is RT8125. Check if the default MAC is written into the NIC.
Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com>
Change-Id: Iaa4c41f94fd6e5fd6393abbb30bfc22a149f5d71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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FSP v2422_01 introduced new FSPM UPD CnviDdrRfim. Add CnviDdrRfim
config to control the CnviDdrRfim UPD from devicetree. Setting
CnviDdrRfim to 1 enable CNVi DDR RFIM
BUG=b:201724512
BRANCH=None
TEST=Build and boot brya with debug FSP and verify CnviDdrRfim UPD value.
Change-Id: Ia06c9ed77d78821fd4724046bae2f31c9d771518
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Due to the vGPIO is not reset when we power on through S5, we would
met MCA when PCIE send L1 request without following Ack
BUG=b:207625007
TEST=S0->S3->S5->power key->S3->S0, see if boot up normal
Change-Id: I20cdd1650d1ca774065a6c051006dfd0b7a3fd79
Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The VR configuration should be based on the different Soc SKU type. And
we also have different SKU in the same SA PCI ID.
Therefore, add TDP to recognize the correct SKU and give the correct
power setting.
BUG=b:202486131
TEST=Build and check fsp log to confirm the settings are set properly.
Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Change-Id: I4d31e7afc76d9a8c772781671f92ec08f9d8713f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Create the beadrix variant of the waddledee reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:204882915
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_BEADRIX
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: Ie08cbc19967eca8ba31ea3203e71c4e1fef044d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Guybrush uses secure counters to protect against High Definition (HD)
protected content rollback. These secure counters are hosted in TPM
NVRAM. Enable secure counters so that they are defined in PSP verstage.
BUG=b:205261728
TEST=Build and boot to OS in Guybrush. Ensure that the secure counters
are defined successfully in TPM NVRAM.
Change-Id: I6818c6f7905aa2eb815059e23c4f79437593f8ca
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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High Definition (HD) protected content playback requires secure counters
that are updated at regular interval while the protected content is
playing. To support similar use-cases, define space for secure counters
in TPM NVRAM and initialize them. These counters are defined once during
the factory initialization stage. Also add
VBOOT_DEFINE_WIDEVINE_COUNTERS config item to enable these secure
counters only on the mainboard where they are required/used.
BUG=b:205261728
TEST=Build and boot to OS in guybrush. Ensure that the secure counters
are defined successfully in TPM NVRAM space.
tlcl_define_space: response is 0
tlcl_define_space: response is 0
tlcl_define_space: response is 0
tlcl_define_space: response is 0
On reboot if forced to redefine the space, it is identified as already
defined.
tlcl_define_space: response is 14c
define_space():219: define_space: Secure Counter space already exists
tlcl_define_space: response is 14c
define_space():219: define_space: Secure Counter space already exists
tlcl_define_space: response is 14c
define_space():219: define_space: Secure Counter space already exists
tlcl_define_space: response is 14c
define_space():219: define_space: Secure Counter space already exists
Change-Id: I915fbdada60e242d911b748ad5dc28028de9b657
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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In next build phase, primus will exchange i2c port for touchscreen and cr50.
BUG=b:207834727
TEST=build pass
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: Ief1b156b866a9aaa2919f0e209b6439c7019e939
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Due to the vGPIO is not reset when we power on through S5, we would
met MCA when PCIE send L1 request without following Ack
BUG=b:207070967
TEST=S0->S3->S5->power key->S3->S0, see if boot up normal
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: Ice522260f288b165ae66dddc3e1979e806b53f9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Create the taniks variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)
BUG=b:207402720
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_TANIKS
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I797051f93019ccf72f1007d9c0b98cfb071717b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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1. Set the PL1, PL2 and PL4 according to issue b:193864533 comment#55
and Intel's doc #626774.
2. Set PsysPL2 and PsysPmax according to the conclusion in issue
b:193864533 comment#23 and comment#29.
BUG=b:193864533
BRANCH=none
TEST=Compare the measured power from adapter with the value of 'psys'
from the command 'dump_intel_rapl_consumption'.
Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com>
Change-Id: I9261902b8c892d0b866f326b24988039c1d30b56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Copy function variant_update_power_limits from brya to set power limits.
Add function variant_update_psys_power_limits and copy the algorithm
from puff. Add structure system_power_limits and psys_config to define
and configure the psys power limits.
BUG=b:193864533
BRANCH=none
TEST=Build pass
Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com>
Change-Id: I183017068e9c78acb9fa7073c53593d304ba9248
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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DVT schematic will exchange TPM_I2C3 to TPM_I2C1, that may need swap
TPM I2C with touchscreen I2C to avoid TPM I2C fall on muxed ISH I2C,
need change I2C map, sch amd GPIO map. b/196293623
BUG=b:207613972
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I26d059a7ea5a3fdf00de260214c00d3bba9aa7f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59580
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Follow the latest HW schematic change.
BUG=b:208556921
TEST=build pass
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ic05843487ea540b8cd9a50d5f73803905fd80d49
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Since we may have either BIOS ACM or both BIOS and SINIT ACMs in CBFS,
the size of txt_heap_acm_element will be different. We cannot always
hardcode the size of ACM addresses array for two ACMs. If only the BIOS
ACM was included, the BDR parsing failed in TBoot due to invalid size
of HEAP_ACM element. Check if SINIT ACM is present in CBFS and push
properly formatted BDR region onto the TXT heap. Use two separate
txt_heap_acm_element structures with different lengths.
TEST=Boot QubesOS 4.0 with TBoot 1.8.2 on Dell OptiPlex 9010 with and
without SINIT ACM in CBFS and see that TBoot no longer complains on
the wrong size of HEAP_ACM element
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ib0c37a66d96e1ca3fb4d3f665e3ad35c6f1c5c1e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Initialize the DPR register and check if SCLEAN needs to be run.
Allows to reliably boot the platform if ungraceful shutdown occured or
the memory controller has been locked by TXT.
TEST=Dell OptiPlex 9010 with Intel TXT enabled boots successfully
after 4s power button override or power cable unplug when SENTER was
executed. Successfully boot QubesOS 4.0 with TBoot v1.8.2
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I4b912f121593fa55c11813262f09be1a1055e950
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Keeping the PM timer enabled will disqualify an ADL system from entering
S0i3, and will also cause an increase in power during suspend states.
The PM timer is not required for brya boards, therefore disabling it.
Fixes: 0e905801 (soc/intel: transition full control over PM Timer from
FSP to coreboot)
BUG=b:206922066
TEST=Boot gimble to OS and verify S0i3 counter incrementing after
exiting S0ix suspend states.
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I8005dacd732c033980ccc479375ff5b06df8dac1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59790
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Alder Lake code currently supports the PCH-M and PCH-P types, which
have some differences (so far, only the amount of PCIe I/O). Mainboards
can use the `SOC_INTEL_ALDERLAKE_PCH_M` Kconfig option to specify which
PCH type they use: select the option to choose PCH-M, do not select the
option to choose PCH-P. While this works, it can be confusing once more
PCH types are added.
Introduce the `SOC_INTEL_ALDERLAKE_PCH_P` Kconfig option so that boards
have to explicitly choose a PCH type. Also, use this option to restrict
the PCH-P defaults for PCH-dependent settings to avoid unintended reuse
of the PCH-P defaults when adding a new PCH type. To make sure only one
PCH type is selected, add some preprocessor in `bootblock.h` to provoke
a build-time error if this requirement is not met. Kconfig doesn't seem
to have a mechanism to describe sets of mutually-exclusive bool options
that allows said options to be selected (a `choice` block doesn't allow
its elements to be selected). Finally, adapt the ADL boards accordingly.
Change-Id: I7deca820e08ce2b5a220f3c97a511a4f3464a976
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Utilize retry() macro in wait_aux_op_finish() and anx7625_init() to
simplify the code.
BUG=none
TEST=emerge-asurada coreboot
BRANCH=none
Change-Id: I207e7075e8ac905efd5f201dd54658dedf531568
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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The current implementations of edid_read() and segments_edid_read() have
a few problems:
1. The type of variable `c` is incorrect, not matching the return type
of sp_tx_aux_rd(). In addition, the meaning of `c` is unknown.
2. It is pointless to do `cnt++` when sp_tx_aux_rd() fails.
3. These two functions ignore the return value of
anx7625_reg_block_read().
4. In segments_edid_read(), anx7625_reg_write() might return a positive
value on failure.
Fix all of the 4 issues, and modify the code to be closer to kernel
5.10's implementation (drivers/gpu/drm/bridge/analogix/anx7625.c). Note
that, however, unlike in kernel, anx7625_reg_block_read() here doesn't
return the number of bytes. On success, 0 is returned instead.
In addition, following coreboot's convention, always return negative
error codes. In particular, change the return value to -1 for
edid_read() and segments_edid_read() on failure.
BUG=b:207055969
TEST=emerge-asurada coreboot
BRANCH=none
Change-Id: Ife9d7d97df2926b4581ba519a152c9efed8cd969
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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This area is used for storing AP RO verification information.
BRANCH=none
BUG=b:141191727
TEST=built a guybrush firmware image and verified that the RO_GSCVD
area was indeed added:
$ dump_fmap /build/guybrush/firmware/image-guybrush.bin | \
grep -B3 RO_GSCVD
area: 25
area_offset: 0x00808000
area_size: 0x00002000 (8192)
area_name: RO_GSCVD
$
- verified that guybrush device boots fine with the new image.
Change-Id: Ifa24d5a6271a8bcbf737d4580ec85b9cfdd9af01
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57864
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The ChromeOS kernel platform driver is adding support for a ChromeOS
privacy screen device, and in order to locate that device, the driver
uses the GOOG0010 reserved HID for this.
Patch for 5.10 kernel can be found at:
https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/3289984
BUG=b:206850071
TEST=dump SSDT, see _HID instead of _ADR
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: If988ca94b6c70d08a7b07cc9f6bbb077fac84e5b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59731
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Some boards may want to use a _HID instead of an _ADR to locate a
graphics device. This patch provides that option in the devicetree.
BUG=b:206850071
TEST=Add `hid` entry in devicetree, dump SSDT and see _HID instead of
_ADR
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I32be4abf5c60be1f94aabaa2e9c734215c4e291e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Tested on Qemu/i440fx. The follow-up commit adds a config file to
buildtest it.
Change-Id: Ieeaa85691e4c4516bb51df0e87c4ecaa940810f0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Fix the issue that power consumption of single rank DRAM is greater
than dual rank DRAM due to incorrect settings of rank1 CKE.
Set rank1 CKE to the correct state to fix this issue.
BUG=b:196867407
TEST=DUT can boot to OS.
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: If336197aea4770dda1332b6e83da8ec9a4f9d77b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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This patch drops unnecessary `pmc_ipc.c` from Makefile as this
file is getting included upon CONFIG_PMC_IPC_ACPI_INTERFACE selection.
Change-Id: Ie66f0833daf033ec16210221610508f9fbb1e6c7
Signed-off-by: Subrata Banik <subi.banik@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Some herobrine variants have USB hub powered by discrete LDO that is
controlled by USB_HUB_LDO_EN gpio. Assert the GPIO on boot.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board.
Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
Change-Id: Ia94e046f9eb0d3ce593f3445e0203a7391c14de2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Initialize by calling `setup_usb_host0()` from SOC code
BUG=b:182963902
TEST=Validated USB enumeration on qcom sc7280 development board
Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
Change-Id: Ic378352a97e4f3ed89089f1f7545f8ebb172b1f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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These values make more sense as an enum, and are currently unused in
ASL files, therefore they can be moved to the appropriate part of the
header file and converted there.
Change-Id: I8b8586b46823b5da3614a0b2a2f2f16802e96962
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Despite Stoneyridge being one only SoC in soc/amd that uses the first
generation of the PSP mailblox interface, this code is common for all
SoCs that use the first PSP mailbox interface generation, so move it to
the common PSP generation 1 code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I78126cb710a6ee674b58b35c8294685a5965ecd6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59701
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BlueTooth disappeared after disabled USB2 port 9,
so we need to re-enable it.
BUG=none
TEST=build pass
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I7971509d7428562c80e781339ead059a189cea13
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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BUG=b:207307897
BRANCH=dedede
TEST=enable CHROMEOS_WIFI_SAR in config of coreboot,
emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage.
Change-Id: Ib1682cdafe1b6ed7cc0cf23624f83d2e5bbfb92e
Signed-off-by: Wizard Shen <shenhu5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com>
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Libpayload requires cbmem_id.h file to support extracting values from
CBMEM IMD entries of coreboot tables. Libpayload use BSD-3-Clause
license, and all of its files used to compile a static library have to
use it too.
Change-Id: I97c080e34ebdbcdf14fe3a3c9515b1dea8ede179
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
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Fork multiple "4ES" variants off some brya devices to
properly support ES SoC.
BRANCH=none
BUG=b:201767461
TEST=emerge-brya coreboot and check the artifacts
Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: Ic9516fec591429238bde1478eca2522d8ed10127
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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New PI 1.0.0.5 has more data in HOB of DMI, which has been uploaded to
google internal repo. The dismatched size of HOB causes the wrong data
tranfer. So the coreboot also need to change.
BUG=b:204732649
Change-Id: Id95c37a0d7027d75afddf9d7528ff41ae3a347f5
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This part was copied from Picasso but Cezanne has some more bits used so
add the definitions now.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icd128dca1ec30e7c70501c0e64482159be71cc7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Both SPI_ROM_BIOS_SEMAPHORE and SPI_ROM_EC_SEMAPHORE bits in the
LPC_PCI_CONTROL are defined in the Stoneyridge BKDG #55072 Rev 3.04,
Raven1 and Picasso PPR #55570 Rev 3.18, Raven2 PPR #55772 Rev 3.08 and
Cezanne PPR #56569 Rev 3.03 which are all platforms that use this code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I855e640d020daf21c9f5b2f62a2ad0fd0274a575
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This one might conflict with '#include <smp/atomic.h>'.
Change-Id: I7413406ca69e78e5a6e539a01e05033243107272
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This patch replaces the use of the deprecated
cbfs_locate_file_in_region() API with the new
cbfs_unverified_area_map().
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: If4855280d6d06cf1aa646fded916fd830b287b30
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This patch adds a new ..._unverified_area_... group of functions to the
cbfs_map/_load/_alloc() APIs. These functions can be used to access
custom FMAP sections and are meant to replace the existing
cbfs_locate_file_in_region(). The name is intended to highlight that
accesses through this API will not be verified when CBFS_VERIFICATION is
enabled and should always be treated as if they may return malicious
data. (Due to laziness I'm not adding the combination of this API with
the ..._type_... variant at this point, since it seems very unlikely
that we'll ever have a use case for that. If we ever do, it should be
easy to add later.)
(Also remove the 'inline' from cbfs_file_hash_mismatch(). I'm not sure
why I put it there in the first place, probably a bad copy&paste.)
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I402265900f7075aa0c2f58d812c67ea63ddf2900
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Adding USB addressmap for sc7280.
Use common USB driver for sc7280.
BUG=b:182963902
TEST=Validated USB enumeration on qcom sc7280 development board
Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
Change-Id: Ib92b74c8035a8c0148a9aa48e7870b261b832a33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Add common USB driver for qualcomm soc sc7180 and sc7280.
This includes dwc3 controller, qmp ss phy, qusb hs phy and snsp hs phy.
BUG=b:182963902
TEST=Validated USB enumeration on qcom sc7180 and
sc7280 development board
Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
Change-Id: I1013ded22855286220cfa747cb25418070fe85a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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When using 32 bit PCI accesses in lpc_enable_port80, we can use the
LPC_IO_OR_MEM_DECODE_ENABLE and DECODE_IO_PORT_ENABLE4 defines and don't
need to re-define bits with offsets from the beginning of the third byte
within this 32 bit register. This allows to drop the
LPC_IO_OR_MEM_DEC_EN_HIGH register definition which points to
LPC_IO_OR_MEM_DECODE_ENABLE + 2 and to drop the re-definitions of the
bit re-definitions with a different offset.
The code in lpc_enable_port80 was originally copied from sb/amd/agesa/
hudson/early_setup.c which might be sort-of a copy from what the AGESA
reference code does.
TEST=When commenting out SOC_AMD_COMMON_BLOCK_USE_ESPI in the Kconfig of
Mandolin and selecting AMD_LPC_DEBUG_CARD, all POST codes still get
shown on the POST code LED display when this patch is applied.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I001bb1c2ccf99e36d4fbd73d3bf96b78ddb87d67
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This function is unused and none of the SoCs using this code has a
physical PCI interface any more, so drop this function.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia5c5a8ec29264a075fefe75038ef2a84684d6427
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This will enable preloading the microcode. By preloading the
file, into cbfs_cache we reduce boot time.
BUG=b:179699789
TEST=Boot guybrush with CL chain and see microcode preloading and a
reduction of 1 ms.
| 112 - started reading uCode | 1.041 | 1.204 Δ( 0.16, 0.01%) |
| 113 - finished reading uCode | 1.365 | 0.011 Δ( -1.35, -0.10%) |
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If0c634c692c97769e71acd1175fc464dc592c356
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This will allow us to preload the dsdt.aml file.
BUG=b:179699789
TEST=Build guybrush
| 80 - write tables | 1.564 | 1.08 Δ( -0.48, -0.03%) |
| 85 - finalize chips | 15.483 | 13.543 Δ( -1.94, -0.14%) |
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ibf69ecb947811a2eec861018e3ba5f858155f1c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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PSP_MAILBOX_BAR is defined as PCI_BASE_ADDRESS_4, so use it instead of
PCI_BASE_ADDRESS_4 in the code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8658b674b9adea85dfc71d7036ccf3ae17464b58
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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PSPV2_STATUS_ERROR and PSPV2_STATUS_RECOVERY aren't used and the bit
definitions are also wrong, so drop those defines. For the PSP mailbox
interface version 2, struct pspv2_mbox is used to access the correct
status bits.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8e2aadfde00e2f7b0f99b462b8e3d6954959a584
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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There are no quad-core CPU models with fam14, \_SB.C002 and .C003 get
removed from ASL.
Change-Id: I96df5b3f93c2dd6a05d5693069b991ca01f71d73
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The checking register will be cleared after EC resets, so we move
bustracker dump from ramstage to bootblock, before triggering EC reset.
TEST=bustracker shows status before watchdog resets
BUG=b:207743045
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ic18dc9742cd9f657a035a374e28371dfc5f04ac3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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There will be no log in cbmem if we trigger ec reset on bootblock
stage. Therefore, call dcache_clean_all() before triggering ec
reset to flush cache to store logs on cbmem.
BUG=b:207743045
TEST=show logs on cbmem
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I1bd900beb4cc84f7121c5fb66907fa73b62517fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Add Alder Lake-N specific CPU, System Agent, PCH (Alder Point aka ADP),
IGD device IDs.
Document Number: 619501, 645548
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I0974fc6ee2ca41d9525cc83155772f111c1fdf86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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The patch enables cse_fw_sync() before DRAM initialization.
cse_fw_sync() sends HECI commands in order to set CSE's boot partition
and to trigger CSE firmware update.
As part of CSE firmware update, coreboot sends HMRPFO_ENABLE HECI
command. Since CSE supports the command after DRAM Initialization,
cse_fw_sync() is called after DRAM initialization.
Starting from CSE Litev16.0.15.1545, CSE support HMRFPO_ENABLE command
before DRAM initialization too. So, cse_fw_sync() is called before DRAM
initialization.
BUG=b:175516533
TEST=Dependency with CSE Litev16.0.15.1545 integration
Change-Id: Iad7403650df8bc4e40aa6e48ccfeba95a5789a2d
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55364
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch renames X86_AMD_INIT_SIPI Kconfig to leverage
the same logic (to skip 2nd SIPI and reduce delay between
INIT and SIPI while perform AP initialization) even on
newer Intel platform.
Change-Id: I7a4e6a8b1edc6e8ba43597259bd8b2de697e4e62
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56651
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add prompt string to allow selecting MTK_DFD manually.
TEST=Select and enable MTK_DFD then successfully built firmware images.
BUG=b:207450135
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ied711321efa592cf1bf7b318fe4d0aa155c15c70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Rename pcicfg to pci_map_bus and add prototype for the platforms not
supporting ECAM.
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Id9517c5ec4fa6b7c7a34552bfdc6d509927f6730
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Only scan one device if it's a PCIe downstream port.
A PCIe downstream port normally leads to a link with only device 0 on
it. As an optimization, scan only for device 0 in that case.
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Id184d03b33e1742b18efb3f11aa9b2f81fa03806
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
Change-Id: Ia65b1873f1d184b8b8c64a61a26820ae0900437d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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There was a duplicate PCI 0:14.4 device in ASL. Only
keep one.
Change-Id: I21af7bdf64ef8a2d31a3452b32bc4a18f8d2df98
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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There was a duplicate PCI 0:14.4 device in ASL. Only
keep one.
There are no PCI devices 0:2.0 or 0:3.0 on fam14 northbridge
for graphics. There are no PCIe root ports 0:9.0 or 0:a.0.
Change-Id: Ifa8abb851f8ae4863b2c6d52224d287fd272048d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The section is the same and at root scope.
Change-Id: I3b3ff2fddc7d4db09903151bcb92e3e1b5dc7d69
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The SMMSTORE_IN_CBFS option was just meant as a workaround for an
attempt to backport SMMSTORE into older Chromebooks that never actually
happened. All current and future users of coreboot should be using
SMMSTORE in an FMAP region. The APIs needed for SMMSTORE_IN_CBFS clash
with the CBFS rdev isolation needed for CBFS_VERIFICATION, so let's just
get rid of it.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ia0604a4ffd20b46774631d585925311b65d5a0e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59680
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Dumped using inteltool from the Dell BIOS version A30.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ifdc41a1e6627b68813fb264aed7e30df58fc6d54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59525
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Disable PS/2 data and clock isolation in order to properly initialize
the PS/2 keyboard and mouse in payload/OS. These bits are set by OS via
ACPI and can survive S5 state. It is necessary to clear them after an
ungraceful shutdown in order to perform PS/2 controller initialization
e.g. in SeaBIOS.
TEST=PS/2 keyboard can always be successfully initialized in SeaBIOS
on Dell OptiPlex 9010
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Iac6be095c996b357b5d4e8d75199f94a89bf73e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59673
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Disable PMEs and clear global PME status to avoid undesired wakeups
or hangs in later stages. These bits are set by OS via ACPI can survive
S5 state so it is necessary to set them back to defaults after an
ungraceful shutdown.
TEST=Dell OptiPlex 9010 does not hang anymore after ungraceful shutdown
when configuring GPE0_EN register in southbridge LPC init
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I790cac3ce1101565b64ed54d9c6b50f5e9aa4cf6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59524
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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IA32_FEATURE_CONTROL does not need to be checked by BIOS, in fact these
bits are needed only by SENTER and SINIT ACM. ACM ENTERACCS does not
check these bits according to Intel SDM. Also noticed that the lock bit
of IA32_FEATURE_CONTROL cannot be cleared by issuing neither global
reset nor full reset on Sandybridge/Ivybridge platforms which results
in a reset loop. However, check the IA32_FEATURE_CONTROL SENTER bits in
ramstage where the register is properly set on all cores already.
TEST=Run ACM SCLEAN on Dell OptiPlex 9010 with i7-3770/Q77
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ie9103041498f557b85019a56e1252090a4fcd0c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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There is no real code or feature dependency on
CPU_INTEL_FIRMWARE_INTERFACE_TABLE for Intel TXT.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I2858c8de9396449a0ee30837a98fab05570a6259
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Although TXT specification says to do power cycle reset if TXT_RESET
is set, all Intel provided implementations issue a global reset here.
TEST=Perform ungraceful shutdown after SENTER to trigger SCLEAN path
on Dell OptiPlex 9010 and successfully call ACM SCLEAN.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I8ee2400fab20857ff89b14bb7b662a938b775304
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Allow to set global reset bits on other platforms which enable
SOUTHBRIDGE_INTEL_COMMON_ME. In certain Intel TXT flows global reset
instead of full power cycle reset is needed.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I561458044860ee5a26f7d61bcff1c407fa1533f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Currently there is only a function that dumps GETSEC CAPABILITIES.
Add dumping GETSEC PARAMETER for completeness and additional debug
information.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I3b2c8337a8d86000a5b43788840d15146b662598
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Region device is no longer used to locate BIOS ACM. Use new CBFS API
to map and unmap the file. Using rdev_munmap on the uninitialized
region device variable causes the platform to jump to a random address.
TEST=Dell OptiPlex 9010 does not raise #UD exception when Intel TXT is
enabled, ACM SCHECK is successful
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I98afba35403d5d2cd9eeb7df6d1ca0171894e9d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Implement the chipset production fuse state reporting as described in
the Intel TXT Software Development Guide. Also fix all occurrences
where the production fuse state is checked.
TEST=Dell OptiPlex 9010 with i7-3770/Q77 reports the chipset is
production fused
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ic86c5a9e1d162630a1cf61435d1014edabf104b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59514
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Following coreboot's convention, return negative error codes from
platform_i2c_transfer().
BUG=none
TEST=emerge-asurada coreboot
BRANCH=none
Change-Id: I955b9aae11e20d75fac414d15714330e364dad2f
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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TXT BIOS Data region version is checked by Trusted Boot code. Older
versions of TBoot (e.g. 1.8.2) may refuse to set up the MLE if BDR
version is not known. Provide an option to set the BDR version in
case an older TBoot code is used. This is very useful for platforms
with TPM 1.2.
TEST=Set BDR version to 4 and successfully boot QubesOS 4.0 with
TBoot 1.8.2 on Dell OptiPlex 9010
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ic2550bd4008559bd47de9e35f8b1c7b52e6e0f5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Include DPR in the memory map calculations if enabled. DPR is required
for Intel TXT support.
TEST=Boot Debian 10 and see the DPR memory being reserved in E820 and
cbmem logs:
"BIOS-e820: [mem 0x000000007fc09000-0x00000000829fffff] reserved"
"TSEG base 0x80000000 size 8M"
"DPR base 0x7fd00000 size 3M"
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ia22e49ba58709acfa0afe0921aa71d83cc06c129
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59512
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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We need to report error while rtc_xosc_write() returns false.
TEST=error logs for RTC disappear
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I5fdf4de0383ef373dd45e8d8741aa861c9c4bdc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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There is no support for SD card on Corsola reference board, so
we add a configuration to disable SD card initialization to
prevent setting GPIOs in a mistaken way.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ia05fd046335c6ce6f9198ddbb7cbda2afc6ae3cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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On Chromebooks the RAM code is implemented by the resistor straps
that we can read and decode from ADC. For Corsola the RAM code can be
read from ADC channel 2 and 3.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I485c32dec7b425b604b4063d742a0e37d3961513
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Raise little CPU to 2GHz at romstage.
TEST=check little core cpu frequency is 2GHz
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: If4c983d15beb2b588230f3db7416cb767b29978d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Add VPROC12/VSRAM_PROC12 to adjust power for raising little
CPU frequency.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I59b4627220022a51a116716036a8ba0048039508
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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The types of pwrap_read_field()'s return value and pwrap_write_field()'s
`val` argument are u16, so correct the usage in MT6366.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ie05ab65ecd9b8ea1379ef74393285c4f5d2db8a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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To raise little CPU frequency, add support for VPROC12 and VSRAM_PROC12 of MT6366.
TEST=build pass
BUG=b:202871018
Signed-off-by: James Lo <james.lo@mediatek.corp-partner.google.com>
Change-Id: I718fdf36d34969a6e21ddc8c1ec6f525e0e20904
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Configure Chromebook specific GPIOs, including EC_AP_INT,
EC_IN_RW, GSC_AP_INT, EN_SPK, GPIO_AP, and GPIO_RESET.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I76bde75788889111c0a051eed731dadc9898c0e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Some boards with the chrome EC will need to support more than 4
temperature sensors, so modify the number of TSRs supported when
generating the ACPI code. Note that the EC memory map already has
support for up to 16 TSRs, so no change is required on the EC
side.
BUG=b:207585491
TEST=with previous patch and some test data in brya0 overridetree.cb,
dump the SSDT and verify that all of the existing Methods for TSR0-TSR3
are also added for TSR4, as well as all Notify, etc.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Id002230bc872b0f818b0bf2b87987298189c973d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59633
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Some boards may use more than 4 temperature sensors for DPTF thermal
control, so this patch adds support for one more temperature sensor.
BUG=b:207585491
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ibf9666bade23b9bb4f740c6c4df6ecf5227cfb45
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Kano EVT will exchange i2c port for touchscreen and cr50.
BUG=b:195853169
TEST=build pass
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I500f0721689ca66b65b8fb1deb79bef2bd988465
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Reveal watchdog status value on bootblock stage.
BUG=b:207646327
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I2c5ad222a41085616565dd5c10b0e967bb64ec63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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In different sku, some unused GPIO pins are processed by NC for power
consumption.
BUG=b:196790249
TEST=emerge-brya coreboot chromeos-bootimage and check power
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I753e41dec1825299e6cd437b5f67e2d957bc6148
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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