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2021-03-22soc/amd/cezanne: Get I2C specific code for cezanneZheng Bao
Add macros, settings and callbacks to support I2C for cezanne. Change-Id: Ic480681d4b7c6fb8591e729090e4faeb5fccf800 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-22trivial: Fix the tab and rearrange the linesZheng Bao
Change-Id: I1ded9fcec9594977b9b9c8d3c105f9998c0ee2bc Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51656 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22mb/amd/majolica: Set IOMUX to enable I2C2 & I2C3Zheng Bao
Change-Id: I142c06c150214d58acc04b8c6b3b027fff0256db Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2021-03-22soc/amd/common/block/i2c: Move SoC agnostic parts into commonKarthikeyan Ramasubramanian
The logic behind I2C bus initialization, I2C MMIO base address getter and setter, I2C bus ACPI name resolution are identical for all the AMD SoCs. Hence moving all the SoC agnotic parts of the driver into the common driver and just configure the SoC specific parts into individual I2C drivers. BUG=None TEST=Build Dalboz and Grunt. Boot to OS in Dalboz. Ensure that the I2C peripherals are detected as earlier in Dalboz. Verify some I2C peripheral functionality like trackpad and touchscreen. Change-Id: Ic9c99ec769d7d8ad7e1e566fdf42a5206657183d Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Suggested-by: Kyosti Malkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51509 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22soc/amd/common: Introduce I2C driver common to all AMD SoCsKarthikeyan Ramasubramanian
I2C driver is replicated in each generation of AMD SoCs. Introduce a common I2C driver that can be used across all the AMD SoCs. To begin with, peripheral reset functionality is moved into this common driver. SoC specific I2C driver passes the SCL pin configuration in order for the common driver to reset the peripherals. More functionality can be moved here in subsequent changes. Also sb_reset_i2c_slaves() is renamed as sb_reset_i2c_peripherals() as an effort towards using inclusive language. BUG=None TEST=Build Dalboz and Grunt. Boot to OS in Dalboz. Ensure that the I2C peripherals are detected as earlier in Dalboz. localhost ~ # i2cdetect -y 0 Warning: Can't use SMBus Quick Write command, will skip some addresses 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 10: 20: 30: -- -- -- -- -- -- -- -- 40: 50: 50 51 -- -- -- -- -- -- 58 59 -- -- -- -- -- -- 60: 70: localhost ~ # i2cdetect -y 1 Warning: Can't use SMBus Quick Write command, will skip some addresses 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 10: 20: 30: -- -- -- -- -- -- -- -- 40: 50: UU -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60: 70: Change-Id: I9f735dcfe8375abdc88ff06e8c4f8a6b741bc085 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Suggested-by: Kyosti Malkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-22soc/mediatek/mt8192: devapc: Add SCP domain settingTinghan Shen
Configure SCP domain from 0 to 3 and lock it to prevent changing it unexpectedly. BUG=b:163300760 TEST=emerge-asurada coreboot BRANCH=asurada Change-Id: Idccb001f0cf58492f7f1655203106470637b9b82 Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-03-20soc/intel/xeon_sp/cpx: Set PCU locksMarc Jones
Set the PCU locks as indicated by the BWG. Lock the following: P_STATE_LIMITS PACKAGE_RAPL_LIMIT SAPMCTL DRAM_PLANE_POWER_LIMIT CONFIG_TDP_CONTROL Change-Id: I5f44d83e2dd8411358a83b5641ddb4c370eb4e84 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51505 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-20soc/intel/xeon_sp/: Fix SMI_LOCK settingMarc Jones
Move the SMI_LOCK to post SMM setup. Also, use the correct access method for SMI_LOCK. GEN_PMCON_A is in PCI config space and not in MMIO space on this PCH. Change-Id: Ibbb183ef61ca7330198c1243ecfc2d4df51e652b Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51452 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-20mainboard/: Register chipset_lockdown on xeon_sp mainboardsMarc Jones
Set chipset_lockdown in devicetree for recommended security settings. Change-Id: Ie27450dd32463243b1456932a1d39d40afa81da1 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51388 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-20soc/intel: Drop unused `GPIO_NUM_GROUPS` macroAngel Pons
This macro is unused and its value is often wrong. Drop it. Change-Id: Id3cfaa4d2eef49eddc02833efbe14e0c5c816263 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51662 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-20mb/purism/librem_cnl: Add new board/variant Librem 14Matt DeVillier
Add support for the CometLake-U based Librem 14 laptop. Change-Id: I24a2a92091cc272638ecaf8ea23a896cab8a7153 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51549 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-20google/trogdor: Add new variant MarzipanKevin Chiu
This patch adds a new variant called Marzipan that is identical to Lazor for now. BUG=b:182181519,b:182018606 BRANCH=master TEST=make Change-Id: I92b667c63b0a06255d1e9511d7486293d8b4426a Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-03-20mb/google/trogdor: Add support for SPI_FLASH_GIGADEVICExuxinxiong
Add support SPI_FLASH_GIGADEVICE for some project. BUG=b:182246432 BRANCH=trogdor TEST=emerge-strongbad and test with power on. Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com> Change-Id: I6ab948909f4e17b4b992be6d699646f7a62bef7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-03-19mb/lenovo/x200: Fix boot-time docking stateKevin Keijzer
The X200 would undock itself when waking up from S3, requiring a physical reconnection before the dock would work again. Similar to 4611ad8, this reintroduces h8_mb_init() for the X200. A hook function h8_mb_init() will be called at the end of h8_enable(), in place of the ancient h8_mainboard_init_dock(). This should fix the regression the X201 and T410 also suffered from for the X200. Change-Id: Icb6dd145e56b90e0e04133810c5e9ac7b641ad68 Signed-off-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51123 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19mb/scaleway/tagada: Don't change FIAMUX when Security Override is setJulien Viard de Galbert
This will not enable M.2 SATA drive if the ME config was lost (For instance after flashing a full flash factory image) This is required so that the system can boot without FIA MUX error during flash update procedure. Change-Id: I55a8bcdc30bc67af2d3e9ccb8844eac599727108 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/25443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19security/intel/cbnt: Make CBNT compatible with CMOS option tableArthur Heymans
Make sure the bytes in RTC cmos used by CBNT don't collide with the option table. This depends on what is set up in the BPM, Boot Policy Manifest. When the BPM is provided as a binary the Kconfig needs to be adapted accordingly. A later patch will use this when generating the BPM. Change-Id: I246ada8a64ad5f831705a4293d87ab7adc5ef3aa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-03-19cpu/x86/mp_init.c: Drop unnecessary preprocessor usageArthur Heymans
Change-Id: If67bcbf0c8ffbd041e2e4cab8496f4634de26552 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19cpu/x86/mp_init.c: Don't overwrite the global variable per CPUArthur Heymans
Global variables are located in .bss and not on the CPU stack. Overwriting them a per CPU case is bound to cause race conditions. In this case it is even just plainly wrong. Note: This variable is set up in the get_smm_info() function. Change-Id: Iaef26fa996f7e30b6e4c4941683026b8a29a5fd1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19cpu/x86/smm_module_loaderv2.c: Remove noop stack size checkArthur Heymans
The argument provided to the function was always the same as the one computed inside the function so drop the argument. Change-Id: I14abf400dce1bd9b03e401b6619a0500a650fa0e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19cpu/x86/mp_init: Allow stub sizes larger than the save state sizeArthur Heymans
The permanent handler module argument 'save_state_size' now holds the meaning of the real save state size which is then substracted from the CPUs save state 'top' to get the save state base. TESTED with qemu Q35 on x86_64 where the stub size exceeds the AMD64 save state size. Change-Id: I55d7611a17b6d0a39aee1c56318539232a9bb781 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19cpu/x86/smm_loaderv2: Remove unused variablesArthur Heymans
Remove variables that are either constants or are just assigned but not used. Change-Id: I5d291a3464f30fc5d9f4b7233bde575010275973 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19cpu/x86/smm/smm_module_loaderv2.c: Constify setup_stub()Arthur Heymans
Change-Id: I6648d0710bc0ba71cfbaaf4db7a8c1f33bbc9b35 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19cpu/x86/smm_module_hander: Set up a save state mapArthur Heymans
With the smm_module_loaderv2 the save state map is not linear so copy a map from ramstage into the smihandler. TESTED on QEMU q35: Both SMMLOADER V1 and V2 handle save states properly. Change-Id: I31c57b59559ad4ee98500d83969424e5345881ee Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50769 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19cpu/x86/smm_loaderv2: Fix when only 1 CPU is presentArthur Heymans
Move out smm_create_map as this was not run if concurrent_save_states is 1. The cpus struct array is used in the smm_get_cpu_smbase() callback so it is necessary to create this. TEST: run qemu/q35 with -smp 1 (or no -smp argument) Change-Id: I07a98bbc9ff6dce548171ee6cd0c303db94087aa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50783 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19cpu/x86/smm_stub.S: Drop smm_runtime from the stubArthur Heymans
The parameters that the permanent handler requires are pushed directly to the permanent handlers relocatable module params. The paremeters that the relocation handler requires are not passed on via arguments but are copied inside the ramstage. This is ok as the relocation handler calls into ramstage. Change-Id: Ice311d05e2eb0e95122312511d83683d7f0dee58 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-03-19cpu/x86/smm.h: Remove smm runtime pointer from smm_loader_paramsArthur Heymans
struct smm_loader_params is a struct that is passed around in the ramstage code to set up either the relocation handler or the permanent handler. At the moment no parameters in the stub 'smm_runtime' are referenced so it can be dropped. The purpose is to drop the smm_runtime struct from the stub as it is already located in the permanent handler. Change-Id: I09c1b649b5991f55b5ccf57f22e4a3ad4c9e4f03 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19cpu/x86/mp_init.c: Copy the stub parameter start32_offset into ramstageArthur Heymans
Keep a copy of start32_offset into ramstage to avoid needing to pass arguments, calling from assembly. Doing this in C code is better than assembly. Change-Id: Iac04358e377026f45293bbee03e30d792df407fd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50765 Reviewed-by: Eugene Myers <cedarhouse1@comcast.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19cpu/x86/smm_module_handler: Add relocatable module paramsArthur Heymans
Instead of passing on parameters from the stub to the permanent handler, add them directly to the permanent handler. The parameters in the stub will be removed in a later patch. Change-Id: Ib3bde78dd9e0c02dd1d86e03665fa9c65e3d07eb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19cpu/intel/fit: Reserve the FIT pointer using a .c fileArthur Heymans
No need to do this assembly anymore. Change-Id: I69b42c31e495530fe96030a5a25209775f9d4dca Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-03-19cpu/intel/fit: Add the FIT table as a separate CBFS fileArthur Heymans
With CBnT a digest needs to be made of the IBB, Initial BootBlock, in this case the bootblock. After that a pointer to the BPM, Boot Policy Manifest, containing the IBB digest needs to be added to the FIT table. If the fit table is inside the IBB, updating it with a pointer to the BPM, would make the digest invalid. The proper solution is to move the FIT table out of the bootblock. The FIT table itself does not need to be covered by the digest as it just contains pointers to structures that can by verified by the hardware itself, such as microcode and ACMs (Authenticated Code Modules). Change-Id: I352e11d5f7717147a877be16a87e9ae35ae14856 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50926 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19soc/amd/picasso/soc_util.c: Fix typo in macro nameAngel Pons
Change-Id: I3225fa4e53a75c2bf6fe0dcea85db57efe489482 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51615 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19mb/google/volteer/var/elemi: Config GPP_B7/GPP_B8 as NCWisley Chen
elemi does not use the GPP_B7/GPP_B8, so config to NC. Currently, there is no functional impact. BUG=b:182981460 TEST=emerge-volteer coreboot, boot into OS, and suspend/resume successfully. Change-Id: I7b491fd595b0e77e6dcce08e3172dbe592f63c37 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-03-19soc/intel/tgl: Add configurable value for PmcUsb2PhySusPgEnableDerek Huang
PmcUsb2PhySusPgEnable is enabled by default. Expose devicetree parameter to disable Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com> Change-Id: Ibd54a10c57d39bb8762b705ef0d6ff4cd47f0d89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-03-19mb/purism/librem_cnl: drop MAX_CPUS from KconfigMatt DeVillier
No need to restrict this further than the platform default, and will be problematic with the addition of the upcoming 6C/12T Librem 14 board. Change-Id: I1913992ec12578e1ad3bf6bf679d1a35a46d7370 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19mb/{clevo/cml-u,system76/lemp9}: Clarify `gen2_dec` useAngel Pons
This I/O range is for a PM channel on the EC, not the PCH PMC. Change-Id: I64422e537c1edcd0673cf87f16139fb117b10e75 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51604 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19nb/intel/haswell: Consolidate memory-down SPD handlingAngel Pons
Mainboards do not need to know about `pei_data` to tell northbridge code where to find the SPD data. Adjust `mb_get_spd_map` to take a pointer to a struct instead of an array, and update all the mainboards accordingly. Currently, the only board with memory-down in the tree is google/slippy. Mainboard code now obtains the SPD index in `mb_get_spd_map` and adjusts the channel population accordingly. Then, northbridge code reads the SPD file and uses the index that was read in `mb_get_spd_map`, and copies it to channel 0 slot 0 unconditionally. MRC only uses the first position of the `spd_data` array, and ignores the other positions. In coreboot code, `setup_sdram_meminfo` uses the data of each SPD index, so `copy_spd` has to account for this. Tested on Asrock B85M Pro4, still boots and still resumes from S3. Change-Id: Ibaed5c6de9853db6abd08f53bbfda8800d207c3e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51448 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19mb/google/slippy: Correct memory-down SPD handlingAngel Pons
MRC only uses the SPD data for the first index, and ignores the rest. Moreover, index 1 corresponds to the second DIMM on the first channel, which does not exist on ULT (only one DIMM per channel is supported). Copy the SPD to the first DIMM on channel 1 instead. Adjust northbridge code to retrieve the serial number from the correct SPD data block. Tested on Google Wolf, both channels are still correctly detected. Change-Id: Ic60ff75043e6b96a59baa9e5ebffb712a100a934 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-18mb/google/brya: Implement SLP_S0_GATE signalTim Wawrzynczak
The SLP_S0_GATE# signal is used in conjunction with the PCH's SLP_S0# to provide an indication to the rest of the platform when the system is entering its software-initiated low-power state (i.e. S0ix). This lets the platform distinguish between opportunistic S0ix entry and the runtime suspend mechanism. BUG=b:180401723 TEST=abuild Change-Id: I7fe2e3707465778baf56283617a8485a94f2dbca Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50881 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18vc/google/chromeos/acpi: Add type to OIPG declarationRaul E Rangel
OIPG is a Package. Define the type so it doesn't default to UnknwonObj. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I068ed4ae95967aa884506c4971ee2e2dba7b5e4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51537 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18mb/amd/majolica: Generate OIPG PackageRaul E Rangel
This fixes the unknown reference errors for OIPG. Since Majolica doesn't actually have any of the GPIOs ChromeOS uses, we leave the arrays empty. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifeae84e0ccab187a4e7131cd6ea9e1336d79df67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51536 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18mb/google/guybrush: Add eSPI GPIO back to init tableMathew King
GPIOs should be configured in ramstage even if they are configured in an earlier stage. BUG=b:180721208 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I9896db41dbe2812856357510bc4420482e73ab3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51547 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18mb/google/guybrush: Configure UART0 gpio in early stageMathew King
BUG=b:180721208 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I8aa54acf1fa9295b27c33a0066432665e6e3755c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-03-18soc/amd/common: Make fch_spi_config_modes staticMathew King
It is currently only used in this translation unit. Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Ib779a38306fb45320f3e4eb71f63630023d59906 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51535 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18mb/ocp/deltalake: Initialize VPD 'coreboot_uart_io' with default value 1Johnny Lin
In case the VPD variable cannot be read. Change-Id: I79fae6f4b4aad91a4040387ca6ddee8dfcc34d90 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51559 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18mb/google/mancomb: Configure eSPI GPIOs in early stageEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ifa51705b3b5aab16f9cd2c11084220aafacd2774 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-18mb/google/mancomb: Configure early GPIOs in earliest stageEric Lai
Configure early GPIOs in verstage if it is run in PSP otherwise configure them in bootblock. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ic1faeea59462319c1652c69034b4dde01669e13b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-18mb/google/mancomb: Enable internal graphics deviceEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I0f5026b77513118a6c21eca78c9788c0bdc7ec6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-18mb/google/mancomb: Enable verstageEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ic07a3ac556637919742fcbe899ee3fdfac38bb94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-18mb/google/zork/var/shuboz: adjust telemetry settingsKane Chen
According to stardust test tracking report to adjust telemetry setting. VDD Slope : 30518 -> 30595 VDD Offset: 435 -> 77 SOC Slope : 22965 -> 24063 SOC Offset: 165 -> 105 BUG=b:182399760 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Ie7e6af77bdaad6cc964ac206a69ccb854aae869f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-03-18mb/prodrive/hermes: Disable HDA codec Port E by default on R04+Angel Pons
If the board settings aren't valid, Port E uses the settings for earlier board revisions, which is undesired. Disable Port E by default on R04+. Change-Id: I03bd50b915a2120283b77179debaa735bb7ef027 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51529 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18cpu/x86/mp_init.c: Calculate perm_smbase from ramstage dataArthur Heymans
The data needed to compute the permanent smbase for a core, when relocating, is present in the ramstage data which the stub located at DEFAULT_SMBASE (0x30000) calls back to. There is no need to fetch this from via the stub params. Change-Id: I3894c39ec8cae3ecc46b469a0fdddcad2a8f26c4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50763 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18cpu/x86/smm: Move apic_id_to_cpu map to smm_stub paramsArthur Heymans
This is only consumed by the stub and not by the relocation handler or the permanent handler, so move it out of the runtime struct. Change-Id: I01ed0a412c23c8a82d88408be058a27e55d0dc4d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-18cpu/x86/smm_stub.S: Drop unused module_handler parameterArthur Heymans
Change-Id: I15b433483c36cce04816e8895789997d91702484 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-03-18cpu/x86/smm: Move relocatable stub paramsArthur Heymans
These stub params need to be synced with the code in smm_stub.S and are consumed by both the smmloader and smmloader_v2. So it is better to have the definition located in one place. Change-Id: Ide3e0cb6dea3359fa9ae660eab627499832817c9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50761 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18cpu/qemu-x86: Add an option to use the smmloader v2Arthur Heymans
The idea is to get rid of having 2 different smmloaders so add this option only to qemu/q35 to get it buildtested. Change-Id: Id4901784c4044e945b7f258b3acdc8d549665f3a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51525 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18mb/emulation/qemu-q35: Add support for SMM_TSEG with parallel MP initArthur Heymans
Tested with and without -enable-kvm, with -smp 1 2 and 32. Change-Id: I612cebcd2ddef809434eb9bfae9d8681cda112ef Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48262 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18soc/intel/block/cpu/mp_init.c: Remove weak functionsArthur Heymans
All platforms implement those and using a no-op function is not expected, so it is better to fail the build if the soc specific code is not implemented. Change-Id: Id946f5b279dcfa6946381b9a67faba6b8c1ca332 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51522 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18soc/amd/cezanne/pci_gpp: Add ACPI names for GPP bridgesRaul E Rangel
We are currently writing invalid ACPI tables. We are missing the GPP ACPI names. There is an assert in acpi_device_write_pci_dev that checks to see if we have a scope, but by default asserts don't halt, so we were writing a NULL scope. BUG=b:171234996 TEST=Boot majolica and dump ACPI tables Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I6a861ad1b9259ac3b79af76e18a9354997b0491e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-17spd_bin: Replace get_spd_cbfs_rdev() with spd_cbfs_map()Julius Werner
In pursuit of the goal of eliminating the proliferation of raw region devices to represent CBFS files outside of the CBFS core code, this patch removes the get_spd_cbfs_rdev() API and instead replaces it with spd_cbfs_map() which will find and map the SPD file in one go and return a pointer to the relevant section. (This makes it impossible to unmap the mapping again, which all but one of the users didn't bother to do anyway since the API is only used on platforms with memory-mapped flash. Presumably this will stay that way in the future so this is not something worth worrying about.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Iec7571bec809f2f0712e7a97b4c853b8b40702d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-17amd: refcode_loader: Switch to new CBFS APIJulius Werner
This patch rewrites some parts of the Agesa refcode loader to eliminate the passing of raw rdevs between functions, so that we can get rid of cbfs_boot_locate() in favor of more high-level APIs. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I2a6e1158ed7425c69c214462bc52e8694a69997a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-17cbfs: Replace more instances of cbfs_boot_locate() with newer APIsJulius Werner
In pursuit of the eventual goal of removing cbfs_boot_locate() (and direct rdev access) from CBFS APIs, this patch replaces all remaining "simple" uses of the function call that can easily be replaced by the newer APIs (like cbfs_load() or cbfs_map()). Some cases of cbfs_boot_locate() remain that will be more complicated to solve. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Icd0f21e2fa49c7cc834523578b7b45b5482cb1a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-17cbfs: Move stage header into a CBFS attributeJulius Werner
The CBFS stage header is part of the file data (not the header) from CBFS's point of view, which is problematic for verification: in pre-RAM environments, there's usually not enough scratch space in CBFS_CACHE to load the full stage into memory, so it must be directly loaded into its final destination. However, that destination is decided from reading the stage header. There's no way we can verify the stage header without loading the whole file and we can't load the file without trusting the information in the stage header. To solve this problem, this patch changes the CBFS stage format to move the stage header out of the file contents and into a separate CBFS attribute. Attributes are part of the metadata, so they have already been verified before the file is loaded. Since CBFS stages are generally only meant to be used by coreboot itself and the coreboot build system builds cbfstool and all stages together in one go, maintaining backwards-compatibility should not be necessary. An older version of coreboot will build the old version of cbfstool and a newer version of coreboot will build the new version of cbfstool before using it to add stages to the final image, thus cbfstool and coreboot's stage loader should stay in sync. This only causes problems when someone stashes away a copy of cbfstool somewhere and later uses it to try to extract stages from a coreboot image built from a different revision... a debugging use-case that is hopefully rare enough that affected users can manually deal with finding a matching version of cbfstool. The SELF (payload) format, on the other hand, is designed to be used for binaries outside of coreboot that may use independent build systems and are more likely to be added with a potentially stale copy of cbfstool, so it would be more problematic to make a similar change for SELFs. It is not necessary for verification either, since they're usually only used in post-RAM environments and selfload() already maps SELFs to CBFS_CACHE before loading them to their final destination anyway (so they can be hashed at that time). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I8471ad7494b07599e24e82b81e507fcafbad808a Reviewed-on: https://review.coreboot.org/c/coreboot/+/46484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-17program_loading: Replace prog_rdev() with raw start pointer and sizeJulius Werner
Since prog_locate() was eliminated, prog_rdev() only ever represents the loaded program in memory now. Using the rdev API for this is unnecessary if we know that the "device" is always just memory. This patch changes it to be represented by a simple pointer and size. Since some code still really wants this to be an rdev, introduce a prog_chain_rdev() helper to translate back to that if necessary. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: If7c0f1c5698fa0c326e23c553ea0fe928b25d202 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-17mb/google/kukui: Add new config 'cozmo'Lucas Chen
New board 'cozmo'. BUG=b:181144502 TEST=None BRANCH=kukui Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Change-Id: Ia0ec1d89444d2634bfcfb3475a422f4e4ae92b7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chen-Tsung Hsieh <chentsung@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-03-17mb/google/dedede/var/sasukette: Enable ALC1015 AMP (Auto Mode) driverwuweimin
Enable gpio mode driver for ALC1015 AMP Auto Mode. BUG=b:176956779 BRANCH=dedede TEST=ALC1015Q-VB drive speaker OK Change-Id: Iaa5650e120362e81fa36530f6a207c9c07e1139a Signed-off-by: wuweimin <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-17ipmi/ocp: Remove duplicate IPMI OEM command set processor informationJingleHsuWiwynn
IPMI OEM command set processor information has already been implemented in u-root payload: https://github.com/u-root/u-root/commit/efdc3a30ecca53e8b50b863969173969127fa384 Also this command has a higher chance to see BMC KCS timeout issue when coreboot log level is 4, which can be avoided if this command is run at a later stage such as LinuxBoot. Signed-off-by: JingleHsuWiwynn <jingle_hsu@wiwynn.com> Change-Id: If0081e5195cbd605e062723c197ac74343f79a13 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51276 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-17soc/intel/alderlake: Enable CSE Lite driver for ADL platform in romstageSridhar Siricilla
This patch sets up cse_fw_sync() call in the romstage. The cse_fw_sync() must be called after DRAM initialization. Test=Verified on Alderlake platform Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I6779f4a9e140deebf7f3cecd9fc5dac18813f246 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-17mb/google/dedede/var/lantis: Update DPTF parametersTony Huang
DPTF paramerters from thermal team. 1. PL2 =15W 2. Add TSR sensor charger, 5V regulator BUG=b:177249297 BRANCH=dedede TEST=build image and verified by thermal team. Change-Id: Ia5f6cc2a4564bb5558cbaca8daf31ee70145019f Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-17mb/intel/shadowmountain: Update HDMI audio mode to 8TSugnan Prabhu S
This patch sets the HDMI audio mode to 8T as required by the latest FSP version v2081_02 TEST: HDMI audio codecs detection is failing without this change. Change-Id: Ie5a825da7d199c9ee61e64d8f4ee7dec28fdaacd Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-03-17mb/intel/shadowmountain: Disable xDCISugnan Prabhu S
This patch disables the xDCI which is causing PC8 to PC10 state transitions during sleep. TEST: Confirmed that the transition is happening with this change. Change-Id: I9bbf7b52c36954600d7e66f9b03fad39b8881a5f Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2021-03-17sar: Fix semantics of `get_wifi_sar_cbfs_filename()`Furquan Shaikh
Currently, if `get_wifi_sar_cbfs_filename()` returns NULL, then `get_wifi_sar_limits()` assumes that the default filename is used for CBFS SAR file. This prevents a board from supporting different models using the same firmware -- some which require SAR support and some which don't. This change updates the logic in `get_wifi_sar_limits()` to return early if filename is not provided by the mainboard. In order to maintain the same logic as before, current mainboards are updated to return WIFI_SAR_CBFS_DEFAULT_FILENAME instead of NULL in default case. Change-Id: I68b5bdd213767a3cd81fe41ace66540acd68e26a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51485 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-17drivers/wifi, mb/google: Drop config `WIFI_SAR_CBFS`Furquan Shaikh
Now that SAR support in VPD is deprecated in coreboot, there is no need for a separate Kconfig `WIFI_SAR_CBFS` as the SAR table is only supported as a CBFS file. This change drops the config `WIFI_SAR_CBFS` from drivers/wifi/generic/Kconfig and its selection in mb/google/.../Kconfig. wifi_sar_defaults.hex is added to CBFS only if CONFIG_WIFI_SAR_CBFS_FILEPATH is not empty because current mainboards do not provide a default SAR file in coreboot. Thus, CONFIG_WIFI_SAR_CBFS_FILEPATH is updated to have a default value of "". BUG=b:173465272 Cq-Depend: chromium:2757781 Change-Id: I0bb8f6e2511596e4503fe4d8c34439228ceaa3c7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-17vc/google/chromeos: Deprecate support for SAR tables in VPDFurquan Shaikh
SAR table in VPD has been deprecated for Chrome OS platforms for > 1 year now. All new Chrome OS platforms have switched to using SAR tables from CBFS. This change drops the support for SAR table in VPD from coreboot to align with the factory changes. `get_wifi_sar_limits()` is thus updated to look for SAR file in CBFS only. Anyone building ToT coreboot for an already released Chrome OS platform with SAR table in VPD will have to extract the "wifi_sar" key from VPD and add it as a file to CBFS using following steps: - On DUT, read SAR value using `vpd -i RO_VPD -g wifi_sar` - In coreboot repo, generate CBFS SAR file using: `echo ${SAR_STRING} > site-local/${BOARD}-sar.hex` - Add to site-local/Kconfig: ``` config WIFI_SAR_CBFS_FILEPATH string default "site-local/${BOARD}-sar.hex" ``` BUG=b:173465272 Change-Id: I21d190dcc9f3554fab6e21b4498e7588a32bb1f0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-17vendorcode/mt8192: devapc: fix register offset for PCIe domainNina Wu
Correct the wrong offset for setting PCIe domain. Change-Id: I9de2bdf5a0a4fb5b34985b11976fd50b397e97ba Signed-off-by: Nina Wu <nina-cm.wu@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51512 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-17prog_loaders: Remove prog_locate()Julius Werner
This patch rewrites the last few users of prog_locate() to access CBFS APIs directly and removes the call. This eliminates the double-meaning of prog_rdev() (referring to both the boot medium where the program is stored before loading, and the memory area where it is loaded after) and makes sure that programs are always located and loaded in a single operation. This makes CBFS verification easier to implement and secure because it avoids leaking a raw rdev of unverified data outside the CBFS core code. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I7a5525f66e1d5f3a632e8f6f0ed9e116e3cebfcf Reviewed-on: https://review.coreboot.org/c/coreboot/+/49337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-17cbfs: Remove prog_locate() for payloads (SELF and FIT)Julius Werner
This patch removes the prog_locate() call for all instances of loading payload formats (SELF and FIT), as the previous patch did for stages. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I582b37f36fe6f9f26975490a823e85b130ba49a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49336 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-16cbfs: Remove prog_locate() for stages and rmodulesJulius Werner
This patch removes the prog_locate() step for stages and rmodules. Instead, the stage and rmodule loading functions will now perform the locate step directly together with the actual loading. The long-term goal of this is to eliminate prog_locate() (and the rdev member in struct prog that it fills) completely in order to make CBFS verification code safer and its security guarantees easier to follow. prog_locate() is the main remaining use case where a raw rdev of CBFS file data "leaks" out of cbfs.c into other code, and that other code needs to manually make sure that the contents of the rdev get verified during loading. By eliminating this step and moving all code that directly deals with file data into cbfs.c, we can concentrate the code that needs to worry about file data hashing (and needs access to cbfs_private.h APIs) into one file, making it easier to keep track of and reason about. This patch is the first step of this move, later patches will do the same for SELFs and other program types. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ia600e55f77c2549a00e2606f09befc1f92594a3a Reviewed-on: https://review.coreboot.org/c/coreboot/+/49335 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-16AGESA,binaryPI boards: Drop invalid MP table filesKyösti Mälkki
If we spot any error in the file, treat it as untested and broken copy-paste. Change-Id: Idd13b8b006fce7383f3f73c3c0a5d51a71c0155b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38313 Reviewed-by: Mike Banon <mikebdp2@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-16AGESA,binaryPI boards: Move IRQ table programmingKyösti Mälkki
IRQ programming should be done outside (obsolete) MP table generation. Change-Id: Ibce2af4de91549c4c9743cd997f625164672a713 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38564 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Mike Banon <mikebdp2@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-16mb/google/dedede/var/storo: Add USB Port ConfigurationZanxi Chen
Add USB Port into devicetree for storo BUG=b:177389444 BRANCH=dedede TEST=built firmware and verified USB3.0 function is OK Change-Id: I4d5160ff23d2bd386cb33164b580e6d6f3bf30fd Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-16vendorcode/mt8192: change to short log macro namesXi Chen
Originally, log macro names are too long, and they use double parentheses style: ((...)), which causes compile or runtime error easily. Now, change them to single parenthesis mode (...), and use shorter name. Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: I2959dc1ba0dd40a8fb954406072f31cf14c26667 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-03-16soc/mediatek/mt8192: adjust i2c "tLOW" and "tSU,STO"Daolong Zhu
The i2c actiming with the default reg setting cannot meet spec, so we need to set some regs. 1. adjust the ratio of SCL high and low level, to adjust "tLOW". 2. modify ext_conf reg to adjust "tSU,STO". BUG=b:179000159 TEST=Test on asurada (MT8192), boot pass, timing pass. Signed-off-by: Daolong Zhu <jg_daolongzhu@mediatek.corp-partner.google.com> Change-Id: Ifbe97edbc38972af5b782fb93342ee0616127dd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51024 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-16mb/google/dedede/var/blipper: Add camera supportZanxi Chen
Add camera support in devicetree and associated GPIO configuration. BUG=b:181729304 BRANCH=dedede TEST=built blipper firmware and verified camera function is OK Change-Id: I806ec207a454d4383aca093159553b7e618e16b2 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-16mb/google/dedede/var/blipper: Add codec and speaker amplifier supportZanxi Chen
Add audio codec and speaker amplifier support into devicetree BUG=b:181732574 BRANCH=dedede TEST=built blipper firmware and verified audio function is OK Change-Id: Id4633649b5e0595ed99a40ae35eb54b005154604 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-16mb/google/dedede/var/blipper: Enable touchscreen for blipperZanxi Chen
Add G2 and ELAN touchscreen into devicetree for blipper. BUG=b:181098785 BRANCH=dedede TEST=built blipper firmware and verified touchscreen function is ok Change-Id: Ie0bfc2972fc1a33a6f02495d3976b816209e956b Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-16mb/google/dedede/var/sasuke: Configure GPP_B7 as GPO_HIGHSeunghwan Kim
Configuring GPP_B7 as GPO_HIGH. Sasuke doesn't have SAR sensor, GPP_B7 is routed to the LTE module and is kept high so that the LTE module uses the default emission power. BUG=b:180492044 BRANCH=firmware-dedede-13606.B TEST="FW_NAME=sasuke emerge-dedede coreboot" Change-Id: Ib38c649830db2291b3a2a771f5c884acf37dcbeb Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51049 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-16vendorcode/mt8192: fix fast-k gating PI P1 initializationXi Chen
In RX Gating flow, PI P1 delay is missing, so re-add the initialization. Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: Ic72ccecd205062ee79f6928993fac772fc10f880 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-03-16vendorcode/mt8192: limit fast-k frequency count from 7 to 3Xi Chen
For bootup faster, fast-k elapsed time is improved by ~400ms. Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: Ifa945012aa66df4433fe63aab75a1e785d343d9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51406 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-16mb/google/asurada: fix boot failure when reading SKU IDHung-Te Lin
The SKU IDs also need mapping table when reading voltages. BUG=None BRANCH=asurada TEST=emerge-asurada coreboot Change-Id: Ice91961d6c33cfa27254221663edca1547c9ddcc Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-03-16mb/google/guybrush: Add initial fch irq routingMathew King
BUG=b:181972598 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I1abb070324254e21b03bfe00d6eee3b70120564c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-15mb/google/guybrush: Enable eSPI VW SCI eventsMathew King
Guybrush does not have a dedicated SCI pin so it uses VW. BUG=b:181134664 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I12fb7c23718ad2350478b89b321e9f0aa099e53b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51238 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/google/dedede/var/magolor: Fix DPTF passive and critical policiesKarthikeyan Ramasubramanian
Some of the temperature sensors defined in baseboard do not exist in magolor. With the format the DPTF policies are defined in magolor, all the entries from the baseboard are included and then the overrides applied. This causes the non-existent DPTF devices to be exported in the ACPI table and in turn OS reading invalid temperatures. Fix the format for DPTF passive and critical policies. BUG=None BRANCH=dedede TEST=Build and boot to OS in magolor. Ensure that the DPTF entries look correct in both static.c and SSDT tables i.e. passive and critical policies for applicable devices only are present. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I43f0b188e49e24657db055ce898ce159d499a22e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-03-15mb/google/dedede/var/madoo: Fix DPTF passive and critical policiesKarthikeyan Ramasubramanian
Some of the temperature sensors defined in baseboard do not exist in madoo. With the format the DPTF policies are defined in madoo, all the entries from the baseboard are included and then the overrides applied. This causes the non-existent DPTF devices to be exported in the ACPI table and in turn OS reading invalid temperatures. Fix the format for DPTF passive and critical policies. BUG=b:182513022 BRANCH=dedede TEST=Build and boot to OS in madoo. Ensure that the DPTF entries look correct in both static.c and SSDT tables i.e. passive and critical policies for applicable devices only are present. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Idc5d0b357d61b9346b4d20ec8322b124c9655b4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Ben Kao <ben.kao@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-03-15mb/supermicro/x11-lga1151-series: add support of X11SSH-LN4F to X11SSH-FAlexander Couzens
The X11SSH-LN4F and X11SSH-F are very similiar. They both use the same PCB and use the same Supermicro BIOS ID. The X11SSH-LN4F has 4 NICs in difference to the X11SSH-F which only has 2 NICs. The two additional NICs aren't populated on the X11SSH-F. Enable the PCIe root ports connected to the two additional Intel NICs. Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Change-Id: Id4e66be47ceef75905ba760b8d5a14284e130f63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-03-15mb/prodrive/hermes: Drop AZALIA_PLUGIN_SUPPORTPatrick Rudolph
Already selected by SoC. Change-Id: I1d941881f50350b6b581416a2e722ea2e7485a1c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-03-15mb/google/dedede/var/sasukette: Add USB2 PHY parametersTao Xia
This change adds fine-tuned USB2 PHY parameters for sasukette. BUG=180753635 TEST=Built and verified USB2 eye diagram test result Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I5612e7dcca15b340763dee1475e979ee551a2146 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-15soc/intel/alderlake: Drop 100ms delay and do not poll Link ActiveJohn Zhao
Drop the 100ms delay in the _PS0 method because kernel already adds this 100ms. This change also drops polling TBT PCIe root ports Link Active State because this scheme is not applicable for SW CM. BUG=None TEST=Built Alderlake coreboot image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I792d3c8ca4249ed74d4090ec1efba5a180429c75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51191 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/google/volteer/variant/lindar: Disable SA GV for Samsung memory with ↵Kevin Chang
wrong date code MB Disable SA GV, because factory used Samsung memory with wrong date code. So we need to use board version to identify build MB phase to disable SA GV. Disable SA GV when board version equal one. BUG=b:179747696 BRANCH=firmware-volteer-13672.B TEST=Built and booted into OS. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I51f4adcf0dd8dbf1cf39d8aec6e4303565551e5f Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-15vc/intel/fsp/fsp2_0/cooperlake_sp: Update memory map hob for WW06 FSPJohnny Lin
Change-Id: Id534e1b73e73bbb9d944c988d1ef66bc1f463eff Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50867 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Deomid "rojer" Ryabkov <rojer9@fb.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/intel/tglrvp: Enable RTD3 for WWANBora Guvendik
Enable the PCIe RTD3 driver for WWAN device attached to PCIe Root Port 4 and provide the reset GPIO / src clk pin. BUG=none TEST=Boot to OS, verify the link is in L2 state during S0ix. Change-Id: I669e02bd02e3af878648a6f3cf4fbb4d06c9857f Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>