summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2021-12-23mb/google/brya/var/anahera: Enable SaGvWisley Chen
Enable SaGv support for anahera/anahera4es. BUG=b:211362081 TEST=FW_NAME=anahera emerge-brya coreboot Change-Id: I68c916dbc570759dba3a4c32fbb8ebfc6e387be4 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-23mb/google/brya/var/taeko4es: Fix PLD group order (W/A)Joey Peng
In commit 667471b8d8 (ec/google/chromeec: Add PLD to EC conn in ACPI table), PLD is added to ACPI table. It causes the DUT to not boot into the OS. So fix the USB3/USB2 Type-C Port C2 PLD group order from 3 to 2 to solve this issue. Fixes: 667471b8d8 ("ec/google/chromeec: Add PLD to EC conn in ACPI table") BUG=b:209723556 BRANCH=none TEST=build coreboot and boot into OS. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Iff1302fa758bcde1ce8b03c16f7cc6eac807e5c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60187 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-23sb/intel/common/rcba_pirq: Use correct size_t length modifierPaul Menzel
Building an image for the Lenovo T60 with `x86_64-linux-gnu-gcc-11` fails with the format warning below. CC ramstage/southbridge/intel/common/rcba_pirq.o src/southbridge/intel/common/rcba_pirq.c: In function 'intel_acpi_gen_def_acpi_pirq': src/southbridge/intel/common/rcba_pirq.c:86:69: error: format '%ld' expects argument of type 'long int', but argument 5 has type 'size_t' {aka 'unsigned int'} [-Werror=format=] 86 | printk(BIOS_SPEW, "ACPI_PIRQ_GEN: %s: pin=%d pirq=%ld\n", | ~~^ | | | long int | %d 87 | dev_path(dev), int_pin - PCI_INT_A, 88 | pirq_idx(pin_irq_map[map_count].pic_pirq)); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | | | size_t {aka unsigned int} The return value of `pirq_idx()` is of type `size_t`, so use the appropriate length modifier `z`. Change-Id: I7af24cee536b81e4825b77942bcac75afeb9f476 Found-by: gcc (Debian 11.2.0-13) 11.2.0 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-23drivers/intel/pmc_mux/conn: Change usb{23}_port_number fields to device pointersReka Norman
Currently, the pmc_mux/conn driver uses integer fields to store the USB-2 and USB-3 port numbers from the SoC's point of view. Specifying these as integers in the devicetree is error-prone, and this information can instead be represented using pointers to the USB-2 and USB-3 devices. The port numbers can then be obtained from the paths of the linked devices, i.e. dev->path.usb.port_id. Modify the driver to store device pointers instead of integer port numbers, and update all devicetrees using the driver. These are the mainboards affected (all are Intel TGL or ADL based): google/brya google/volteer intel/adlrvp intel/shadowmountain intel/tglrvp system76/darp7 system76/galp5 system76/lemp10 Command used to update the devicetrees: git grep -l "usb._port_number" src/mainboard/ | \ xargs sed -i \ -e 's/register "usb2_port_number" = "\(.*\)"/use usb2_port\1 as usb2_port/g' \ -e 's/register "usb3_port_number" = "\(.*\)"/use tcss_usb3_port\1 as usb3_port/g' BUG=b:208502191 TEST=Build test all affected boards. On brya0, boot device and check that the ACPI tables generated with and without the change are the same. Change-Id: I5045b8ea57e8ca6f9ebd7d68a19486736b7e2809 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-12-23mb/google/guybrush/var/dewatt: update USB 2.0 Lane Parameter settings for ↵Kenneth Chan
USB ports Tune the USB phy settings to update txpreempamptune to 3 and txvreftune to 6 for passing USB 2.0 SI Eye diagram measurement (port 0/1/4). BUG=b:199468920 TEST= emerge-guybrush coreboot; pass USB 2.0 SI Eye diagram measurement. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: Ie46c9019186f1893d736fc2806ab74a4f1171be7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-23nb/intel/ironlake: Use `NUM_CHANNELS` macroAngel Pons
Change-Id: I3f4dc26699e3618740af5a0ade1a19599d5a2cc7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-23mb/google/brya/var/vell: update overridetree for SSD setting=
Change CLKSRC#3 to CLKSRC#1 in override devicetree based on schematics BUG=b:208756696 TEST=emerge-brya coreboot Change-Id: I4d452eaa690a91814739cc1b80966fc3a9f1be37 Signed-off-by: = <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-23mb/google/brya/var/vell: update overridetree for touchpad=
update override devicetree for touchpad based on schematics BUG=b:209554950 TEST=emerge-brya coreboot Change-Id: I835958349537ed490191db7c8e35847630de64ed Signed-off-by: = <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-23lib/Makefile.inc: Remove effect-free lineAngel Pons
Because of a typo, `bootblcok-y += rtc.c` does nothing. Drop it. Change-Id: Ife2ee152ab32ef23df5986c47bec490db592ab60 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56216 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-23mb/intel/{adlrvp,sm}: Remove unused header `helpers.h`Subrata Banik
This patch removes unused header inclusion as <commonlib/helpers.h> from several mainboard gpio definition files. Change-Id: I36758089a4981bba916f4d9cf485f64fca2f81ae Signed-off-by: subratabanik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-12-22mb/google/brya/var/taeko: Enable Bayhub LV2 driverTim Wawrzynczak
Some SKUs of google/taeko have a Bayhub LV2 card reader chip, therefore enable the corresponding driver for the mainboard. BUG=b:204343849 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I738af7e77a3c076742a3d6c6f48fad29dfc978ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/60017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-22drivers/generic/bayhub_lv2: Work around known errataTim Wawrzynczak
The Bayhub LV2 has a known errata wherein PCI config registers at offsets 0x234, 0x238, and 0x24C will only correctly accept writes when they are addressed via a DWORD (32-bit) wide write operation on the PCIe bus. Offset 0x234 is the LTR max snoop and max no-snoop latency register, therefore add a finalize callback to this driver which will program the LTR max-snoop/no-snoop register with a 32-bit write using the values from pciexp_get_ltr_max_latencies(). BUG=b:204343849 TEST=verified the PCI config space writes took effect on google/taeko Change-Id: I1813f798faa534fb212cb1a074bc7bcadd17a517 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-22device: Make pciexp_get_ltr_max_latencies a public functionTim Wawrzynczak
Some device drivers may need to get access to the LTR values for their respective devices, therefore export this function instead of marking it static. BUG=b:204343849 Change-Id: Id372600e8adec0d55d3483726bb9353139685774 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2021-12-22mb/google/brya/var/gimble: Configure GPIO to release PERST# earlierMark Hsieh
This change in power sequencing appears to fix issues with power consumption of the SD card controller. Possibly this change ensures the device has enough time to properly initialize itself after reset is deasserted but before it is accessed. BUG=b:206014046 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I90e5dd074ceda365283fe7e1f43dfd8c692d7338 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-22soc/intel/alderlake: remove SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADSScott Chao
This causes the I2C touchpad device to stop working after warm reboot. BUG=b:210701402 BRANCH=none TEST=after warm reboot, the touchpad still works. Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I106ddc96c3185656d3f1fbcd45f198d2d46f3f4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/60126 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-21mb/google/brya/variant/taniks: Add devicetree settingsJoey Peng
Based on schematic G570_MB_CHROME_1207_1630_ADC and gpio table of taniks, generate overridetree.cb settings for taniks. BUG=b:209926534 TEST=FW_NAME=taniks emerge-brya coreboot chromeos-bootimage Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Ib333150117832480f70fbe13bdbdf2982a7f70e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-21arch/x86: Init firmware pointer for EC SMSC KBC1098/KBC1126 at build timeBill XIE
According to util/kbc1126/README.md, for these ECs to work, the address and size of their two firmware should be written to $s-0x100` (`$s` means the image size, done with kbc1126_ec_insert), which means that every existing section (especially those used to store code) should not overlap this address, otherwise the bootblock will get damaged when inserting firmwares of the EC. In this commit, ecfw_ptr is a structure initialized at build time according to CONFIG_KBC1126_FW1_OFFSET and CONFIG_KBC1126_FW2_OFFSET (to do so, they should be redefined as hex), and linked to CONFIG_ECFW_PTR_ADDR within bootblock, so kbc1126_ec_insert is not needed at build time any more. Test passed on Elitebook Folio 9470m. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I4f0de0c4d7283e630242fbe84a46e0547783c49e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-12-21Revert "vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2471_02"Nick Vaccaro
This reverts commit ae0ea32c52905d6bcb527b04727463bc2d1b9e09. This change should not have merged until the 2471_02 FSP change is ready for merge. BUG=b:211481222 TEST='emerge-brya coreboot chromeos-bootimage', flash and boot brya0 to kernel. Change-Id: Iae5b0c53ace196053e1e155efd2e08f438979ba7 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-20mb/google/reef: Move selects from Kconfig.name to KconfigFelix Singer
Move selects from Kconfig.name to Kconfig so that the configuration is at one place and not distributed over two files. Change-Id: Id71c63556da73a09c5a6d3e844686ddc3e113ea7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-20mb/google/reef: Restore alphabetical order on Kconfig selectsFelix Singer
Change-Id: I9578dd7cd4766b4b2ce8fb14992b1ef4701d9878 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-20mb/google/poppy: Select board-specific options per boardFelix Singer
Move board-specific selects out of common configuration and add them to each board where necessary. Change-Id: I5bda94b20da4c9184cef2a39598e25a214c044b1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-20mb/google/poppy: Drop unnecessary Kconfig optionsFelix Singer
These variant-specific options are only selected by their board options and are not used for anything else. Thus, merge their selects into the board options and drop them. Change-Id: I0eb3fdc4fd7306e76d5479494e3ab80bbdb984fe Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-20mb/google/poppy: Move selects from Kconfig.name to KconfigFelix Singer
Move selects from Kconfig.name to Kconfig so that the configuration is at one place and not distributed over two files. Change-Id: I462426f2ef4a0ff62c0a7c1eb2a4946fba68c4a9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-20mb/google/poppy: Restore alphabetical order on Kconfig selectsFelix Singer
Change-Id: If5cb98712767e2acab8955931d4f342c8f3d7824 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-20mb/google/guybrush: Enable PSP_S0I3_RESUME_VERSTAGERob Barnes
Enable PSP_S0I3_RESUME_VERSTAGE for all guybrush based boards. This will cause verstage to run during s0i3 resume. The TPM will be reinitialized in verstage during s0i3 resume. This is necessary on guybrush boards because the TPM_RST_L pin is asserted by the SOC in S0i3. BUG=b:200578885 BRANCH=None TEST=TPM initialized after s0i3 Change-Id: I9d64fe92ffc67a421be6d5e013e636332ce86dd5 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-20soc/amd/cezanne: Correct S0i3 verstage softfuse bitRob Barnes
PSP_S0I3_RESUME_VERSTAGE softfuse bit is 58, not 40. BUG=b:202397678 BRANCH=None TEST=Boot guybrush, ensure S0i3 verstage runs with latest PSP. Change-Id: Ia27f6e48e345aac0d5f6579d663a6b655688239a Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-12-20commonlib: Add new TS for CSE firmware SyncSridhar Siricilla
The patch defines new TS for CSE firmware synchronization. Also, removes unused TS_FIT_UCODE_LOADED TS. TEST=Build the code for Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I9ed82c5358eb94b5e7c91b9fd783c5e09189b77a Reviewed-on: https://review.coreboot.org/c/coreboot/+/59668 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-20mb/google/brya/var/brask: Add wake-on-lan functionRory Liu
Add a wake-on-lan GPIO in devicetree for RTL8125. Modify GPIO A7 for wake-on-lan. BUG=b:204289108 TEST=emerge-brask coreboot chromeos-bootimage Signed-off-by: Rory Liu <rory.liu@quanta.corp-partner.google.com> Change-Id: Ic40301888a138df4a67398485f2a484d69b83fc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-20soc/intel/common: Do not trigger crashlog on all resets by defaultCurtis Chen
Crashlog has error records and PMC reset records two parts. When we send ipc cmd "PMC_IPC_CMD_ID_CRASHLOG_ON_RESET", PMC reset record is enabled. At each warm/cold/global reset, crashlog would be triggered. The cause of this crash would be "TRIGGER_ON_ALL_RESETS", it is used to catch unknown reset reason. At the same time, we would see [Hardware Error] in the kernel log. If we default enable TRIGGER_ON_ALL_RESETS, we would have too many false alarm. Now we disable PMC reset records part by default. And we could enable it when we need it for the debug purpose. The generated bert dump is under /var/spool/crash/, we could check this path to verify this CONFIG disable/enable status. BUG=b:202737385 TEST=No new bert dump after a warm reset. Signed-off-by: Curtis Chen <curtis.chen@intel.com> Change-Id: I3ec4ff3c8a3799156de030f4556fe6ce61305139 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-20mb/google/brya/var/vell: update memory settingsShon Wang
DQ/DQS info from Intel_Platform_DQ_DQS_RCOMP_Info_Utility GPIO_MEN_CONFIG_0 GPP_E11 to GPP_E3 GPIO_MEN_CONFIG_3 GPP_E12 to GPP_E7 GPIO_MEM_CH_SEL_GPP_E5 GPP_E13 to GPP_E5 BUG=b:205908918 TEST=emerge-brya coreboot Change-Id: Ic0bbac5eaebc77639be6c1bc399658ac90e72fbb Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-20mb/google/brya/var/vell: update gpio overrideKevin Chiu
Configure GPIOs according to schematics BUG=b:205908918 TEST=emerge-brya coreboot Change-Id: Icc91866f7555c294af7eed9e5d1550e73d8059d0 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-20mb/google/brya/var/*: Add disable_gpio_export_in_crs to all devicetreesTim Wawrzynczak
None of the touchscreens used in the brya program (any brya board) should require exporting of GPIOs in the ACPI _CRS method for any i2c device. This can cause i2c devices to malfunction or cause timing sequence violations if: 1) ACPI exports a PowerResource for the device that uses GPIOs that are also exported in _CRS 2) The kernel driver for the device uses the GPIOs exported in _CRS for its own purposes. This means the state of the pin is out of sync between platform firmware and the kernel. The Linux ELAN I2C touchcsreen driver (https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/upstream/drivers/input/touchscreen/elants_i2c.c;l=1429) is one example of this. Therefore, add disable_gpio_export_in_crs to all brya variants that use the drivers/i2c/generic or drivers/i2c/hid chip drivers. Change-Id: Ib4475bd0dc885e230911de6298fd95baa868ef29 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-20mb/google/brya/var/primus: Update thermal table for primusAriel_Fang
- Because primus have five sensors,we need to define 5 sensors. BUG=b:200836803 TEST=USE="project_primus emerge-brya coreboot" and verify it builds without error. Signed-off-by: Ariel_Fang <ariel_fang@wistron.corp-partner.google.com> Change-Id: I02fb8eee644f9999d9c5d48e3a056499d968f85d Reviewed-on: https://review.coreboot.org/c/coreboot/+/60101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-20mb/google/brya/variants/brask: Disable autonomous GPIO power managementZhuohao Lee
We experienced the `Cr50 i2c TPM IRQ timeout!` error when the device executed the reboot test even though we have updated the Cr50 firmware to the latest version 0.6.70. Besides, we also experienced the device failed with the IRQ timeout when using the 0.3.22 Cr50 firmware in the factory. In order to fix these issues, we disable the gpio power management from the devicetree. BUG=b:210540890 TEST=reboot 100 cycles without the error message. Change-Id: I5f18fea5bc28493107c6d4951805de640a0b8ae5 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-12-20soc/amd/common/lpc/espi_util: use enum cb_err type for return valuesFelix Held
Use enum cb_err as return type of all remaining functions that only return success or failure. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6cff8480d99641fdfb613bb3e4edc4055ad5efc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-20soc/amd/common/lpc/espi_util: use enum cb_err type for return valuesFelix Held
Use enum cb_err as return type of all functions that aren't exposed outside of this compilation unit. The checks if a function has returned a failure are replaced with checks if the return value isn't CB_SUCCESS which is equivalent if only those two values are used, but also detects a failure if any unexpected value would be returned. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If8c703f62babac31948d0878e91bd31b31bebc01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-20soc/amd/common/lpc/espi_util: simplify espi_configure_decodesFelix Held
The intermediate ret variable isn't needed. espi_open_generic_io_window only returns 0 or -1, so if ret is != 0, it has to be -1. This is a preparation to use the enum cb_err type for the return values. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia6c7f4cedf8c2defadcf4c4da1697a97c7b401f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-20soc/amd/common/lpc/espi_util: simplify espi_get_general_configurationFelix Held
The intermediate ret variable isn't needed. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4e6747cf468c5ba8da6c1a3b20022851e32ad951 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-20soc/amd/cezanne/fch: disable 48MHz output in S0i3Felix Held
S0i3 is a low power state which reduces the power consumption to about the level of the S3 suspend state where the DRAM is kept in a self- refresh state and most of the rest of the system is powered down. So everything that can be switched off in the S0i3 state should be switched off in order to maximize the standby time. BUG=b:210722314 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If445f5825dc7b795c95d73c061156cc485421ada Reviewed-on: https://review.coreboot.org/c/coreboot/+/60125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-20soc/amd/stoneyridge/fch: add GNVS-related TODOsFelix Held
The AOAC device states shouldn't be stored in GNVS, but be read from the AOAC registers during runtime. Same for the EHCI controller's BAR0. The location and size of the XHCI firmware can either be statically determined at build-time or have coreboot generate ACPI objects that contain the needed addresses. Since I can't easily test changes that require booting to a desktop on Stoneyridge at the moment, only add TODOs for now. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: I3691b05606b9430cb60923780a6131993a9887d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-20soc/amd/stoneyridge: split southbridge codeFelix Held
Split the southbridge code into a bootblock and a ramstage part to align it more with Picasso and Cezanne. Also move the implementation of fch_clk_output_48Mhz to the end of early_fch.c since it's not really related to the functions that were previously around it. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib660fbef8dc25ba0fab803ccd82b3408878d1588 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-20soc/amd/stoneyridge: factor out AGESA-wrapper related FCH functionsFelix Held
Split the code that gets called from the AGESA wrapper from the rest of the FCH/southbridge code that directly interacts with the hardware. Since the remaining parts of southbridge.c aren't used in romstage, drop it from the list of build targets for romstage. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6197add0e1396a82545735653110e1e17bf9c303 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-20soc/amd/stoneyridge: factor out early AOAC initializationFelix Held
Factor out enable_aoac_devices out of southbridge.c to aoac.c to align Stoneyridge more with Picasso and Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ied4d821138507639cad1794f6c5017b5873b761f Reviewed-on: https://review.coreboot.org/c/coreboot/+/60140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-20mb/starlabs/labtop: Add enum for `power_profile`Angel Pons
Introduce and use an enum for the `power_profile` CMOS option. Add a helper function that converts CMOS values into enum values. Using an enum allows GCC to warn about switch statements using enum types for their control expressions not handling all possible enum values, and also improves readability. Change-Id: I47a453ea12d164d26908a9944a89a481757e753c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <admin@starlabs.systems> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-20mb/starlabs/labtop: Rename some filesAngel Pons
Rename `mainboard.c` to `smbios.c` as it only contains SMBIOS functions. Rename `ramstage.c` to `mainboard.c` as it contains the mainboard chip operations struct. Change-Id: I9548ca72a7583de98f5b154e3381825bba00d5cf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <admin@starlabs.systems> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-20soc/amd: remove root of SoC directory from include pathFelix Held
We shouldn't be providing -I include paths to the root of the soc specific directory. It allows for lazy includes that can collide, but there's no way of knowing the winning path since the winning path is determined by Makefile.inc parsing order. This is taken from CB:41355 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I45ed219e4e0cccf3d4f04cc70dc1ef77c518afff Reviewed-on: https://review.coreboot.org/c/coreboot/+/60201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-20mb/google/zork: use full path of SoC's chip.hFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I50d8c45e711dc62afe6f80e0f66422bcc9924dfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/60202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-20mb/amd/bilby,mandolin: use full path of SoC's chip.hFelix Held
This is taken from CB:41355 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iba1948ae2332788b7e0ec9b4e3cea35c6608b152 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-20soc/amd/stoneyridge/include/southbridge: remove unneeded chip.h includeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9b37efc89e505c2de99536b59e7d7e2bb1d54bff Reviewed-on: https://review.coreboot.org/c/coreboot/+/60199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-20mb/amd/gardenia,padmelon;mb/google/kahlee: use full path of SoC's chip.hFelix Held
This is taken from CB:41355 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I10a18efb92ac0c3cad31044156e32aa6afe1d4d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-20mb/amd/gardenia,padmelon;mb/google/kahlee: add missing soc/gpio includesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie716633bd7602d5e4a7e186aa9e444b7f70dab56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-19mainboard: Fix comment about early GPIOsAngel Pons
These boards program the early GPIO table in bootblock, not romstage. Change-Id: Iae9353d106483f30cefa2d035d96e63e4c127261 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Sean Rhodes <admin@starlabs.systems> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-12-18mb/siemens/chili: Reuse options from Kconfig.nameFelix Singer
Reuse the options from Kconfig.name for variant-specific selects. Change-Id: I35f51756180882d019a3ea8c555ccd18cd588f44 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-18mb/kontron/bsl6: Reuse options from Kconfig.nameFelix Singer
Reuse the options from Kconfig.name for variant-specific selects. Change-Id: I29ce7ef6f5137c1cf43726faed6081a04c83dea6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-18sb/intel/lynxpoint: Update `intel_me_status()` signatureAngel Pons
Update the parameter types of `intel_me_status()` to not be pointers. Change-Id: I0fd577c49bec7a581c340fc2fcadcadd50b1a638 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-18sb/intel/lynxpoint/me.c: Refactor MEI CSR functionsAngel Pons
Change the signature of MEI CSR functions to reduce pointer usage. Change-Id: I1e4885daf8b3e11056421e663e67c8f360699a98 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-18sb/intel/lynxpoint: Use unions for MEI registersAngel Pons
Wrap bitfield structs in unions to reduce pointer usage. This adds more uses of the `mei_dump()` function, only used for debugging. Refactoring the MEI CSR functions to not use pointers is done in a follow-up. Change-Id: I4defbb8c0e7812bf95c672ce529959f67c34537a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-18sb/intel/lynxpoint: Use unions for ME PCI registersAngel Pons
Wrap bitfield structs in unions to reduce pointer usage. Change-Id: I8ac901211beb0ef24dff926b1a06004a99e68bda Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-18sb/intel/lynxpoint: Drop typedefs of enum typeAngel Pons
There's no need to use typedefs for enum types. Get rid of it. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I830d95018b33fe6ab7e2c37ebf15bb1df6ceec38 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-18sb/intel/lynxpoint: Drop typedefs of struct typesAngel Pons
There's no need to use typedefs for struct types. Get rid of them. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I109bd690500a9f03b9da0fd72044be79abf660d3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-18soc/amd/cezanne/acpi: Add support for RTC workaroundRaul E Rangel
The RTC on Cezanne is an unstable wake source when the system is in S0i3. We instead need to use an internal timer that triggers a GPIO that acts as a wake source. This change provides the ACPI necessary to allow the OS to manage the wake source. BUG=b:209705576 TEST=Boot guybrush with this patch and several OS patches. Verified the OS sets the correct wake bit, the system correctly suspends and resumes, and the wake source is correctly accounted for. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1f14d14df5d30d48d244416f2ec8c10ac5c8040e Reviewed-on: https://review.coreboot.org/c/coreboot/+/60172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Limonciello <mario.limonciello@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-18mb/google/guybrush: Disable GPIO export for Goodix TouchscreenRaul E Rangel
We want ACPI to own the GPIOs. This will stop the GPIOs from being exposed to the OS driver. BUG=b:209705576, b:210694108 TEST=Dump ACPI table and verify GPIO are no longer in _CRS. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I8d2af41e1d04b98f0e3e19a95d7b91d08ecdf17b Reviewed-on: https://review.coreboot.org/c/coreboot/+/60173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-18soc/amd/common/block/acpimmio/print_reset_status: add missing status bitFelix Held
Both the Picasso PPR #55570 Rev 3.18 and the Cezanne PPR #56569 Rev 3.03 define bit 9 of the PM_RST_STATUS register as internal Thermal Trip reset status bit. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ida8b13fe62b16c18fc9924520b83220e73eca624 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-12-17soc/intel/denverton_ns: Use `popcnt()` helperAngel Pons
Use the `popcnt()` helper instead of manually counting the number of set bits in the first `CONFIG_MAX_CPUS` bits with a loop. Also, use unsigned types to store the number of active/total cores. Change-Id: Iae6b16991fcf07c9ad67d2b737e490212b8deedd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-17mb/google/guybrush/var/nipperkin: config eSPI as dedicated alertKevin Chiu
Setup eSPI to dedicated alert per the latest schematic changes. DUT won't hang up at power on boot due to eSPI alert is triggerred unexpectedly. BUG=b:199458949,b:203446084 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage test power on/reboot on DUT (6 units) each 10 loops->pass Change-Id: I55cda7a1af22e555a4f55285cb7e337a69e6c234 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-17google/trogdor: Enable Parade ps8640 edp bridge for pazquelYunlong Jia
BRANCH=none BUG=b:201478528 TEST=build and boot Change-Id: I6130ee00a0e6f469142f5416627e38c7b5076071 Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-12-16mb/google/brya/var/felwinter: Add stylus probe for garageEric Lai
Felwinter has non-stylus sku. Add a FW_CONFIG field to indicate stylus presence and add a probe statement to the devicetree for the corresponding device. BUG=b:208937710 TEST=non-stylus doesn't register garage driver. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I06a2c125f2b5a73f9f7c27bf1b20ff8712664809 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-16Revert "security/vboot: Add NVRAM counter for TPM 2.0"Tim Wawrzynczak
This reverts commit 7dce19080889955576f8fd197658077aced96a96. Reason for revert: Unable to boot in factory mode Change-Id: I1b51010080164c6e28d77a932f77c10006fd4153 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-16mb/google/guybrush/var/dewatt: Add audio codecKenneth Chan
Add ALC5682I-VD and ALC1019 for dewatt. BUG=b:208172493 TEST=emerge-guybrush coreboot chromeos-bootimage; Tested with proto build. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: Ie4d21a11377c73b913a8f79a92d5869ea70f4394 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-16mb/google/brya/var/vell: update overridetreeKevin Chiu
Init basic override devicetree based on initial schematics BUG=b:205908918 TEST=emerge-brya coreboot Change-Id: Ibaa910eb1c5584197907963781258035c668298e Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-16Spell *Boot Guard* with a space for official spellingPaul Menzel
See for example Intel document *Secure the Network Infrastructure – Secure Boot Methodologies* [1]. Change all occurrences with the command below: $ git grep -l BootGuard | xargs sed -i 's/BootGuard/Boot Guard/g' [1]: https://builders.intel.com/docs/networkbuilders/secure-the-network-infrastructure-secure-boot-methodologies.pdf Change-Id: I69fb64b525fb4799bcb9d75624003c0d59b885b5 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-15lib/cbfs: Disable cbfs_preload in romstage when VBOOT_STARTS_IN_ROMSTAGERaul E Rangel
Preloading files before vboot runs and using them after vboot has finished will result in the wrong files getting used. Disable cbfs_preload to avoid this behavior. BUG=b:179699789 TEST=none Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7698b481a73fb24eecf4c810ff8be8b6826528ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/59876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-12-15rules.h, thread.h, lib/cbfs: Add ENV_STAGE_SUPPORTS_COOPRaul E Rangel
This change consolidates the COOP rules. Co-op in theory works in all x86 stages now, but it hasn't been enabled yet. BUG=b:179699789 TEST=Boot guybrush to OS and verify preloads still work Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1197406d1d36391998b08e3076146bb2fff59d00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-12-15mb/google/fizz/Kconfig: Select board-specific options per boardFelix Singer
Move board-specific selects out of common configuration and add them to each board where necessary. Change-Id: I2b8a9906671b327bec249f3d16cba3ba80a95669 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-15mb/google/fizz: Move selects from Kconfig.name to KconfigFelix Singer
Move selects from Kconfig.name to Kconfig so that the configuration is at one place and not distributed over two files. Change-Id: I9201b5bcbf53422cefc6027a0d67fcf2201b14a4 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-15mb/google/fizz: Restore alphabetical order on Kconfig selectsFelix Singer
Change-Id: Iaaca82aad3c687939291c051f203b58a9c8cdb70 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-15mb/google/glados/Kconfig: Select board-specific options per boardFelix Singer
Move board-specific selects out of common configuration and add them to each board where necessary. Change-Id: I70ab37588a6b08a0cc194469fd2642b3cfefe301 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-15mb/google/glados: Move selects from Kconfig.name to KconfigFelix Singer
Move selects from Kconfig.name to Kconfig so that the configuration is at one place and not distributed over two files. Change-Id: Ifccf2b3521d84f6a678872bbccf9bf390c25ce37 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-15mb/intel/adlrvp_n: Add initial code for adl-n variant boardKrishna Prasad Bhat
This patch adds the following list of changes: 1. Create a new devicetree for adlrvp-n and copy contents of adlrvp-p devictree. 2. Add support for 2 mainboards as ADL-N board with default EC (Windows SKU) and Chrome EC (Chrome SKU) and copy overridetree contents from adlrvp-p. 3. Add mainboard Kconfig to Kconfig.name file 4. Handle mainboard names in Kconfig file for ADLRVP N 5. Add config options to pick the adlrvp_n devicetree Change-Id: I4abf3bf62ec0398ae75e21575a2fab0d44b5c7ad Signed-off-by: Usha P <usha.p@intel.com> Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-15soc/amd/common/block/psp: move psp_notify_dram to psp_gen1.cFelix Held
The MBOX_BIOS_CMD_DRAM_INFO PSP mailbox command is only available on the first generation of PSP mailbox interface and not on the second generation. The second generation of the PSP mailbox interface was introduced with the AMD family 17h SoCs on which the DRAM is already initialized before the x86 cores are released from reset. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I97b29fdc4a71d6493ec63fa60f580778f026ec0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/60124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-15drivers/spi/spi-generic: document SPI_CNTRLR_DEDUCT_CMD_LEN betterFelix Held
This should make it a bit clearer what the differences between SPI_CNTRLR_DEDUCT_OPCODE_LEN and SPI_CNTRLR_DEDUCT_CMD_LEN and the corresponding functionality in spi_crop_chunk are. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I809adebb182fc0866b93372b5b486117176da388 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-15drivers/spi/spi-generic: fix edge case in spi_crop_chunkFelix Held
In the case of deduct_cmd_len being set and the adjusted cmd_len >= ctrlr_max, ctrlr_max wasn't being adjusted and still had the value of ctrlr->max_xfer_size. Handle this edge case (which we should never run into) by setting ctrlr_max to 0 and printing a warning to the console. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9941b2947bb0a44dfae8ee69f509795dfb0cb241 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-15soc/amd/common/block/spi/fch_spi_ctrl: improve printk messagesFelix Held
Replace FCH_SC with FCH SPI in the printk messages to make those a bit clearer and also remove an unneeded line break in another printk call. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6ff02163e6a48a2cc8b7fe89b15826e154715d29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-15soc/amd/common/block/spi/fch_spi_ctrl: handle failure in execute_commandFelix Held
When wait_for_ready returned a timeout, execute_command still ended up returning success. Fix this be returning a failure in this case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id012e74e26065c12d003793322dcdd448df758b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-15soc/amd/common/block/spi/fch_spi_ctrl: rework dump_stateFelix Held
Introduce and use enum spi_dump_state_phase to indicate from which phase of the SPI transfer dump_state gets called to print the relevant debug information for that phase. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2f54d4a7eb2f3b9756b77a01533f7c99e8597bfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/60118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-15soc/amd/common/include/spi: add Cezanne-specific commentFelix Held
The Cezanne PPR #56569 Rev 3.03 has one more SPI FIFO bytes defined compared to the previous generations. It is unclear if adding some special handling for Cezanne would be worth the effort, since the current code just doesn't use the last byte which should be safe to do, since this only affects the maximum number of bytes that can be used for one SPI transaction. Having another byte to use on Cezanne wouldn't reduce the number of SPI transactions to write a 256 byte data block. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic730f4fe838f59066120c811833995c132c84c1c Reviewed-on: https://review.coreboot.org/c/coreboot/+/60117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-15soc/amd/common/include/spi: fix SPI_FIFO_LAST_BYTE defineFelix Held
The last byte of the SPI FIFO SPI_FIFO_LAST_BYTE is at offset 0xc6 of the SPI controller's MMIO region for Stoneyridge and Picasso. Both SPI_FIFO_LAST_BYTE and SPI_FIFO_DEPTH had an off-by-one error that ended up cancelling out each other, so the resulting value for SPI_FIFO_DEPTH isn't changed. TEST=Timeless build results in identical image for Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1676be902ccf57e2e9f69d81251b4315866a0628 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-15mb/google/guybrush: Set TPM to to be kernel power managed.Rob Barnes
Set TPM power_managed_mode to TPM_KERNEL_POWER_MANAGED. This will cause the TPM kernel driver to send a shutdown command before s0i3 entry. This change depends on S0i3 verstage running and reinitializing the TPM. BUG=b:200578885 BRANCH=None TEST=TPM shutdown sent during s0i3 entry on guybrush Change-Id: I206022cc2a29690186206966c5d45bd55c303248 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-15mb/google/dedede/var/madoo: Generate new SPD ID for new memory partsDtrain Hsu
Add new memory parts in the mem_list_variant.txt and generate the SPD ID for the parts. The memory parts being added are: 1. Micron MT53E512M32D1NP-046 WT:B 2. Samsung K4U6E3S4AB-MGCL 3. Hynix H54G46CYRBX267 BUG=b:209889645 BRANCH=dedede TEST=FW_NAME=madoo emerge-dedede coreboot chromeos-bootimage Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I0b2f447a610a0a857e819ede257ac89cfd817018 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59991 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-15Denverton-NS boards: Drop useless `thermal.asl`Angel Pons
The code in these files is meaningless, and can be dropped. Change-Id: I11571885059e8d5f930f741172c74b25faa09a15 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-12-15mb/google/brya/var/primus{4es}: Configure Acoustic noise mitigationCasper Chang
- Enable Acoustic noise mitigation - Set slow slew rate VCCIA and VCCGT to 8 BUG=b:204844399 TEST=USE="project_primus emerge-brya coreboot" and verified the setting meets the audible noise specification Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I0e0baf78a841278efda912cc5e4e9970329aacf6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-15mainboard/starlabs/labtop: Hook up Thunderbolt to CMOSSean Rhodes
Hook up Thunderbolt and related settings to CMOS value of `thunderbolt`. Changes TcssXhciEn, UsbTcPortEn and the relevant PCI devices. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ibadc7464831242ae51982610b410ccf0a6811edd Reviewed-on: https://review.coreboot.org/c/coreboot/+/59705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
2021-12-15mb/google/guybrush/var/nipperkin: update LPDDR4X DRAM tableKevin Chiu
add Hynix H54G56CYRBX247 support BUG=b:210365851 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage power on successfully Change-Id: I99bed32025d10f62e63ace8f7f23e7cc3a740e93 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60075 Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-15mb/google/brya/var/taniks: Configure DRIVER_TPM_I2C_BUSJoey Peng
Add I2C bus for taniks in Kconfig BUG=b:210390520 TEST=emerge-brya coreboot and can boot to OS. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I9b1719c3140c13f67e7cb0e6a69257774884bd4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/60077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-15mb/google/brya/variant/taniks: Add memory settingsJoey Peng
Based on the Taniks's schematic, generate memory settings. Schematic version is G570_MB_CHROME_1207_1630_ADC. BUG=b:209531192,b:209553289 TEST=FW_NAME=taniks emerge-brya coreboot chromeos-bootimage Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I0c0794fb94d1f6271de604835ae1d2b20696ee70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-12-15mb/google/brya/variants/taniks: Configure GPIOs according to schematicsJoey Peng
Add initial gpio configuration for taniks according to schematics G570_MB_CHROME_1207_1630_ADC. The schematics reserved HPS and FP but taniks doesn't use them, so set FP and HPS related pins to NC. BUG=b:209492408, b:209553289 TEST=FW_NAME=taniks emerge-brya coreboot Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Ic5c4ead4ad59137e1764e1226415ab6041c68aab Reviewed-on: https://review.coreboot.org/c/coreboot/+/59938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-15soc/intel/denverton_ns: Fix MRC_RW_CACHEKyösti Mälkki
It is required to set WPD (Write Protect Disable) bit to make it possible to use MRC_RW_CACHE region with CACHE_MRC_SETTINGS=y. Change-Id: Iacab44b00d08c9bdc18bc3bdcb88833634c0b02e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-15soc/intel/denverton_ns: Use common SMBus support codeKyösti Mälkki
Change-Id: I233d198b894f10fbf0042a5023ae8a9c14136513 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-15soc/intel/baytrail,denverton_ns: Call setup_lapic()Dmitry Ponamorev
A custom board with soc/intel/denverton_ns does not respond to the keyboard and does not boot from the sata/USB disks. Last post code 0x7b and the last line that is displayed at log from SeaBIOS is: All threads complete. The issue is gone when adding setup_lapic() call to configure EXTINT delivery of i8259 originated interrupts for the LAPIC. Replicate call from other soc/ and make the call for both BSP and AP CPUs. Similar change was done for soc/intel/braswell in commit b4f57bb3cac3ab29b9fa9c526ad4358faffb77a1. Signed-off-by: Dmitry Ponamorev <dponamorev@gmail.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: Iafbfb733d0be546e0e2fba937fd1d262785aa54d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-15mb/google/corsola: move USB3 HUB reset funtion to bootblockRex-BC Chen
To save the S3 power, USB3_HUB_RST_L is externally pulled up to a weak resistor, so we have to reset the hub as early as possible. Otherwise the USB3 hub may be not usable. Therefore, move USB3 HUB reset function to bootblock. BUG=b:210065282 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I92feb2316302fda32478b24c014bcd380d0ac55d Reviewed-on: https://review.coreboot.org/c/coreboot/+/60088 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 14:15:46 +0000