summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2023-04-04mb/starlabs/starbook/adl: Remove Soundwire workaroundSean Rhodes
This was added to solve Debian 10 not booting. Debian 10, which now isn't the latest stable version works, so remove the workaround that was included in the original port. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ic11f355eb218ff3bad00fff83537c99c1b6985bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/72669 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-04mb/google/brya/var/omnigul: Add ADL and RPL dptf settingsJamie Chen
Add Alder Lake (ADL) and Raptor Lake (RPL) dptf settings for omnigul BUG=b:273415170 BRANCH=firmware-brya-14505.B TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I8280f82ff1534ea63bcb448da231712bb4abd6d3 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-04Revert "mb/starlabs/*: Remove sleepstates.asl"Sean Rhodes
This reverts commit ac69ce91229dee68d4135c596f49cf9e5efbe1e9. Reason for revert: Removing breaks suspend in kernels > 6.2 and Windows. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3e90266e66192b328b9af51c5e614774a248ddf0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
2023-04-04mb/google/rex: Enable CSE pre-cpu timestampsBora Guvendik
Enables pre-cpu boot timestamps from cse. 990:CSME ROM started execution 0 944:CSE sent 'Boot Stall Done' to PMC 47,000 945:CSE started to handle ICC configuration 225,000 (178,000) 946:CSE sent 'Host BIOS Prep Done' to PMC 225,000 (0) 947:CSE received 'CPU Reset Done Ack sent' from PMC 516,000 (291,000) 991:Die Management Unit (DMU) load completed 587,000 (71,000) 0:1st timestamp 597,427 (10,427) BUG=b:259366109 TEST=Boot on rex, check "cbmem -t" Change-Id: I68cd53c18af6a400bcd9dc15d428a904b0647495 Signed-off-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73759 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-04soc/intel/meteorlake: Inject CSE TS into CBMEM timestamp tableBora Guvendik
Get boot performance timestamps from CSE and inject them into CBMEM timestamp table. 990:CSME ROM started execution 0 944:CSE sent 'Boot Stall Done' to PMC 47,000 945:CSE started to handle ICC configuration 225,000 (178,000) 946:CSE sent 'Host BIOS Prep Done' to PMC 225,000 (0) 947:CSE received 'CPU Reset Done Ack sent' from PMC 516,000 (291,000) 991:Die Management Unit (DMU) load completed 587,000 (71,000) 0:1st timestamp 597,427 (10,427) BUG=b:259366109 TEST=Able to see TS elapse prior to IA reset on Rex Change-Id: I548cdc057bf9aa0c0f0730d175eaee5eda3af571 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73713 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2023-04-04commonlib: Add new "DMU load completed" TSBora Guvendik
990:CSME ROM started execution 0 944:CSE sent 'Boot Stall Done' to PMC 47,000 945:CSE started to handle ICC configuration 225,000 (178,000) 946:CSE sent 'Host BIOS Prep Done' to PMC 225,000 (0) 947:CSE received 'CPU Reset Done Ack sent' from PMC 516,000 (291,000) 991:Die Management Unit (DMU) load completed 587,000 (71,000) 0:1st timestamp 597,427 (10,427) BUG=b:259366109 TEST=Boot to OS, check cbmem -t Change-Id: I4d2da820f39c40ea864d15d25a94a68497b2af3d Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74047 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-04soc/intel/alderlake: Add support for CSE timestamp data versionsBora Guvendik
CSE performance data timestamps are different for version 1 Alder Lake/Raptor Lake and version 2 Meteor Lake. This patch moves the current ADL/RPL timestamp definitions to a separate header file. It marks current structure as version 1. BUG=b:259366109 TEST=Boot to OS, check ADL/RPL pre-cpu timestamps. Change-Id: I780e250707d1d04891a5a1210b30aecb2c8620d3 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73712 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2023-04-04mb/google/mtlrvp: Update MTLRVP Flash LayoutUsha P
This patch updates the MTLRVP flash layout to allow CSE Lite FW update and accommodate multiple ESx SoC stepping blobs. SI_BIOS: SI_EC: Removed RW_SECTION_A/B: Increased by ~1.9MB. RW_LEGACY: Reduce to 1MB. RW_MISC: Reduce to 152KB. - Drop RW_SPD_CACHE - Optimize other sections Additionally, moved RW_LEGACY under extended BIOS region. For chromeos-debug-fsp.fmd SI_BIOS: RW_SECTION_A/B: Increased by ~1.2MB. RW_LEGACY: Dropped RW_MISC: Reduce to 152KB. - Drop RW_SPD_CACHE - Optimize other sections BUG=b:271407315 TEST=Able to enable CSE update on MTLRVP and have free space to add one more PUNIT FW to support different SoC stepping. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I8cfba861e6d3122b0795a5a8e589c67cebad9762 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73378 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
2023-04-04mb/intel/mtlrvp: Add fmd for debug FSPUsha P
Debug FSP is ~920KiB larger than release FSP and we don't have sufficient space for MTL-P RVP flash layout. Remove RW_LEGACY and split them into RW_SECTION_A/B so we can have a room for it. BUG=b:271407315 TEST=Build intel/mtlrvp with CONFIG_BUILDING_WITH_DEBUG_FSP. Change-Id: Ief7dd39af018c4c1519ca80d1303085d8298cda6 Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74193 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
2023-04-03option: Allow to use the EFI variable driver as option backendPatrick Rudolph
Use the introduced EFI variable store driver on top of the SMMSTORE region in SPI flash to read/write options. Change-Id: I520eca96bcd573f825ed35a29bf8f750e313a02d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62562 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-03drivers/efi: Add EFI variable store option supportPatrick Rudolph
Add a driver to read and write EFI variables stored in a region device. This is particularly useful for EDK2 as payload and allows to reuse existing EFI tools to set/get options used by the firmware. The write implementation is fault tolerant and doesn't corrupt the variable store. A faulting write might result in using the old value even though a 'newer' had been completely written. Implemented basic unit tests for header corruption, writing existing data and append new data into the store. Initial firmware region state: Initially the variable store region isn't formatted. Usually this is done in the EDK2 payload when no valid firmware volume could be found. It might be useful to do this offline or in coreboot to have a working option store on the first boot or when it was corrupted. Performance improvements: Right now the code always checks if the firmware volume header is valid. This could be optimised by caching the test result in heap. For write operations it would be good to cache the end of the variable store in the heap as well, instead of walking the whole store. For read operations caching the entire store could be considered. Reclaiming memory: The EFI variable store is append write only. To update an existing variable, first a new is written to the end of the store and then the previous is marked invalid. This only works on PNOR flash that allow to clear set bits, but keep cleared bits state. This mechanisms allows a fault tolerant write, but it also requires to "clean" the variable store for time to time. This cleaning would remove variables that have been marked "deleted". Such cleaning mechanism in turn must be fault tolerant and thus must use a second partition in the SPI flash as backup/working region. For now to cleaning is done in coreboot. Fault checking: The driver should check if a previous write was successful and if not mark variables as deleted on the next operation. Tested and working: - Enumerate all existing variables - Read variables - Write variables Change-Id: I8079f71d29da5dc2db956fc68bef1486fe3906bb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52564 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-03mb/google/rex: Use FW_CONFIG for generating ACPI code for WIFISubrata Banik
This patch avoids creating runtime ACPI for unused WIFI solutions. For example: if the Rex SKU is with WIFI_CNVI then you don't need to populate ACPI code for WIFI_PCIE. FW_CONIG can be used for making those decisions. TEST=No ASL entries being created for WIFI_PCIE if the FW_CONIG is set to WIFI_CNVI. Also, helped to save the boot time on google/rex (FSP-S API) by 9ms. Change-Id: I60e4332d8d8c360fdf425b30513ff79209979e85 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74147 Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-03commonlib/coreboot_tables.h: Fix typo in enum type nameAngel Pons
Fix a typo in an enum's type name, "tmp" ---> "tpm". The enum type is not used anywhere in the coreboot tree. Change-Id: Ie7529e7ee80aa9661ec053da8211c2c3295b3942 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-04-03soc/amd/cezanne,glinda,mendocino,phoenix,picasso/Kconfig: use all targetFelix Held
The i2c.c compilation unit is added to all stages in all cases, so use the all target instead of adding it to all stages separately. Also order the all targets alphabetically. TEST=Timeless build on Mandolin results in identical image. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie90380075a3c87d226cdcb0f41f7e94275eaaa42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-04-03mb/amd/birman/port_descriptors: split files for phoenix/glindaFred Reitberger
Glinda and Phoenix have different requirements, so split the birman port_descriptors file to betty apply to each SoC. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ia28cf4172b6adada10809e0135b2459077fa3da0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-03mb/google/brask/var/constitution: correct Type-A USB3 port0/1 tx_de_empMorris Hsu
Set Type-A USB3 port0/1 tx_de_emp to 0x2B to fix the USB3 Gen2 RX signal integrity issue. BUG=None TEST=build FW and check Type-A USB3 port0/port1 RX pass Change-Id: I9296ae5a8a9d7aa49b3c7529a9c1b2d2829b15d0 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-04-03soc/intel/alderlake: Fix RPL-U 15W and RPL-P 28W TDC current valuesJeremy Compostella
The Intel Power and Performance (PnP) team requested to update the following: - TDC settings for RPL-U 15W variant should be 22A. - TDC settings for RPL-P 28W variant should be 33A. BUG=b:275694022 BRANCH=firmware-brya-14505.B TEST=PnP validated performance impact with these settings on both RPL-U 15W and RPL-P 28W Change-Id: I1141414785a990b975e32ebc03e490b83082aab7 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74046 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-03mb/google/brya/variants/hades: Add CPU power limitsTarun Tuli
Add CPU power limits support and values for RPL on Hades BUG=b:269371363 TEST=builds Change-Id: I22ef56152abe5a23067c5e923b07d60dc9fac8e7 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73895 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-03arch/ppc64/rom_media.c: move to mainboard/emulation/qemu-power*Krystian Hebel
CBFS location in memory is different than on the real hardware. Change-Id: Icd806a57f449042c883b624056c05c1ff7e4c17e Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
2023-04-03mb/google/nissa/var/uldren: Add overridetreeVan Chen
Add override devicetree based on schematics(ver. 20230308). BUG=b:272829190 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I9cd918c6a48cc6007a18c5aa94afe31fd9608718 Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73974 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-04-02soc/intel/common: Order the CPUs based on their APIC IDsSridhar Siricilla
The patch defines acpi_set_cpu_apicid_order() which orders the APIC IDs based on APIC IDs of Performance cores and Efficient cores, calculates the total core count and total Performance cores count, populates the information in the cpu_apicid_order_info struct. The helper function useful to present the Performance and Efficient cores in order to OS through MADT table and _CPC object. TEST=Verify the build for Gimble (Alder Lake board) Change-Id: I8ab6053ffd036185d74d5469fbdf36d48e0021ce Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72131 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-02soc/intel/meteorlake: Set Power Performance Platform OverrideSubrata Banik
According to document 640858 MTL EDS Vol2, bit 18 (PWR_PERF_PLATFRM_OVR) of MSR_POWER_CTL must be set. This patch is backported from `commit 117770d32468e63df ("soc/intel/ alderlake: Enable Energy/Performance Bias control")`. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic83225b619c49db0b49b521a83a2f1dc1ad69be8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74155 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-02soc/intel/meteorlake: Add EPP override supportSubrata Banik
This updates energy performance preference value to all logical CPUs when the corresponding chip config is true. This patch is backported from `commit 0bb2225718ef898c ("soc/intel/alderlake: Add EPP override support")`. BUG=b:266522659 TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8172276159fe3987dae36ec30ebceb76dd0ef326 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74154 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-02commonlib/coreboot_tables.h: Replace spaces with tabsAngel Pons
Indent with tabs for the sake of consistency with the rest of the code. Change-Id: Ibd325a7a8348cc1f9023e54dceab40d02a0df233 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-04-02soc/intel/alderlake: Add ADL-P 4+4 with 28W TDPPatrick Rudolph
Add the 28W TDP version of the ADL-P with MCHID 0x4629. Verified that all 28W SoCs have the same PL1/PL2 defined in Intel document #655258 "12th Generation Intel Core Processors Datasheet, Volume 1 of 2". Fixes the error seen in coreboot log: [ERROR] unknown SA ID: 0x4629, skipped power Limit Configuration Change-Id: Iad676f083dfd1cceb4df9435d467dc0f31a63f80 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-04-01mb/google/rex: Add FW_CONFIG for FP/UWB/WIFISubrata Banik
This patch adds FW_CONFIG to accommodate different Rex BoM components across various SKUs. 1. Fingerprint sensor - FP Present/Absent 2. Ultra wideband - UWB Absent/Using BITBANG/Using GSPI1 3. WIFI - CNVi/PCIe TEST=Able to build and boot google/rex. Change-Id: I97b0dc25f239103a0a235f14b50008a633e2f88d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com>
2023-04-01mb/google/rex: Update Rex Flash LayoutSubrata Banik
This patch updates the Rex flash layout to allow CSE Lite FW update and accommodate multiple ESx SoC stepping blobs. For default chromeos.fmd SI_BIOS: RW_SECTION_A/B: Increased by ~1.9MB. RW_LEGACY: Reduce to 1MB. RW_MISC: Reduce to 152KB. - Drop RW_SPD_CACHE - Optimize other sections Additionally, moved RW_LEGACY under extended BIOS region. For chromeos-debug-fsp.fmd SI_BIOS: RW_SECTION_A/B: Increased by ~1.2MB. RW_LEGACY: Dropped RW_MISC: Reduce to 152KB. - Drop RW_SPD_CACHE - Optimize other sections BUG=b:262868089 TEST=Able to enable CSE update on google/rex and have free space to add one more PUNIT FW for support different SoC stepping. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6146b36c4ce2c0141277eeb906d6ad1f503f3c78 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-01soc/amd/stoneyridge: factor out P-state utils to link in all stagesFelix Held
tsc_freq.c gets built into all stages, but the tsc_freq_mhz function it implements calls the get_pstate_0_reg function which was only built into ramstage. Since tsc_freq_mhz was only called in ramstage, commit 2323acab6a7a ("soc/amd/stoneyridge: implement and use get_pstate_0_reg") didn't cause the build to fail, but better factor out the P-state- related utility functions into a separate compilation unit and include it in all stages that also include tsc_freq.c. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id3a3ee218f495be5e60a888944487704e7e8a1a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-04-01soc/amd/stoneyridge/Makefile: use all target for more compilation unitsFelix Held
monotonic_timer.c, tsc_freq.c and uart.c get added to all stage targets, so just add those to the all stage targets. They still need to be added to the smm stage target, since the all target doesn't add things to the smm stage. TEST=Timeless build results in identical image for Gardenia. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I16c02bc0ff54553f212b94d110abef6a7bdedbb4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74144 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-01soc/intel/xeon_sp/spr: Add ACPI support for Sapphire RapidsJonathan Zhang
Add ACPI support for Sapphire Rapids. Passes FWTS ACPI tests. The code was written from scratch because there are Xeon-SP specific implementation especially Integrated Input/Output (IIO). Change-Id: Ic2a9be0222e122ae087b9cc8e1859d257e3411d6 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71967 Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-01mb/google/rex: Add fmd for debug FSPSubrata Banik
Debug FSP is ~920KiB larger than release FSP and we don't have sufficient space for rex flash layout. Remove RW_LEGACY and split them into RW_SECTION_A/B so we can have a room for it. Note: This fmd will only used for internal testing/debugging and not for the firmware in released devices. BUG=b:262868089 TEST=Build google/rex with CONFIG_BUILDING_WITH_DEBUG_FSP. Change-Id: I58b0af9c43c5d096dc80084497b39f13f67c25cd Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-01soc/intel/meteorlake: Add BUILDING_WITH_DEBUG_FSPSubrata Banik
Intel FSP has "debug" build which is not public, used for debugging by approved developers. Add a Kconfig to indicate that coreboot is building with debug version of FSP so we can adjust few things (i.e. flash layout) in the case. BUG=b:262868089 TEST=Able to build and boot google/rex. Change-Id: I5555a2ab4182ad0036c42be6fea3d934ffd0db8c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-01soc/intel/meteorlake: Fix PortUsb30Enable configurationIvy Jian
PortUsb30Enable has been overridden unexpectedly, this patch fixed it. BUG=b:276181378 Test=boot to rex and check USB3 ports are working. Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: Ic04b9eb236ed28a76ee516c52fc0c983cb8f2c0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-01soc/intel/meteorlake: Enable 'struct cpu_info' update for MTLSridhar Siricilla
The patch enables addition of core_type member to 'struct cpu_info' for MeteorLake platform. TEST=Build and verify the code for Rex Change-Id: I01abed6b87bec2f8eb39bfc941faff070b83abe6 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74130 Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-31soc/amd/common/block/cpu/tsc/Makefile: order targets by stageFelix Held
Now that only one build target per stage is included in the build depending on CONFIG_SOC_AMD_COMMON_BLOCK_TSC being set, don't use a separate ifeq block for this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id9e551b37707081eb2ea1d682013f57c7ca8aabd Reviewed-on: https://review.coreboot.org/c/coreboot/+/74017 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-31soc/amd/common/cpu: use TSC_MONOTONIC_TIMER for SOC_AMD_COMMON_BLOCK_TSCFelix Held
All AMD SoCs with Zen-based CPU cores are already using timestamps based on the TSC counter, so use the existing common infrastructure instead of reimplementing it in a similar way. The behavior of the code changes slightly, but results in identical timestamps. The timestamp_get implementation in soc/amd/common/block/cpu divided the result of rdtscll() in timestamp_get by the result of tsc_freq_mhz() and didn't override the weak timestamp_tick_freq_mhz implementation that returns 1. The non AMD specific code returns the result of rdtscll() in timestamp_get, but returns tsc_freq_mhz() instead of 1 in timestamp_tick_freq_mhz, so we still get the correct timestamps. TEST=The raw timestamps printed on the serial console are now multiplied by the expected factor of the TSC frequency in MHz. TEST=Normalized timestamps printed on the serial console by the x86 code don't change significantly on Mandolin when comparing before and after this patch. A slight variation in the timestamps is expected. An example would be: Before: CPU_CLUSTER: 0 init finished in 630 msecs After: CPU_CLUSTER: 0 init finished in 629 msecs TEST=The calculations of the time spent in verstage on PSP before entering the bootblock on Guybrush result in similar times when multiplying the value before the patch with the TSC frequency in the case with the patch applied. The raw values printed on the serial console by the verstage on PSP use the 1us time base, but the timestamp logs that end up in CBMEM will be fixed up to use the same time base as the x86 part of coreboot. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I57b732e5c78222d278d3328b26bb8decb8f4783e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-03-31mb/google/skyrim: Disable L1.2 for SD portMartin Roth
Having L1.2 enabled on the SD port increases the kernel resume times by between 30 & 40ms. This patch disables L1.2 on SD to get that time back. As with needing to have hotplug enabled on the SD card, this seems like a driver issue, so hopefully that will get sorted out and this patch can be reverted. BUG=b:274025743 TEST=resume times are decreased. BRANCH=skyrim Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I2c409fa2cd66c712c5ba7104635499d63fa0d2be Reviewed-on: https://review.coreboot.org/c/coreboot/+/74118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-03-31mb/google/brya: Enable asynchronous End-Of-PostJeremy Compostella
Set the `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag to request End-Of-Post right after PCI enumeration and handle the command response at `BS_PAYLOAD_BOOT'. With these settings we have observed a boot time reduction of about 20 to 30 ms on brya0. BUG=b:268546941 BRANCH=firmware-brya-14505.B TEST=Tests on brya0 with `SOC_INTEL_CSE_SEND_EOP_ASYNC' show End-Of-Post after PCI initialization and EOP message received at `BS_PAYLOAD_BOOT'. Change-Id: I81e9dc66f952c14cb14f513955d3fe853396b21c Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73922 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-31soc/intel/cmn/cse: Handle EOP completion asynchronouslyJeremy Compostella
coreboot supports three instances of sending EOP: 1. At CSE `.final' device operation 2. Early as with Alder Lake in chip_operations.init if `SOC_INTEL_CSE_SEND_EOP_EARLY' is selected 3. At BS_PAYLOAD_BOOT as designed for Meteor Lake if `SOC_INTEL_CSE_SEND_EOP_LATE' is selected Currently, Alder Lake uses #3 as it results in better and more stable boot time. However, what would deliver even better result is to not actively wait for CSE completion. This patch introduces a new `SOC_INTEL_CSE_SEND_EOP_ASYNC' Kconfig which split the action of sending EOP request and receiving EOP completion response from the CSE. This patch used in conjunction with #1 can significantly improves the overall boot time on a Raptor Lake design. For example `SOC_INTEL_CSE_SEND_EOP_ASYNC' on a skolas board can deliver up to 36 ms boot time improvement as illustrated below. | # | Late EOP | Async EOP | |----------+----------+-----------| | 1 | 1020.052 | 971.272 | | 2 | 1015.911 | 971.821 | | 3 | 1038.415 | 1021.841 | | 4 | 1020.657 | 993.751 | | 5 | 1065.128 | 1020.951 | | 6 | 1037.859 | 1023.326 | | 7 | 1042.010 | 984.412 | |----------+----------+-----------| | Mean | 1034.29 | 998.20 | | Variance | 4.76 % | 5.21 % | The improvement is not stable but comparing coreboot and FSP performance timestamps demonstrate that the slowness is caused by a lower memory frequency (SaGv point) at early boot which is not an issue addressed by this patch. We also observe some improvement on an Alder Lake design. For example, the same configuration on a kano board can deliver up to 10 ms boot time improvement as illustrated below. | # | Late EOP | Async EOP | |----------+----------+-----------| | 0 | 1067.719 | 1050.106 | | 1 | 1058.263 | 1056.836 | | 2 | 1064.091 | 1056.709 | | 3 | 1068.614 | 1055.042 | | 4 | 1065.749 | 1056.732 | | 5 | 1069.838 | 1057.846 | | 6 | 1066.897 | 1053.548 | | 7 | 1060.850 | 1051.911 | |----------+----------+-----------| | Mean | 1065.25 | 1054.84 | The improvement is more limited on kano because a longer PCIe initialization delays EOP in the Late EOP configuration which make it faster to complete. CSME team confirms that: 1. End-Of-Post is a blocking command in the sense that BIOS is requested to wait for the command completion before loading the OS or second stage bootloader. 2. The BIOS is not required to actively wait for completion of the command and can perform other operations in the meantime as long as they do not involve HECI commands. On Raptor Lake, coreboot does not send any HECI command after End-Of-Post. FSP-s code review did not reveal any HECI command being sent as part of the `AFTER_PCI_ENUM', `READY_TO_BOOT' or `END_OF_FIRMWARE' notifications. If any HECI send and receive command has been sent the extra code added in `cse_receive_eop()' should catch it. According to commit 387ec919d9f7 ("soc/intel/alderlake: Select SOC_INTEL_CSE_SEND_EOP_LATE"), FSP-silicon can sometimes (on the first boot after flashing of a Marasov board for instance) request coreboot to perform a global request out of AFTER_PCI_ENUM notification. Global request relies on a HECI command. Even though, we tested that it does not create any issue, `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag should not be associated to the `SOC_INTEL_CSE_SEND_EOP_EARLY' flag to prevent potential a global reset command to "conflict" with the EOP command. BUG=b:276339544 BRANCH=firmware-brya-14505.B TEST=Tests on brya0 with and `SOC_INTEL_CSE_SEND_EOP_ASYNC' show End-Of-Post sent soon after FSP-s and EOP message receive at `BS_PAYLOAD_BOOT'. Verify robustness by injecting a `GET_BOOT_STATE' HECI command with or without `heci_reset'. The implementation always successfully completed the EOP before moving to the payload. As expected, the boot time benefit of the asynchronous solution was under some injection scenario undermined by this unexpected HECI command. Change-Id: Ib09dcf9140eb8a00807a09e2af711021df4b416f Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73619 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-03-31soc/amd/picasso/graphics: use RAVEN2_VBIOS_REV with RAVEN2_VBIOS_VID_DIDFelix Held
In order for the code to find the correct VBIOS file in CBFS, remap the revision ID in the RAVEN2_VBIOS_VID_DID case to the one that matches the CBFS file name. This will make the code work as expected on devices with the PCI ID RAVEN2_VBIOS_VID_DID and a revision != RAVEN2_VBIOS_REV. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I94412dc2e778e7c4f74e475cd49114a00a81b2ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/74045 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-31mb/intel/dq67sw: Add LGA1155 microATX mainboardMichael Büchler
This is a new port for the Intel DQ67SW desktop board. It is microATX-sized with an LGA1155 socket and four DIMM sockets for DDR3 SDRAM. A list of tested working and non-working features is in the documentation page. Change-Id: Ifc703f2d0ad45495e71d3f7799347430f5196791 Signed-off-by: Michael Büchler <michael.buechler@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-31mb/google/dedede/var/kracko: Add fw_config probe for ALC5682-VD/ALC5682-VSRobert Chen
ALC5682-VD/ALC5682-VS use different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:275644832 TEST=emerge-dedede coreboot BRANCH=firmware-dedede-13606.B Change-Id: I644f3aa3187e08146d78abb70a568833bc9b9211 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-31mb/google/nissa/var/uldren: Update gpio settingsVan Chen
Configure GPIOs according to schematics(ver. 20230308). BUG=b:272829190 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Id414c9b0d94faffd2d71c348fc7146a6101196e9 Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-03-31mb/google/brya/variants/hades: Add initial GPIO config for hades boardTarun Tuli
Initial hades GPIO config. Combination of original brya basebaord, Agah and new arbitrage output for hades design. Also moved GPIO config to the non baseboard variant model as we did on rex0. BUG=b:269371363 TEST=builds Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I2a850240dd7f3ddf137d6a2ebe8a147f8976c16b Reviewed-on: https://review.coreboot.org/c/coreboot/+/72679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-31soc/intel/alderlake: Enable 'struct cpu_info' update for ADLSridhar Siricilla
The patch enables addition of core_type member to 'struct cpu_info' for Alderlake platform. TEST=Build and verify the code for Gimble Change-Id: Ia065b98c2013e78328fd38bed9c667792d6d1f4d Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74089 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-31soc/intel/common: Add core_type member to 'struct apic_path'Sridhar Siricilla
The patch adds new member 'core_type' to the 'struct apic_path' and updates core type information. TEST=Build the code for MTL Change-Id: I1d34068fd5ef43f8408301bf3effa9febf85f683 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74088 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-30soc/amd/picasso/graphics: refactor map_oprom_vendev_revFelix Held
Refactor map_oprom_vendev_rev as a preparation to also remap the revision ID in the RAVEN2_VBIOS_VID_DID case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3b81a9464ed49672889fcb767920154fe6efdfcc Reviewed-on: https://review.coreboot.org/c/coreboot/+/74044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-03-30mb/amd/birman/early_gpio: Add M2 SSD resetsFred Reitberger
Add early configuration of the GPIOs that control the M2 SSD resets. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I81439d193bdd7296d8a8fea83c5c6be2c75adbea Reviewed-on: https://review.coreboot.org/c/coreboot/+/73989 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-30mb/amd/birman/port_descriptors.c: Add USB-C configurationFred Reitberger
Add option decode for USB-C DDI connection type and remove unnecessary break after return. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: If38fa667daeb2dd176ecdf33abaec9b56d633a2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-03-30Revert "mb/google/rex: Enable VPU"Kapil Porwal
This reverts commit 555ceca38a78 ("mb/google/rex: Enable VPU"). Reason: Unable to boot to latest OS image with VPU enabled. BUG=none TEST=Boot to OS image 15376 on google/rex Change-Id: If61282528922304373d492b362056b52995cbcad Signed-off-by: Kapil Porwal <kapilporwal@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paz Zcharya <pazz@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-03-30mb/asrock/h77pro4-m: Make onboard NIC a child device below PCIe port 6Kevin Keijzer
The Realtek RTL8111E NIC is currently not defined as a child device, resulting in the on_board flag not being set to 1. This means that Linux / udev will call the device enp4s0 rather than eno0, as is appropriate for on-board ethernet devices. This patch defines the NIC as a child device of PCIe port 6, so that it's properly defined as an on-board device. Change-Id: I2e1b65e4d27852297a739e332c52c15a8c81b858 Signed-off-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74090 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-30drivers/intel/fsp2_0/hand_off_block: use cb_err in fsp_find_range_hobFelix Held
Use enum cb_err as return value of fsp_find_range_hob instead of using the raw -1 and 0 values. Also update the call sites accordingly. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id6c9f69a886f53868f1ef543c8fa04be95381f53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-30soc/amd/common/block/cpu/noncar/memmap: simplify return value checkFelix Held
Since the return value of the fsp_find_range_hob call is only used in one location, move the call and return value check into the if condition block to not need the status variable. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4b9e9251368b86382dc4e050cf176db79dbfb230 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-30console: Deselect using ANSI escape characters when SimNow is usedZheng Bao
To remove the annoying "ESC [1m" at SimNow console window. Change-Id: I300aee946f342f41b94288b75b843956de9d3e88 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-03-30mb/prodrive/atlas: Rework EEPROM layout structuresAngel Pons
To avoid having to calculate the length of a struct separately, rework the code to give the struct a tag name, so that `sizeof()` can be used instead. This involves refactoring the `get_emi_eeprom_vpd()` function to return a struct instead of a union, so callers can no longer access the EEPROM data as an array of bytes without additional code, but this array view is only used inside `get_emi_eeprom_vpd()` when reading the data from EMI. Change-Id: Id1bc40939631baa131b5f60eadbfe42838294ebe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-30soc/intel/alderlake: Avoid reprogramming the SRAM BARSubrata Banik
This patch avoids the redundant programming of SRAM BAR when the SRAM PCI device is enabled. Rather read the PCH SRAM Base Address Register while enabling crashlog feature. Additionally, this patch relies on PCI enumeration to get the SRAM BAR rather than hijacking the SPI temporary base address which might have resulted in problems if SPI is disabled on some platform with BAR being implemented. TEST=Able to build and boot google/marasov and crashlog is working. Change-Id: I8eb256aa63bbf7222f67cd16a160e71cfb89875a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-03-30mb/google/nissa/var/yavilla: Disable storage devices based on fw_configTony Huang
Disable devices in variant.c instead of adding probe statements to devicetree because storage devices need to be enabled when fw_config is unprovisioned, and devicetree does not currently support this (it disables all probed devices when fw_config is unprovisioned). BUG=b:273791621 TEST=emerge-nissa coreboot Change-Id: I1a6013e0ad0c430d83bbbad4b92392c8c4815b0d Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-30mb/google/nissa/var/yavilla: Update devicetree settingTony Huang
Update devicetree according to yavilla's design. Add Kconfig for TPM I2C bus. BUG=b:273791621 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I1b44436a7f93d62764d0451c738ae33976a24a15 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-03-30mb/google/skyrim: Use die_no_apcbFred Reitberger
Use die_no_apcb to cause a build error when the APCB or SPD sources are not found. TEST=builds with and without matching APCB and SPD sources Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I62dce2c71061bfc5c01e0344b7dc115a47669140 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-29mb/google/skyrim: Get ready to add MP2 firmwareMartin Roth
This sets the location of the skyrim MP2 firmware within the mainboard's blobs directory, and adds the Kconfig option to the mainboard directory so that it can be enabled in a saved .config file. The skyrim MP2 firmware is skyrim specific, so it should not be placed in the main PSP AMD_BLOBS directory. We will also only want to enable the MP2 firmware for chromeos builds as it's not useful for non-chromeos builds. BUG=b:259554520 TEST=Build MP2 firmware into image, see that it gets loaded BRANCH=skyrim Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I04be6f2d0b605d4eca37fd927a70310259dc106c Reviewed-on: https://review.coreboot.org/c/coreboot/+/73659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-03-29soc/amd/stoneyridge: use common AMD CPU power state ACPI generationFelix Held
Instead of using the PSTATE SSDT generated by binaryPI, use the common AMD code by selecting SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE. To match the SSDT from binaryPI, set ACPI_SSDT_PSD_INDEPENDENT to n. There are two differences to the binaryPI SSDT: Now coreboot includes the C1 state in the _CST package instead of just having the kernel add this due to the ACPI_FADT_C1_SUPPORTED bit being set and the address of the PS_STS_REG P state status MSR is written to the corresponding field of the _PCT package instead of being 0. TEST=On Careena the new P and C state ACPI packages are nearly identical to the ones from the SSDT from binaryPI with the two functional differences mentioned above. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icdf6bc8f0e0363f185a294ab84edcb51322e7eb7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-29soc/amd/stoneyridge/cpu: implement get_pstate_latencyFelix Held
Both the algorithm and the registers involved are described in the public version of BKDG #55072 Rev 3.09 in chapter 2.5.2.1.7.3.2 _PSS (Performance Supported States). Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9b2c177d9d80c5c205340f3f428186d6b8eb7e98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-29soc/amd/picasso/Kconfig: update help text for 2nd VBIOS ID detectionFelix Held
The help text for VGA_BIOS_SECOND_ID was outdated and from a time before we found out that just looking at the CPUID doesn't reliably tell us on which type of silicon we're running and which VBIOS file to pick, so we had to use a different method. Update the help text to match what the code does. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia568771ed7dfa0c7bb850b0efcd2959d7ddfd4a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73335 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-29soc/amd/common/acpi/cpu_power_state: introduce & use get_pstate_latencyFelix Held
On the Zen-based CPUs, the transition and bus master latency are always written as 0, but on but on Stoneyridge hardware-dependent values are used. Introduce get_pstate_latency that returns 0 for all non-CAR AMD CPUs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I81086fa64909c7350b3b171ea6ea9b46f1708f67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-29soc/amd/stoneyridge: implement and use get_pstate_0_regFelix Held
Introduce get_pstate_0_reg and use it in tsc_freq_mhz to get the P state register number corresponding to P state 0. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7b92a858bf36b04a570d99c656e5ccfc84457724 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-29soc/amd/common/acpi/cpu_power_state: introduce and use get_pstate_0_regFelix Held
On the Zen-based CPUs, P state 0 corresponds to the first P state MSR, but on Stoneyridge this isn't the case. Introduce get_pstate_0_reg that returns 0 for all non-CAR AMD CPUs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icc11e5b6099d37edb934e66fe329d8013d25f68d Reviewed-on: https://review.coreboot.org/c/coreboot/+/74021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-29soc/amd/common/acpi/cpu_power_state: factor out get_visible_pstate_countFelix Held
Factor out the MSR access into a function with a more descriptive name. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I331c3205390edcbd8749b2d52b7cc7ac3a8ced5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/74020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-29soc/amd/stoneyridge/acpi: add C state config tableFelix Held
The C state ACPI packages binaryPI generates and passes to coreboot in the PSTATE SSDT only include the C2 state, but the kernel will add the C1 state to its usable C states in this case. The native C state code will generate both the C1 and C2 state packages to be more complete and also to be more in line with the other AMD SoCs. The code added in this commit isn't used yet, but will be used as soon as Stoneyridge will be using the common AMD generate_cpu_entries by selecting SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE once all needed helper functions are implemented for Stoneyridge. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I06f90306ac196704e0102d0da6eab03f51513c29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-29soc/amd/common/block/cpu/Kconfig: drop FAM17H_19H suffix from TSC optionFelix Held
The SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H option is valid for all SoCs with Zen-based CPU cores including the family 1Ah, so remove the suffix. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I58d29e69a44b7b97fa5cfeb0e461531b926f7480 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-29soc/amd/common/block/cpu/tsc_freq: move static variable inside functionFelix Held
Move the static mhz variable inside the only function that is accessing it. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ief98c0a1c35fe1bbc4ff38dd175f12e0b3ddc515 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-29soc/amd/common/block/cpu/tsc/tsc_freq: use get_pstate_core_freqFelix Held
Use get_pstate_core_freq instead of open-coding the calculations in tsc_freq_mhz. In the case of the CPU frequency divider being 0, get_pstate_core_freq will return 0; in this case that shouldn't happen, TSC_DEFAULT_FREQ_MHZ will be used as frequency, since for the TSC frequency it's better to err on the end of the expected frequency being too high which will cause longer than expected delays instead of too short delays. Now that the code is using get_pstate_core_freq, this code is valid for Glinda too, so also remove the comment on the SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H option being selected in the Glinda Kconfig. This Kconfig option will be renamed in a follow-up patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I01168834d4018c92f44782eda0c65b1aa392030d Reviewed-on: https://review.coreboot.org/c/coreboot/+/74013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-29soc/amd/stoneyridge/tsc_freq: use get_pstate_core_freqFelix Held
Use get_pstate_core_freq instead of open-coding the calculations in tsc_freq_mhz. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If5d526e6b365c62a6669241f4fcdd25eca3f15fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/74012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-29soc/amd/common/cpu/tsc: add get_pstate_core_freq for family 15h and 16hFelix Held
This function will be used in follow-up patches for both the TSC rate calculation and the still to be implemented P state ACPI table generation in coreboot. The was checked against BKDG 52740 Rev 3.05, BKDG #55072 Rev 3.04, and BKDG #50742 Rev 3.08. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9afaa044da994d330c3e546b774eb1f82e4f30e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-29soc/amd/common/cpu/tsc: factor out family-specific get_pstate_core_freqFelix Held
Factor out the get_pstate_core_freq function from the SoC's acpi.c files to both avoid duplication and to also be able to use the same function in the TSC frequency calculation in a follow-up patch. The family 17h and 19h SoCs use the same frequency encoding in the P state MSRs while the family 1Ah SoCs use a different encoding. The family 15h and 16h SoCs use another encoding, but since this isn't implemented in Stoneyridge's acpi.c, this will be added in a follow-up patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8619822c2c61e06ae5db86896d5323c9b105b25b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-29soc/amd/stoneyridge/monotonic_time: add comment that we can't use TSCFelix Held
Due to a non-constant TSC rate before the microcode update is applied, the Performance Time Stamp Counter is used instead. To clarify this, add a comment to the timestamp_get implementation. See commit 24079323d4d8 ("soc/amd/stoneyridge: provide alternate monotonic timer") and the description of the TscInvariant bit in CPUID Fn8000_0007_EDX Advanced Power Management Information in the public version of BKDG #55072 Rev 3.09 for more details. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I824b372c36fa6f3eb912469b235a9474f6a58ff5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-29mb/google/skyrim/var/winterhold: adjust the eDP panel power sequenceChris.Wang
set pwr_on_varybl_to_blon to 0x1c, which means fw will delay 112ms between backlight on and vary backlight. BUG=b:271704149 BRANCH=none TEST=Build; Verify the UPD was passed to system integrated table; measure the power on sequence on whiterun Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ib966d2ebd4ef4a8085695901ec5da160f467e32e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-03-29soc/amd/mendocino: Add FSP parameter for eDP power sequence adjustmentChris.Wang
Add UPD parameter for eDP power sequence adjust. The pwr_on_vary_bl_to_blon is set one unit per 4ms. BUG=b:271704149 TEST=Build; Verify the UPD was pass to system integrated table; measure the power on sequence on whiterun Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I25c9f962e70f599c780259f0943a03f8aa7cbfd1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2023-03-29vc/amd/fsp/mendocino/FspmUpd: Update UDP structure for MDN-FSPChris.Wang
Update UPD structure to align with MDN-FSP. BUG=b:271704149 BRANCH=none TEST=Build/Boot to Chrome OS Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ie4021cebb57e3ec22191486aafd9099eec0fbd99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2023-03-29arch/x86/smbios: Add socket type for Meteor LakeJay Patel
Add socket type for Meteor Lake as PROCESSOR_UPGRADE_OTHER. BUG=None TEST=processor upgrade is equal to "Other" for "dmidecode -t 4" Signed-off-by: Jay Patel <jay2.patel@intel.com> Change-Id: If891990436a0679697e292b460eaec63c09e7bf8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-29mb/google/rex/Kconfig: Add SMBIOS mainboard version flagJay Patel
Add GOOGLE_SMBIOS_MAINBOARD_VERSION flag for rex board. BUG=None TEST=Verfied board ID for rex using "crossystem" command, giving the output as 1. Without CL: localhost ~ # crossystem arch = x86 # [RO/str] Platform architecture backup_nvram_request = 1 # [RW/int] Backup the nvram somewh battery_cutoff_request = 0 # [RW/int] Cut off battery and shu block_devmode = 0 # [RW/int] Block all use of develo board_id = (error) # [RO/int] Board hardware revision clear_tpm_owner_done = 0 # [RW/int] Clear TPM owner done With CL: localhost ~ # crossystem arch = x86 # [RO/str] Platform architecture backup_nvram_request = 1 # [RW/int] Backup the nvram somewh battery_cutoff_request = 0 # [RW/int] Cut off battery and shu block_devmode = 0 # [RW/int] Block all use of develo board_id = 1 # [RO/int] Board hardware revision clear_tpm_owner_done = 0 # [RW/int] Clear TPM owner done Signed-off-by: Jay Patel <jay2.patel@intel.com> Change-Id: I644ed7a948f0094a0be080153d83eaa2e37b8f1f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74037 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-29nb/intel/i440bx/debug.c: Refactor newlines and save some printk callsKeith Hui
There are two conditions within the config space dump code, one to print offset, one at the end to put a newline. Tweak the printk strings so the first conditioned printk does it all and move the second printk out of the loop to the very end. Change-Id: Ie9dc744406ba20412892df96720e88e24c3d52bc Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73887 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-29mb/google/brya/var/crota: Add lp5x memory parts for `K3KL6L60GM-MGCT`Terry Chen
Update the mem_parts_used.txt, generate Makefile.inc and dram_id.generated.txt for this part. DRAM Part Name ID to assign K3KL6L60GM-MGCT 5 (0101) BUG=b:267249674 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I20a12a58d8a3d66a901a14569ca710acba3c05f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73920 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-03-29soc/intel/common: Add Intel Trace Hub driverPratikkumar Prajapati
From Meteor Lake onwards Intel FSP will generate the Trace Hub related HOB if the Trace Hub is configured to save data in DRAM. This memory region is used by Trace Hub to store the traces for debugging purpose. This driver locates the HOB and marks the memory region reserved so that OS does not use it. Intel Trace Hub developer manual can be found via document #671536 on Intel's website. Change-Id: Ie5a348071b6c6a35e8be3efd1b2b658a991aed0e Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-03-29drivers/intel/fsp2_0: Add API to find FSP resource HOB by GUIDPratikkumar Prajapati
The API finds the FSP resource HOB for the given GUID. Returns the pointer to the HOB if found, otherwise NULL Change-Id: I4ebc9b7d214e5fc731ae45f28e7f5732a7635cbc Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-03-29soc/intel/cmn/crashlog: Add check for zero based SRAM BARSubrata Banik
This patch adds a check for zero based SRAM base address. It will help to avoid running into problems if the SRAM is disabled and the base address register is zero. TEST=Able to build and boot google/marasov with PCH SRAM being disabled. Change-Id: Iebc9dc0d0851d5f83115f966bf3c7aad1eb6bc01 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-29vc/intel/fsp/mtl: Update header files from 3064_81 to 3084_85Kilari Raasi
Update header files for FSP for Meteor Lake platform to version 3084_85, previous version being 3064_81. FirmwareVersionInfo.h: 1. Define INTEL_FVI_SMBIOS_TYPE macro FSPM: 1. Remove deprecated UPD `BclkSource` 2. Address offset changes FSPS: 1. Add `CnviWifiCore` UPD 2. Address offset changes BUG=b:274051289 TEST=Able to build and boot google/rex to ChromeOS. Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Change-Id: I24dea1a31dbb592f9dea4246a3d490e5d23dca9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/73832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-29mb/google/nissa/var/yavilla: Update GPIO settingShon Wang
Configure GPIOs according to schematics. BUG=b:273791621 TEST=emerge-nissa coreboot Change-Id: I5a522b59468667d20674d55597cc06975bc12ab5 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
2023-03-28soc/amd/stoneyridge/graphics: introduce defines for constantsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2021a106e0d3a603b1a05296411700ffea32fc8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/74042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-28soc/amd/stoneyridge: move map_oprom_vendev to graphics.cFelix Held
Move map_oprom_vendev to graphics.c to match the other AMD SoCs. Also change the comment style to be more in line with the rest of coreboot and drop the unneeded line break in the printk call. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icc1f3d73fba973413c5a22e2f5ae01bc58bc3e76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-28soc/amd/stoneyridge/Kconfig: use correct VGA_BIOS_IDFelix Held
Fix the VGA_BIOS_ID IDs to match the PCI IDs in the VBIOS binaries and the PCI ID Stoneyidge's map_oprom_vendev returns. This fixes the problem that the display wasn't initialized due to not finding the VBIOS file in CBFS. This bug in the Stoneyridge Kconfig was unmasked by commit 42f0396a1028 ("device/pci_rom: rework PCI ID remapping in pci_rom_probe"). TEST=Display in Careena lights up again. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4d1e6a3a65d7d7b07f49df9ce90620b79d9a2d78 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74019 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-28soc/intel/xeon_sp: Use simple device function for setting PMAX_LOCKJonathan Zhang
Change to use simple device function for setting PMAX_LOCK because the Sapphire Rapids PCU device is not scanned during coreboot PCIe bus scan and would see "PCI: dev is NULL!" failure. Change-Id: I3156a6adf874b324b5f4ff5857c40002220e47ab Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72400 Reviewed-by: Simon Chou <simonchou@supermicro.com.tw> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-27soc/amd/stoneyridge/Kconfig: select SOC_AMD_COMMON_BLOCK_SVI2Felix Held
Stoneyridge uses the serial voltage ID 2 standard to tell the VRM on the board which voltage it wants, so select the SOC_AMD_COMMON_BLOCK_SVI2 Kconfig option to have the corresponding code to decode the raw SVI2 value into a voltage. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7d7031d9ad997a86c18d0e9e7af9a88ddf2d873c Reviewed-on: https://review.coreboot.org/c/coreboot/+/73999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-27mb/google/geralt: Set up open-drain ChromeOS pinsjason-ch chen
Set open-drain GPIOs for ChromeOS as input and bias-disable mode. After applying this patch, the voltage of these pins will become the expected value 1.8V (previously 1.0V), preventing wrong judgement of low/high. Reference document: MT8188G_GPIO_Formal_Application_Spec_V0.3 BUG=b:274058085 TEST=build pass Change-Id: I057716df6c59efb84fc395109db022b82ce528c4 Signed-off-by: jason-ch chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73963 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-27mb/google/skyrim: Add UPD usb3_port_force_gen1 for skyrimPatrick Huang
Add UPD usb3_port_force_gen1 for skyrim The default setting is set to disable Skyrim -> set default as disable BUG=b:273841155 BRANCH=skyrim TEST=Build, verify the setting will be applied on skyrim. Change-Id: Id53bed82a9fef93b574c3f30830555e02d7f4737 Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-03-27soc/amd/common/block/cpu/Makefile: group build targets by stageFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idb6087dc44e76ab63bc6b462c3328c23d83ae018 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74009 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-27soc/amd/common/block/cpu/svi2: drop unneeded core_vid checkFelix Held
A core voltage ID larger than 0xff shouldn't happen, since SVI2's core VID is only 8 bit long. In order for making it more difficult to use this function in a wrong way that results in a very wrong voltage being returned, also return 0 for those invalid core VID values. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I95417c45db86cd2373879cdad8a07fb9eb8dfdda Reviewed-on: https://review.coreboot.org/c/coreboot/+/74000 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-27soc/amd/mendocino: Add UPD to support USB3 force to gen1 by portPatrick Huang
Add UPD usb3_port_force_gen1 to support USB3 port force to gen1 BUG=b:273841155 BRANCH=skyrim TEST=Build, verify USB3 port setting to gen1. Change-Id: Iaa476f56cf10588d7de2203deca4122958c00783 Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-03-27vc/amd/fsp/mendocino:Add fch_usb_3_port_force_gen1 tp AGESA FSP-M UPDPatrick Huang
To add fch_usb_3_port_force_gen1 parameter to force usb3 port to gen1 BUG=b:273841155 BRANCH=None TEST=Build Change-Id: I7560abb9a5fda6af3c2814f8b26c92925d8c17f4 Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-03-27soc/amd/mendocino: Add UPDs for DPTC current limitsPatrick Huang
Add UPD vrm_current_limit_mA, vrm_maximum_current_limit_mA, vrm_soc_current_limit_mA for DPTC. Make sure UPD parameterare are set to be aligned. BUG=b:245942343 BRANCH=none TEST=confirm the UPD parameters has been set correspondingly with the FSP UPD. Change-Id: Iacf0ce0d51d4c8698ec1ae7e810fd00574deeadb Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73875 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-03-27soc/amd/stoneyridge/include/msr: add pstate_msr bitfield structFelix Held
Add the pstate_msr union of a bitfield struct and a raw uint64_t to allow easier access of the bitfields of the P state MSRs which will be used in future patches to generate the P state ACPI packages for the CPU objects. BKDG #55072 Rev 3.04 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I944c8598ba95a0333124655c61ef9eba8a7595c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73998 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-22 18:27:44 +0000