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2020-10-03soc/intel/xeon_sp/acpi: Rename pci_irq.aslMarc Jones
Rename pci_irq.asl to pci_irqs.asl to match other intel soc file names. This makes comparing differences much easier. Change-Id: I622dfef675c3df2dff7a3024ccbe14c356a5cd86 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45834 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03soc/intel/xeon_sp: Clean up pci_devs.hMarc Jones
Prepare for merging cpx and skx pci_devs.h. Remove duplicate defines. Move defines so they match each other. Checked TiogaPass and DeltaLake BUILD_TIMELESS. Change-Id: I146dd9e3f7eba053977d48dcf34d927dea310059 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45833 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03soc/intel: Make use of PMC low power program from common blockSubrata Banik
List of changes: 1. Select PMC_LOW_POWER_MODE_PROGRAM from applicable SoC directory 2. Remove redundant PMC programming from SoC and refer to common code block 3. Remove unused 'reg8' and 'reg32' variable as applicable from SoC function. Change-Id: I18894c49cfc6e88675b5fb71bca0412e5639fb4b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45796 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03soc/intel/common/block/pmc: Add PMC API for low power programmingSubrata Banik
List of changes: 1. Create Kconfig to select pmc low power program by SoC 2. Add API to make ACPI timer disable 3. Add API to ignore XTAL shutdown for SLP_S0# assertion Change-Id: I017ddc772f02ccba889d316319ab3d5626b80ba5 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45794 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03soc/intel: Move pch_misc_init() to common codeSubrata Banik
List of changes: 1. Move pch_misc_init() into common block code. 2. Remove redundant LPC functions from SoC directory and refer from block/lpc directory. 3. Create macros for IO port 0x61 and 0x70 as applicable. TEST=Able to build and boot hatch and tglrvp platform without seeing any functional impact. Change-Id: Ie36ee63869c076d251ccfa5409001d18f22600d7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-03soc/intel: Move soc_pch_pirq_init() to common codeSubrata Banik
List of changes: 1. Rename soc_pch_pirq_init() as pch_pirq_init() and move into common block code. 2. Remove redundant LPC functions from SoC directory and refer from block/lpc directory. TEST=Able to build and boot hatch and tglrvp platform without seeing any functional impact. Change-Id: I856b5ca024e58fd14b4d1721f23d9516a283ebf8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-03soc/intel: Move pch_enable_ioapic() to common codeSubrata Banik
List of changes: 1. Move pch_enable_ioapic() into common block code. 2. Remove redundant LPC functions from SoC directory and refer from block/lpc directory. TEST=Able to build and boot hatch and tglrvp platform without seeing any functional impact. Change-Id: I2a6afc1da50c8ee5bccda7f5671b516dc31fe023 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-03soc/intel/xeon_sp/include: De-duplicate .h filesMarc Jones
Move duplicate .h files to top level xeon_sp/include/soc from silicon specific cpx/include/soc and skx/include/soc. Change-Id: I11d8a95a4b2f9451615b236798b3bd030c724858 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45221 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03soc/intel/xeon_sp/skx: Prepare acpi.* for mergingMarc Jones
Clean up acpi.h in preparation for merging with cpx/ acpi.* files Change-Id: I2a0dc964eeb7f8da53676eb94c4385ff8668f6af Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45218 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03soc/intel/xeon_sp: Use common ASL code for xeon_spMarc Jones
Move and use the common xeon_sp/cpx/acpi asl for skx/. There were only minor whitespace differences between the directories. Update the mainboards to build the moved files. TiogaPass coreboot.rom checked with BUILD_TIMELESS. Change-Id: I5058a3fe8d96075a266fb92f10707bb94308c85b Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45217 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03soc/intel/xeon_sp/skx: Fix uncore.asl \_SB namespace issueMarc Jones
The skx uncore ACPI scope was missing the \ on \_SB causing the uncore IRQs to not be in the namespace. This addresses ACPI uncore IRQ routing issues. This was found preparing skx acpi to match cpx acpi for merging in the future. Check scope in dsdt.asl in tiogapass build. Change-Id: I799042babbe60287e5e4ec60b21c08d57ccda04b Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45269 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03soc/intel/xeon_sp/skx: Update ITSS OperationRegion to ACPI2.0 notationMarc Jones
Prepare for merge with cpx. Use the C style operators instead of the ACPI1.x polish notation. This is much easier to read and matches the cpx code. This generates the same ASL code. Checked with BUILD_TIMELESS on TiogaPass. Change-Id: Id44138894d2ffed4c93afe5d4bbb4d59b538b577 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45270 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03soc/intel/xeon_sp/skx: Update uncore IRQ routing ACPI tablesMarc Jones
Update the skx uncore ACPI routing tables to match cpx. This adds the IRQ routing for B-D for legacy and IOAPIC modes. Change-Id: Iac0ffdb467a78b9befe7402c074835ea602d43c8 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-02mrc_cache: Update mrc_cache data in romstageShelley Chen
Previously, we were writing to cbmem after memory training and then writing the training data from cbmem to mrc_cache in ramstage. We were doing this because we were unable to read/write to SPI simultaneously on older x86 chips. Now that newer chips allow for simultaneously reads and writes, we can move the mrc_cache update into romstage. This is beneficial if there is a reboot for some reason after memory training but before the previous mrc_cache_stash_data call originally in ramstage. If this happens, we would lose all the mrc_cache training data in the next boot even though we've already performed the memory training. Added new config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES to accomodate older x86 platforms that don't do mmapping but still want to use the cbmem to store the mrc_cache data in order to write the mrc_cache data back at a later time. We are maintaining the use of cbmem for these older platforms because we have no way of validating the earlier write back to mrc_cache at this time. BUG=b:150502246 BRANCH=None TEST=reboot from ec console. Make sure memory training happens. reboot from ec console. Make sure that we don't do training again. Signed-off-by: Shelley Chen <shchen@google.com> Change-Id: I3430bda45484cb8c2b01ab9614508039dfaac9a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44196 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-02soc/intel/braswell: Increase dcache sizeShelley Chen
Increase the DRAM cache size for Braswell to address the compilation error Cache as RAM area too full when moving the mrc_cache writeback to romstage. We need to increase this first before landing the CL moving mrc_cache writeback to romstage. BUG=b:150502246 BRANCH=None TEST=Able to successfully compile braswell boards Change-Id: I1538d504ddad8654c79a789e58ffe6b11b5d544c Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45827 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-02drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES configShelley Chen
Added new config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES to accomodate older x86 platforms that don't allow writing to SPI flash when early stages are running XIP from flash. If BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is not selected, BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY will get auto-selected if BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y. This allows for current platforms that write to flash in the earlier stages, assuming that they have that capability. BUG=b:150502246 BRANCH=None TEST=diff the coreboot.rom files resulting from running ./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a --timeless with and without this change to make sure that there was no difference. Also did this for GOOGLE_CANDY board, which is baytrail based (and has BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES enabled). Change-Id: I3aef8be702f55873233610b8e20d0662aa951ca7 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-10-02mb/clevo/l140cu: Add variant specific romstage.c to buildFelix Singer
While restructuring the mainboard directory, it was forgotten to add the variant specific romstage.c to the build. Therefore, add romstage.c to the Makefile fixing the raminit. Change-Id: I7afbf1574803128f7d62592eed2398c945334757 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45928 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-02drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory regionJonathan Zhang
APEI (ACPI Platform Error Interface) defines BERT (Boot Error Record Table) memory region: * Bootloader (firmware) generates UEFI CPER (Common Platform Error Record) records, and populates BERT region. * OS parses ACPI BERT table, finds the BERT region address, inteprets the data and processes it accordingly. When CONFIG_ACPI_BERT is defined, update FSP UPD BootLoaderTolumSize, so FSP allocates memory region for it. The APEI BERT region is placed on top of CBMEM, for the size of CONFIG_ACPI_BERT_SIZE. Apart from APEI BERT region, we also have plan to add APEI HEST region which holds OS runtime hardware error record, based on firmware first hardware error handling model. HEST region will be reserved same way as BERT region. Note that CBMEM region can not be used for such purpose, the OS (bert/hest) drivers are not able to access data held in CBMEM region, as CBMEM is set as type 16 (configuration table). An option considered was to reserve the BERT region under CBMEM. However, we do not know the size of CBMEM till acpi tables are set up. On the other hand, BERT region needs to be filled up before ACPI BERT table is finalized. Change-Id: Ie72240e4c5fa01fcf937d33678c40f9ca826487a Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-01mb/intel/tglrvp/variants/tglrvp_up4 - Enable onboard HDMI and type-C ↵Jason Le
displays for TGL-Y RVP - Enable DDC pins for DDI-B - Enable HPD pins for DDI-1/DDI-2 - Update MPHY/USB2 Mapping to match with the TGL-Y RVP schematic BUG: System not able to detect displays attached to onboard micro-HDMI or Type-C connectors TEST: hot-plug/unplug HDMI displays with onboard micro-HDMI connector and USB Type-C connectors to make sure the displays get detected and enabled Change-Id: I08a1b16a8fa45cf0f366661395b9f2aa25c44935 Signed-off-by: Jason Le <jason.v.le@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-01drivers: sn65dsi86: Retry link training up to 10 timesJulius Werner
The kernel guys have found that automatic link training from this bridge can occasionally fail and needs to be retried. They have added up to 10 retries just to be sure, so let's do the same in coreboot. BUG=b:169535092 Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I713b6851bd51d3527ed4c6e6407dee6b42d09955 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45882 Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-01mb/google/zork: Configure EMMC_RESET_L to drive highKevin Chiu
Configure EMMC_RESET_L (GPIO68) to drive high by default. As per JEDEC specification for eMMC, RST_n_FUNCTION defaults to temporarily disable reset using RST_n signal (which is connected to EMMC_RESET_L on zork). Chrome OS platforms do not configure RST_n_FUNCTION thus making the reset signal unused. The spec also says that there are no internal pulls on the card and hence the RST_n signal should be driven appropriately to prevent the input circuits from flowing unnecessary leakage current. Thus, even though the line remains unused, since it is connected in hardware, this change drives EMMC_RESET_L to high. BUG=b:169222156 BRANCH=zork TEST=emerge-zork coreboot eMMC DUT reboot/suspend x100 iterations pass Change-Id: I9feb826eec8a8cdad5e2bd7efcbb1dcf96185dfd Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-10-01security/intel/stm: Fix size_t printf format errorFelix Held
This sort-of reverts commit 075df92298fe3bb0ef04233395effe668c4a5550 and fixes the underlying issue. The printf format string type/length specifier for a size_t type is z. Change-Id: I897380060f7ea09700f77beb81d52c18a45326ad Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eugene Myers <cedarhouse1@comcast.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-10-01mb/clevo/l140cu: Align comment with rest of the devicetreeFelix Singer
Change-Id: Idcaedd3d5b7e465644f79e5a882e42eff040fdbd Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-01vc/amd/fsp/picasso: Add bit definitions for PSP info in transfer blockMartin Roth
BUG=b:168895748 TEST=None BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I299fdd0f007f7e4a8f597931a52f68dc98acc9ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/45804 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-01mb/google/zork: Initialize the backlight in the OSMartin Roth
This fix needs to go into ACPI in the long-term, but this should suffice in the short-term. BUG=b:158087989 TEST=Boot berknip, verify backlight is enabled. Test suspend & resume sequence, backlight is still enabled. BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I6ecc3c9e397c9756a78e480d3f639c507879a0ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/45854 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-01mb/google/zork: Remove code that reconfigured the backlight GPIOMartin Roth
The SMU code was assuming that GPIO 85 was used for a fan, which caused interesting backlight flickering. That has now been fixed, so remove the code that reconfigured it to a GPIO on resume. BUG=b:155667589 TEST=Verify the screen does not flicker on resume from S3 BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I6d4f9d98e9df52fefab9b20d0ab0f0b67512d356 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-09-30mb/amd: Add Pollock CRB Cereme as Mandolin variantFelix Held
Even though the devicetrees of Mandolin and Cereme are relatively similar, they are kept as separate files instead of using devicetree overrides to facilitate creating mainboard ports based on those CRBs. The two boards are reference boards for different zen/zen+ APU platforms that share the silicon, but use different packages. This is also consistent with the google/zork boards that have two different full base devicetrees for the two different platforms and then use devicetree overrides for the different variants of the two reference designs. BUG=b:159617786,b:169644059 BRANCH=zork Change-Id: Ief8a05b0a360563d26a81941720b78014feb0d25 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42786 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-30mb/amd/mandolin: change EFS SPI mode from 1-4-4 to 1-1-4Felix Held
With this change the flash addresses will only get transferred over one data pin like in the non-quad SPI mode and only the data will get sent over all four data pins. Since this gives the flash chip a bit more time to fetch the data the host requested, this allows higher SPI frequencies resulting in a higher throughput when bigger chunks of memory get read. BRANCH=zork Change-Id: Iad4c922ffcdba4b17e6e81244ff37302eb171d97 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45831 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-30mb/amd/mandolin: add missing SPI configuration to devicetreeFelix Held
This fixes the board not booting reliably when running from flash without the EM100 option selected during build time. Selecting EM100 mode overrides the settings, so when testing with an EM100 I didn't run into this issue. BUG=b:169644059 BRANCH=zork Change-Id: I2c7043c174dcf4501776a03b7689d8a20c214afb Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45830 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-30soc/amd/picasso: Add fields for the PSP to the transfer structMartin Roth
The PSP will be adding information into these fields after verstage runs. This allows data to be passed directly to coreboot very early in the boot process. BUG=b:168895748 TEST=None Branch=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Idbd1dfece59e99f6f15dfd8d002529ea6417cdbe Reviewed-on: https://review.coreboot.org/c/coreboot/+/45803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-30mb/google/volteer: Update SLP_Sx assertion widths and PwrCycDurJamie Ryu
This patch updates the SLP_Sx assertion widths and power cycle duration for volteer. Power cycle duration: With default value, S0->S5 -> [ ~4.2 seconds delay ] -> S5->S0 With value set to 1, S0->S5 -> [ ~1.2 seconds delay ] -> S5->S0 BUG=b:159108661 TEST=Verified that the power cycle duration is 1~2s with a global reset on volteer. Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: Idf4e0c3a60b4ac59e31df1357f2ff28f195ff17f Reviewed-on: https://review.coreboot.org/c/coreboot/+/44559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-09-30security/intel/stm: Fix size_t printf format errorEugene D Myers
Size_t seems to have a compiler dependency. When building on the Purism librem 15v4, size_t is 'unsigned long'. In this instance, the compiler is the coreboot configured cross-compiler. In another instance, size_t is defined as 'unsigned short'. To get around the formatting conflict caused by this, The variable of type size_t was cast as 'unsigned int' in the format. Change-Id: Id51730c883d8fb9e87183121deb49f5fdda0114e Signed-off-by: Eugene D Myers <cedarhouse@comcast.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2020-09-30soc/intel/tigerlake: Set TME upd param based on configPratik Prajapati
Set TmeEnable FSP-M upd based on config. TEST: TME ENABLE and LOCK bits get set when Tme is enabled. Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: Ia804c88057e17844f055fd852fc0b36cfe316432 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-09-30mb/51nb/x210/gpio: Remove comments that contain pad functionsMaxim Polyakov
Remove these comments, because they do not contain useful information that helps to understand the circuit, which we do not have. Change-Id: I8a994a6f27d830bd05819043336d12c2ecef2f48 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45371 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-30mb/51nb/x210/gpio: 4/4 Convert field macros to PAD_CFGMaxim Polyakov
Converts bit fields macros to target PAD_CFG_*() macros. To do this, the following command was used: ./intelp2m -n -t 1 -file ../../src/mainboard/51nb/x210/gpio.h This is part of the patch set "mb/51nb/x210/gpio: Rewrite pad config using intelp2m": CB:43566 - 1/4 Decode raw register values CB:43567 - 2/4 Exclude fields for PAD_CFG CB:43568 - 3/4 Fixes PAD_RESET to convert to PAD_NC() CB:43410 - 4/4 Convert field macros to PAD_CFG Tested with BUILD_TIMELESS=1, 51NB-X210, remains identical. Change-Id: I18c0c321561eee04ff927681b0a231f6d79c63e2 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-30drivers/pc80/rtc: Fix linking verstage (and use `all` target)Nico Huber
`option.c` was already linked into verstage but needs `mc146818rtc.c` to work. While we are at it, also make use of the `all` target. Change-Id: I8f545e036962ed0716bcd3b9a5b5d06e18a367f6 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45802 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-30soc/intel/icelake/acpi/gpio.asl: Correct GADD methodAngel Pons
Some cases are inconsistent. Refer to the 495 series on-package PCH to confirm which GPIO pads are the first for each community and fix it. Change-Id: Ie4c4c12c6629478d754f55fa3fb75fa16eb01335 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-09-30lenovo/t440p: Add HDA verbs from the OEM firmwareIru Cai
To get the HDA verbs from the OEM firmware, open the firmware with UEFITool, search for the existing HDA verbs, extract the UEFI module and look for the verbs. Copy the consecutive 4 dword sets that look like HDA verbs. It is tested to make audio output from both the speaker and headphone work. Change-Id: Ie359fdf6785b1c0be8dc201cd76176c0a7fe7942 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-30mb/packardbell/ms2290/acpi: Convert 'battery.asl' to ASL 2.0 syntaxElyes HAOUAS
Change-Id: Id8b7d3776ab2cc8c487095273582cd013241bd3a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-30mb/packardbell/ms2290/acpi/battery.asl: Remove unused remainderElyes HAOUAS
We store the remainder in Local0, but we never use it. Change-Id: I4d209d7434508cb626aca8e7df50cc1c424e294a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-30soc/intel/skylake: Move PMC MMIO offset macro into pmc.hSubrata Banik
This patch ensures PMC offset 0xfc resides into pmc.h rather defining into p2sb.h. Change-Id: Iae1c38beae15355a077be80112b723b8ad3d0a44 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45800 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-30soc/intel/skylake: Align PMC offset 0x31C name with CNLSubrata Banik
As per EDS PMC BASE Offset 0x31C is known as CPPMVRIC hence rename CIR31C with CPPMVRIC. Change-Id: Idaff62fb742e6c58b1d8e662b5e4087fa2da79a3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45795 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-30soc/intel/skylake: Align soc_pch_pirq_init() with CNLSubrata Banik
This patch replaces pch_interrupt_routing[] with PCH_IRQx macro. Change-Id: I9645b0e185bcde7b27da35863564dbcf73850e8c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45788 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-30soc/intel/apollolake: Add PCH_IRQx into irq.hSubrata Banik
This patch is needed to make use of LPC common code. Change-Id: I5d0e8dbf8f8e52caf4ba78c0e3969efaac387204 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-30mb/google/puff: Update DPTF parameters for faffyDavid Wu
1. TSRO trip point from 75C change to 73C 2. Sample period time from 5s change to 60s BUG=b:160385395 BRANCH=puff TEST=build and verify by thermal team Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I0b000841845ce793be0e52fc28a07ac6a931ef7a Reviewed-on: https://review.coreboot.org/c/coreboot/+/45729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-09-29mb/google/volteer: Change default camera power GPIO to 0Daniel Kang
The default GPIO values for camera power were set as 1 so the LED was turned on by default when the board is powered on. This status is kept until the camera is probed then being turned off. So the LED is turned on for a few seconds during the boot up. By setting the default power to 0, the LED is lit only when camera is turned on for probing and this should be just a blink. BUG=b:167635396 BRANCH=none TEST=Build and boot volteer board. Monitor camera privacy LED and check it is not lit more than 0.5 seconds. Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Change-Id: Ic7df391aa512daafe6e1ce49e9222b90e17ad806 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45058 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-29mb/google/volteer/halvor: Update settings for audio functionFrank Wu
Configure overridetree settings for audio function. BUG=b:153680359, b:163382106 TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I107f6fc21b99d80d69931139dc50e7d5873a8e52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-09-29mb/google/volteer: Add "i2c-allow-low-power-probe" property forDaniel Kang
cameras There is a patch https://lkml.org/lkml/2020/9/3/235 which allows i2c device can support driver probe without power up the device. In order to support this, need add coreboot add "i2c-allow-low-power-probe" property. BUG=b:169058784 BRANCH=none TEST=Build and boot volteer board. Monitor camera privacy LED and check it blinks. It should not blink. Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Change-Id: I46f90ff8d412b18c7ee4bd7f22f9a7db771eb84f Reviewed-on: https://review.coreboot.org/c/coreboot/+/45160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-09-29cpu/qemu-x86/car: Move long mode entry right before c entryPatrick Rudolph
This fixes non-emulation platforms as those are using 32bit code after the bootblock_crt0 entry, like setting up CAR and updating microcode, which isn't yet converted to support long mode. This is a noop for the only supported x86_64 platform and all x86_32 platforms. Change-Id: I45e56ed8db9a44c00cd61e962bb82f27926eb23f Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-29soc/intel/jasperlake: Add IGD, MCH Device IDKrishna Prasad Bhat
Add IGD Device ID and MCH Device ID for Jasperlake. Reference is taken from Jasperlake EDS volume 1(Document Number: 613601). TEST=Build and boot Jasperlake platform. Change-Id: I00ee7950ffa378b428a76bf367a9a05ab287e7ed Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-09-29mb/clevo/cml-u: drop PcieRpSlotImplemented for card readerMichael Niewöhner
PcieRpSlotImplemented should only be set to 1 for PCIe ports implementing a PCIe slot. Drop it for the on-board card reader. Change-Id: I22628b4d4a7e317a01e46a61b5cd7bb9ebf548a0 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-29nb/intel/gm45: Answer question about conversion stepping A1Angel Pons
The datasheet briefly mentions what this mysterious stepping is about. Change-Id: I5bc1040b74fcdf3822b15e7564f8e4ccebd7d45f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45449 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-29cpu/x86/smm/smihandler.c: Implement smm_get_save_state()Arthur Heymans
This will be used in common save_state handling code. Change-Id: I4cb3180ec565cee931606e8a8f55b78fdb8932ae Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44320 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-29cpu/x86/smm/smmhandler.c: Get revision using C codeArthur Heymans
This allows to remove some assembly code. Tested with QEMU Q35 to still print the revision correctly. Change-Id: I36fb0e8bb1f46806b11ef8102ce74c0d10fd3927 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-29mb/intel/jslrvp: Update PMC as hidden deviceMaulik V Vaghela
This change allows treating the PMC as a 'hidden' PCI device on JasperLake, so that the MMIO & I/O resources can be exposed as belonging to this device, instead of the system agent and LPC/eSPI. Original patch for jasperlake SoC here: CB:42018 This change was missing for JasperLake rvp board. TEST=Checked PMC init function is called and also checked PCI resource for PMC device 1f.2. Change-Id: I7531d32c62d3f9735938f744f2892ab9c9bebddf Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-09-29soc/intel/common: Add config option to enable TME/MKTMEPratik Prajapati
Add config option to enable TME/MKTME. The spec is available at: "https://software.intel.com/sites/ default/files/managed/a5/16/Multi-Key-Total-Memory-Encryption- Spec.pdf" Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: I181aed2bf4a79005fe42e3e133b5faee91201dad Reviewed-on: https://review.coreboot.org/c/coreboot/+/45087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-09-28mb/google/fizz/endeavour/gpio: Reflow long linesMaxim Polyakov
Use the 96 character limit. Change-Id: I865288051869e50602a579a6999b1b23ef68ec2f Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-28Revert "soc/intel/xeon_sp: Improve performance efficiencies"Subrata Banik
This reverts commit d51449d017410fedb55e93f71fb322749ba888b5. Reason for revert: Causing compilation issue as below src/soc/intel/xeon_sp/cpx/acpi.c: In function 'acpi_create_rhsa': src/soc/intel/xeon_sp/cpx/acpi.c:825:4: error: initialization discards 'const' qualifier from pointer target type [-Werror=discarded-qualifiers] &hob->PlatformData.IIO_resource[socket]; ^ Change-Id: I7050060f1db7b9a9b5a77b5a6245c8fda05623a4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44998 Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28mb/google/octopus/variants/fleex: Only do LTE power off for LTE skuEric Lai
Only do LTE power off for LTE sku in order to save extra 130ms delay for non-LTE sku. BUG=b:168075958 BRANCH=octopus TEST=build image and verify on the DUT with LTE DB. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: If983185ff2f09fb1b2553c6ff1a1473d3254de4b Reviewed-on: https://review.coreboot.org/c/coreboot/+/45687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com>
2020-09-28mb/clevo/cml-u/Kconfig: Remove MAINBOARD_SMBIOS_PRODUCT_NAMEElyes HAOUAS
MAINBOARD_SMBIOS_PRODUCT_NAME is duplicated. Change-Id: I011f83c4d4e0657256839db207bfd1517922744c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-28soc/amd/picasso: Set eMMC preset UPDsRaul E Rangel
Now that all boards have bootable driver strengths and init frequency, we can pass them to FSP. BUG=b:159823235 TEST=Boot ezkinil to kernel and print presets. SDHC0x8F0 Initialization 3.3V or 1.8V => 0x03ff 14 => 0 [B]: DvrStrength 10 => 0: ClkGen 00 => 0x3ff: SdClkFreq SDHC0x8F2 Default Speed 3.3V => 0x0004 14 => 0 [B]: DvrStrength 10 => 0: ClkGen 00 => 0x4: SdClkFreq SDHC0x8F4 High Speed 3.3V => 0x0002 14 => 0 [B]: DvrStrength 10 => 0: ClkGen 00 => 0x2: SdClkFreq SDHC0x8F6 SDR12 1.8V => 0x0008 14 => 0 [B]: DvrStrength 10 => 0: ClkGen 00 => 0x8: SdClkFreq SDHC0x8F8 SDR25 1.8V => 0x0004 14 => 0 [B]: DvrStrength 10 => 0: ClkGen 00 => 0x4: SdClkFreq SDHC0x8FA SDR50 1.8V => 0x0002 14 => 0 [B]: DvrStrength 10 => 0: ClkGen 00 => 0x2: SdClkFreq SDHC0x8FC SDR104 1.8V => 0x4000 14 => 0x1 [A]: DvrStrength 10 => 0: ClkGen 00 => 0: SdClkFreq SDHC0x8FE DDR50 1.8V => 0x0002 14 => 0 [B]: DvrStrength 10 => 0: ClkGen 00 => 0x2: SdClkFreq SDHC0x900 HS400 => 0x4000 14 => 0x1 [A]: DvrStrength 10 => 0: ClkGen 00 => 0: SdClkFreq Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5fe5c0a5a5ecf292ce8703e9c9ea80b6f1b6440e Reviewed-on: https://review.coreboot.org/c/coreboot/+/45661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-09-28mb/google/zork: Set eMMC presetsRaul E Rangel
They should be tuned per board to get the best signal and boot time. This fixes the HS400 preset, so it's correctly set to A. It also changes the SDR50 and DDR50 presets to B. We can't boot correctly when DDR50 is set to A. I chose 1 as the init kHz value since that's what depthcharge uses to calculate the init clock. BUG=b:159823235 TEST=Boot Ezkinil and dump SDHCI preset registers. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ie2f3497b65d771820ab1a803fec73265547f8906 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-09-28soc/amd/picasso: Add eMMC driver strength and init kHz settingsRaul E Rangel
This allows passing in the presets to FSP. I will set the UPD values after all the zork boards have had their presets correctly set. This way we don't override the UPD defaults with 0s. BUG=b:159823235 TEST=Build test Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I44951cacb1e9d788016a70283cf9688bf88a09f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-09-28mb/ocp/deltalake: add LPC device entry in ACPIJonathan Zhang
PCH LPC device is on CSTACK. Add LPC ACPI device entry. Without this change, following error message shows up in target OS boot log: ACPI BIOS Error (bug): Failure looking up [\_SB.PCI0.LPCB], AE_NOT_FOUND (20180105/dswload-211) ACPI Error: AE_NOT_FOUND, During name lookup/catalog (20180105/psobject-252) ACPI Error: AE_NOT_FOUND, (SSDT:COREBOOT) while loading table (20180105/tbxfload-228) ACPI Error: 1 table load failures, 1 successful (20180105/tbxfload-246) Also TPM device is not created. TESTED=Booted DeltaLake DVT, run following command in target OS: [root@dhcp-100-96-192-153 ~]# dmesg | grep tpm [ 7.331890] tpm_tis MSFT0101:00: 2.0 TPM (device-id 0x1B, rev-id 16) Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I8614f6951389bd5c8f8f33522d0a9a9160ac3f66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-09-28soc/intel/xeon_sp/cpx: add ACPI name for CSTACKJonathan Zhang
Add ACPI name for CSTACK. The name is PC00 to match with ACPI table generated. The PCIe domain has multiple PCIe stacks. devicetree.cb at the moment does not support multiple PCIe stacks, eg. IIO stacks. For now, assign the name to PCIe domain. In future, the name needs to be assigned to CSTACK. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I24a6f29734452426218419cdcf66702edde96f46 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45591 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-09-28soc/intel/common/block/lpc: add acpi nameJonathan Zhang
Add ACPI name for LPC device. The name matches with what is in soc/intel/common/block/acpi/acpi/lpc.asl. Since several Intel SOCs select CONFIG_SOC_INTEL_COMMON_BLOCK_LPC, remove duplicated acpi name assignments. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: If418c83caafe5d9e2af135a8946cbe5eb687b9ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/45590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-28vc/intel/fsp/fsp2_0/CPX-SP: upgrade to ww38 FSP releaseJonathan Zhang
Intel CPX-SP FSP ww38 release made some changes to FSP-M header file. Those changes do not need corresponding soc code change. TESTED=built image with ww38 FSP RELEASE binary, booted DeltaLake DVT to target OS. Change-Id: I320c4a674f9f4d37c30ce6df510f18ad1ae057eb Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-28mb/google/octopus/var/fleex: Use Wifi SAR table for non-LTE sku onlyEric Lai
Use Wifi SAR table for non-LTE sku only. BUG=b:169115341 BRANCH=octopus TEST=Check no SAR table can be loaded with sku id 4. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I086fa14a9f23e4a0fc0ef8085040219c932dbf17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45640 Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28include/cpu/x86/tsc: Fix rdtsc on x86_64Patrick Rudolph
The used assembler code only works on x86_32, but not on x86_64. Use the inline functions to provide valid rdtsc readings on both x86_32 and x86_64. Tested on Lenovo T410 with additional x86_64 patches. Change-Id: Icf706d6fb751372651e5e56d1856ddad688d9fa3 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-09-28arch/x86/smbios: Add SMBIOS Thread CountFrancois Toguo
Add Thread Count in SMBIOS type 4 "Processor Information". Modify Thread Count 2 according to SMBIOS spec, it should be the number of threads per processor socket. TEST="dmidecode -t4" to check. Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com> Change-Id: I0e00ba706eecdc850a2c6a4d876a7732dcc8f755 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-28mb/volteer: Use Genesys Logic GL9755 for Delbin, Volteer2Ravi Sarawadi
Enable newly added PCIe Gen2 to SD 4.0 card reader controller GL9755 for Delbin and Volteer2. BUG=b:166141961 TEST=Boot to kernel on Delbin, Volteer2 boards. Check PC10 in IDON. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I2589ab2334625ec0d20dbdd5f3a31d98235aad2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/45708 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28arch/x86/Kconfig: Move pagetables down by 4KPatrick Rudolph
In case of 64K bootblock the pagetables don't fit, as the CBFS header also needs a few bytes. Fixes build error on platforms that use 64KiB bootblock. Tested on Lenovo T410 with additional x86_64 patches. Change-Id: I854c5f575e2376827a366cca8d25682c4d90bc8f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37394 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28mb/purism/librem_whl: Drop 3Gbps SATA limit; enable and set SATA tuning paramsMatt DeVillier
Some Librem Minis exhibit issues with 6Gbps SATA operation on certain SSDs, setting the Receiver Equalization Boost Magnitude adjustment resolves this, so limiting SATA speeds to 3Gbps is no longer needed. Test: build/boot Librem Mini with Crucial SATA SSD, observe no issues booting, no ATA-related errors in dmesg on PureOS 10 / kernel 5.8.7 Change-Id: I8b3cbcff7f181bcab35d71e859033578c822bb20 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-28mb/purism/librem_skl: Enable and set SATA tuning paramsMatt DeVillier
Some Librems have issues with 6Gbps SATA operation on certain SSDs, setting the Receiver Equalization Boost Magnitude adjustment resolves this. Test: build/boot Librem 15v3 with Crucial SATA SSD, observe no issues booting, no ATA-related errors in dmesg on PureOS 10 / kernel 5.8.7 Change-Id: I078deeff7fc54694393b5b16c41c5d622b332781 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-28mb/google/volteer/variants/eldrid: Configure GPP_S4 and GPP_S5nick_xr_chen
GPP_S4 and GPP_S5 use as DMIC pins that need to be defined as NF2 BUG=b:168564129 Signed-off-by: nick_xr_chen <nick_xr_chen@wistron.corp-partner.google.com> Change-Id: Ia1fca960ac85f253882f0aa68b370eed49ac67b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
2020-09-28mb/google/volteer/var/terrador: Enable audio SMBIOS OEM stringKevin Cheng
It needs to use probe statement in overridetree.cb to enable the cache of fw_config field implemented by cb:44782 and cb:44783. BUG=b:161963281 TEST= dmidecode -t 11 shows correct audio fw_config. Handle 0x0009, DMI type 11, 5 bytes OEM Strings String 1: DB_USB-USB4_GEN2 String 2: AUDIO-MAX98373_ALC5682I_I2S_UP4 Signed-off-by: Kevin Cheng <kevin.cheng@intel.com> Change-Id: I68c19b67d945aaca3e9ebec87eb27a4b07e1a49e Reviewed-on: https://review.coreboot.org/c/coreboot/+/45673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-28mb/google/zork: update telemetry settings for berknipKevin Chiu
update telemetry to improve the performance. BUG=b:168581158 BRANCH=zork TEST=1. emerge-zork coreboot 2. pass AMD SDLE test Change-Id: Ib93905cd89132664b06f2476e94494e96980642c Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-28mb/google/dedede/var/magolor: apply DPTF settingRen Kuo
add tcc, critical, passive policy, and pl values from thermal team BUG=b:168353037 TEST=build and verify by thermal tool Change-Id: I887d494ff097a881d519a456f24578a278323051 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45453 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28mb/google/dedede/var/magolor: Add ACPI camera supportRen Kuo
1. enable DRIVERS_INTEL_MIPI_CAMERA/SOC_INTEL_COMMON_BLOCK_IPU 2. add IPU/VCM/NVM/CAM0 in devicetree BUG=b:166527568 TEST= build and verify function by cam ap on DUT Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: Ica6aa8ddc03a1dab5b548a759825dd3a4de3101f Reviewed-on: https://review.coreboot.org/c/coreboot/+/45329 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28mb/google/dedede/var/madoo: Clean-up static camera ASL fileKarthikeyan Ramasubramanian
Camera ACPI tables are generated at run-time for all variants of Dedede. BUG=None TEST=Build madoo variant. Change-Id: Icb74c01a0a6dbc620466b64cd2b5652408ca41b9 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-09-28soc/intel/common/../pmclib.h: Include <types.h>Angel Pons
This file uses `bool` and `size_t` types, so <stdint.h> isn't enough. Change-Id: I8099142d92cc8ca6721f76522f3d30d4b6b9ee80 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-28superio/common: Fix NULL pointer dereferencesJohn Zhao
Coverity detects the dev->link_list NULL pointer dereferences while calling report_resource_stored. Add sanity check for dev->link_list to prevent NULL pointer dereference. Found-by: Coverity CID 1419488 TEST=None Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I953a6524fff509a7833896392b25a3245c8cd705 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-28mb/google/volteer: Improve Eldrid Port 1 USB2 Eye Diagramnick_xr_chen
In order to pass DB type-C USB2 eye diagram, DB USB2 PHY register needs to be overridden. port#1 PortUsb20Enable=1 Usb2PhyPetxiset=7 Usb2PhyTxiset=7 Usb2PhyPredeemp=3 Usb2PhyPehalfbit=0 BUG=b:169105751 Signed-off-by: nick_xr_chen <nick_xr_chen@wistron.corp-partner.google.com> Change-Id: If076c644783fa2992ac062d6469f9c49e6d5ff24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-28azalia_device.h: Add new macro to configure pins as NCFelix Singer
Change-Id: I740d0d756599688165458a9c6e925d5d94754bb2 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45604 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28mb/acer/g43t-am3: add Acer G43T-AM3 mainboardMichael Büchler
Adds a new port for the Aspire G43T-AM3. It is from an Aspire M3800 desktop model of which I only own the mainboard. The silkscreen label calls it "G45T/G43T-AM3 V:1.0". In DMI data it is additionally called Acer EG43M. The Aspire M5800 model seems to use the same mainboard. The BIOS you can download from Acer is identical for both. Various similar mainboards by Acer exist: G41T-AM, G43T-AM, G43T-AM4, Q45T-AM, to name a few. ECS has some models that are obiously based on the same design, e.g. G43T-WM and G43T-M. This model is a microATX-sized board with an LGA 775 socket, four DDR3 DIMM slots, one PCIe x16 slot, one PCIe x1 slot and two PCI slots based on the Intel G43 chipset. The port was started by copying mb/intel/dg43gt (not going to lie here) and adapting things by looking at dumps from the system when running with the vendor BIOS. Serial console output is possible by soldering to a point at the corresponding Super I/O pin. The service manual for the board was helpful for setting the correct PCI IRQ links. It can be found publicly on the internet as the "Acer Aspire M3800 Service Manual". Working: - CPUs from Pentium Dual-Core E2160 to Core 2 Quad Q9550 at FSB1333 - Native raminit - All four DIMM slots at 1066 MHz (tested 2x2GB + 2x4GB) - PS/2 mouse - PS/2 keyboard (needs CONFIG_SEABIOS_PS2_TIMEOUT, tested: 500) - USB ports (8 internal, 4 external) - All six SATA ports - Intel GbE - Both PCI ports with various cards (Ethernet, audio, USB, VGA) - Integrated graphics (libgfxinit) - HDMI and VGA ports - boot with PCIe graphics and SeaBIOS - boot with PCI VGA and SeaBIOS - Both PCIe ports - Flashing with flashrom - Rear audio output - SeaBIOS 1.14.0 to boot slackware64 - SeaBIOS 1.14.0 to boot Windows 10 (needs VGA BIOS) - Temperature readings (including PECI) - Super I/O EC automatic fan control - S3 suspend/resume - Poweroff Not working: - Resource issues with the VGA BIOS of a PCI rv100-based card - Super I/O voltage reading conversions Untested: - The other audio jacks or the front panel header - On-board Firewire - EHCI debug - VBT (was extracted and added, but don't know how to test) - Super I/O GPIOs Signed-off-by: Michael Büchler <michael.buechler@posteo.net> Change-Id: I846cf5f4f1ef27fc644676a4c6f7a333e061f6cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/44167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-28soc/intel/xeon_sp: Improve performance efficienciesJohn Zhao
Coverity detects performance inefficiencies as IIO_RESOUCE_INSTANCE structure (size 623 bytes) is PASS_BY_VALUE. Fix it with PASS_BY_REFERENCE. Found-by: Coverity CID 1432759 TEST=None Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I9ae9ae38fe2c13c5433aa5e1dcbb30ebd30622ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/45608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-28mb/intel/tglrvp: Add DTT support for tglrvpSumeet R Pawnikar
Add DTT (Dynamic Tuning Technology) support for Tiger Lake based rvp board. Set power limits and CPU sensor thresholds for DTT based thermal control. BRANCH=None BUG=None TEST=Build and boot on tglrvp board Change-Id: I0dbee370b8dc9e1e3ae6f1a1101047ac6fd76f53 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-09-28ec/hp/kbc1126: Support not putting EC firmware in CBFSIru Cai
For mainboards using the HP KBC1126 EC interface, but with a different EC implementation, we don't put the EC firmware in the CBFS image. Add a Kconfig option to prevent the build system warning on not inserting the EC firmware. After this change, building coreboot for EliteBook Folio 9480m will not have a warning on not inserting the EC firmware. The build system still builds a working coreboot image for EliteBook 2560p, and gives a warning if not choosing to insert the EC firmware. Change-Id: I3be83a13d138d3623064ef2803f3e3a340207ead Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-28soc/intel/skl: Fix error code of send_global_reset()Nico Huber
With commit f2eb687d19 (soc/intel/{cnl,icl,skl,tgl,common}: Make changes to send_heci_reset_req_message()) the return value was changed on a single path. Update the other paths too, even though it's the discouraged 0-is-failure. Change-Id: I179a6a4b1e13565dd58c908eb2a9725052a4de9d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-28mb/google/vilboz: update telemetry settingsChris Wang
update the telemetry setting for second SDLE testing(for APU power adjusting). Those values are used to power calibration the APU power and achieving the best performance. BUG=b:160698427 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I4cf5b8f090befd6a3c4990f44f2f200bc66aa1f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44804 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28drivers/spi: Check return value for error handlingJohn Zhao
Coverity detects calling function spi_sdcard_do_command without checking return value. Fix this issue by checking return value for error handling. Found-by: Coverity CID 1407737 TEST=None Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ie0d28806b5c0b4c6d509e583d115358864eeff80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-28cpu/intel/206ax/acpi.c: Fix get_cores_per_packageEvgeny Zinoviev
Current implementation uses CPUID 0Bh function that returns the number of logical cores of requested level. The problem with this approach is that this value doesn't change when HyperThreading is disabled (it's in the Intel docs), so it breaks generate_cpu_entries(). - Use MSR 0x35 instead, which returns the correct number of logical processors with and without HT. - Rename the function to get_logical_cores_per_package, which is more accurate. Tested on ThinkPad X220 with and without HT. Related to CB:29669. Change-Id: Ib32c2d40408cfa42ca43ab42ed661c168e579ada Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-28mb/google/zork: update telemetry settings for dirinbozKevin Chiu
update telemetry to improve the performance. BUG=b:168585079 BRANCH=zork TEST=emerge-zork coreboot Change-Id: I464b90550aaa1666ce3f2393856bf46fe7686d1d Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-28mb/google/dedede/var/drawcia: Enable EC keyboard backlightWisley Chen
BUG=b:168847046 TEST=emerge-dedede coreboot chromeos-bootimage Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Change-Id: I16ed22aa5e270ad2d5c964764cc134b72941d4e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-09-28mb/google/zork/vilboz: Add new memory part H5ANAG6NDMR-XNCAmanda Huang
Add new ID for memory part H5ANAG6NDMR-XNC. Command to generate files: go build gen_part_id.go local variant=vilboz ./gen_part_id ../../../src/mainboard/google/zork/spd ../../../src/mainboard/google/zork/variants/${variant}/spd/ ../../../src/mainboard/google/zork/variants/${variant}/spd/mem_parts_used.txt BUG=b:165611994 TEST=none Change-Id: Iaf613d54bf23b637e38917937ce3e78702b26a28 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45682 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28mb/google/zork/vilboz: Remove unused memory part IDsAmanda Huang
These parts have not been used in any vilboz devices. Removing so IDs can be assigned more efficiently. Command to generate files: go build gen_part_id.go local variant=vilboz ./gen_part_id ../../../src/mainboard/google/zork/spd ../../../src/mainboard/google/zork/variants/${variant}/spd/ ../../../src/mainboard/google/zork/variants/${variant}/spd/mem_parts_used.txt BUG=b:165611994 TEST=none Change-Id: I99614acaf45db0556120c883577494d9f753ea12 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45679 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28util: Add new memory part for zork boardsAmanda Huang
Add memory part H5ANAG6NDMR-XNC. Attributes are derived from data sheets. BUG=b:165611994 TEST=Compared generated SPD with data sheets and checked in SPD Change-Id: Ifdcc7536441e9f0b94543c6f06fe466596f752dc Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-09-28mb/google/zork: disable eMMC per FW_CONFIG for MorphiusKevin Chiu
Morphius has SSD/eMMC SKU, we should turn off eMMC if storage is NVMe SSD. BUG=b:169211959 BRANCH=zork TEST=1. emerge-zork coreboot 2. Check eMMC is enabled or disabled based on the eMMC bit in FW_CONFIG. Change-Id: I67d5d77ce3d827ae89b82529de59925f67eaf894 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2020-09-27soc/intel/icelake/acpi/gpio.asl: Use ASL 2.0 syntaxAngel Pons
While we're at it, fix up cosmetics on a few comments. The GADD method seems to suffer from copy-paste symptoms. A follow-up will address this. Some methods deliberately remain untouched in this commit, so as not to collide with another patch train that already takes care of them. Tested with BUILD_TIMELESS=1, Intel Ice Lake U RVP does not change. Change-Id: I613f5f65638b92ca23f3ce15a15dd063afa52c31 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-09-27soc/intel/skylake/acpi/gpio.asl: Use ASL 2.0 syntaxAngel Pons
While we're at it, fix up cosmetics on a few comments. Some methods deliberately remain untouched in this commit, so as not to collide with another patch train that already takes care of them. Tested with BUILD_TIMELESS=1, Purism Librem 15v4 does not change. Change-Id: Ib27c5b48459e3ea7eabc34457cb204994ee9b617 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45691 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-25 21:46:44 +0000