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2022-11-10mb/google/brya/var/marasov: Update devicetree setting for marasovFrank Chu
update devicetree setting per the schematic BUG=b:254365935 BRANCH=None TEST=Built successfully Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Ifa4cb18b8e1a7b162f505ff12612ef808fb7061a Reviewed-on: https://review.coreboot.org/c/coreboot/+/69364 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-10soc/nvidia/tegra124: Fix building with clangArthur Heymans
This kind of allocation without '=' is not working with clang. Change-Id: I2d3e9eb44c3e0e25e5a67c5386e5ddde1487cc74 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63063 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-10soc/sifive/ux00ddr.h: Remove set but unused variablesArthur Heymans
It looks like this code was not finished so it's left commented out for now. Change-Id: I442a42e297f2968dd2c824a93a9a1e2bc74ea2f4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63074 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-10drivers/spi: Add support for Macronix SPI ROM MX77U25650FRitul Guru
Change-Id: I8fedea1d566f0c35a9e028d4b2bb939592bd5f74 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-11-10ec/google/chromeec: Fix USB_PD_PORTS response data typeCaveh Jalali
The EC_CMD_USB_PD_PORTS host command returns a struct ec_response_usb_pd_ports, not a struct ec_response_charge_port_count. Luckily, both structs have the same memory layout, so this is simply a name change. BUG=b:258126464 BRANCH=none TEST=none Change-Id: I0d7710ca8a45f0ea3939f58bbba6bab31ff41919 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69370 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-10ec/google/chromeec: Simplify KEYBOARD_BACKLIGHT error handlingCaveh Jalali
Simplify the implementation of setting the keyboard backlight PWM value. Host command stubs typcially don't need to examine the host command's return value as stored in cmd_code because that level of detail is not very interesting. Higher value error codes are returned in actual result structures. This host command can return EC_RES_ERROR for out of range PWM values which is already a generic error and unlikely to happen since we already limit the range to 0..100 here. Finally, none of the callers in coreboot check the return value. BUG=b:258126464 BRANCH=none TEST=none Change-Id: If17bc4e31baba02ba2f7ae8e7a5cbec7f97688c5 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69369 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-10ec/google/chromeec: Fix keyboard_backlight callCaveh Jalali
The EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT command does not return data, so don't specify a result buffer. BUG=b:258126464 BRANCH=none TEST=none Change-Id: I5b9a0d228e187a9337498246a3b9ed8db07b95c7 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
2022-11-10google/chromeec: Add ACPI method for EC PanicRob Barnes
Add an ACPI method to handle EC_HOST_EVENT_PANIC (bit 24) events. EC panic is not covered by the standard (0-F) ACPI notify values. Arbitrarily choosing B0 notify, which is in the 84-BF device specific ACPI notify range. This will be a no-op until the kernel driver is also updated to handle this event. BUG=b:258195448 BRANCH=None TEST=Observe event with modified cros_ec_lpc driver Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: Iafa642c1c50f9a0083a8e618e1eabec9a7ce39b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69391 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-10mb/google/nissa/var/craask: Disable stylus GPIO pins based on fw_configTyler Wang
BUG=b:257879909 Test:Boot to OS on craask and check stylus GPIO pins Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I7e3a2583187c8a8e2616a5272b5a7a61debe982b Reviewed-on: https://review.coreboot.org/c/coreboot/+/69138 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-10mb/google/nissa/var/craask: Modify DPTF related settingsTyler Wang
Request by thermal team, make below changes: 1) tdp_pl2_override: 12 --> 25 2) pl1.min_power: 3000 --> 5500 3) pl1.time_window_max: 32 * MSECS_PER_SEC --> 28 * MSECS_PER_SEC 4) pl2.min_power: 12000 --> 25000 5) pl2.max_power: 12000 --> 25000 6) pl2.time_window_min: 28 * MSECS_PER_SEC --> 1 7) pl2.time_window_max: 32 * MSECS_PER_SEC --> 1 BUG=b:239495499 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I88c8c4e6798ec5bc2930dd713e8c8b2c543cfaf9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68523 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
2022-11-10mb/google/nissa/var/pujjo: Update register parameters for SX9324 tunningVictor Ding
Update SX9324 related settings based on tunned values from the ODM. This patch supports both legacy and upstream Linux's SX9324 driver. BUG=b:242662878 TEST=i2cdump -y -f 13 0x28 (Verified register values on Pujjo) Signed-off-by: Victor Ding <victording@google.com> Change-Id: I34d8073ffe93e6939f8da0cd7efb8667c0e9ac37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69366 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-10mb/kontron/bsl6/romstage.c: Clean up includesElyes Haouas
Change-Id: Ie3a08799294729beec83faf819fb1f249c6461cd Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-11-10cpu/x86/Kconfig.debug_cpu: Drop unused symbolArthur Heymans
Change-Id: I2b611773e596bea4788b05a3f58485fb3e002402 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69362 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-10cpu/x86/lapic.h: Fix CONFIG_X2APIC_RUNTIMEArthur Heymans
The deadlock prevention is also needed with CONFIG_X2APIC_RUNTIME when the cpu is in x2apic mode. TESTED: Fixes SMI generation on xeon_sp hardware with CONFIG_X2APIC_RUNTIME. Change-Id: I6a71204fcff35e11613fc8363ce061b348e73496 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-09device/xhci: Factor out `struct xhci_usb_info`Robert Zieba
This commit factors out `struct xhci_usb_info` from intel specific code as it will be useful on other platforms. BUG=b:186792595 TEST=Builds for volteer Change-Id: I5b4cc6268f072c6948f11c7498a564d7a5c0a190 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-11-09device/xhci: Factor out common PORTSC codeRobert Zieba
This commit factors out some code for XHCI port status values. BUG=b:186792595 TEST=Built coreboot for volteer device Change-Id: I045405ed224aa8f48f6f628b7d49ec6bafb450d7 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-09ec/google/chromec: Expand EC share memory for DTTSEricKY Cheng
DTTS is Dynamic Thermal Table Switching Proposal. DTTS needs one bit to save the body detection result from EC. Define mode change STTB bit for Desktop (1) and laptop (0). This bit is Switch thermal table by body detection status. BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I37b3a0d8f6546361c8d5501e98e3e1b0d814fce3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68077 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-09Revert "mb/aopen/dxplplusu: Remove board"Kyösti Mälkki
This reverts commit eb76a455cd39ec59b7f2ba28baeec9538befd59e and applies minor fixes to make it build again. PARALLEL_MP was working prior to board removal and no relevant SMI handlers were implemented. So NO_SMM choice is now selected. Change-Id: Ia1cd02278240d1b5d006fb2a7730d3d86390f85b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-09cpu/*: Drop PARALLEL_MP leftoversArthur Heymans
These symbols and codepaths are unused now so drop them. Change-Id: I7c46c36390f116f8f8920c06e539075e60c7118c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69361 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-09soc/amd/picasso/acpi: include pci_int_defs.asl from soc.aslFelix Held
Instead of including pci_int_defs.asl in each board's DSDT, include it in the common soc.asl. This moves the PRQM OperationRegion and the PRQI IndexField defined in pci_int_defs.asl into the \_SB scope, but those are defined inside the \_SB scope both in the Picasso reference code and for the AMD SoCs from Cezanne on. TEST=Both Linux and Windows still boot and don't show ACPI errors on Mandolin after moving this inside the \_SB scope Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib4e7bfb15de184cc43cd17c8249be0f59405793f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
2022-11-09soc/amd/picasso/acpi: rename pcie.asl to pci_int_defs.aslFelix Held
This aligns Picasso more with the newer AMD SoCs and also makes it a bit clearer what this file does. Also remove the unneeded tabs at the beginning of each line. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie6e5ee815e4346004bc864a6111a255dc689eae8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
2022-11-09nb/intel/haswell: Hook up PCI domain and CPU cluster ops to devicetreeArthur Heymans
Change-Id: I955274bc6bda587201f130762c0735c36f5501d1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69289 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-09soc/intel/common/xhci: Fix building for 64bitArthur Heymans
Tested with clang on prodrive/hermes: Boots to payload Change-Id: I66392bcb4ed94c97dde43342dd29dab15d1dd9ea Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69234 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-09mb/intel/harcuvar: Fix strict prototype warningArthur Heymans
Clang warns on both the declaration and the definction. Change-Id: I94d979fcdbe41349c59248656066615bffd215b6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-09superio/nuvoton/nct6687d: Fix unexpected expressionArthur Heymans
Expression after a case statement are not allowed. This fixes building with clang. Change-Id: Ie369454f10b515aa5601a5e78330e12f4b7a5e4c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-09mb/prodrive/hermes: Fix format mismatchArthur Heymans
Change-Id: I2a6947c1a39b115a7c7f5da1c9becfd51f45fad9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69239 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-09cpu/x86/smm/module_loader: Fix ASEG loadingArthur Heymans
This code was never tested with SSE enabled. Now qemu enables it and FX_SAVE encroaches on the save states. Without SSE enabled the handler just happened to be aligned downwards enough to have the save states fit. With SSE enabled that's not the case. The proper fix is to give the code setting up stubs the right base address, which is the same as for the TSEG codepath. Change-Id: I45355efb274c6ddd09a6fb57743d2f6a5b53d209 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69233 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-11-09mb/siemens/mc_ehl2: Provide I2C timing parameter for SSDTWerner Zeh
Provide timing parameter for SSDT generation to achieve the requested 100 kHz speed with a high accuracy. Test: Measure I2C bus clock, high and low times during I2C access from Linux and confirm they match the specification. Change-Id: Ifb6019421b612133b8f25c076519bc0e7200dad8 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-09mb/siemens/mc_ehl2: Add dummy I2C devices to limit the I2C speed in OSWerner Zeh
In Linux, the I2C speed defaults to 400 kHz if there is no device registered in ACPI which requests a different speed. Due to board limitations (layout, bus load), 400 kHz are too fast which results in a timing violation. Therefore, add a dummy I2C device to both used I2C buses (I2C1 and I2C2) with a speed of 100 kHz. This will limit the bus speed in Linux accordingly. Change-Id: I507c53c9ec7f763cef18903609231b1a66ed98fa Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-11-09soc/intel/elkhartlake: Correct I2C base clock to 100 MHzWerner Zeh
According to measurements Elkhart Lake seems to drive the internal I2C controllers with 100 MHz instead of the common 133 MHz. The datasheet itself is quite vague on this definition, just one place mentions that it is 100 MHz (register description for offset 0x94). This patch changes the I2C controller base frequency to 100 MHz. The verification was done by measuring the set up resulting I2C clock for both 100 and 400 kHz. Change-Id: I7c826bbb01b53e3661746e49f25441565068d1c2 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-09drivers/i2c/designware: Add 100 MHz controller base clockWerner Zeh
There are SoCs (for instance Intel Elkhart Lake) that do use 100 MHz as the base clock for I2C controllers. To support them properly add a frequency setting for 100 MHz to the designware I2C controller driver. Change-Id: I9ea11c6a41fd3758b771a416251e108cbe722769 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-11-09mb/google/nissa/var/craask: Add wifi sar tableTyler Wang
Add wifi sar table for craask/craaskbowl. Use fw_config to separate different project settings. BUG=b:247652032,b:251287099,b:251287101 Test=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I5c92f0ab53ece12a97068f09241e5298909116aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/68660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-09soc/amd/common/block/spi: Mainboard to override SPI Read ModeKarthikeyan Ramasubramanian
On certain mainboards due to hardware design limitations, certain SPI Read Modes eg. (Dual I/O 1-2-2) cannot be supported. Add ability to override SPI read modes in boards which do not have hardware limitations. Currently there is an API to override SPI fast speeds. Update this API for mainboards to override SPI read mode as well. BUG=b:225213679 TEST=Build and boot to OS in Skyrim. Observe a boot time improvement of ~25 ms with 100 MHz SPI speeds. Before: 11:start of bootblock 688,046 14:finished loading romstage 30,865 16:FSP-M finished LZMA decompress (ignore for x86) 91,049 Total Time: 1,972,625 After: 11:start of bootblock 667,642 14:finished loading romstage 29,798 16:FSP-M finished LZMA decompress (ignore for x86) 87,743 Total Time: 1,943,924 Change-Id: I160b56f6201a798ce59e977ca40301e23ab63805 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-11-09mb/google/nissa/var/xivu: Add Hynix new memory supportIan Feng
Add new ram_id:0 (0000) for memory part H9JCNNNCP3MLYR-N6E. DRAM Part Name ID to assign H9JCNNNCP3MLYR-N6E 0 (0000) BUG=b:257867226 TEST=Use part_id_gen to generate related settings and emerge-nissa coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: If663afbcd2e0457636f4a1c7475f1e3e40f0dd96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-11-09drivers/i2c/sx9324: Add support for Linux's SX9324 driverVictor Ding
SX9324 driver is updated per Linux's documentation found at https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/iio/proximity/semtech,sx9324.yaml Supporting logic for the deprecated SX932x driver is hence guarded by DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER This patch by itself does not introduce functional changes to any board. The legacy SX932x Linux driver never reached upstream Linux and is only available in ChromeOS kernel fork of 4.4 and 5.4. Linux later accepted a different implementation named SX9324 and has been available since 5.4. Ideally all variants should adopt the new driver; however, during the transition phase, coreboot must support both drivers. It is better to have a single firmware build that can work with both Linux kernel drivers by specifying both sets of properties. Legacy driver support should be deleted once all variants finish migration. BUG=b:242662878 TEST=Dump ACPI SSDT then verify _DSD entries related to the legacy SX932x driver are identical w/ and w/o this patch (Tested on Craask and Nivviks) Change-Id: I42cd6841c3a270c242ed2e739db245e858eadb3b Signed-off-by: Victor Ding <victording@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69192 Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-09mb/google/rex: Add fingerprint SPIEran Mitrani
Add Fingerprint SPI, and power-off FPMCU during romstage. For reference see CL:66915 for a similar change to Brya's power sequence SHA: 2b523ce6316e5c5ec86fe812d739fe48ca81d83d ("Invoke power cycle of FPMCU on startup") TEST=Tested on Rex - setup and logged in using fingerprint Change-Id: I4e6be24e72a8232ae2c958a01cf8ea9a272d7365 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66992 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-09drivers/ipmi/ocp: add functions to get board configurationJonathan Zhang
These functions are added for ramstage: * add IPMI OEM command to get board configuration. * add function to get blade index in the sled. Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com> Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Change-Id: I85ec7ba68d580c13e368e7d656dba47ea043d33e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68779 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-09drivers/ipmi/ocp: add PCIe SEL supportJonathan Zhang
Add Kconfig SOC_RAS_BMS_SEL and corresponding support for generating PCIe error SEL records and sending them to BMC. Add PCIe error definitions. This is needed for SMM, so build the ipmi kcs driver in SMM. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Rocky Phagura <rphagura@fb.com> Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Change-Id: I1ee46c8da7dbccbe1e2cc00bfe62e5df2f072d65 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68758 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-08vboot: Add VBOOT_CBFS_INTEGRATION supportJakub Czapiga
This patch introduces support signing and verification of firmware slots using CBFS metadata hash verification method for faster initial verification. To have complete verification, CBFS_VERIFICATION should also be enabled, as metadata hash covers only files metadata, not their contents. This patch also adapts mainboards and SoCs to new vboot reset requirements. TEST=Google Volteer/Voxel boots with VBOOT_CBFS_INTEGRATION enabled Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I40ae01c477c4e4f7a1c90e4026a8a868ae64b5ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/66909 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-08soc/intel/xeon_sp: accomodate xeon_sp FSPX_CONFIG definitionsJonathan Zhang
Intel FSPs of XEON server platforms define FSPX_CONFIG instead of FSP_X_CONFIG, which is expected by coreboot. Re-define in the common code. Update coreboot code to use FSP_X_CONFIG consistently. Tested=On OCP Delta Lake, boot up OS successfully. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: Ifa0e1efa1618fbec84f1e1f23d9e49f3b1057b32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-08arch/x86 & commonlib: Add macros for postcodes used in x86/tablesMartin Roth
The 0x9a, 0x9b, and 0x9c postcodes are not used anywhere else in the coreboot tree other than in arch/x86/tables.c. Add macros to standardize these postcodes. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I16be65ffa3f0b253fe4a9bb7bfb97597a760ad3f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-11-08vboot: Introduce handy vboot reboot functionsJakub Czapiga
This patch groups vboot context, recovery reason and subcode saving, and reboot calls into two handy functions: - vboot_save_and_reboot() - save context and reboot - vboot_fail_and_reboot() - store recovery reason and call function above Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ie29410e8985e7cf19bd8d4cccc393b050ca1f1c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69208 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-11-08/: Remove unused <inttypes.h>Elyes Haouas
Change-Id: I16aa756039973e164c887ff5237bda69d042a235 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-08soc/ti/am335x/cbmem.c: Use MiB macroElyes HAOUAS
Use "* MiB" instead of "<< 20". Change-Id: Iab6592804961a34fae6dc8012bfbc70023421a49 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-08cpu: Include <cpu/cpu.h> instead of <arch/cpu.h>Elyes Haouas
Also sort includes. Change-Id: Ia4a3807e45777e2a596878fe09e3c80b1fd2704d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-08soc/intel/meteorlake: Remove PM Energy Report WARavi Sarawadi
Disable Pch PM Energy Report WA was added to enhance boot time with HFPGA only. SoC needs reporting enabled. BUG=None TEST=Build and Boot Google, Rex and Intel, MTLRVP without any boot time regression.. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: If5f1f9c6ab31652977d436a49a3531edffbd60c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69042 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-11-08mb/google/brask: Disable PCH USB2 phy power gating for braskRicky Chang
The patch disables PCH USB2 Phy power gating to prevent possible display flicker issue for moli board. Please refer Intel doc#723158 for more information. BUG=b:257415959 TEST=Verify the build for brask board Change-Id: I518e90e9032e8f2186300b6b907cc9d84a1682e4 Signed-off-by: Ricky Chang <rickytlchang@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-08soc/intel: Use `PWRMBASE` over static `Index 0` for PMCSubrata Banik
This patch replaces static index 0 for PMC read resources with PCI configuration offset 0x10 (PWRMBASE). TEST=Able to build and boot Google, Rex to OS. Without this change: [SPEW ] PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0 With this change: [SPEW ] PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 10 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iee2523876a8045e70effd5824afc327d1113038b Reviewed-on: https://review.coreboot.org/c/coreboot/+/69227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-11-08mb/google/nissa/var/craask: Add ambient thermal sensor settingsTyler Wang
BUG=b:239495499 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I026a8b3e1a27bedc3e0082e15e80a74a2f8adfda Reviewed-on: https://review.coreboot.org/c/coreboot/+/69197 Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
2022-11-08mb/google/brya/var/kano: Add mipi hi556 camera supportDavid Wu
This patch supports multiple camera modules based on FW_CONFIG. BUG=b:251235140 TEST=Test the changes with ov2740/hi556 camera. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I34dbf67634ecd364c40c6e934217af3d8efe1689 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jim Lai <jim.lai@intel.com> Reviewed-by: Ricardo Ribalda <ribalda@google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-11-08mb/google/brya/var/kinox: Disable PCH USB2 phy power gatingDtrain Hsu
The patch disables PCH USB2 Phy power gating to prevent possible display flicker issue for kinox board. Please refer Intel doc#723158 for more information. BUG=b:257373738 TEST=Verify the build for kinox board Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ifcf4f89ea4c61ec4f9a31edba069d2111ca06010 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-08mb/google/brya/var/lisbon: Disable thunderbolt portsKevin Chiu
Lisbon doesn't support thunderbolt. BUG=b:246657849 TEST=FW_NAME=lisbon emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: Iac44315d000c3c0c572efb00e877d039e0308455 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68916 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-08mb/intel/mtlrvp: Enable ACPI and add ACPI tableJamie Ryu
This enables ACPI configuration and add ACPI table. BUG=b:224325352 TEST=util/abuild/abuild -p none -t intel/mtlrvp -a -c max Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: I8264197fd0acdd7e19b9a36fb22822447b013202 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66100 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-07vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP RPL.3361.07Selma Bensaid
The headers added are generated as per FSP v3361.07 In the future, when Alder Lake and Raptor Lake fsp align, Raptor Lake fsp headers can be deleted and Raptor Lake soc will also use headers from alderlake/ folder. BUG=b:254054169 BRANCH=firmware-brya-14505.B TEST=Boot to OS Signed-off-by: Selma Bensaid <selma.bensaid@intel.com> Change-Id: If486867477c88ad3e2ec5041ef94a0c364f5dfd6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-07soc/qualcomm/sc7280: Move AOP load and reset handle to RomstageSudheer Kumar Amrabadi
As AOP takes 500 msec delay to get up, moving aop load and reset to romstage improves the performance. BUG=b:218406702 TEST=reboot from AP console (on CRD3) prior to fix (from cbmem dump): 1000:depthcharge start 1,139,809 (152,679) after fix (from cbmem dump): 1000:depthcharge start 1,041,109 (46,353) Signed-off-by: Sudheer Kumar Amrabadi <samrabad@codeaurora.org> Change-Id: Iabc8ee8f6e7b14d237b0aeaae42da8077f9dafc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-11-07soc/amd/mendocino: Enable x86 SHA acceleratorKarthikeyan Ramasubramanian
Enable x86 SHA accelerator for use by VBOOT library. This is useful when CBFS verification verifies the hash of the file being loaded in x86. BUG=b:227809919 TEST=Build and boot to OS in Skyrim. Observe a boot time improvement of ~10 ms with CBFS verification enabled. Change-Id: I14efe7be66f28f348330580d2e5733e11603a023 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68954 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-07security/vboot: Update build rules using x86 SHA extensionKarthikeyan Ramasubramanian
Currently build rules allow using x86 SHA extensions for all coreboot stages when enabled. On some SoCs where verstage can run in non-x86 environment, x86 SHA extension cannot be used. Update build rules accordingly such that x86 SHA extensions can be used in AMD SoCs. This is particularly useful when CBFS verificiation is enabled which verifies the hash of the CBFS file being loaded. BUG=b:227809919 TEST=Build and boot to OS in Skyrim. Observe that hardware acceleration is used when a CBFS file is loaded and observe an overall improvement of 10 ms. Change-Id: I4f388e963eb82990cda41d3880e66ad937334908 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68953 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-11-07drivers/intel/fsp2_0/memory_init.c: clean codeMaximilian Brune
No need to call a function that just instantly returns. It greatly enhances readability to just check before calling a funtion and it also removes an extra argument. Change-Id: I4d57c45ede520160ef615725c023b7e92289a995 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07mb/intel/mtlrvp: Add MTL reference mainboard for MTLRVP-PJamie Ryu
This adds an initial mainboard code for mtlrvp, Intel Meteorlake reference platform. BUG=b:224325352 TEST=util/abuild/abuild -p none -t intel/mtlrvp -a -c max Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I097db4de9734ff81283cf470aabf3eb23b63aab8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66097 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Balaji Manigandan <balaji.manigandan@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-07soc/intel/common/block/pcie/rtd3: Skip Power On if _STA returns 1Kane Chen
RTD3,_ON method sometimes can create delays during system boot. Even when the power is already up, kernel still tries to call _ON method to power up device, but it's unnecessary. RTD3._STA returns device power, so _ON method can check _STA and see if the power on process can be skipped BUG=b:249931687 TEST=system can boot to OS with RTD3 pcie storage and save ~80 ms on Crota. Suspend stress test passes 100 cycles Change-Id: I296ce1b85417a5dbaca558511cd7fc51a3a38c84 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-07mb/intel/adlrvp: Fix expected statementArthur Heymans
Switch cases expect a statement so move the default label. TEST: With BUILD_TIMELESS=1 binary remains identical. Change-Id: I9a5d39bb3cbde64f82fc90186b0f2fb64bcde595 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66266 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-07soc/intel/meteorlake: Implement SOC Die lock down configurationRavi Sarawadi
This patch implements a function to enable IOSF Primary Trunk Clock Gating. BUG=b:253210291 TEST=Able to build and boot rex to OS. Also needed for S0ix, tested with Sandbox OS + Firmware combination for S0ix entry/exit. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I02e191336e99f97f4db58b27f4414001b642ad02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68430 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-07vendorcode/amd/ccx_cppc_data.h: Fix header guardArthur Heymans
Change-Id: I027c3aa7bb206112107ee120cf6f9854e37c5636 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69230 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-07soc/intel/meteorlake: Fix incompatible function pointersArthur Heymans
const void is a meaningless return type and clang complains about incompatible function pointer signatures. Change-Id: Ia00706b9cd718e590819621986dbd20555f6c226 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66263 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-07mb/starlabs/*: Enable the Mirror flag for boards that support itSean Rhodes
Enable the mirror flag for CML and TGL. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I51678bdb8d876d238076e12c6315a53c5da59628 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07ec/starlabs/merlin: Add support for enabling the mirror flagSean Rhodes
When enabled, the EC will mirror the firmware contained inside the coreboot ROM. This allows it to be updated at the same time as coreboot. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ief088e012b65be32648f581fc3190e1000bca241 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07mb/google/guybrush: Use detect vs probed flag for touchscreensMatt DeVillier
Now that coreboot performs the necessary power sequencing, switch from using the 'probed' flag to 'detect' for all I2C touchscreens. This alleviates ChromeOS from having to probe to see which touchscreen model is actually present, prevents breaking ACPI spec by generating device entries with status 'enabled and present' which aren't actually present, and improves compatibility with upstream Linux and Windows. BUG=b:121309055 TEST=build/boot ChromeOS and Linux on guybrush, ensure touchscreen is functional, and ACPI device entry generated for correct touchscreen model. This mirrors the changes made for skyrim in CB:67779. Change-Id: Ib6a76b969d3a245eccde5352231eb7e36736f2e0 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-11-07mb/google/guybrush: Implement touchscreen power sequencingMatt DeVillier
As all variants have a touchscreen option, in baseboard table set the enable GPIO high and hold in reset during romstage, then release reset in ramstage. This will allow the touchscreen to make use of the runtime I2C detect feature (enabled in a subsequent commit) so that an ACPI device entry is created only for the touchscreen actually present. Variants/SKUs which do not have a touchscreen (if any) can use the romstage/ramstage GPIO override tables to set the associated enable/ reset GPIOs to NC. This mirrors the change to skyrim in CB:67778. BUG=b:121309055 TEST=build/boot guybrush with rest of patch series Change-Id: I9b3356b8b3a0e68a307838a4b18775d25b32e548 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-11-07mb/google/brya : Set EPP value for Vell boardSridhar Siricilla
The patch sets the EPP to 50% (0x80) for Vell. With EPP at 50%, the Vell system demonstrated better power improvement without sacrificing the performance. PLT Results(Perf) with EPP@40% and EPP@50%: EPP@40%: Device1-656 mins, Device2-664 mins. EPP@50%: Device1-678 mins, Device2-677 mins. In short, with EPP@50%, PLT KPI ran for more than 13 to 22mins compared to EPP@40%. Branch=firmware-brya-14505.B BUG=b:215526166 TEST=Verified code build for Vell board Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I41b15b84025d25cf59dac2d85826a3de9d725bae Reviewed-on: https://review.coreboot.org/c/coreboot/+/68900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-07mb/google: Probe p-sensor only for selected variantsVictor Ding
Only a subset of variants has proximity sensors. This patch by itself does not introduce functional changes to any board. It is mainly to ease migrating SX9324 from the legacy driver to the linux one - allowing gradual migration variant by variant. BUG=b:242662878 TEST=Dump ACPI SSDT then verify they are identical w/ and w/o this patch Change-Id: Ic00e0d9eafcef2c9eaf32571fecf6190777cec36 Signed-off-by: Victor Ding <victording@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69191 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-07device/resource_allocator_v3: Drop codeArthur Heymans
No platform uses this anymore. Change-Id: Ifccb59ae45daa8fec41a9a2d46c628ff24a0c998 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69140 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-07cpu/x86: Drop !CPU_INFO_V2 codeArthur Heymans
Now that all platforms use parallel_mp this is the only codepath used for cpu_info() local thread storage. Change-Id: I119214e703aea8a4fe93f83b784159cf86d859d3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69122 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07cpu/x86: Drop LEGACY_SMP_INITArthur Heymans
This codepath is deprecated after the 4.18 release. Change-Id: I7e90f457f3979781d06323ef1350d5fb05a6be43 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69121 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07mb/qemu/x86: Remove option for LEGACY_SMP_INITArthur Heymans
This is deprecated after the 4.18 release. Change-Id: I17327c31f8ade51716578e45c2d90a327efcd4ad Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69128 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-07sb/amd: Remove dropped platformsArthur Heymans
This code is now unused by any platform. Change-Id: I60afbde6ead70f0c887866fc351b4a6a15a89287 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69120 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07nb/amd/agesa: Remove leftover codeArthur Heymans
This code is now unused by any platform. Change-Id: I5464daa8cfb8231e2b19447c343fc80ab1d68ce8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69119 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07cpu/amd/agesa: Remove leftover codeArthur Heymans
Now that all agesa CPUs are removed this code is unused. Change-Id: If0c082bbdb09457e3876962fa75725add11cb67c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69118 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07vendorcode/amd/agesa: Drop unused common codeArthur Heymans
No platform uses this. Change-Id: If32a4de7ef263f1d4f7ab7a36751ad9dcf52dc7e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69127 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07vendorcode/amd/agesa/family16: Drop unused platformArthur Heymans
This platform use the LEGACY_SMP_INIT which is to be deprecated after release 4.18. Change-Id: Ie2ef5424c3ebe75ff98361639a0f9980101c1141 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69126 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07{cpu/nb}/amd/family16: Remove platformArthur Heymans
This platform use the LEGACY_SMP_INIT which is to be deprecated after release 4.18. Change-Id: I589f30ccf81b6cf243ac7cbf8320a3f830649ad8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69117 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07vendorcode/amd/agesa/fam15tn: Drop unused platformArthur Heymans
This platform use the LEGACY_SMP_INIT which is to be deprecated after release 4.18. Change-Id: I749cf33fad12bb9bc5cd5d682df2652107d60a0f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69125 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07{cpu/nb}/amd/family15tn: Remove platformArthur Heymans
This platform use the LEGACY_SMP_INIT which is to be deprecated after release 4.18. Change-Id: I18eb1c1ccad16980a4e57318dec411b82c45b25a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69116 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07vendorcode/amd/agesa/fam14: Remove dropped platformArthur Heymans
This platform use the LEGACY_SMP_INIT which is to be deprecated after release 4.18. Change-Id: I9dd3ce763418ff767acd0c55be26a998df77081b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69124 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07{cpu/nb}/amd/family14: Remove platformArthur Heymans
This platform use the LEGACY_SMP_INIT which is to be deprecated after release 4.18. Change-Id: Ieaac0a32e71d208b66fd2c4e26f5349abc921d4f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69115 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07mb/aopen/dxplplusu: Remove boardArthur Heymans
This board use the LEGACY_SMP_INIT which is to be deprecated after release 4.18. Change-Id: Idf37ade31ddb55697df1a65062c092a0a485e175 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69114 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07mb/*/*: Remove AMD agesa family16 boardsArthur Heymans
These boards use the LEGACY_SMP_INIT which is to be deprecated after release 4.18. Change-Id: I43c7075fb6418a86c57c863edccbcb750f8ed402 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07mb/*/*: Remove AMD family14 boardsArthur Heymans
These boards use the LEGACY_SMP_INIT which is to be deprecated after release 4.18. Change-Id: I3495d140a244bbbf63e846fcd963d69907e09719 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07mb/*/*: Remove AMD FAMILY15TN boardsArthur Heymans
These boards use the LEGACY_SMP_INIT which is to be deprecated after release 4.18. Change-Id: I9efb5cb1149cc4cf6337c47af8a2f4c4b55f4368 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07soc/amd/common/include/gpio_defs.h: Add comment for accuracyFred Reitberger
The GPIO debounce timebase bit 4 is only 183uS on Picasso. On the other SoCs it is 244uS. This affects the 1mS and 2mS actual debounce times slightly. Time PCO Others 1mS 0.915mS 1.220mS 2mS 2.013mS 2.684mS Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Id84bef75e6ab134778721ca269d763a4bb2ddde5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69209 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-07mb/google/brya: Create marasov variantFrank Chu
Create the marasov variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:254365935 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_MARASOV Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Ibe2dc442480f6a73877b40625e228cdb2038aa4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/69052 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Reviewed-by: Kyle Lin <kylelinck@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-07lib: Add LPDDR5x DRAM typeSubrata Banik
BUG=none TEST=Able to build and boot Google, Rex SKU2 (Micron LPDDR5x MT62F1G32D2DS-026). Without this code change: [INFO ] SPD: module type is UNKNOWN With this code change: [INFO ] SPD: module type is LPDDR5X Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: If620cf51133ca295fd3f1cbecbb472beb337b9fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/69226 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-07soc/intel/cannonlake: Fix GPIO reset mappingAngel Pons
According to document 337348-001 (Intel® 300 Series and Intel® C240 Series Chipset Family Platform Controller Hub Datasheet - Volume 2 of 2), the only GPIOs that support PWROK reset are those in the GPD group. The mappings themselves are correct, but they're assigned to the wrong communities. Change-Id: Ib586c987f768ddff31b053f4c108a8526326a7dc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69214 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-07mb/google/brya/variants/volmar: Add firmware config field for FPMCURen Kuo
The fingerprint(FP) feature is only for volmar,and it's not for zavala. Add FPMCU_MASK field in fw_config to disable the FP function for zavala, and reserve FP function for shipped volmar. Define the value as following: field FPMCU_MASK 10 option FPMCU_ENABLED 0 option FPMCU_DISABLED 1 end BUG=b:250807253 TEST=build firmware and verify the fp function in volmar DUT. write `disable=1` and 'enable=0' in FPCMU_MASK field. check the fp function and run `ectool --name cros_fp version` It works as expected. Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: I867771904811459697056662d5e29c545a1a9474 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68917 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-05cpu/x86/mp_init.c: Use existing code to create cpu struct deviceArthur Heymans
Change-Id: I80baadd405b31d6be2fdbb894b0f4b7c775da6f8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-05mb/google/guybrush: Rename pcie_gpio_table to romstage_gpio_tableMatt DeVillier
Rename so table more indicative of when GPIOs are set, and so it can be used for more than just setting PCIe GPIOs. Will be used to set touchscreen GPIOs as part of power sequencing in a subsequent commit. Rename all variant tables and getter functions to match. This mirrors the changes made for skyrim in CB:67810 Change-Id: I72e7febfb532262be7e4c14bf136e0d69c91301e Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-11-05mb/google/guybrush: rename baseboard GPIO table getter for clarityMatt DeVillier
Rename variant_pcie_gpio_table() to baseboard_pcie_gpio_table(), since the GPIO table comes from the baseboard and is overridden by a separate table from the variant. Drop the __weak qualifier as this function is not overridden. This is similar to the change made for skyrim in CB:67809 Change-Id: I14c79fad04f18d874ce6ff7e572bb237445db8b1 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-11-05mb/google/brask: Disable PCH USB2 phy power gating for moliCasper Chang
The patch disables PCH USB2 Phy power gating to prevent possible display flicker issue for moli board. Please refer Intel doc#723158 for more information. BUG=b:257373742 TEST=Verify the build for moli board Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I457d410501be996f0f29ec622e1829f1581c4970 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69193 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
2022-11-05soc/intel/block/power_limit: Avoid MSR read if it is not neededWerner Zeh
In function 'set_power_limits' there is a path to bail out early if the Kconfig switch SOC_INTEL_DISABLE_POWER_LIMITS is selected. In this case reading the MSR PLATFORM_INFO is useless and can be avoided. So read it right before the value is needed. This was found by the scanbuild. In addition, fix an unnecessary line break to increase code readability. Change-Id: Ibdededdfd56287fb9b9223e78033a3cd6425e1a2 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-05drivers/i2c/generic: Print error when using _CRS and PowerResourceRaul E Rangel
Exposing the GPIOs via an ACPI PowerResource and the _CRS results in the OS driver and ACPI thinking they own the GPIO. This can cause timing problems because it's not clear which system should be controlling the GPIO. I'm making this an error because we should really clean these up. BUG=b:210694108 TEST=Boot guybrush and see error: > I2C: 02:5d: ERROR: Exposing GPIOs in Power Resource and _CRS > \_SB.I2C1.H05D: Goodix Touchscreen at I2C: 02:5d Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifcc42ed81fff295fb168a0b343e96b3a650b1c84 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2022-11-04src/soc/amd/mendocino: Enable override of MAINBOARD_BLOBS_DIRNikolai Vyssotski
When using site-local we need to have ability to override MAINBOARD_BLOBS_DIR with a different location (presumably somewhere in site-local). site-local Makefiles.inc should be pulled in first (different CL) allowing MAINBOARD_BLOBS_DIR to be overwritten. Change-Id: I028042b947887d1182642ad4482dd1bba7ad8e23 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>