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Glinda doesn't contain I2C4 and I2C5 like Mendocino it was copied
from. Remove their definitions.
Reference: Document 57254
Change-Id: I676e76aa2309d9ab82d63b48a2dec3c100241131
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Add wifi sar for bujia.
BUG=b:345364452
BRANCH=firmware-brya-14505.B
TEST=emerge-brask coreboot-private-files-baseboard-brya coreboot
chromeos-bootimage
Change-Id: I5a67f3723a9dc33793a5cd95f9a3a2596c3c1fc6
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84501
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
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GCC with LTO cought this.
Warning:
src/mainboard/google/kahlee/variants/careena/variant.c:44:12: error: 'bid' may be used uninitialized [-Werror=maybe-uninitialized]
44 | if (bid == 7)
| ^
src/mainboard/google/kahlee/variants/careena/variant.c: In function 'car_stage_entry':
src/mainboard/google/kahlee/variants/careena/variant.c:24:18: note: 'bid' was declared here
24 | uint32_t bid;
Change-Id: Ie732b5be5cd9dc0abaf1a5efe023bcb0738dba1d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84206
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: coreboot org <coreboot.org@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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After reboot, the system does not need to serve pending IRQ from
systimer. Therefore, clear systimer IRQ pending bits in init_timer().
For that to work, the systimer compensation version 2.0 needs to be
enabled.
TEST=Build pass and timestamp is not reset in ATF and payload
BUG=b:343881008
Change-Id: I520986b81ca153ec3ce56558a80619448cfc0c59
Signed-off-by: Zhanzhan Ge <zhanzhan.ge@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83928
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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This should be the sane default, as having this option enabled when the
AT24RF08C (Asset Identification EEPROM) is not present on the mainboard
can cause SMBIOS table entries to become "*INVALID*". This can,
for example, result in strange hostnames when an OS installer uses
SMBIOS information to automatically generate one. On the other hand,
the coreboot generated SMBIOS tables will at least always contain basic
information. Therefore, this driver should be treated as an enhancement
rather than a default.
Currently, the following mainboards have this option disabled:
- ThinkCentre M710s
- ThinkCentre M700 / M900 Tiny
- Haswell ThinkPads
- ThinkPad T440p
- ThinkPad W541
Therefore, we can remove this option entirely on these mainboards. Note
that there may be other mainboards which do not have this chip present
but still have the option enabled. However, this requires a more
detailed investigation which would be out of scope of this change.
TESTS=Timeless builds on lenovo mainboards produce the same binary.
config INCLUDE_CONFIG_FILE
default n
Was temporarily added to `mb/lenovo/Kconfig` during these tests, as
while the configuration does not change, the order of entries do.
Therefore, technically producing a different binary when included.
Change-Id: I5bb101bd6696c39718ee779426d0ec3e721e1b51
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84544
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add two new memory parts
1. K3KL8L80CM-MGCT (Samsung)
2. H58G56BK8BX068 (Hynix)
BUG=None
TEST=Run part_id_gen tool and check the generated files.
Change-Id: I557b359d9e639f6c3fac4239eb28aa7e0bed4c0e
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This was found due to the `_Static_assert()` from CB:84360 failing.
Change-Id: Ibb167b8dc379ca331812255c3e7e049556f2b57b
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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This corrects the mismatch found in the verb tables of Monroe Chromebase
and Link Chromebook.
The verb data was not aligned to a multiple of 4, therefore an entry was
repeated as padding.
This was found due to the `_Static_assert()` from CB:84360 failing.
TEST=Tested on LINK under Linux and Win11, audio working properly under both.
Change-Id: Id377281af310642a6ba77e5a0002ca1dfca38827
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84414
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The verb data was not aligned to a multiple of 4, therefore an entry was
repeated as padding. This has not been tested.
This was found due to the `_Static_assert()` from CB:84360 failing.
Change-Id: I3a40e6229419ee7d1a238916ee6d49cf9314f6ab
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84395
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This allows to configure a default screen rotation in 90-degree
steps. The framebuffer contents will then be displayed rotated,
by the same amount in the other direction; i.e. if you turn the
screen to the left, the picture has to be rotated to the right
to accommodate.
This is only supported by libgfxinit from Skylake / Apollo Lake
on (earlier GPUs didn't support the 90-degree steps anyway) and
it only works with the linear-framebuffer option.
Change-Id: Iac75cefbd34f28c55ec20ee152fe67351cc48653
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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regist*re*s → regist*er*s
Change-Id: Ie5f5cb481f0fac335e592fd3f1f56d5462e37c1e
Fixes: 2b0b2ef9a258 ("soc/intel/common/systemagent: select CAPID_A, BDSM and BGSM by Kconfig")
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
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Poweroff does not seem to use the ACPI _OFF function, but rather the
smihandler. Creating variant_smi_sleep function for nami to handle
the power off sequence during reboot/poweroff.
BUG=b:364193909
TEST=emerge-brox coreboot
Change-Id: I0108be4e5e7c0265aae0f16fd4e2b7cbe5936112
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84412
Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update DTT settings according to b:348285763#comment20 in
order to increase the limit of the charging current to 3A.
BUG=b:348285763
TEST=emerge-brox coreboot, and thermal engineer verifies OK.
Change-Id: I24978afd819666f635c85f2be9b71d39e0a39f27
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84527
Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Modify start-up timing for WWAN RW101R-GL to follow spec:
PWR_EN H H H
FCPO# Tpr H H
RESET# L Ton H
Tpr: delay for Power stable (>0ms)
Ton: delay for reset time (>20ms)
BUG=b:349698817
BRANCH=None
TEST= Build firmware and verify on jubilant with RW101R-GL
Measure the start-up timing sequence to meet spec
Boot up in OS, and confirm WWAN can connect to cell site
Change-Id: I7aa3e7a172143ff1cebea7f48bda45d4fb2c77f7
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Many sources include device.h and thus static.h, but many only need the
function declarations and type definitions, not the compiled devicetree
from sconfig. This causes many unnecessary recompiles whenever the
devicetree is updated due to the dependency. Address this by moving the
config_of_soc macro directly into the generated static.h header, as it
seems to be the only line in device.h that actually requires static.h.
For now, static.h remains included in device.h so that the build is not
affected. Subsequent commits will include static.h directly into sources
that actually need it, after which it can be dropped from device.h.
Some statistics for C objects:
Dell Latitude E6400 (GM45/ICH9):
669 total objects
181 depend on static.h
2 require static.h
Dell Latitude E6430 (Ivy Bridge/Panther Point):
693 total objects
199 depend on static.h
3 require static.h
Lenovo ThinkCentre M700 / M900 Tiny (Kaby Lake):
794 total objects
298 depend on static.h
23 objects require static.h
MSI PRO Z690-A (WIFI) DDR4 (Alder Lake):
959 total objects
319 depend on static.h
25 require static.h
The number of objects was determined by grepping the build log for
calls to CC, the number of objects that depend on static.h was
determined by grepping for calls to CC after touching static.h, and the
number of objects that actually require the static.h related lines from
device.h was determined by grepping for objects that failed to build
after removing the static.h lines from device.h and running make with
the --keep-going flag.
Change-Id: I7c40135bf2815093b81e47201c38b7d0a6ac8fa8
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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FSP-M UPDs are programmed according to the configuration (Kconfig and
device tree).
BUG=348678529
TEST=Memory is initialized successfully and hardware is programmed as
desired on Intel pantherlake reference board.
Change-Id: Iea26d962748116fa84afdb4afcba1098a64b6988
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84443
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update generated FSP headers for Panther Lake from v2382_01
Changes include:
- Update FspmUpd.h, FspsUpd.h, MemInfoHob.h and FirmwareVersionInfo.h
BUG=b:348678529
TEST=Able to build google/fatcat
Change-Id: Ibe382615db1a7c7a0841d8fe4ae43c226e2c2020
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add wifi sar table support for fatcat. Bit 4-5 in CBI/FW_CONFIG
is used to select different sar table (index 0 to 3).
BUG=b:348678529
TEST=emerge-fatcat coreboot chromeos-bootimage
Change-Id: I2d82f76d7c11378ee5c221a6b9621b4cba83720d
Signed-off-by: YH Lin <yueherngl@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
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As https://doc.coreboot.org/contributing/coding_style.html#typedefs
states: "In general, a pointer, or a struct that has elements that can
reasonably be directly accessed should never be a typedef". This
commit makes the Intel Panther Lake SoC code comply with this by using
explicitly `struct soc_intel_pantherlake_config' in the
soc/intel/pantherlake code as I have been suggested to for the
`fsp_params.c' files. The rule being the rule and consistency across
a project matters more than personal preferences.
The documentation lists five exceptions and none on them cover the use
of `config_t' instead `struct soc_intel_pantherlake' but I believe it
does not make the code better for the following three reasons:
1. It is repetitive, make the line longer and the code is in
soc/intel/pantherlake so obviously the config_t data structure is
the pantherlake soc configuration.
2. It makes re-usability from one generation to another unnecessarily
harder.
3. This config_t abstraction is required for and used by some common
block code anyway. Hence, we end-up with some code using `config_t'
and other using the final structure which break the consistency of
the code when the project in looked as a whole.
BUG=348678529
TEST=Google fatcat mainboard compiles
Change-Id: Ibe382615db1a7c7a0841d8fe4ae43c226e2c2021
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
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Add support for the ODROID-H4 family of boards. Tested on an ODROID-H4+
board, but all of them use the same PCB (with different components).
The four SATA ports on the mainboard are provided by an onboard ASMedia
ASM1064B PCIe-to-SATA bridge. Unlike other mainboards in the tree using
an ASMedia ASM1061 or ASM1062 PCIe-to-SATA bridge, the ODROID-H4+ comes
with a SPI flash chip for the ASM1064B and does not seem to have issues
regarding PCIe power management (e.g. ASPM) or unusable SATA AHCI mode.
The ODROID-H4 comes with a single 16 MiB SPI flash chip. The ODROID-H4+
and the ODROID-H4 Ultra feature Dual BIOS, consisting of another 16 MiB
SPI flash chip and a 3-pin header to select between them. The board can
be flashed internally or using a SOIC-8 clip, but the M.2 slot may need
to be empty for the clip to fit.
Working:
- DDR5 SO-DIMM slot
- All SATA ports on ASMedia ASM1064B PCIe-to-SATA controller
- UART to emit spam
- All video outputs (FSP GOP only lights up one output at a time)
- All USB ports (on the Ethernet connectors and on EXT_HDR1)
- M.2 M connector (PCIe only)
- PCIe power management
- Ethernet NICs
- eMMC
- HD audio codec and display audio
- S3 suspend/resume
- SeaBIOS <current version>
- MrChromebox edk2 <current version>
- Super I/O HWM on Linux (using out-of-tree it87 kernel module)
- Booting Arch Linux from NVMe and SATA
- Booting Windows 10 from NVMe
Not working:
- PECI: undocumented protocol and undocumented Super I/O
- Resuming on Windows 10 BSODs with `VIDEO_TDR_FAILURE`
Untested:
- Fan curves: may need to lower the temperature limits a bit
Change-Id: I7e0d395ba3d15dfcf6d47a222b90499ca371e4eb
Signed-off-by: David Milosevic <David.Milosevic@9elements.com>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Trulo ISH uses the MAIN FW loaded by the kernel driver. This commit
enables DRIVER_INTEL_ISH_HAS_MAIN_FW for trulo, which skips printing the
ISH BUP version.
BUG=b:360144613
TEST=Local build successful and tested on trulo by toggling the
config. enabling this config skips printing the ISH version in cbmem.
1. CONFIG enabled
```
trulo-rev1 ~ # cbmem -c | grep ISH
[INFO ] \_SB.PCI0.ISHB: Set firmware-name: ish_fw.bin
```
2. CONFIG disabled
```
trulo-rev1 ~ # cbmem -c | grep ISH
[DEBUG] ISH version: 5.4.2.36864
[INFO ] \_SB.PCI0.ISHB: Set firmware-name: ish_fw.bin
```
Change-Id: Ifebd563ec8ddb0378e1215a90396687857f3f71d
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84494
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This commit introduces a new config DRIVER_INTEL_ISH_HAS_MAIN_FW to
indicate that the Intel Sensor Hub (ISH) is using the ISH MAIN firmware.
The ISH MAIN firmware is located in rootfs, hence we no longer need to
store the ISH BUP version in the CSE partition.
When this config is enabled, fetching the ISH BUP version from the CSE
firmware partition is skipped.
BUG=b:360144613
TEST=Local build successful and tested on trulo by toggling the
config. Enabling this config skips printing the ISH version in cbmem.
Change-Id: I6cacf7b44ce6895ecb96db295d184c7b7d5a872c
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84493
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
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BUG=b:348678529
TEST=Able to build google/fatcat.
Change-Id: I5c90aac4873dcc57e65e641656dca3a96f84d6b8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84543
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Source: Document 57254
Change-Id: I9675d45eba257e52d9a870a4cc153b925267f840
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Change-Id: Ida2499d9894aa99f341c7a6ef2cd93b3f8ea61fe
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This also updates the mainboards depending on it.
Change-Id: I1138f27bfd47f6fa70a0c2afcc65a5553a609d57
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84376
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add default value in nissa and trulo devicetree.cb, ODM have to review
the board design to follow RDC#646929 Power Map requirement.
NOTE: The VccInAuxImonIccImax remains unchanged w/ and w/o this CL.
BUG=b:330117043
BRANCH=firmware-nissa-15217.B
TEST='emerge-nissa coreboot chromeos-bootimage'
Change-Id: Iaedd34757aa6802edcae402e751bc39b9cfe9e0c
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83725
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable the AST 2600 native graphics init driver to have a working
UEFI firmware menu displayed over KVM.
Change-Id: I2961576077ed3286df080cd09ffe68d835d8c3e7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Add support for AST2600 as found on Intel Archer City CRB by using
the code found on Linux's ast drm driver.
While on it do minor modifications found on the Linux drm driver
that also affect the other ast chips.
New log messages:
[INFO ] ASpeed AST2050: initializing video device
[INFO ] ast_detect_chip: VGA not enabled on entry, requesting chip POST
[INFO ] ast_detect_config_mode: Using P2A bridge for configuration
[INFO ] ast_detect_chip: AST 2600 detected
[INFO ] ast_detect_chip: Analog VGA only
[INFO ] ast_driver_load: dram MCLK=890316000 MHz type=3 bus_width=16 size=01000000
[ERROR] No header found
[INFO ] ast_select_mode: Failed to decode EDID
[DEBUG] Assuming VGA for KVM
[DEBUG] AST: Display has 1024px x 768px
[DEBUG] Using framebuffer 1024px x 768px pitch 4096 @ 32 BPP
[INFO ] framebuffer_info: bytes_per_line: 4096, bits_per_pixel: 32
[INFO ] x_res x y_res: 1024 x 768, size: 3145728 at 0x94000000
[INFO ] ASpeed high resolution framebuffer initialized
TEST: Booted on Intel/ArcherCity CRB and used the UEFI firmware menu
over KVM using native graphics init.
Change-Id: I3d2d58d493706673c1b2ba4953967b1641bd6395
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
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Change-Id: I6e94f44d50f2b53855adc1bb1cd6a1a5d9929003
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
|
Update PCIe Segment, Bus, Device & Function for various IIO bridge
devices.
Change-Id: I01d164cf0717b3e817348e64e32478c2bb11a8b8
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
|
|
This commit drops tcss_d3_hot_disable chip config as FSP is not
exposing the same purpose UPD anymore starting with Panther Lake
SoC.
BUG=b:348678529
TEST=Build for fatcat
Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d58
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
|
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The declarations describing interface functions between SoCs
and openSIL glue code are common for the stub and Genoa POC,
and likely with future SoC openSIL implementations. Therefore,
move these out of SoC-specific header files and into
vc/amd/opensil/opensil.h.
This change facilitates swapping out the stub for the actual
openSIL glue code.
Change-Id: Icc8783ddb868f9f0c4cd357245604313eadfe531
Signed-off-by: Nicolas Kochlowski <nickkochlowski@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84428
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
For next DVT build, hw adds this power ctrl.
BUG=b:359409425
TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage
Change-Id: Id256b3a94d3c8ed6f6832d63ecc74c2438c7d15a
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84254
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
When battery not present, increase PL4 limit from 9 to 40.
Get PL setting from internal thermal and power team.
AC+DC/DC:
PL1=15W
PL2=25W
PL4=114W
AC ONLY:
PL1=15W
PL2=25W
PL4=40W
BUG=b:355094551
TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage
Confirm on lotso EVT board, as expected.
Change-Id: I5848c776399a1bdc455db604bb3b22d16f6b2928
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84202
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:342929824
BRANCH=None
TEST=boot to kernel success
Change-Id: Ibc13137488948ec6cea1904b3964ffed4ff7ea7d
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84499
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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We use ALC256 as HDA codec on fatcat hence, added the verb table.
BUG=b:348678529
TEST=Tested audio playback using HDA ALC256 codec on PTL reference
board
Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d55
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84409
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:348678529
TEST=Memory training is successful on google fatcat board
Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d51
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84406
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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This commit updates the fatcat mainboard to use the Panther Lake SoC
instead of Meteor Lake.
The changes include:
- Selecting the `SOC_INTEL_PANTHERLAKE_U_H` config option.
- Updating the `mainboard_update_soc_chip_config()` function to use the
`soc_intel_pantherlake_config` struct.
- Updating the devicetree to use the `soc/intel/pantherlake` chip.
- Updating variant header files to reflect the SoC change.
This update enables support for the Panther Lake SoC and its
features on the fatcat mainboard.
BUG=b:347669091
TEST=Able to build google/fatcat.
Change-Id: Ie0c6257dfb9dd1f627472ad220614f9b24c911ef
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84537
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This commit removes the virtual GPIOs for recovery and write protection
from the fatcat variant.
These GPIOs are not utilized on the fatcat platform, and their removal
simplifies the GPIO configuration and improves code readability.
The `CROS_GPIO_DEVICE_NAME` macro is no longer applicable for Panther
Lake SoCs. Future changes will introduce a suitable GPIO device name
that meets the requirements of Panther Lake.
BUG=b:347669091
TEST=Able to build google/fatcat.
Change-Id: I492fec28637edb2f84e9290b28dabce3f23aa867
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84536
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Enable the SOC_INTEL_COMMON_BASECODE_RAMTOP Kconfig option for the
google/vell mainboard. This option ensures improving the boot time
on google/vell by 40ms in an average.
BUG=b:352330495
TEST=Able to reduced google/vell boot time by 40ms.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iedfd346c62b1ac79796042dd3569d846007b8f10
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
When compiling with the C23 standard, bool, true, and false are
pre-defined by the language, so defining them in stdbool.h isn't allowed.
This fixes the following error:
src/include/stdbool.h:6:17: error: two or more data types in declaration specifiers
6 | typedef _Bool bool;
| ^~~~
src/include/stdbool.h:6:1: error: useless type name in empty declaration [-Werror]
6 | typedef _Bool bool;
| ^~~~~~~
Change-Id: Iec9b4e3f308008ece773ce3460daff97370161ea
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
"enable_c6dram" needs only 2 "states" to be clearly defined.
C provides "true/false", so use it instead of using unsigned int.
Change-Id: Icff1b42ceb2e89cc0b2e7abab6743430c635db7b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84155
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add device IDs for GNR PCIe root ports so that these devices can
be supported by the Xeon-SP PCIe root port driver.
Change-Id: I450c0088aa2e3be60489becf0600f534ea90d7a4
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84311
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Configure FSP UPD VMX from Kconfig ENABLE_VMX.
Change-Id: I0c03f535b6f93761419657127e791c02e8ee4988
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84327
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Both lpc.c and chip.c will create HPET table.
remove hpet_device_ops for avoiding create two HPET table.
Change-Id: I32628e98b5c1fac4b72ea3abf755b62847161bec
Signed-off-by: Lu, Pen-ChunX <pen-chunx.lu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Change-Id: I578b2c213ff1b33b4ca37e0422f690bedc9f5ba1
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84325
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
IBL eSPI should be correctly configured by LPC driver so that console
input is usable.
Change-Id: I77cc6dd67b36035974e7f268d32b8473e8d83483
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
|
Work around a GCC LTO bug. Even if no buffer overflow is bound to happen
as the soldered down path is taken GCC LTO complains about this.
Change-Id: Ib3d4ed8032bb06b6d08fbc2dc4b697df88745243
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Deku S0ix is blocked by the SSD. Enable RTD3 for the SSD to unblock
S0ix. RTD3 for SSDs has already been enabled on Rex and Screebo, too.
To prevent this S0ix blocking issue, RTD3 should also be enabled for
Karis.
BUG=361011799
TEST=Run suspend_stress_test and check whether DUT can enter S0iX.
suspend_stress_test w/o this CL
(with Phison PCIE Gen4 SSD PSENN256GA87FC0)
Suspend failed, s0ix count did not increment from 19182060
Substate Residency
S0i2.0 0
S0i2.1 0
S0i2.2 0
And PC10 residency is only 60% (by SoCWatch)
suspend_stress_test w/ this CL
(with Phison PCIE Gen4 SSD PSENN256GA87FC0)
Substate Residency
S0i2.0 0
S0i2.1 19186
S0i2.2 3389654
And PC10 residency is ~90% (by SoCWatch)
Change-Id: Iaded43a84ad1e245106d36a9d4aa83c40b046649
Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84452
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Select SOC_INTEL_RAPTORLAKE to force coreboot to use the RPL FSP headers
for FSP as vell is using a converged firmware image.
This effort also helps to save vell boot time by 80-100ms as RPL FSP is
better optimized.
Additionally, Raptor Lake platform only needs 1 SIPI-SIPI which saves
10ms of the boot time.
BUG=b:352330495
TEST=Able to build and boot google/vell.
warm reboot time w/o this CL
```
Total Time: 1,408,669
```
warm reboot time w/ this CL
```
Total Time: 1,235,651
```
Change-Id: I8f7dd76f00cfeff2908aeb805524706ac23403fa
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84491
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch disables unused I2C6 controller for the 'vell' variant of
the 'brya' mainboard.
BUG=b:352330495
TEST=Able to build and boot google/vell.
Change-Id: I5b39e44bb64bf2285c962249c0d94a8d5325f0c7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
TME, Total Memory Encryption will be enabled once the feature is
fully verified with Panther Lake.
Change-Id: I600c8a499df3b8796df35813422d0e89f67cc630
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84418
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
|
|
Menu option wasn't showing due to wrong config flag.
Change-Id: I30592a8c3e57017473511366a8cf11928e55b5e9
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Create the kanix variant of the rex0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:368501705
TEST=util/abuild/abuild -p none -t google/rex -x -a
make sure the build includes GOOGLE_KANIX
Change-Id: Id74a084ed3cebb65625166e3098f43e41a63f5f9
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84432
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Earlier change (https://review.coreboot.org/c/coreboot/+/84019)
pushed to resolve the privacy LED blinking issue regressed the camera
autofocus functionality. This change updates the power resource for
NVM and VCM in line with the tivviks schematics to fix the issue.
BUG=b:365899407
TEST=Build and boot tivviks. Verified the Autofocus and all the
camera basic sanity tests.
Change-Id: Id3e256d59982ac176844e289f18ee450079704b9
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
|
|
Compared to MT8186, MT8186T requires initializing the PMIC MT6319 in the DTS file, which necessitates using different SKU ID to distinguish between the MT8186 and MT8186T.
For MT8186, factory pre-flashed 0x7fffffff as unprovisioned SKU ID and
kernel can use the corresponding DTS file. To make MT8186T functional
on unprovisioned devices, change the SKU ID to 0x7ffffeff, so that the
correct DTS file will be selected by the payload.
BUG=b:365730137
TEST=1. Pre-flashed 0x7fffffff and boot OS.
2. Check OS boot normally by 0x7ffffeff.
BRANCH=corsola
Change-Id: I91306d3abd508e104851916882fb36a4fd302036
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84342
Reviewed-by: Knox Chiou <knoxchiou@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
|
|
This patch updates the fatcat flash map layout to accommodate the growth
in Panther Lake IFWI blobs over Meteor Lake.
Release FMD:
SI_ALL: 8MB -> 9MB
SI_BIOS: 24MB -> 23MB
RW_UNUSED: 4MB -> 3MB
Debug FMD:
SI_ALL: 8MB -> 9MB
SI_BIOS: 24MB -> 23MB
RW_UNUSED: 3MB -> 2MB
TEST=Able to build google/fatcat inside chroot.
Change-Id: I8febb4df5d3b3eb07ebff8e56a1ce2dfd2f52e7d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
|
|
This was found due to the `_Static_assert()` from CB:84360 failing.
Change-Id: I6012fd948b4350bda7af5390badac737553fa872
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84430
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Similarly to what is done in Meteor Lake, the PortResetMessageEnable
UPD can be set based on usb2_port[].type_c setting and therefore
usb2_port_reset_msg_en is not necessary.
BUG=b/348678529
TEST=Build for fatcat
Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d57
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84429
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Each TCSS port can be associated a setting via the tcss_cap_policy
device tree field. The setting can be picked within five values listed
by this commit.
BUG=b/348678529
TEST=fatcat board build tcss_cap_policy[0]=TCSS_TYPE_C_PORT_FULL_FUN
Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d56
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Because PLATFORM_USES_FSP2_X86_32 default to false when
PLATFORM_USES_FSP1_1, efi_datatype.h wrongly defines EFI as
__attribute__((__ms_abi__)).
TEST=When some code involved in the build of a platform using
FSP 1.1 such as Google/CYAN includes efi_datatype.h, it does
not hit the following error: '__ms_abi__' calling convention
is not supported for this target
Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5d
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84402
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This was found due to the `_Static_assert()` from CB:84360 failing.
Change-Id: I08881e3fb25abca8c34a04b3bea6534c0dbf391a
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84424
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Mediatek SoCs start operating at eMMC clock around 3MHz right after
power-on due to wrong src_hz value. In JEDEC spec, eMMC clock needs
under 400kHz.
When we need to set a clock output frequency, we actually set a
frequency division value. Originally, we set the source clock
frequency to 50MHz, the target frequency to 400KHz, and get the
division value 128. However, the actual source clock frequency is
400MHz, so the final actual output is 400MHz/128=3.125MHz.
So we correct source clock frequency to 400MHz for eMMC output
clock of 400KHz.
BUG=b:356578805
TEST=test boot ok; measure eMMC clock ok; no boot time impact
Change-Id: I9c8836b23fb21e9b0bdc80fbe85142ea0fa5e381
Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.corp-partner.google.com>
Signed-off-by: Kiwi Liu <kiwi.liu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84298
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
|
|
Use CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 to add GPE1 block
rather than checking if GPE1_STS(0) is '0'.
BUG:362310295
TEST=with the flag, boot google/fatcat or intel/ptlrvp to OS and check
that FADT table includes GPE1. FADT should have:
GPE1 Block Address : 00001810
GPE1 Block Length : 18
GPE1 Base Offset : 80
Without the flag, boot to OS and check that FADT table does not include
GPE1. FADT should have:
GPE1 Block Address : 0
GPE1 Block Length : 0
GPE1 Base Offset : 0
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Idd8115044faff3161ea6bd1cae6c0fe8aa0ff8d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Due to beadrix DB has C1 port before, and add FW_CONFIG without C1 port for LTE sku.
BUG=b:364431483
BRANCH=firmware-dedede-13606.B
TEST=emerge-dedede coreboot chromeos-bootimage
Set fw config to DB_PORTS_LTE and check
1.fw_config match found: DB_PORTS=DB_PORTS_LTE <= show LTE present message
2.USB3 port 3: enabled 1 <= LTE port enable
Change-Id: Ica5a2d6e19421b132a0bdbad77806a17e2c1ce69
Signed-off-by: Kevin Yang <kevin.yang@ecs.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84232
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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psys is not an optimal solution for no/low battery boot. Hence remove
function and macros related to psys implementation.
BUG=b:335046538
BRANCH=None
TEST=Build and boot on brox board
Change-Id: I6c0e9561367b5846b00be27012f002dd7c299414
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84397
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This was found due to the `_Static_assert()` from CB:84360 failing.
Change-Id: I01db9dad872cd4c9238b6c6aac73f3e6367710a4
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This was found due to the `_Static_assert()` from CB:84360 failing.
Change-Id: I3870bcd2482e55a5abcbd27cd0be18f25a35afbc
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84415
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add gfx register so GMA ACPI data is generated. Fixes brightness
controls on Windows.
Change-Id: I10948fb2ba670ba5232f1b116acdd1820ad0c07d
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Add function needed to generate ACPI backlight control SSDT, along with
Kconfig values for accessing the registers.
Change-Id: Ied08e5e9fe4913bd60474ed7dcf88b945172558d
Signed-off-by: Jeremy Soller <jeremy@sysetm76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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In newer SOC, such as PTL, there is no DMI. Exclude DMI memory range in
northbridge.asl if DMI_BASE_SIZE is '0'
BUG=b:348678529
TEST=Build CB with DMI_BASE_SIZE set to '0' in the SOC directory. Boot
to OS and check ACPI PDRC device from the ACPI DSDT table. There should
not have an entry for DMI in its _CRS method.
Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I971af2eb214b5940fa09d9dc0f9717bb5f0dfb4d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84349
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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According to the CL:chrome-internal:7651905,
Riven will use the fw_config to separate SAR setting.
CNVI + ID_0 --> wifi_sar_0.hex for WIFI6
PCIE + ID_1 --> wifi_sar_9.hex for WIFI7
BUG=b:366060274
TEST=build, enabled iwlwifi debug, and check dmesg as below.
iwl_sar_fill_table Chain[0]:
iwl_sar_fill_table Band[0] = 132 * .125dBm
iwl_sar_fill_table Band[1] = 136 * .125dBm
iwl_sar_fill_table Band[2] = 136 * .125dBm
iwl_sar_fill_table Band[3] = 136 * .125dBm
iwl_sar_fill_table Band[4] = 136 * .125dBm
iwl_sar_fill_table Band[5] = 144 * .125dBm
iwl_sar_fill_table Band[6] = 144 * .125dBm
iwl_sar_fill_table Band[7] = 144 * .125dBm
iwl_sar_fill_table Band[8] = 144 * .125dBm
iwl_sar_fill_table Band[9] = 144 * .125dBm
iwl_sar_fill_table Band[10] = 144 * .125dBm
iwl_sar_fill_table Chain[1]:
iwl_sar_fill_table Band[0] = 132 * .125dBm
iwl_sar_fill_table Band[1] = 136 * .125dBm
iwl_sar_fill_table Band[2] = 136 * .125dBm
iwl_sar_fill_table Band[3] = 136 * .125dBm
iwl_sar_fill_table Band[4] = 136 * .125dBm
iwl_sar_fill_table Band[5] = 144 * .125dBm
iwl_sar_fill_table Band[6] = 144 * .125dBm
iwl_sar_fill_table Band[7] = 144 * .125dBm
iwl_sar_fill_table Band[8] = 144 * .125dBm
iwl_sar_fill_table Band[9] = 144 * .125dBm
iwl_sar_fill_table Band[10] = 144 * .125dBm
Cq-Depend: chrome-internal:7651905
Change-Id: I647d64a008991a7a20791b2c87ea6308af6bb82e
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84339
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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tuning
If real-time tuning was enabled, 'PchPwrOptEnable' was set two times
with different values. This patch fixes the issue.
BUG=none
TEST=Enabled FSP UPD debug output and checked 'PchPwrOptEnable' offset
Change-Id: I2f31015c1da51a4ae1b8d5226f5d7b60a6023f3d
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84399
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The real-time feature should also be activated for all mc_ehl
mainboards, as it has already been done for mainboard mc_ehl1. It
improves performance in the real-time environment for these mainboards.
Change-Id: I04859b2f32bc11344b0620925f2414e7a6df625e
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84391
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The ordering of the USB-C port locations is swapped. When facing the
left panel, the correct ordering is port 1 (left) then port 0 (right).
Swap the positions of the two USB-C ports to their correct values.
BUG=b:349822718
TEST=Booted to OS, confirmed correct physical_location at
/sys/class/typec.
Change-Id: I98e3042c64aba885b602c99916734c2dbb9d66bd
Signed-off-by: Jameson Thies <jthies@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84403
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I465a6eebc2a41ca9a618b1e86dee015cea40800b
Signed-off-by: Nigel Tao <nigeltao@golang.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The ELOG for CSE updates was being added in fsp_params.c, but the
actual update happens in cse_lite.c. This commit moves the ELOG to
cse_lite.c to more accurately reflect where the event is happening.
This also removes the need for a sol_type variable in
meteorlake/romstage/fsp_params.c.
It also helps to avoid redundant ELOG event entry while performing
CSE update (due to CSE RO to RW switch dependency).
BUG=b:361253028 (Multiple CSE sync elog prints for Nissa/Trulo)
TEST=Able to see only one instance of ELOG while performimg CSE sync.
w/o this patch:
elogtool list
0 | Log area cleared | 4088
1 | Kernel Event | Clean Shutdown
2 | Early Sign of Life | MRC Early SOL Screen Shown
3 | Early Sign of Life | CSE Sync Early SOL Screen Shown
4 | System boot | 29
5 | Memory Cache Update | Normal | Success
6 | Early Sign of Life | CSE Sync Early SOL Screen Shown
w/ this patch:
elogtool list
0 | Log area cleared | 4088
1 | Early Sign of Life | MRC Early SOL Screen Shown
2 | Memory Cache Update | Normal | Success
3 | System boot | 30
4 | Memory Cache Update | Normal | Success
5 | Early Sign of Life | CSE Sync Early SOL Screen Shown
Change-Id: I37fe3f097e581f79bf67db1ceb923f10ce651d62
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
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This was found due to the `_Static_assert()` from CB:84360 failing.
Change-Id: I60bb9e7df368b786e17bb49a6f35d27372fd21de
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84394
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This was found due to the `_Static_assert()` from CB:84360 failing.
Change-Id: I5cf34d8c4e27835d126eb66f2015d2e9d93b700f
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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List of changes:
1. Select common ACPI Kconfig to include common ACPI code block
from IA-common code
2. Select ACPI Kconfig support for wake-up from sleep states.
3. Add SoC ASL code for SoC IPs like IPU, HDA etc.
4. PTL replaces DMI3 with SAF to ensure
common/block/acpi/acpi/northbridge.asl binding with PTL change,
#if DMI_BASE_SIZE guard check is added in northbridge.asl
5. include GPIO ASL that supports new pinctrl schema.
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f15
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This commit drops redundant CRASHLOG option for the brox and brya
mainboards as SOC_INTEL_CRASHLOG config is now selected by the
Alder Lake SoC directly.
TEST=Able to build and boot google/brox w/o any functional impact of
the crashlog feature.
Change-Id: I83859d6e61a151d6930785df3466c185c69e8e66
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84366
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable the CRASHLOG config option for Chrome OS boards. This allows the
Chrome OS crash reporter to collect and analyze crash dumps, aiding in
debugging and improving system stability.
TEST=Able to build and boot google/brox
Change-Id: Ia23ef1cbebdba9a3b724204eb25ee788afa3e8fd
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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This patch configures the GPIO pins for ISH to notify EC about the
tablet mode change in accordance with schematic_20240607.
BUG=b:347811875
TEST=Build and boot google/trulo. Placed the device in tabletmode & on
EC console,"tabletmode" command shows "tablet mode".
Change-Id: Id22e397e46b522428ffdabe34a445ed7e4fb6fc5
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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This reverts commit 88a496a9c81ba6447a4c1453a45d09ee79f30309.
This workaround is not valid with the latest Intel PRQ silicon,
so I'm dropping it now. Additionally, able to boot to ChromeOS without
any hang, and I also ran an S0ix cycle without any failures.
BUG=b:244082753
TEST=Able to boot google/rex0 to CrOS.
Change-Id: Idf0da5841705888d2787f61dd6e6fada2fbe3e3e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84368
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch removes the redundant crashlog config (SOC_INTEL_CRASHLOG)
entry from BOARD_GOOGLE_BRYA0 and BOARD_GOOGLE_BRASK.
BOARD_GOOGLE_BRYA_COMMON already selects a crashlog config, and
brya0/brask board eventually selects the BOARD_GOOGLE_BRYA_COMMON
config, making SOC_INTEL_CRASHLOG redundant.
TEST=Successfully built and booted google/brya0.
Change-Id: Iaff7954d4dafb4c6ca72a1521dfb434fb36b495a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84364
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch removes the redundant crashlog config (SOC_INTEL_CRASHLOG)
entry from BOARD_GOOGLE_BASEBOARD_BROX. BOARD_GOOGLE_BROX_COMMON
already selects a crashlog config, and brox baseboard eventually selects
the BOARD_GOOGLE_BROX_COMMON config, making SOC_INTEL_CRASHLOG
redundant.
TEST=Successfully built and booted google/brox.
Change-Id: Idcb03d13ee3943f188246663d47f47cb8afccbd9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84363
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I794899fa55b510e6f39dadc1a831b86389ab31ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Commit bc8f5405b542 ("tgl mainboards: Move usb{2,3}_ports settings into
XHCI device scope") not only moved the USB port definitions under the
XHCI device reference, but also combined multiple register definitions.
In doing so, it broke the inheritance from the baseboard, since the
variant overridetree registers now replaced the entire usb2_ports/
usb3_ports structs, rather than replacing individual array elements
therein. This resulted in any USB ports inherited from the baseboard
and not overridden by the variant being non-functional as they were
not included in the resulting combined devicetree.
To fix this, return to overriding individual array elements in the
usb2/3_ports structs.
TEST=build/boot google/drobit. Verify all USB ports present and
functional. Verify mainboard/static.c in built shows all ports.
Change-Id: I54921fa4ecf594a1ecbcfa7c45e5d745d4a95652
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84348
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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1)Modify jubilant cpu power limit setting depend on the brox
baseboad settgins,refer to CL:
https://review.coreboot.org/c/coreboot/+/83752
2)Update PL1,PL2, and PL4 value from jubilant thermal design
PL1 = 15W
PL2 = 41W
PL4 = 87W
BUG=b:364441688
BRANCH=None
TEST=Able to successfully boot on jubilant photo SKU1 and SKU2
boards with AC w/o battery.
Test on AC 65W and 45W w/o battery,and check the PL values.
Change-Id: I9a143d9faaa6c57b0d314c0ff6c0e55f556d7216
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
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This commit refactors the long battery string implementation to include
caching of the EC response for battery information (model, serial, and
manufacturer).
This optimization reduces resume time by approximately 63ms by
minimizing communication overhead between the AP and EC.
BUG=b:366338622
TEST=Verified on google/tivviks_ufs:
* Long battery string is displayed when
EC_GOOGLE_CHROMEEC_READ_BATTERY_LONG_STRING is enabled.
* Short battery string is displayed when
EC_GOOGLE_CHROMEEC_READ_BATTERY_LONG_STRING=n.
Change-Id: I32ae5b5e618f20335f3d344811a97f1416df529e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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Older ChromeOS devices (pre-CR50) do not support reading long battery
strings. This commit adds a Kconfig option,
EC_GOOGLE_CHROMEEC_READ_BATTERY_LONG_STRING, to enable or disable this
feature.
This allows devices with TPM_GOOGLE (CR50/TI50) to read and display
long battery strings, while older devices like google/link, wolf, samus,
and chell will continue to display only the first 8 characters.
This change ensures compatibility with older devices while enabling
the display of complete battery information on newer platforms.
BUG=b:366338622
TEST=Verified on google/tivviks_ufs:
* Long battery string is displayed when
EC_GOOGLE_CHROMEEC_READ_BATTERY_LONG_STRING is enabled.
* Short battery string is displayed when
EC_GOOGLE_CHROMEEC_READ_BATTERY_LONG_STRING=n.
Change-Id: I7859809278b7e926bbe8beb1a0a9e12c7e6c220d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84352
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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Change-Id: I88baa159475ac57ec6a2a638ab84f76a6af4fe82
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84318
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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When battery is disconnected and only adaptor is connected higher PL2
power draw causes cpu brown out and system does not boot to kernel. To
avoid this set Boot frequency UPD to 1. Reduce PL4 value to overcome
power spikes from SoC during boot. Remove Psys implementation as it
impacts active state platform performance.
BUG=b:335046538,b:329722827
BRANCH=None
TEST=Able to successfully boot on 3 different Brox proto2 SKU1
and SKU2 boards with 65W, 45W and 30W adaptors for 3
iterations of cold boot.
Change-Id: I58e136c607ea9290ecac0cee453d6632760a6433
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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It return 0 when google_chromeec_command() on success, so
get_input_power_voltage() should return adaptor voltage instead of
psys_config default value.
BUG=b:329037849
BRANCH=firmware-brya-14505.B
TEST= cbmem -c | grep -i PsysPmax
Change-Id: I848c92752b7a7b53f47c6296aad0bdda20e9b0bd
Signed-off-by: Shon <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84333
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Iebfadffd2da83992af983b8c0dfe2706f81eb728
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84317
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I816c6f68840c122fbc37085e31a1b0368a819f4a
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84313
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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GNR-AP supports up-to 128 cores/256 threads per socket. Enlarge
MAX_CPUS to 512 = 128*2*2 with 2 socket configuration considered.
Change-Id: I8dc46dcdd3ca1c3ddfa47fbb28912a2c6e4c46fa
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84312
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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FSP n-1 headers in vc/intel/fsp/fsp2_0/graniterapid are updated to
pass compilation with full platform codes.
Change-Id: I1d13ddd4db8409a4928bd1bf152a9c284d138e48
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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For Xeon-SP, DCACHE_BSP_STACK_SIZE is by default 0x10000. For GNR,
this default size is enough. Use the default size so that more
CAR spaces could be saved for other purpose.
Change-Id: I68a79df150c4954ef8d703987d7c0bb446ba4cda
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84302
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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