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2021-11-03soc/mediatek/mt8186: Initialize watchdogRex-BC Chen
MT8186 requires writing speical value to mode register to clear status register. The flow of clear status is different from other platforms, so we override mtk_wdt_clr_status() for MT8186. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I290b69573a8e58db76814e16b5c17c23413f1108 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58835 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-03soc/mediatek: Add an overridable function for WDT clear statusRex-BC Chen
mtk_wdt_clr_status is different for MT8186 and MT8195, so we move this function to soc folder. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ia8697ffdca1e2d1443f2259713c4ab6fdf1b1a9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58834 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-03soc/amd/cezanne/include/aoac_defs: drop leading newlineFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8458fbee7edd19117a207f39ac8f9575b1374fbc Reviewed-on: https://review.coreboot.org/c/coreboot/+/58863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-03soc/amd/cezanne/include: replace PICASSO with CEZANNE in include guardsFelix Held
Somehow missed renaming those when creating the coreboot support for Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I13c28f67d32ba987987cfc2b45e248d535ccdca9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-03soc/amd/*/cpu: handle mp_init_with_smm failureFelix Held
When the mp_init_with_smm call returns a failure, coreboot can't just continue with the initialization and boot process due to the system being in a bad state. Ignoring the failure here would just cause the boot process failing elsewhere where it may not be obvious that the failed multi-processor initialization step was the root cause of that. I'm not 100% sure if calling do_cold_reset or calling die_with_post_code is the better option here. Calling do_cold_reset likely here would likely result in a boot-failure loop, so I call die_with_post_code here. BUG=b:193809448 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifeadffb3bae749c4bbd7ad2f3f395201e67d9e28 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-03cpu/amd/mtrr: Remove topmem global variablesArthur Heymans
The comments are not correct anymore. With AGESA there is no need to synchronize TOM_MEMx msr's between AP's. It's also not the best place to do so anyway. Change-Id: Iecbe1553035680b7c3780338070b852606d74d15 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-03cpu/x86/Kconfig: Remove unused CPU_ADDR_BITSArthur Heymans
Change-Id: I88f62c18b814ac0ddd356944359e727d6e3bba5a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
2021-11-03cpu/amd/mtrr/amd_mtrr.c: Remove unused functionsArthur Heymans
AGESA sets up MTRRs so these functions are now unused. Change-Id: Ic2bb36d72944ac86c75c163e130f1eb762a7ca37 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-03soc/amd/stoneyridge/cpu: remove unneeded line break in get_cpu_countFelix Held
The line length is no longer limited to 80 characters, so there's no need for that line break any more. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7a8fb472f00e039f25a71ee526a3dd0bc6c754f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-03soc/intel/xeon_sp: disable PM ACPI timer if chosenMichael Niewöhner
Disable the PM ACPI timer during PMC init, when `USE_PM_ACPI_TIMER` is disabled. This is done to bring SKL, CNL, DNV in line with the other platforms, in order to transition handling of the PM timer from FSP to coreboot in the follow-up changes. Disabling is done in `finalize` since FSP makes use of the PMtimer. Without PM Timer emulation disabling it too early would block. Change-Id: If85c64ba578991a1b112ceac7dd10276b58b0900 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao
2021-11-03soc/intel/alderlake: Allow devicetree override to leave some VR settings as ↵Bora Guvendik
default Allow devicetree override to leave ac_loadline, dc_loadline and icc_max as default. Test=Boot to OS Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I715345d5ea83aed9ee929b2a4e13921c9d8895b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-03cpu/amd: Always fetch CPU addr bits at runtimeArthur Heymans
All supported AMD CPUs support getting the physical address size from cpuid so there is no need for a Kconfig default value. Change-Id: If6f9234e091f44a2a03012e7e14c380aefbe717e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-03lib/list: Add list_appendRaul E Rangel
This method will add a node to the end of the list. BUG=b:179699789 TEST=Boot guybrush to the OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1792e40f789e3ef16ceca65ce4cae946e08583d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-03mb/google/corsola: Add MediaTek MT8186 reference boardRex-BC Chen
Add mainboard folder and drivers for new reference board 'Corsola'. TEST=build pass BUG=b:200134633 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I2d701c03c97d3253effb6e93a2d55dcf6cf02db6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-03soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoCRex-BC Chen
Add new folder and basic drivers for Mediatek SoC 'MT8186'. Difference of modules including in this patch between MT8186 and existing SoCs: Timer: Similar to MT8195, MT8186 uses v2 timer. EMI/PLL/SPI: Different from existing SoCs. TEST=boot from SPI-NOR and show uart log on MT8186 EVB BUG=b:200134633 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I579f79c15f4bf5e1daf6b35c70cfd00a985a0b81 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58640 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-03soc/mediatek/mt8195: move timer enum variables to timer_v2.hRex-BC Chen
Some enum variables of timer v2 are the same between MT8195 and MT8186, so we move them to common timer_v2.h. TEST=emerge-cherry coreboot BUG=b:200134633 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I89891a19e622aa24783025e73c38c4ffa43aa166 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58829 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-03device/include: Fix potential build errorAlan Huang
Add include guard for usbc_mux.h BUG=none BRANCH=none TEST=Build Pass Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Change-Id: I47988edee84d17f0a15cfda1ac6f0187326bd331 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-03mb/siemens/mc_ehl1: Adjust PCIe clock settings in devicetreeWerner Zeh
On mc_ehl1 there are three of the 6 PCIe clocks used to drive PCIe devices. None of the used clock output is dedicated to a special device (CLK0 drives several devices on the mainboard, CLK1 and CLK2 are connected to a PCIe switch). Therefore do not use a port mapping of the clocks to avoid a stopping clock once a device is missing and the matching root port is disabled. Instead set the mapping to 'PCIE_CLK_FREE' to have a free running clock. In addition, use the defined constant 'PCIE_CLK_NOTUSED' instead of the value 0xFF to disable the CLKREQ-feature and unused clocks. Change-Id: I2beea76ff8fefd79f476bef343d13495b45cdfcf Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58740 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-03soc/mediatek/mt8195: add apusys init flowFlora Fu
Set up APU mbox's functional configuration registers. BUG=b:203145462 BRANCH=cherry TEST=boot cherry correctly Signed-off-by: Flora Fu <flora.fu@mediatek.com> Change-Id: I5053d5e1f1c2286c9dce280ff83e8b8611b573b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58794 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-02mb/system76/oryp8: Add System76 Oryx Pro 8Jeremy Soller
https://tech-docs.system76.com/models/oryp8/README.html Tested with TianoCore (UeifPayloadPkg). Working: - PS/2 keyboard, touchpad - Both DIMM slots - Both M.2 SSD slots - All USB ports - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Internal microphone - Internal speakers - Combined 3.5mm headphone & microphone jack - Combined 3.5mm microphone & S/PDIF jack* - S3 suspend/resume - Booting to Pop!_OS Linux 21.10 and Windows 10 20H2 - Flashing with flashrom Not working: - Discrete/Hybrid graphics Not tested: - Thunderbolt functionality - S/PDIF output Change-Id: Iabc8e273f997d7f5852ddec63e0c1bf0c9434acb Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-02mb/system76/bonw14: Add System76 Bonobo Workstation 14Jeremy Soller
Change-Id: I55a827f8d6a5421c36f77049935630f4db4ba04d Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-02mb/system76/kbl-u: Add Galago Pro 2 as a variantJeremy Soller
Change-Id: Ia277b3ad50c9f821ab3e1dcb8327314ba955fa79 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-02mb/system76/kbl-u: Add Galago Pro 3 as a variantJeremy Soller
Change-Id: Ie203883cc9418585da4f9c7acd89e7624234caf1 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-02mb/system76/kbl-u: Add System76 Galago Pro 3 Rev BJeremy Soller
Change-Id: I25464d3a2dd02e613a8392db90b1eaf0f9b3ca70 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-02mb/system76/gaze15: Add Gazelle 14 as a variantTim Crawford
Change-Id: Ib455951d1d26ddfa010d4eb579905235bd1385a9 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-02mb/system76/gaze15: Convert to variant setupTim Crawford
Change-Id: I6d8a97d71ff3b4408f5e11230ed3ff00357f7123 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-02mb/system76/oryp6: Add Oryx Pro 7 as a variantJeremy Soller
Change-Id: Id00a45a6a6acf0880934c55f1a3f18e63f2aed43 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-02mb/system76/oryp6: Convert to variant setupTim Crawford
The Oryx Pro 6 has the same board layout as the next model in series, Oryx Pro 7. The primary difference between the two is the dGPU (20 series to 30 series). Convert oryp6 to a variant setup in preparation for adding the oryp7. Change-Id: I976750c7724d23b303d0012f2d83c21a459e5eed Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-02soc/intel/denverton_ns: Fetch addr bits at runtimeArthur Heymans
Change-Id: Ic46a7d56cbaf45724ebc2a1911f5096af2fe461a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-02Revert "mb/google/brya/var/kano: disabled autonomous GPIO power management"David Wu
This reverts commit 287cc02c007fd47b515d19389ea00ea0461fd5a1. Reason for revert: it will break s0ix. BUG=b:201266532 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I393077b26e2cdeae055d8eea1030754602e94ada Reviewed-on: https://review.coreboot.org/c/coreboot/+/58809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-02include/device/pci_ids,soc/amd/common/block/lpc: drop duplicate PCI IDsFelix Held
PCI_DEVICE_ID_AMD_FAM17H_LPC and PCI_DEVICE_ID_AMD_FAM17H_SMBUS redefine the same values that are already defined by PCI_DEVICE_ID_AMD_CZ_LPC and PCI_DEVICE_ID_AMD_CZ_SMBUS, so drop PCI_DEVICE_ID_AMD_FAM17H_LPC and PCI_DEVICE_ID_AMD_FAM17H_SMBUS. Also add some comments to the places in the code where the defines are used to clarify which ID is used on which hardware generation. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id0b3d7b5a886ccc76d82ada6be4145e85fd51ede Reviewed-on: https://review.coreboot.org/c/coreboot/+/58696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-02mb/google/volteer: allow MKBP devices and disable TBMC deviceFrankChu
Enable MKBP (Matrix Keyboard Protocol) interface for all volteer family to use for buttons and switches. Disable TBMC (Tablet Mode Switch device), as it is not needed anymore. BUG=b:171365305 TEST=manual test on Volteer: Volume Up/Down and Power buttons, Tablet Mode switch Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I2bb2e895af17fa4280113e57e2b0ca780af8840e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Boris Mittelberg <bmbm@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-02mb/intel/adlrvp: Configure EC in RW GPIOAnil Kumar
EC_IN_RW signal from EC GPIO is connected to GPIO E7 of SOC. This GPIO can be used to check EC status trusted (LOW: in RO) or untrusted (HIGH: in RW). Branch=none Bug=none Test=Issue manual recovery and confirm DUT is entering recovery mode on ADL-M RVP. Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I20804db450ab0b3ebe19c51ba2b294a0137d81a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-02mb/google/guybrush: Update STT coefficientsJason Glenesk
Update guybrush STT (Skin Temperature Tracking) configuration settings to values provided by power team after tuning. BUG=b:203123658 Change-Id: I14c69dbe044e4f3f2711be96e5ea80db0686b3eb Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-11-02mb/system76/*: CMOS: Drop power_on_after_fail optionTim Crawford
Our boards do not boot if power_on_after_fail=Disable. Drop the option and use the default of powering on. Change-Id: Ia1857e52f838337048f79f8ca5c12d669cae321a Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-11-02soc/amd/common/block/cpu: Add support for cbfs_cache regionRaul E Rangel
This change adds the cbfs_cache region into the x86 memlayout. The SoC or mainboard can decide how big the region should be by specifying CBFS_CACHE_SIZE. BUG=b:179699789 TEST=Build guybrush and verify cbfs_cache region wasn't added. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I268b6bc10906932ee94f795684a28cfac247a68c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-02psp_verstage: convert relative address in EFS2Kangheui Won
Addresses in AMD fw table with EFS gen2 are relative addresses, but PSP doesn't accept relative addresses in update_psp_bios_dir(). Check for EFS gen2 and convert them as needed. BUG=b:194263115 TEST=build and boot on guybrush and shuboz Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I95813beba7278480e6640599fcf7445923259361 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-02google/trogdor: Add backlight support for Parade ps8640xuxinxiong
Add backlight support in ps8640 through the AUX channel using eDP DPCD registers. BUG=b:202966352 BRANCH=trogdor TEST=verified firmware screen works on homestar rev4 Change-Id: Ief1bf56c89c8215427dcbddfc67e8bcd4c3607d2 Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-02mb/google/brya: Correct AT24 NVM address sizeVarshit B Pandya
Currently, the address size field of AT24 NVM is incorrect, and Linux v5.10 kernel logs the message below: at24 i2c-PRP0001:01: Bad "address-width" property: 14 The valid size of the AT24 NVM is 16 bits so modify the value from 0x0E to 0x10. TEST=Boot brya and check the kernel log and see "Bad address-width" error message is not shown. Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I6c1ed5334396e0ca09ea0078426a7b5039ae4e8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58769 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-11-02mb/google/brask: add the mkbp deviceZhuohao Lee
In order to let the ec passing the key event like recovery and power key to the OS, we need to include EC_ENABLE_MKBP_DEVICE to generate the MKBP device. BUG=b:204519353, b:204512547 BRANCH=None TEST=pressed recovery key and power button in the OS and checked the UI behavior. Change-Id: Ia1d0b9b301994ad9a0f4bf28b75ab0310a1d63a0 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-02mb/siemens/mc_ehl1: Clean up PCIe root port settings in devicetreeWerner Zeh
PCIe root ports #5 (00:1c.4) and #6 (00:1c.5) are not used on this mainboard and are not routed either, so remove them from the devicetree completely. PCIe root port #7 (00:1c.6) is connected and used. Add the missing settings for L1 substates and latency reporting to disable these features for this port as well. Change-Id: I06f59f0369ffcd958b5fe12bb3c646d37103811f Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58568 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-02mb/siemens/mc_ehl1: Clean up devicetreeWerner Zeh
There are a bunch of devices in the devicetree that are disabled in FSP-S and not used on this board. Having them around in the devicetree, even if disabled, is not necessary and leads to a message in the log (left over static devices...check your devicetree). This commit cleans up devicetree.cb and removes all unused and disabled devices. Change-Id: Ia5ffb382e3524e61b8583aca801063942fe2f247 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-11-02lib: Add new argument as `ddr_type` to smbios_bus_width_to_spd_width()Subrata Banik
Add DDR5 and LPDDR5 memory type checks while calculating bus width extension (in bits). Additionally, update all caller functions of smbios_bus_width_to_spd_width() to pass `MemoryType` as argument. Update `test_smbios_bus_width_to_spd_width()` to accommodate different memory types. Create new macro to fix incorrect bus width reporting on platform with DDR5 and LPDDR5 memory. With this code changes, on DDR5 system with 2 Ch per DIMM, 32 bit primary bus width per Ch showed the Total width as: Handle 0x000F, DMI type 17, 40 bytes Memory Device Array Handle: 0x0009 Error Information Handle: Not Provided Total Width: 80 bits Data Width: 64 bits Size: 16 GB ... BUG=b:194659789 Tested=On Alder Lake DDR5 RVP, SMBIOS type 17 shows expected `Total Width`. Change-Id: I79ec64c9d522a34cb44b3f575725571823048380 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-11-02mb/google/zork/var/vilboz: Generate new SPD ID for new memory partsFrank Wu
Add new memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: 1. Hynix H5ANAG6NCJR-XNC 2. Micron MT40A512M16TB-062E:R 3. ADATA 4JQA-0622AD BUG=b:199469240 BRANCH=firmware-zork-13434.B TEST=FW_NAME=vilboz emerge-zork coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I57cca403800d9731a7b689ac9773a7940e83904e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-11-01commonlib/region: Add rdev_readat_full helper methodRaul E Rangel
This helper method makes the code a bit cleaner. BUG=b:179699789 TEST=none Suggested-by: Julius Werner <jwerner@chromium.org> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ie442217eba2e8f99de1407d61f965428b5c6f3bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/58761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-01soc/intel: Don't send CSE EOP if CSME is disabledSean Rhodes
CSE EOP will fail if the CSE is disabled (CB:52800) Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ic00fdb0d97fefac977c0878d1d5893d07d4481ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/57149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-01soc/intel/braswell: Set GNVS DPTE via devicetreeAngel Pons
Introduce the `dptf_enable` devicetree setting to set the DPTE GNVS field, as newer Intel platforms do. Change-Id: I88b746c64ca57604f946eefb00a70487a2fb27c0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-01soc/intel/braswell/chip.h: Use `bool` typeAngel Pons
Use `bool` type where applicable. Change-Id: I4d5422c16381676738b8614e8e50737b59739921 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-01security/intel/txt: Get addr bits at runtimeArthur Heymans
This removes the need for a Kconfig value. Change-Id: Ia9f39aa1c7fb9a64c2e5412bac6e2600b222a635 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-11-01mb/google/dedede/var/storo: Add fw_config probe for multi audio codecZhi Li
Compatible headphone codec "Realtek ALC5682I-VD" and "ALC5682I-VS" BUG=b:202463494 BRANCH=dedede TEST=ALC5682I-VD or VS audio codec can work normally Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com> Change-Id: Ib808ddadef1029d3f06eb2d68164243c386d4905 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-01mb/google/brya/var/brya0: add HPS as generic I2C peripheralDan Callaghan
Some brya0 units have HPS fitted and connected to PCH I2C2, rather than a user-facing camera. Because HPS uses I2C address 0x51, which may conflict with the user-facing camera EEPROM, introduce a new fw_config bit to indicate whether HPS is present. BUG=b:202784200 TEST=FW_NAME=brya0 emerge-brya coreboot chromeos-bootimage TEST=ectool cbi set 6 0x28191 4 # set bit 17 for HPS TEST=flashrom -p internal -w image-brya0.serial.bin Signed-off-by: Dan Callaghan <dcallagh@google.com> Change-Id: I322548bcfccf16ba571396bc88fd6fc03c036a4e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58646 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-01vc/mediatek/mt8195: Remove unused code and commentsRyan Chuang
Remove unused code and comment to align with the latest MTK memory reference code which is from MTK internal dram driver code without upstream. version: Ib59134533ced8de09d23dd9f347c934d315166e2 TEST=boot to kernel Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: I95ab3cf8809ad22a341ceb7fd53a68e13fb0420d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58635 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-01amd/lpc: Remove the weak functionZheng Bao
BUG=b:140165023 Change-Id: Idb4613dc08c8dee6c92b4dabb39c2f5c189471aa Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-01soc/intel/common/block/cse: Add get_me_fw_version functionJohnny Lin
Modify print_me_fw_version to get ME firmware version by calling it. Tested=On a not yet to be public platform, verified the function can get ME FW version successfully. Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: I50d472a413bcaaaa085955657bde6a0e6ec2c1db Reviewed-on: https://review.coreboot.org/c/coreboot/+/58520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-01commonlib: Add new TS for IA pre-cpu reset entitiesBora Guvendik
The idea here is to capture the various boot entities prior to IA cpu reset. BUG=b:182575295 TEST=Boot to OS, check cbmem -t output Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: If89befa362d7852a2c0743d05155a0b6c1634672 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-01mb/google/brya: Enable DRIVERS_GENESYSLOGIC_GL9755 for braskDavid Wu
Enable DRIVERS_GENESYSLOGIC_GL9755 support for brask. BUG=b:197385770 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: If421e0df058b6f2b87267d5e3822940b90062f71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-01mb/google/brya/var/taeko: Add probe for MAX98357+ALC5682I_VSJoey Peng
Add probe function for the "VS" version of the audio amplifier so taeko can recgonize MAX98357 with ALC5682I_VS. BUG=b:202913837 TEST=FW_NAME=taeko emerge-brya coreboot and check taeko can recgonize MAX98357 with ALC5682I_VS Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Id4ff2003ee6a6f6f4ad98694996689e1a84092c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: YH Lin <yueherngl@google.com>
2021-11-01mb/google/dedede/var/kracko: Add Wifi SAR for krackoRobertChen
Add wifi sar for kracko BUG=b:194460420 TEST=emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage Change-Id: I83bca544c9f71142f95ea1137f732c182b3f29b7 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
2021-10-30soc/intel/common: Add DDR5 and LPDDR5 into the SMBIOS tableSubrata Banik
Add DDR5 and LPDDR5 memory technology into the SMBIOS Memory Type table. Change-Id: I1ec442cf0bd830db99e3636445724b6be01c5564 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-30lib: Use `smbios_bus_width_to_spd_width` for setting dimm.bus_widthSubrata Banik
Make use of `smbios_bus_width_to_spd_width()` for filling DIMM info. Additionally, ensures dimm_info_util.c file is getting compiled for romstage. TEST=dmidecode -t 17 output Total Width and Data Width as expected. Change-Id: I7fdc19fadc576dec43e12f182fe088707e6654d9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-30drivers/intel/fsp2_0: Check return type against CB_SUCCESSSubrata Banik
commit 6af980a2a (drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run serially) drops CB_SUCCESS check for mp_run_on_all_aps function hence, this changes bring back the required return type against CB_SUCCESS. Change-Id: I9fc81e6a7eebbf0072ea2acb36b3c33539b517a7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-29mb/google/brya/var/brask: Correct the GPIO config of buzzerAlan Huang
GPP_B14 is used by buzzer and should be set to NF1 'SPKR'. BUG=b:198998974 TEST=emerge-brask coreboot depthcharge and verify if the buzzer beeps. Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Change-Id: I84978af152a7117c1f3398a9b7adde161db058dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/58692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-29lib/cbfs: Enable cbfs_cache for x86Raul E Rangel
The reason cbfs_cache was disabled on x86 was due to the lack of .data sections in the pre-RAM stages. By using ENV_STAGE_HAS_DATA_SECTION we enable x86 to start using the cbfs_cache. We still need to add a cbfs_cache region into the memlayout for it to be enabled. BUG=b:179699789 TEST=Build guybrush and verify cbfs_cache.size == 0. Suggested-by: Julius Werner <jwerner@chromium.org> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I74434ef9250ff059e7587147b1456aeabbee33aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/56577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-29mb/google/brya/anahera: Disable autonomous GPIO power managementWisley Chen
With cr50 fw 0.3.22 or older version, it needs to disable autonomous GPIO power management and then can update cr50 fw successfully. BUG=b:202246591 TEST=FW_NAME=anahera emerge-brya coreboot chromeos-bootimage. Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I9137b6264ee80bc9e00dfdc3ab3926bccb4bf47c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-29soc/intel/alderlake: Add ACPI addition for USB4/TBT latency optimizationJohn Zhao
The PCI-SIG engineering change requirement provides the ACPI additions for firmware latency optimization. This change adds additional ACPI DSM function with both of FW_RESET_TIME and FW_D3HOT_TO_D0_TIME to the USB4/TBT topology which has the same implementation on Tiger Lake in commit I5a19118b75ed0a78b7436f2f90295c03928300d7. BUG=b:199757442 TEST= It was validated that the first connected device waits only 50ms instead of 100ms and all functions work on Alder Lake platform boards. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I0c8977c96de27ab0e554469eba658660975b8493 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-29mb/google/brya/var/kano: disabled autonomous GPIO power managementDavid Wu
Used H1 firmware where the last version number is 0.0.22, 0.3.22 or less to production that will need to disable autonomous GPIO power management and then can get H1 version by gsctool -a -f -M BUG=b:201266532 TEST=FW_NAME=kano emerge-brya coreboot and verify it builds without error. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: If6783e0df1404c9a353061fb564210aa0d12896e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-29mb/prodrive/hermes: Enable LTR for all PCIe portsAngel Pons
Set the `PcieRpLtrEnable` option to enable the LTR capability on all PCH PCIe root ports. TEST=Verify LTR capability enabled in `DevCap2` using `lspci -vv` Change-Id: I07ea37d178ea61d904c4f131fdea31479e899ef3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58326 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-29mb/prodrive/hermes: Map PCIe clocks to root portsAngel Pons
Map each PCIe clock source to the corresponding root port. Also, correct the CLKREQ# mapping for clock sources not associated to any CLKREQ# pin. The default `PcieClkSrcClkReq` value of 0 corresponds to CLKREQ# 0. TEST=Check that Linux sees the same PCIe devices with this commit: - All 5 onboard Ethernet NICs - BMC - Two random graphics cards in PEG0 and PEG1 slots - M.2 M NVMe SSD Change-Id: I0515877a36d42fb8858a0f0b3c0af1199a18d9af Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-29soc/intel/apollolake: Fix BUG-message when checking for XDCI deviceWerner Zeh
The current check for XDCI enabled uses a static device path to an internal PCI device at a very late point in the boot flow. At this time the devicetree has been processed and disabled devices have been already removed. If this device (00:15.1, XDCI) is disabled in devicetree this will trigger the message 'BUG: check_xdci_enable requests hidden 00:15.1' in the log. This looks weird and is wrong since it is not a bug to disable this device when it is not needed. To avoid this look up the devicetree by a tree walk instead of using a static value for the devicetree. Change-Id: If193be724299c4017e7e10142fac8db9fac44383 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-29mb/prodrive/hermes: Fix PCIe ClkSrc configurationAngel Pons
Correct the PCIe clock source configuration as per the schematics. Apparently, FSP does not turn off unused PCIe clock sources when using SPS (Server Platform Services) firmware, but it does when using CSME firmware. TEST=BMC and Ethernet NICs get detected when using CSME firmware. Change-Id: Id25a34816f512510640db95251a7a792c1eebe62 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-29drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run seriallySubrata Banik
As per MP service specification, EDK2 is allowed to specify the mode in which a 'func' routine should be executed on APs. `SingleThread` sets to 'true' meaning to execute the function one by one (serially) or sets to 'false' meaning to execute the function simultaneously. MP service API `StartupAllAPs` was designed to pass such options as part of function argument. But another MP service API `StartupAllCPUs` doesn't specify any such requirement. Running the `func` simultaneously on APs results in a coherency issue (hang while executing `func`) due to lack of acquiring a spin lock while accessing common data structure in multiprocessor environment. BUG=b:199246420 Change-Id: Ia95d11408f663212fd40daa9fd9b0881a07f1ce7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-29Revert "mb/intel/adlrvp: Remove EC region"Bernardo Perez Priego
This reverts commit 0a1602217fd0d60c59a497cb83a23b44cf4973d9. EC region is required in order to provide unified coreboot image for Chrome and Windows SKU RVP's. Also removing EC region causes a regression for ADL-P platforms. With this patch EC region is included back into flash map. Change-Id: I0f7f2b5dd392b08e1978a3b3f3236eac0dab1f12 Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-10-29mb/google/brya/var/kano: Add fw_config probe for MIPI cameraDavid Wu
Add fw_config probe for MIPI OVTI2740 camera BUG=b:194926283 TEST=FW_NAME=kano emerge-brya coreboot Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ic5a7cebf1f5c847c01e951a237af691e0ad6c73d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-29acpi/acpigen.c: Remove weak gpio definitionArthur Heymans
Compiletime errors > runtime errors. Change-Id: I1db0a8f01eaecf012e5444c03f8d4e2bb6e42a77 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-29soc/intel/icelake: select SOC_INTEL_COMMON_BLOCK_ACPI_GPIOArthur Heymans
The Intel icelake rvp boards actually rely on this but this failure was hidden in a runtime error instead of a compile time error, due to weakly linked functions. Change-Id: Idbbe774efa1515ce1d34ce2ce8f87953300a3312 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58662 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-28mb/google/brya/var/taeko: add HPS as generic I2C peripheralDan Callaghan
BUG=b:202784200 TEST=FW_NAME=taeko emerge-brya coreboot chromeos-bootimage Signed-off-by: Dan Callaghan <dcallagh@google.com> Change-Id: I400719d762b001811f809f9549fd030dff9928d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-28drivers/net/r8168.c: Guard against generating power resourceArthur Heymans
Not all platforms need to generate power resources, but the code does not get optimized out at build time because the devicetree gets compiled into a linked list. As this code pulls in some heavy ACPI dependencies that is even implemented with weak empty function it makes sense to optimize out this code using a Kconfig constant. This saves 1.5K in ramstage size on gigabyte/ga-945gcm-s2l. Change-Id: I82289aa7e6e82318417f3b827b86182891dfc2a6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58657 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-28mb/google/guybrush/var/nipperkin: update telemetry settingsKevin Chiu
Currently, the AMD SDLE stardust test fails with incorrect VDD/SOC scale/offset value, it needs to update the two load line slope settings for the telemetry. AGESA sends these values to the SMU, which accepts them as units of current. Proper calibration is determined by the AMD SDLE tool and the Stardust test. VDD scale: 92165 -> 73457 VDD offset: 412 -> 291 SOC scale: 30233 -> 30761 SOC offset: 457 -> 834 BUG=b:200194315 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage pass AMD SDLE/Stardust test Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: If53c173000a276a80247ccb08736280a25948939 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-27mb/google/guybrush: Move EN_PWR_FP from GPIO_32 to GPIO_3Rob Barnes
EN_PWR_FP is used to enable power to the FPMCU. This frees up GPIO_32 for other uses. This move applies to all board except: * Guybrush * Nipperkin board version 1 Add callbacks for variants to override fpmcu shtudown gpio table and fpmcu disable gpio table. BUG=b:202992077 TEST=Build and boot to OS in Guybrush and Nipperkin. Ensure fingerprint still works. Change-Id: I4501554da0fab0cb35684735e7d1da6f20e255eb Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-27mb/google/guybrush: Move GSC_SOC_INT_L from GPIO_3 to GPIO_85Karthikeyan Ramasubramanian
GSC_SOC_INT_L gpio is used by Google Security Chip (GSC) to interrupt SoC when the SoC is in S0 state. Hence use GPIO_85 which is in S0 domain and save the GPIO_3 in S5 domain for other use-cases. This move applies to all board except: * Guybrush * Nipperkin board version 1 Update the GPIO configuration, device tree configuration accordingly. BUG=b:202992077 TEST=Build and boot to OS in Guybrush and Nipperkin. Ensure that the SoC <-> TPM communication is working fine. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I019f10f2f457ab81bcff77ce8ca609b2b40cb2ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/58638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-27mb/google/guybrush: Fix GPIO overrides during verstageKarthikeyan Ramasubramanian
GPIO overrides are defined for verstage. But the overrides are neither enabled nor applied during verstage. Enable the overrides and apply them during verstage. BUG=None TEST=Build and boot to OS in Guybrush. Perform suspend/stress, warm and cold reboot cycling for 10 iterations each. Ensure that all the PCIe devices are enumerated fine. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I510313bf860d8d55ec3b04a9cfdfa942373163f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-27soc/intel/common/acpi: Correct IPC sub command for reading LPM requirementEthan Tsao
Modify IPC sub command to 2 from 0 for reading LPM requirement from PMC. Reference: https://github.com/otcshare/CCG-ADL-Generic-Full ClientOneSiliconPkg\Include\Register\PmcRegs.h #define V_PMC_PWRM_IPC_SUBCMD_GEN_COMM_READ 2 It is consumed in below. ClientOneSiliconPkg\IpBlock\Pmc\Library\PeiDxeSmmPmcLib\PmcLib.c Change-Id: I58509f14f1e67472adda78e65c3a2e3ee9210765 Signed-off-by: Ethan Tsao <ethan.tsao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-27mb/google/brya/var/gimble: disabled autonomous GPIO power managementMark Hsieh
Used H1 firmware where the last version number is 0.0.22, 0.3.22 or less to production that will need to disable autonomous GPIO power management and then can get H1 version by gsctool -a -f -M BUG=b:200918380 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I83cc1a5d80bf23d052e83c9791ef866966a3d9b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58626 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-27soc/amd/common/block/graphics: add missing GPU PCI IDsFelix Held
Since the iGPU PCI device IDs for AMD Renoir (family 17h, model 60h) and Lucienne (family 17h, model 68h) are already defined in pci_ids.h, also add them to the pci_device_ids list in the common AMD graphics support block. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1c554d21eece182ecea7b09b45b7aa8a733425d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-27mb/google/dedede/var/lantis: Generate new SPD ID for new memory partsWisley Chen
Add new memory parts in memory_parts_used.txt and generate SPD id for these parts: Hynix H54G46CYRBX267 Samsung K4U6E3S4AB-MGCL BUG=b:204015941 TEST=run part_id_gen to generate SPD id Change-Id: I78ec575d354a5ae7c014a6050364d0a5214e4e92 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Henry Sun <henrysun@google.com>
2021-10-27mb/google/dedede/var/driblee: Generate new SPD ID for new memory partsFrank Wu
Add new memory parts in the mem_list_variant.txt and generate the SPD ID for the parts. The memory parts being added are: 1. K4U6E3S4AB-MGCL 2. H54G46CYRBX267 BUG=b:204023388 BRANCH=firmware-keeby-14119.B TEST=FW_NAME=driblee emerge-keeby coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I1b40e24faf8d85f32839a3d44fd936ca7ee7e09f Reviewed-on: https://review.coreboot.org/c/coreboot/+/58572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-27mb/google/guybrush: Remove WWAN_DISABLE GPIOKarthikeyan Ramasubramanian
In-band controls work to enable/disable the WWAN module. Hence WWAN_DISABLE_GPIO is not critical and can be marked as not connected. BUG=b:188415287 TEST=Build and boot to OS in Guybrush. Ensure that the WWAN module is enumerated on boot and reboot. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I7fefba3de9c749971911b21ed4712e950cef5a6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-27mb/google/guybrush: Update SD_AUX_RESET_L signalKarthikeyan Ramasubramanian
On all upcoming variants and board versions of existing variants, SD_AUX_RESET_L signal moves from GPIO_69 to GPIO_5. This means all boards except: * All board versions of Guybrush * Nipperkin Board Version 1. Also in Nipperkin, LCD_PRIVACY_PCH signal moves from GPIO_5 to GPIO_18. Configure the gpios accordingly in baseboard, guybrush and nipperkin variants accordingly. Also update the DXIO port descriptor for SD PCIe engine with the corresponding AUX reset GPIO. BUG=b:202992077 TEST=Build and boot to OS in Guybrush & Nipperkin. Ensure that the SD Controller and SD Card are enumerated fine. Ensure that the enumeration is successful after a suspend/resume cycle. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: If28810747e6b4eaae2a693a98e1adc830f80bcf6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-10-27mb/google/brya/var/kano: Disable unused PCIE root port in devicetreeDavid Wu
The baseboard enables PCIe RPs 6, 8 and 9, but kano doesn't use these. Having them enabled will occasionally cause suspend attempts to fail, therefore disable them in the overridetree. BUG=b:203389490 b:192370253 TEST=FW_NAME=kano emerge-brya coreboot and verify it builds without error. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ie2b82cff6d910c961eeb56704dcbae2bdc2a8c53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-27mb/google/guybrush: Reconfigure GPIO_5Karthikeyan Ramasubramanian
On Guybrush, pen is stuffed and GPIO_5 is used to enable Pen power. On Nipperkin board version 1, pen is not stuffed and instead the GPIO is used to control LCD Privacy settings. On upcoming Nipperkin board versions and other variants, GPIO_5 is not used. Configure GPIO_5 accordingly. BUG=b:202992077 TEST=Build and boot to OS in Guybrush. Ensure that the configuration is retained on existing boards. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I2aa2f16282b91f157701212ee27ddd2e89918767 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-10-27mb/siemens/chili: Drop redundant Kconfig selectAngel Pons
The `SMBIOS_PROVIDED_BY_MOBO` Kconfig option is already selected through the `SECUNET_DMI` option. So, there's no need to select both of them. Change-Id: I784df87893043a011906af8808aff27d636c7626 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58625 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-27src/lib/fmap.c: use le*toh() functions where neededKrystian Hebel
FMAP was developed with assumption about endianness of the target machine. This broke the parsing of the structure on big endian architectures. This patch converts the endianness of the fields where applicable. Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Change-Id: I8784ac29101531db757249496315f43e4008de4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-10-27mb/google/dedede/var/drawcia: Generate new SPD ID for new memory partsWisley Chen
Add new memory parts in memory_parts_used.txt and generate SPD id for these parts: Hynix H54G46CYRBX267 Samsung K4U6E3S4AB-MGCL BUG=b:204014463 TEST=run part_id_gen to generate SPD id Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I43df98d84c6a274d6f96c8818ce6acff9337d8d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-27mb/google/dedede/var/haboki: Generate new SPD ID for new memory partsWisley Chen
Add new memory parts in memory_parts_used.txt and generate SPD id for these parts: Micron MT53E512M32D1NP-046 WT:B Hynix H54G46CYRBX267 Samsung K4U6E3S4AB-MGCL BUG=b:204015944 TEST=run part_id_gen to generate SPD id Change-Id: Icf2f7352a4bd6a58e3e7abdcaac823b863984732 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-27mb/google/brask: Correct GPIO GPP_R6 and GPP_R7 settingDavid Wu
Correct GPIO GPP_R6 and GPP_R7 setting to NF2 (DMIC_CLK1 and DMIC_DATA1). BUG=b:197385770 TEST=emerge-brask coreboot and verify it builds without error. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ia3813306f8c7b69fe5cf0e188c55256b68d329ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/58578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-27mb/google/brya/var/kano: Update the FIVR configurationsDavid Wu
This patch set disables the external voltage rails since kano board doesn't have V1p05 and Vnn bypass rails implemented. BUG=b:192370253 TEST=FW_NAME=kano emerge-brya coreboot and verify it builds without error. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ia1f3f4b2ada0154c716aedd521d4151124411ba3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-27mb/google/guybrush/var/nipperkin: config eSPI alert as in-bandKevin Chiu
To prevent unexpected alert from eSPI to SOC, configure this alert pin to in-band. BUG=b:199458949,b:203446084 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I18d38fe504bd9f2069b9977d5a35729691f672d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-10-27mb/google/guybrush/var/nipperkin: Add G2 GTCH7503 HID TS supportKevin Chiu
Follow up the G2 spec: G7500_Datasheet_Ver.1.2 BUG=b:203607764,b:202090378 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage TS is functional Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I98dd3095043ab537d91e81b84944779240b203ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/58564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-26intel/adlrvp: Add sub-regions to SI_ME in chromeos.fmdFurquan Shaikh
This change adds sub-regions to SI_ME in chromeos.fmd. These are required to support stitching of CSE components. BUG=b:189177538 Change-Id: Ife48aafcec43555175aad44f8b6307beeaea9184 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58592 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-26src/cpu: drop CPU_X86_CACHE_HELPER and x86_enable_cache wrapper functionFelix Held
Selecting CPU_X86_CACHE_HELPER only added the x86_enable_cache wrapper function around enable_cache which additionally wrote a POST code to port 0x80 and printed a message to the console. This function was only called during multi-processor initialization in ramstage via the init function pointer in the CPU's device operations struct and was run on all cores, so the message on the console was printed once per CPU core. This patch replaces all x86_enable_cache calls by calls to enable_cache and removes the wrapper function and the Kconfig symbol CPU_X86_CACHE_HELPER which was used to only add this when the corresponding CPUs used the x86_enable_cache wrapper function. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Angel Pons <th3fanbus@gmail.com> Change-Id: I5866b6bf014821ff9e3a48052a5eaf69319b003a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58579 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-14 18:31:16 +0000