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2021-07-13intel/kblrvp: Move lockdown config to baseboard devicetreeFelix Singer
Clean up lockdown configuration and move it to the baseboard's devicetree. Since most of the mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, use it for the rvp8 variant for consistency as well. Built intel/rvp11 with `BUILD_TIMELESS=1` and coreboot.rom remains identical. intel/rvp8 changes, as expected. Change-Id: I78e847c321c61c3a974b26f30bc2823ff84df651 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56212 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-13mb/intel/kblrvp/variants: Fix indentation and remove empty linesFelix Singer
Change-Id: I4b5e0992494949bcb2fbda1361e0118c087a437a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56211 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-13vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2237_00Ronak Kanabar
The headers added are generated as per FSP v2237_00. Previous FSP version was v2207_01. Changes Include: - Add VccInAuxImonIccImax in FspsUpd.h - Adjust Reserved UPD Offset in FspmUpd.h and FspsUpd.h - Few UPDs description update in FspmUpd.h and FspsUpd.h BUG=b:192199787 BRANCH=None TEST=Build and boot brya Change-Id: Ie291204a3fa0b9451c418c84bd40a17ef08a436c Cq-Depend:chrome-internal:3970327,chrome-internal:3925290 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55896 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-13soc/intel/alderlake: Implement WA for DDR5 DIMM modulesMeera Ravindranath
The coreboot SMBus driver requires additional changes to accomodate the DDR5 EEPROM read which has resulted in a broken code flow for boot. This CL serves as a temp WA to let FSP perform the SPD read for DDR5 and pass SPD addresses to FSP UPD array. BUG=b:180458099 TEST=Build and boot DDR5 adlrvp to OS Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I9998bfcd12b81c11fcc9f791da2a27d3c788e48a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50996 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-13soc/intel/alderlake: Add (and fix) devices in IRQ tableTim Wawrzynczak
Some devices were missing from the IRQ table, and this lack of IRQ programming for the devices (although unused), was causing S0ix entry to fail. BUG=b:176858827 TEST=suspend_stress_test -c10 passes, EC observes SLP_S0IX# toggle correctly upon entry/exit from S0ix Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ia7612ee008842ba2b8dcd36deb201f4f26130660 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-07-13mb/siemens/chili: Use CHIPSET_LOCKDOWN_COREBOOTFelix Singer
Currently, internal flashing is not possible due to FSP lockdown. Thus let coreboot do chipset lockdown. Change-Id: Iee4f6986e5edfe1bf6c84fe132bcb47b15bb81f5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56198 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-13vc/mediatek/mt8195: Remove redundant codeRyan Chuang
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: I10b2d3c6cb3480f9e3e3232b5ce87ecf7074bbbf Reviewed-on: https://review.coreboot.org/c/coreboot/+/56203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-07-12security/intel/txt: use mca_get_bank_count()Felix Held
Use the common mca_get_bank_count function instead of open-coding the functionality to get the MCA bank number. Change-Id: I28244c975ee34d36d0b44df092d4a62a01c3c79c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-07-12Revert "drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory region"Felix Held
This reverts commit ce0e2a014009390c4527e064efb59260ef4d3a3b which was originally introduced as a workaround for the bug that the Linux kernel doesn't know what to do with type 16 memory region in the e820 table where CBMEM resides and disallowed accessing it. After depthcharge was patched to mark the type 16 region as a normal reserved region, the Linux kernel now can access the BERT region and print BERT errors. When SeaBIOS was used as payload it already marked the memory region correctly, so it already worked in that case. After commit 8c3a8df1021b8a2789c2a285557401837f9fc2b8 that removed the usage of the BERT memory region reserved by the FSP driver by the AMD Picasso and Cezanne SoCs and made them use CBMEM for the BERT region, no other SoC code uses this functionality. The Intel Alderlake and Tigerlake SoCs put the BERT region in CBMEM and never used this reserved memory region and the change for the Intel server CPU to use this was abandoned and never landed in upstream coreboot. AMD Stoneyridge is the only other SoC/chipset that selects ACPI_BERT, but since it doesn't select or use the FSP driver, it also won't be affected by this change. TEST=Behavior of the BERT code doesn't change on Mandolin Change-Id: I6ca095ca327cbf925edb59b89fff42ff9f96de5d Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56163 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12include/cpu/x86/msr: fix MCG_CTL_P definitionFelix Held
MCG_CTL_P is bit 8 of the IA32_MCG_CAP MSR and not bit 3. Bits 0-7 of that MSR contain the number of MCA banks being present on the CPU. At the moment this definition of MCG_CTL_P is unused. Change-Id: I39a59083daa5c2db11a8074d5c4881bf55688f43 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-12security/intel/txt: add missing cpu/x86/msr.h includeFelix Held
msr_t and a few other things used in here are defined in cpu/x86/msr.h, so include it directly in this file. Change-Id: I7a3299381ff54b7665620861dec60642f27bac8d Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-07-12soc/amd/*/mca: use mca_get_bank_count()Felix Held
Use the common mca_get_bank_count function instead of open-coding the functionality to get the MCA bank number. Also re-type the num_banks variable from signed in to unsigned int, since the number of MCA bank is always positive. Change-Id: I126767cf9ad468cab6d6537dd73e9b2dc377b5c4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-07-12mb/google/brya: Update generic device number for mipi_camera deviceVarshit B Pandya
If two generic devices use the same number, device coming later overrides the earlier device, as a result of this the static.c has only one device. In the case where we have UFC set to UFC_USB, this will result in no IPU device scope in SSDT, since its entry will be set to disbled after UFC probe. TEST=Build, Boot and Check UFC camera preview with UFC=UFC_USB Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I034cb7da787313d1cb53484922149589ac0f1c5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-12cpu/amd/*/model_*_init: use mca_get_bank_count()Felix Held
Use the common mca_get_bank_count function instead of open-coding the functionality to get the MCA bank number. Also re-type the num_banks variable from signed in to unsigned int, since the number of MCA bank is always positive. Change-Id: I70ad423aab484cf4ec8f51b43624cd434647aad4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-07-12include/cpu/x86/msr: add mca_get_bank_count functionFelix Held
In multiple locations within the coreboot tree the IA32_MCG_CAP MSR gets read and masked with MCA_BANKS_MASK to get the number of available MCA banks on the CPU, so add this to the common code to avoid duplication of code. Change-Id: Id118a900edbe1f67aabcd109d2654c167b6345ea Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-07-12soc/amd/{cezanne,common}: Enable IOMMU PCIe DeviceRaul E Rangel
This change only enables the IOMMU device. We still require the IVRS table to take advantage of the IOMMU. This will happen when the picasso IVRS code is moved into common. BUG=b:190515051 TEST=lspci shows IOMMU device 00:00.2 IOMMU: Advanced Micro Devices, Inc. [AMD] Device 1631 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5c7cae3d25af5a45d48658ffa948a2856adc4346 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-12acpi: Add function to simplify If (CondRefOf (..)) sequencesTim Wawrzynczak
The new function is called acpigen_write_if_cond_refof(), and it must be paired with a following acpigen_write_if_end() call. Change-Id: I6e192a569f550ecb77ad264275d52f219eacaca1 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-07-12vc/amd/sb800: Cast to UINT32 for shift out of bounds fixPaul Menzel
It’s defined as `unsigned char`. SB800: sb_Before_Pci_Init shift out of bounds src/vendorcode/amd/cimx/sb800/SBCMN.c:643:53 ubsan: unrecoverable error. Found-by: UBSAN Change-Id: I0c5fa16bce5b68ed3b48bb17eae6d81af894b688 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-07-12vc/amd/sb800: Cast variable to 32-bit before shiftPaul Menzel
SB800: sb_Before_Pci_Init shift out of bounds src/vendorcode/amd/cimx/sb800/Gpp.c:151:61 ubsan: unrecoverable error. Found-by: UBSAN Change-Id: I6cbef2fa9806fd6da67031ca01bb25205013b478 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-07-12vc/amd/sb800: SBCMN: Cast to 32-bit before shiftPaul Menzel
SB800: sb_Before_Pci_Init shift out of bounds src/vendorcode/amd/cimx/sb800/SBCMN.c:486:57 ubsan: unrecoverable error. Found-by: UBSAN Change-Id: Id05b96f1f4cf4a1cf8283db22e10ab8df833406d Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51286 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12drivers/intel/usb4/retimer: remove redundant structure member group(PLD)Maulik V Vaghela
Currently, we get PLD information from USB port structure itself, so devicetree does not need to fill PLD structure anymore. Thus remove obsolete variable. Change-Id: I7a561677ab65ddb870d1b00b35ee9d7a22ef9c70 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-12mb/google/brya,primus,voxel: Update controller field for tbt_dma entriesMaulik V Vaghela
We need to reference correct USB port number for driver to identify type-C port number correctly. BUG=b:189476816 BRANCH=None TEST=Check the transactions are happening on correct port. Also checked retimer firmware update on both the ports. Change-Id: I20c088ee81610155067abad086eba8d72f73ad60 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-12drivers/intel/usb4/retimer: Update code to assign correct port numberMaulik V Vaghela
Since TBT controller can have maximum 2 ports per controller, our code will loop over DFP structure twice and determine port number. Retimer driver used to assign port number as below: 1. Check if power GPIO is assigned for particular DFP entry or not 2. If entry is there, assign loop count as port number Since loop count is 2, retimer will never assign port number = 2 even if it's present. In case of more than 1 controller, port number assigned will still be 0 or 1 even though actual port index might be 2 or 3. This will create an issue where even if you do transaction on device on controller 2 (port index 2 or 3), EC will route it on port 0 or 1 due to incorrect port index. Update the driver flow as per below to handle this scenario: 1. Check if power GPIO is assigned for particular DFP entry or not 2. Get USB port number from config since it's stored in usb port information under devicetree 3. Pass the port number to ACPI SSDT and EC code Above changes will ensure that we're assigning correct port number as per calculation and EC will use correct port index. BUG=b:189476816 BRANCH=None TEST=Checked that retimer firmware update works on both ports and update happens on correct port index. Change-Id: Ib11637ae39046e0afdacd33bc34e8a59e6f2bfb1 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-12drivers/usb/acpi: Create function to get PLD informationMaulik V Vaghela
Create a separate function to get PLD information from USB device. This is helpful in retimer driver where we can attach same USB port information to retimer instance and we can avoid duplication of information. BUG=None BRANCH=None TEST=Check if code compiles and function returns correct value Change-Id: Iaaf140ce1965dce3a812aa2701ce0e29b34ab3e7 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-12mb/google/kukui: Add a new config 'Munna'Sunway
Introduce a new board 'Munna' to Kukui family. BUG=None TEST=make # select Munna BRANCH=kukui Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com> Change-Id: Ie53750d0b79fe6d7c6e7778ba4616b557708601d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56169 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12soc/intel/alderlake: Increase PRERAM_CBMEM_CONSOLE_SIZE to 8KBSubrata Banik
This patch increases PRERAM_CBMEM_CONSOLE_SIZE from 5KB to 8KB to fix cbmem buffer overflow issue. Test=Boot ADLRVP and check cbmem -c | grep 'CBFS: Found' lists all stages. Change-Id: I38fd74c2edd71ce9f6c08db9dacb18e553745877 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-07-12soc/amd/cezanne/acpi: Change GPIO controller interrupt to sharedRaul E Rangel
The Majolica UEFI ACPI tables have this listed as shared. It's already a level interrupt, so no reason it shouldn't be shared. This change makes it so Windows can correctly initialize the GPIO controller. BUG=b:186212501 TEST=Boot guybrush to windows and see GPIO controller functional. Also boot guybrush to windows and verify GPIO controller still works. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I48c6d548a2a8d67599f25e37eeafc90764d9e2d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-12soc/intel/common/irq: Program IRQ pin in irq_program_non_pch()Tim Wawrzynczak
Previously, irq_program_non_pch() was only programming the IRQ line, but the pin is required as well. BUG=b:176858827 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I2a2823c183a3495721a912de285cddb4a9444c55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56174 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12soc/intel/alderlake: Add missing devices to pci_devs.hTim Wawrzynczak
There were some devices missing from pci_devs.h: 1) GNA 2) I2C6 and I2C7 3) UART3, UART4, UART5, UART6 4) UFS 5) GSPI4, GSPI5, GSPI6 BUG=b:176858827 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I2b9f8cceb4bd0c77fc43ef2e48190dd736a84ad8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56172 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12soc/amd/picasso,stoneyridge/mca: remove unneeded line breakFelix Held
Change-Id: Ib74ff1d585f8ef54960e6a1eafd5a280907f8675 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56180 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12mb/google/guybrush: enable psp_verstage by defaultKangheui Won
Select VBOOT_STARTS_BEFORE_BOOTBLOCK to turn on psp_verstage by default. BUG=b:182477057 TEST=boot guybrush Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I08befb93213aeb67e6a1e5fa91273ae61025707e Reviewed-on: https://review.coreboot.org/c/coreboot/+/55832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-12mb/google/brya/variants/primus: Update GPIO for PS8811 initCasper Chang
Route GPP_D14 to USB_A1_RT_RST_ODL for PS8811 init sequence BUG=b:193099675 Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: Ia950da61a50f30f7c4aaef572c5ed162ee76dd0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-12soc/intel/alderlake: Set max Pkg C-states to AutoV Sowmya
This patch configures max Pkg C-state to Auto which limits the max C-state to deep C-state Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: Iab92eaadad3f17ed8dddc4f383d6eeaab8c9ea6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/55706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-12mb/intel/adlrvp_m: Enable EC software syncThejaswani Putta
This patch enables CONFIG_VBOOT_EARLY_EC_SYNC. EC software sync will be performed in romstage. BUG=None BRANCH=None TEST=Verify EC software sync works on adlrvp_m Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com> Change-Id: I3a13094e5da2f672a6789fe86528de44e909045e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56154 Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12mb/google/brya: Create kano variantDavid Wu
Create the kano variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:193052432 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_KANO Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ib0670e346c113291054cb92fb57aae52f844e8c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56155 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12soc/mediatek/mt8195: fine tune pmif spi hardware settings for stabilityJames Lo
Update IO driving setting for pmif spi. Signed-off-by: James Lo <james.lo@mediatek.corp-partner.google.com> Change-Id: I48268cda8845a591592d8ca828ffe492e6dfe0ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/56166 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12vc/mediatek/mt8195: Enable DRAM Vcore DVFS settingsRyan Chuang
Add the implementation for vcore voltage control. Also remove the reporting of vio18 because it is fixed during DRAM init, and we won't provide drivers for reading or writing it. Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: I39342aea902a87cdc2c5b862e5d1a889fcc822c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56106 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12vc/mediatek/mt8195: add FOR_COREBOOT defineRex-BC Chen
The CONFIG(CHROMEOS) in DRAM calibration code was incorrectly used to identify implementations for Chromebooks (in coreboot) so we want to introduce a new flag FOR_COREBOOT to prevent confusion. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ic7a6e24f41c1fda167b5d6bb2d8a2c5c79dda8de Reviewed-on: https://review.coreboot.org/c/coreboot/+/56158 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-09soc/intel: Fix microcode loadingTim Wawrzynczak
Commit 1aa60a95bd8363d2 broke microcode loading for chipsets that have a microcode blob with a total_size field set to 0. This appears to be support for older chipsets, where the size was set to 0 and assumed to be 2048 bytes. The fix is to change the result of the subtraction to a signed type, and ensure the following comparison is done without promoting the signed type to an unsigned one. Resolves: https://ticket.coreboot.org/issues/313 Change-Id: I62def8014fd3f3bbf607b4d58ddc4dca4c695622 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56153 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Stefan Ott <coreboot@desire.ch> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-09ppc64/byteorder.h: define use of big endianKrystian Hebel
All of the build configuration is set to produce big endian image on PPC64. In addition, the toolchain produced by coreboot-sdk does not include little endian libraries so it is not possible to build LE image even when that configuration is changed. This patch changes byte order definition which is required for proper work of functions that deal with endianness, like read_{le,be}*() or {le,be}*toh(). It also revealed bugs related to the endianness on BE targets that are addressed in the following patches. Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Change-Id: Id31328a832d11db20822733304b0ae477e858d25 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-07-08mb/google/volteer/var/voema: Remove stop delay time for ELAN TSDavid Wu
Remove register "generic.stop_delay_ms" and measure data, it still can meet elan touchscreen specification that reset pull high to I2C time > 150ms (T3 > 150ms). BUG=b:185308246 TEST=Measure the T3 delay time is greater than 150ms on voema Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Id326fd4d9d71eef171580b1c6001505e698b40a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56087 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-08mb/google/brya/var/redrix: Generate SPD ID for supported partsWisley Chen
Add supported memory parts in mem_parts_used.txt, and generate SPD id for these parts. MT53E1G32D2NP-046 WT:A H9HCNNNBKMMLXR-NEE K4U6E3S4AA-MGCR MT53E512M32D2NP-046 WT:E H9HCNNNCPMMLXR-NEE K4UBE3D4AA-MGCR H9HCNNNFAMMLXR-NEE MT53E2G32D4NQ-046 WT:A BUG=b:190818098, b:190874372, b:192052098 TEST=build Change-Id: I62ee401e43bef22b4b09f41ea59bbdbc479f293c Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55885 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-08mb/google/brya: Create redrix variantWisley Chen
Create the redrix variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:192052098 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_REDRIX Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I4cfa0bd84e1ba9f8140f95d18a6da960da8124ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/55883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-07-08mb/google/brya0: Update the FIVR configurationsV Sowmya
This patch sets the disable the external voltage rails since brya board doesn't have V1p05 and Vnn bypass rails implemented. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I1c4fdb38c5c56798935b2c6627a75c3f1ac9fbef Reviewed-on: https://review.coreboot.org/c/coreboot/+/55704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-08mb/intel/tglrvp: Update Power Limit2 minimum valueSumeet Pawnikar
Update Power Limit2 (PL2) minimum value to the same as maximum value. DTT does not throttle PL2, so this minimum value change here does not impact any existing behavior on the system. BUG=None BRANCH=None TEST=Build and test on tglrvp system Change-Id: I6bbbfa8e43a241df721b91425294983c1d561f2c Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-08soc/intel/alderlake: Avoid NULL pointer deferenceJohn Zhao
Coverity detects dereference pointers req and res that are NULL when calling the pmc_send_ipc_cmd function. This change prevents NULL pointers dereference. Found-by: Coverity CID 1458077, 1458078 TEST=None Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I151157e7a9a90c43075f431933ac44f29fd25127 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-08IMOK: Add IMOK method support for DPTFSumeet Pawnikar
Add IMOK method support for DPTF BRANCH=None BUG=b:187797417 TEST=Built and tested on dedede board Change-Id: I8edfa3bcaa6bde0b9690fcace000cd582dcc81d2 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-07mb/google/dedede/var/boten: Modify Wifi-SAR sku conditionstanley.wu
Due to new sku id apply for AMP ALC1015Q-VB. Modify correct WIFI-SAR detect condition for boten/botenflex sku. BUG=b:186174768 TEST=build and test on boten/botenflex Change-Id: I0a4fb08e558fee26534564aa5e37cac814c5a98a Signed-off-by: stanley.wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-07mb/google/dedede/var/storo: Update DPTF parametersTao Xia
Update DPTF parameters from internal thermal team. BUG=b:180875582 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I6d87bc63a66ff38bc2f706d58b8537c052bf4594 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-07mb/google/dedede/var/sasukette: Configure I2C times for touchpadTao Xia
Configure I2C high / low time in the device tree to ensure I2C CLK runs accurately between 380 kHz and 400 kHz. Measured I2C frequency just as below after tuning: touchpad:390.4 kHz BUG=b:192601250 BRANCH=dedede TEST=Build and check after tuning I2C clock is between 380 kHz and 400 kHz Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: Ibe1603a48a3e841b6a50aa0c703697ec615b2854 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-07mb/siemens/mc_ehl: Switch to 16 MB ROM and provide a flashmapWerner Zeh
There is a 16 MB flash chip on mc_ehl. Set the ROM size accordingly and provide a flashmap for partitioning. Select the used flashmap on variant level to allow different layouts for different variants. Change-Id: I694729ad98f91e27308220903c49e7cb7fc436b4 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-07-07mb/siemens/mc_ehl: Clean up KconfigWerner Zeh
Remove Kconfig switches that are not needed for mc_ehl based mainboards. Change-Id: If231f37f06c6763d52a821799e87fdb3010af0aa Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-07-07arch/x86: Save resume vector to stack in x86_64 modeIru Cai
In x86_64, the first function parameter is passed in rdi register, and the 32-bit code after exiting long mode reads the resume vector in 4(%esp), so it's needed to save the resume vector from rdi to 4(%rsp). Also note that the function attribute "regparm" only works on x86-32 targets according to the GCC manual, so "asmlinkage" doesn't change the ABI of an x86_64 function. Tested on HP EliteBook 2560p. The laptop can resume from S3 in x86_64 mode after this change. Change-Id: I45f2678071b2511c0af5dce9d9b73ac70dfd7252 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55947 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-07Makefile.inc: Fix IFITTOOL dependenciesArthur Heymans
Add IFITTOOL as a dependency where needed and remove where it is unneeded. Change-Id: I88c9fc19cca0c72e80d3218dbcc76b89b04feacf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-07-07vc/mediatek/mt8195: Enable VREF calibration at DDR3200 for S0 stabilityRyan Chuang
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: I9df776b393f6b6166d1d6f02d5e96bd7ebc4a707 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-07-07vc/mediatek/mt8195: Improve settings of duty calibrationRyan Chuang
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: Ic4aeaec947356001d073df72977899ca06b18bda Reviewed-on: https://review.coreboot.org/c/coreboot/+/56104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-07-07soc/mediatek/mt8195: Add dramc_param.hRyan Chuang
The dramc_param.h defines the header version, structure and APIs for the DRAM calibration parameters stored on the flash, and should be platform independent. Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: Ib8a6ea1b6cf1538854890b653d5d9a934f7f687e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-07-07soc/mediatek/mt8195: Enable DCMGarmin Chang
Enable DCM settings on the MT8195 platform. DCM means dynamic clock management, and it can dynamically slow down or gate clocks during CPU or bus idle. Change-Id: Ib431a0334c157d440d6e89dcb154241d980d97ce Signed-off-by: Garmin Chang <garmin.chang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-07-07mb/google/zork/var/shuboz: adjust telemetry settingsKane Chen
According to stardust test tracking report to adjust telemetry setting. VDD Slope : 30595 -> 30400 VDD Offset: 77 -> 317 SOC Slope : 24063 -> 23789 SOC Offset: 105 -> 94 BUG=b:190338440 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Id997f9cd220d704c5b0882c257a596fb3d2485ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/56077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2021-07-07cpu/intel/car/core2/cache_as_ram: Add x86_64 supportPatrick Rudolph
Tested on Lenovo T500 with additional patches. Change-Id: I27cdec5f112588b219f51112279b2dfbb05b6c97 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-07-07ironlake: Add support for x86_64Patrick Rudolph
Allow to compile the experimental x86_64 code. Tested on Lenovo Thinkpad T410. Hangs in SMM relocation. When skipped boots into GNU/Linux. Change-Id: I60f2fccba357cb5fb5d85feb4ee8d02abfe6bc7e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2021-07-06soc/amd/picasso: Allow end range entry for max device ID in IVRSAamir Bohra
Allow hot plug devices to subscribe to IOMMU services. Currently the IOMMU end range is limited to device B:0 D:1f F:6. This prevents the devices on bus 1 and higher to subscribe to IOMMU services. As per AMD IOMMU spec v3 section 5.2.2.1 all possible device IDs must be defined, whether the device ID is actually populated or not. Device entries are used to report ranges when hot-plug and SR-IOV devices are possible. With this change the hot plug devices can now bind to IOMMU services (as tested on kernel v5.4), and below errors are not seen in dmesg. AMD-Vi: Event logged [IO_PAGE_FAULT device=04:00.3 domain=0x0000] AMD-Vi: Event logged [IO_PAGE_FAULT device=05:00.0 domain=0x0000] AMD-Vi: Event logged [IO_PAGE_FAULT device=04:00.4 domain=0x0000] TEST= Verify dGPU can enumerate on hotplug. No IO page fault errors seen. The hot plug devices can successfully bind to IOMMU services in kernel. Signed-off-by: Aamir Bohra <aamirbohra@gmail.com> Change-Id: I256c0f8032662674a4d75746de49c250e341c579 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55816 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: ritul guru <ritul.bits@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-06nb/intel/x4x: Expose x86_64 supportArthur Heymans
TESTED on foxconn g41m. Change-Id: I2d5d5dfbd76a84aa400e44b4bc2ac4f3b5b6f739 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56022 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-06cpu/intel/car/p4: Add x86_64 supportArthur Heymans
Change-Id: I77516e3cd5f0d3b7442be660c005a65b00454343 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-07-06arch/x86: Use ENV_X86_64 instead of _x86_64_Patrick Rudolph
Tested on Intel Sandybridge x86_64 and x86_32. Change-Id: I152483d24af0512c0ee4fbbe8931b7312e487ac6 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-05mb/siemens/mc_ehl: Provide a proper scheme for variantsWerner Zeh
There will be more variants of this mainboard so prepare the scheme for Kconfig to handle the variants properly. Change-Id: If1cf418836d77a45955ee55d30ba670db8ff2533 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-07-05mb/siemens/mc_ehl: Add new mainboard based on elkhartlake_crbWerner Zeh
Add a new mainboard called mc_ehl which is based on Intel's 'elkhartlake_crb'. This commit simply copies the mainboard directory and adjusts the naming to match the new board's name. Follow-up commits will introduce the needed changes for the new mainboard. Change-Id: Ia7c0616098046d975aa698910ac81f435d7882cb Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-07-05device: Reflow strings in printk statementsAngel Pons
To ease finding some log messages, reflow their strings to use one line. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I5284429ca6d07debf2d6c4fdbffa286140fb7694 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-07-05mb/intel/adlrvp_m: Remove ASL code and enable dynamic SSDT creation for ↵Varshit B Pandya
camera ACPI This change updates device tree to enable SSDT generation for world facing camera and user facing camera for ADLRVP. Also reverts DSDT changes related to both camera. TEST=Build and Boot aldrvp check i2c enumeration and output of media-ctl Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I39f82dc9eb91496d80479ae3f59ca5e03402a599 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-07-05mb/intel/adlrvp: Remove ASL code and enable dynamic SSDT creation for camera ↵Varshit B Pandya
ACPI This change updates device tree to enable SSDT generation for world facing camera and user facing camera for ADLRVP. Also reverts DSDT changes related to both camera. TEST=Build and Boot aldrvp check i2c enumeration and output of media-ctl Compared SSDT with this patch against DSDT without this patch, they are same Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I08834bbcf80dc46737de07f69a2402ed6bf93d4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-07-05mb/google/dedede: Fix the pointer/address used in memcpyKarthikeyan Ramasubramanian
The caller is already passing the address to the required LTE reset and enable GPIO. During memcpy, the address to that pointer is used which will lead to copying undefined data. Fix the pointer/address used in memcpy. BUG=None BRANCH=dedede TEST=Build Kracko, Drawcia and Metaknight mainboards which use this function. Change-Id: I79d6d9af03acd59ab5e1cd7df97bf451011dfeaa Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Found-by: Coverity CID 1458053, 1458054. Reviewed-on: https://review.coreboot.org/c/coreboot/+/56046 Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-05timestamp,vc/google/chromeos/cr50: Add timestamp for enable updateRaul E Rangel
cr50_enable_update takes a non-trivial amount of time. TEST=Boot guybrush and dump timestamps 553:started TPM enable update 3,615,156 (444) 554:finished TPM enable update 3,632,810 (17,654) Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I522d0638a4a6ae9624965e49b47bca8743c3206c Reviewed-on: https://review.coreboot.org/c/coreboot/+/55402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-05device/resource_allocator_v4: Only highlight log message with ===Paul Menzel
Currently, four instead of three = are used in one log message. Done reading resources. ==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) === === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) === As the ending mark is `===` change it to `===` in the beginning. Done reading resources. === Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) === === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) === Change-Id: I40c3876e1f895b7f9771479234c9529cca2b97ba Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56045 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-05sb/intel/i82801gx: Prepare for x86_64Arthur Heymans
Do the usual int conversions. TESTED: BUILD_TIMELESS=1 produces identical image on foxconn/g41m. Change-Id: Idebfe4669854b307bee653df6d93e46ae3f39dec Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56020 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-05nb/intel/x4x: Use write32p and read32pArthur Heymans
This removes the need for type conversions all over the place. Change-Id: I633a453aff17f1cbbe06b60e3efb67661733d06c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56029 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-05nb/intel/x4x: Prepare for x86_64 supportArthur Heymans
Do the usual type conversions TESTED: Same image with BUILD_TIMELESS=1 Change-Id: Id44eeb7660d0b521a326a5b981c04c16cf0a6f84 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56019 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-05cpu/intel/car/p4-netburst: Prepare for x86_64Arthur Heymans
Use proper car symbols. Change-Id: I169fd6020e5b81da66dbe4fe83ba446eedc882e9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56018 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-05mb/intel/adlrvp: Update the FIVR configurationsV Sowmya
This patch sets the optimized FIVR configuration for adlrvp cutomized based on the pnp measurements to achieve the better power savings in sleep states. * Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3, S4, S5 states. * Update the supported voltage states. * Set the ICC max to 500mA for v1p05 and vnn. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I83e6910502d5cf9d4c26fa581272f59ac483ae19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-07-05soc/intel/alderlake: Add support to update the FIVR configsV Sowmya
This patch adds the supports to update the optimal FIVR configurations for external voltage rails via devicetree. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: Icf6c74bda5a167abf63938ebed6affc6b31c76f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55702 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-05mb/google/brya/brya0: Enable CrashlogTim Wawrzynczak
brya0 is a reference and development platform, therefore it would be helpful to have Crashlog enabled. Change-Id: I936e73e808e0a05e8b7822cddbb5ee3fa7dee13e Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-07-05mb/google/brya: Add HANG_DETECT host event to EC S0ix wake maskTim Wawrzynczak
The brya EC supports S0ix hang detection, but it was not enabled in coreboot as well, masking that event out of S0ix, therefore add it in to the EC S0ix wake mask. TEST=After EC prints "Warning: Detected sleep hang! Waking host up!", the host actually wakes up Change-Id: I2c699114abcd9a045a41858c731e4b6fe99d3000 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-07-05mb/google/dedede/var/cret: Disable SDCard controllerDtrain Hsu
Cret doesn't support SDCard. Disable SDCard contorller for Cret. BUG=b:191232222 TEST=Build and boot to check lspci Cq-Depend: chromium:2993724 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I889f0545883aa75813dd91dc3e6a4dcfc246687f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-05soc/intel/alderlake: Correct Bus and Device of Touch Host ControllerVarshit B Pandya
Correct Bus and Device for THC0 and THC1 Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I41858ea156c8258ea0e7be9e2f67fb0e24144c80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-07-04supermicro/x11: enable COMB via LPCAlexander Couzens
Allow to use the 2nd COM port of the AST2400 which can be also used via IPMI/serial-over-lan. Change-Id: I6f9c85b1f5428d3c3acf7a2f20296134c4611b1e Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-07-02soc/amd/common/espi: Fix debug message log levelRaul E Rangel
BUG=none TEST=Boot with CONSOLE_LOGLEVEL_3 and no longer see the message printed. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0bdb92f547ceb8be624521211f4a3b94a91dae22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-02drivers/intel/fsp2: Change FSPS returned message to INFORaul E Rangel
This message is not an error, but just informational. BUG=none TEST=Boot with CONSOLE_LOGLEVEL_3 and no longer see it printed Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifb64edbe029cafa82aec99aa50de47f51cd50dce Reviewed-on: https://review.coreboot.org/c/coreboot/+/55971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-02soc/amd/common/block/cpu: Cache the uCode to avoid multiple SPI readsRaul E Rangel
We are currently reading the uCode for each CPU. This is unnecessary since the uCode never changes. BUG=b:177909625 TEST=Boot guybrush and see "microcode: being updated to patch id" for each CPU. I no longer see CBFS access for each CPU. This drops device initialization time by 32 ms. Also boot Ezkinil and verify microcode was also updated. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I98b9d4ce8290a1f08063176809e903e671663208 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-02soc/amd/cezanne: Enable SPI DMA supportRaul E Rangel
Start using the custom boot device. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4ae7272677f563e8827ba154fe5177c8c01155c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-02soc/amd/common/block/lpc: Add custom SPI DMA boot deviceRaul E Rangel
This is a copy of mmap_boot.c and mem_rdev_ro_ops. I split it up so it was easier to review. The next patches will add support for the SPI DMA controller. This will provide a minor speed up vs using mmap reads. It will also provide the facilities to perform asynchronous SPI loading. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Id26e2a69601d0f31e256d0010008904a447c8e21 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-02arch/x86: Add X86_CUSTOM_BOOTMEDIARaul E Rangel
In order to disable X86_TOP4G_BOOTMEDIA_MAP it requires the definition to be overridden. This makes it a little less ergonomic to use. Instead introduce the inverse option that can be selected. I chose to leave X86_TOP4G_BOOTMEDIA_MAP since it keeps the Makefiles simple. BUG=b:179699789 TEST=none Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I65bbc118bde88687a7d7749c87acf1cbdc56a269 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-02cpu/qemu-x86: Increase heap sizeAngel Pons
On x86_64, the default heap size is too small when using 32 CPUs. Change-Id: Ib4f770a7a54d975d213b2456cc7d1ed9151cb6f9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-07-02src: Consolidate x86_64 support KconfigAngel Pons
Introduce `USE_EXP_X86_64_SUPPORT` in `src/arch/x86/Kconfig` and guard it with `HAVE_EXP_X86_64_SUPPORT`. Replace the per-CPU implementations of the same functionality with the newly-added Kconfig options. Update documentation and the config file for QEMU accordingly. Change-Id: I550216fd2a8323342d6b605306b0b95ffd5dcd1c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-07-02src: Introduce `ARCH_ALL_STAGES_X86`Angel Pons
Introduce the `ARCH_ALL_STAGES_X86` Kconfig symbol to automatically select the per-stage arch options. Subsequent commits will leverage this to allow choosing between 32-bit and 64-bit coreboot where all stages are x86. AMD Picasso and AMD Cezanne are the only exceptions to this rule: they disable `ARCH_ALL_STAGES_X86` and explicitly set the per-stage arch options accordingly. Change-Id: Ia2ddbae8c0dfb5301352d725032f6ebd370428c9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-07-02mb/google/dedede/var/magolor: Enable G2 touchscreen for magmaTyler Wang
Add G2 touchscreen support for magma. BUG=b:189852808 TEST=Build and verify that touchscreen works. Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I3e032bff7f3e97f54f3e544035e862058ea0dbfc Reviewed-on: https://review.coreboot.org/c/coreboot/+/55976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2021-07-02soc/intel/common/block/cse: Add ME EOP timestampsTim Wawrzynczak
BUG=b:191362590 TEST=on brya, cbmem -t: 942:before sending EOP to ME 2,628,446 (5,879) 943:after sending EOP to ME 2,631,177 (2,730) Change-Id: I0376610c5cbae7df1bf1a927b3bc99b1022de4cb Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-07-02mb/google/volteer/variants/eldrid: Include SPD for MT40A512M16TB-062E:RMark Hsieh
Add SPD support to eldrid for DDR4 memory part MT40A512M16TB-062E:R. Eldrid should use DRAM_ID strap ID 0 (0000) on SKUs populated with MT40A512M16TB-062E:R DDR4 memory parts. BUG=b:192380070 TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds successfully. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I4d07727c9c41bf494fbef373abce0ac1fc65c316 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55983 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-02soc/intel/alderlake: Add USB TCSS enablementBernardo Perez Priego
In order to detect USB Type C device port as Super Speed, we need to set corresponding bit in UPD UsbTcPortEn. This patch will use device path to determine which port should be enabled. BUG=b:184324979 Test=Boot board, USB Type C must be functional and operate at Super Speed. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I7da63f21d51889a888699540f780cb26b480c26d Reviewed-on: https://review.coreboot.org/c/coreboot/+/55361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-02selfboot: Add support for selfload in romstageShelley Chen
Since bootmem is not available in romstage, calls to bootmem APIs need to be compile-time eliminated in order to avoid linker error: undefined reference to `bootmem_region_targets_type BUG=None BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_HEROBRINE -x -a -B cherry-picked on top of CB:49392 and verified successful compilation. Change-Id: I8dfa2f2079a9a2859114c53c22bf7ef466ac2ad9 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55865 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-01drivers/intel/gma: Move extended VBT just below opregionMaulik V Vaghela
Currently the flow for opregion init is as below: 1. Allocate memory for opregion first (cbmem_add(opregion)) 2. Check if VBT size > 6 KiB (this requires extended VBT support) 3. In case of extended VBT requirement, we allocate another chunk of memory which is equal to size of VBT (cbmem_add(extended_vbt)) 4. Pass physical address pointer to OS via RVDA We can optimize the above flow to allocate single chunk of memory by checking VBT size in earlier step. The new optimized flow for opregion init is as below: 1. Check if VBT size > 6 KiB (this requires extended VBT support) 2. In case of extended VBT requirement, total memory to be allocated is calculated as sizeof(opregion) + sizeof (extended_vbt) In case where VBT size is < 6 KiB, total memory requirement would be equal to sizeof(opregion) 3. Based on above calculation, allocate single chunk of memory based on total size. This will also be helpful for the case of virtualization where guest users don't have access to physical address and when it needs relative address of VBT compared to absolute address. In case of opregion 2.1 spec, we need to pass relative address of VBT from opregion base in RVDA. This optimization will help in meeting this requirement since relative address of extended VBT is easy to get. This change will ensure that it meets opregion specification requirement and will be compatible with future versions as well. BUG=b:190019970 BRANCH=None TEST=check the address of extended VBT region and address is coming correctly. Change-Id: Ic0e255df63145409096b0b9312c6c51c05f49931 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01mb/google/hatch/scout: update gpios and device treeJeff Chase
Scout-specific changes to puff reference following bring-up - copy baseline changes from genesis - update GPIOs - update PCIe ports for TPUs - remove LSPCON - enable eMMC - disable touch I2C - enable uart BUG=b:187078663 TEST=boot scout BRANCH=none Signed-off-by: Jeff Chase <jnchase@google.com> Change-Id: Ic3cb9cf515ab7a4a0ebbee249644dd3f133d8735 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-14 04:54:03 +0000