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2024-05-23mb/amd/birman/display_card_type.h: add missing include guardsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaf4478814e672fb8cfae5ffc4fa89c475f5bb0b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82607 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-23soc/amd/phoenix/chip_opensil.h: add missing include guardsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iba17d44772333ed59e3fdde1443a1862bae8e32f Reviewed-on: https://review.coreboot.org/c/coreboot/+/82606 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-05-23mb/google/brya: Add romstage early graphics for nissaRonak Kanabar
1) Add all changes needed for early graphics 2) select MAINBOARD_USE_EARLY_LIBGFXINIT for nissa The InnoLux (N156HCN-EBA C7) panel is used for the device tree. BUG=b:296433986 TEST=On-screen text message seen during MRC training on Craask Logs: [NOTE ] MRC: no data in 'RW_MRC_CACHE' [SPEW ] bootmode is set to: 0 [0.171409] DP PHY mode status not complete [0.175509] DP PHY mode status not complete [0.179799] DP PHY mode status not complete [0.184087] DP PHY mode status not complete [0.188376] DP PHY mode status not complete [0.192665] DP PHY mode status not complete [0.196954] DP PHY mode status not complete [0.201243] DP PHY mode status not complete [0.205532] DP PHY mode status not complete [0.209821] DP PHY mode status not complete [0.214110] DP PHY mode status not complete [0.218397] DP PHY mode status not complete [INFO ] Informing user on-display of memory training. Change-Id: I33cfc5d1f8c25c344e598befd21c50a78a65275a Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78932 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-23mb/cwwk: Add CWWK CW-ADL-4L-V1.0 boardBrandon Weeks
This board is the CWWK variant based upon Alder Lake with 4 2.5 GbE ports, similar boards are available in other port configurations. As a low cost, relatively high performance board with 4 NICs, it is well suited for networking or 'homelab' tasks. CPU: Intel N100 or N350 Memory: DDR5-4800 SODIMM (max 16 GB) NIC: 4x Intel I226-V 2.5 GbE Expansion: - M.2 2230 E key - M.2 2280 M key - USB 2.0 header - Fan header External ports: - DC power - 4x Ethernet - Display Port - HDMI - 4x USB 2.0 - Micro SD Working: - Boots Debian 12 with SeaBIOS and EDK II payloads - Serial port - External USB ports - DisplayPort / HDMI - 4x Intel I226 2.5 GbE NICs - M.2 ports - Micro SD slot - ACPI S3 Not working / not tested: - Fan (ITE IT8613E) - Audio - S0ix - Internal USB ports VBT extracted from vendor UEFI firmware version ADLN 0.01 x64 (04/04/2023 11:42:38). Change-Id: Ice9174d95c10afc6a22ddd15fb3be4fa38d329be Signed-off-by: Brandon Weeks <me@brandonweeks.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-23cpu/intel/model_206ax: Program Ivy Bridge defaults for MSR_PKGC_IRTLPatrick Rudolph
Ivy Bridge has lower latencies than Sandy Bridge has. Update MSRs MSR_PKGC_IRTL with values from BWG. Test: Lenovo X220 still boots. Change-Id: Ib307e3b191ba68e016cc348f82e2dccf1dc9ae16 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78609 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-05-23soc/intel/xeon_sp: Dump proximity domain info per typesShuo Liu
Some proximity domain info are type specifics, e.g. base/size/dev are effective for PD_TYPE_GENERIC_INITIATOR, but not for PD_TYPE_PROCESSOR. Dump info per their type. TEST=Build and boot on intel/archercity Change-Id: I7e722a0577bba954efba3e91cc152c758c001d68 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-05-23soc/intel/xeon_sp: Move proximity domain setting upShuo Liu
Move proximity domain setting up to ahead of attach_iio_stacks() so that proximity domain info could be ready before attach_iio_stacks()/create_xeonsp_domains(). For example in SPR, is_iio_cxl_stack_res() refers to proximity domain info, and it will be called in create_xeonsp_domains(). TEST=Build and boot on intel/archercity No significant boot log difference except for proximity domain dump info display are moved ahead (with correct contents). Change-Id: I594f0ec0c23e3b62c3bdd917ebf6e45be6e4069e Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82267 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-23mb/google/nissa/var/orisa: Generate RAM ID for Micron MT62F512M32D2DR-031 WT:BAmanda Huang
Add Micron part MT62F512M32D2DR-031 WT:B only for Orisa. DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) BUG=b:337178014 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I559ed817250c40795e6c613794d4f65c636f5fc5 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82586 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-22Revert "mb/google/rex/var/deku: Configure GPIO"Tony Huang
This reverts commit 7088257b1ab715e93506619727e3bf589ea688fb. Reason for revert: Intel suggest is NC only. No need to change anything that isn't broken. Change-Id: I976a85b35c69b03f1bc0ccd2bc7df923e47be815 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82572 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-22mb/prodrive/hermes: Tidy up hda_verb.cAngel Pons
Use the `AZALIA_PIN_CFG_NC(0)` macro instead of `0x411111f0` and tidy up some comments (align them and be consistent with capitalisation). Tested with BUILD_TIMELESS=1, prodrive/hermes remains identical. Change-Id: I1ff1197b1309fc0e5b978d6d36867a3f1a68c67c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-05-22mb/amd/birman/devicetree_phoenix_opensil: add USB PHY configFelix Held
Now that we also have the devicetree registers for the USB PHY config in the openSIL case, add the USB PHY config setting from the Phoenix with FSP devicetree. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3a0acbf1b9d705dbf09f4480eb35e71e587ddd44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-05-22soc/amd/phoenix/chip.h: add USB PHY configuration for openSILFelix Held
Add the USB PHY configuration structs for the openSIL case, so that those can be configured in the devicetree like in the FSP case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ied25e90859c4b1bc9b876bed3f3c46358ca36d32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82584 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-22mb/amd/birman/update_devicetree_phoenix_opensil: update DDI1 configFelix Held
Use the now common get_ddi1_type function to update the connector type of the DDI1 port to match the display output extension card plugged into the reference board. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7c51eab0d32e0a1708da415f690689a8ec38dcd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82583 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-22mb/amd/birman: factor out get_ddi1_typeFelix Held
Both port descriptor files used in the FSP case contain an identical get_ddi1_type implementation, so factor it out into a separate file. This will also allow using the same function in the openSIL case in a following patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6f5b75b9bdbdc67901d157079785c8fa2915bf0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/82582 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-22mb/amd/birman/devicetree_phoenix_opensil: add static DDI configurationFelix Held
Add a static DDI port configuration to the devicetree used in the Phoenix with openSIL case. The configuration is taken from the birman_ddi_descriptors array in port_descriptor_phoenix.c. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7b85b04114591f3e9da183019c98ca2cb08e59da Reviewed-on: https://review.coreboot.org/c/coreboot/+/82581 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-22soc/amd/phoenix/chip.h: add DDI configuration for openSILFelix Held
In the FSP case, the DDI descriptors aren't part of the devicetree and are instead retrieved in romstage by calling the mainboard's mainboard_get_dxio_ddi_descriptors function which allows updating the descriptors during romstage where the devicetree is static. In the openSIL case, the DDI configuration is first needed in ramstage, so we can put this info into the devicetree and update it if needed in ramstage. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3de12ff6af42e38751a3016efa313613677fa87a Reviewed-on: https://review.coreboot.org/c/coreboot/+/82580 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-05-22mb/amd/birman/devicetree_phoenix_opensil: remove unexpected '<'Felix Held
Remove the unexpected '<' char at the end of the comment about the PSPP policy config. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id821351ce3a7a2b7844d8e7478fa3de3227a7da9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82579 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-05-22soc/amd/phoenix/chipset_*.cb: remove TODOFelix Held
Remove the TODO to update the chipset devicetree for Phoenix, since this has already been done. When re-checking the chipset devicetree, I found conflicting information about the existence of the PCI bridge to an external PCIe port on bus 0 device 1 function 5, but after looking into this, I'm reasonably certain that it either doesn't exist or at least wouldn't be usable, so I won't add that one to the chipset devicetree. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8f0e1540ed45408e86186253d3982a7ba0065ac6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-05-22mb/intel/archercity_crb: Fix build for specific configurationsPatrick Rudolph
Guard OCP functions calls to allow builds without OCP drivers. Change-Id: Ie9a82387366a8bb3387bcba3ec7a4c7f0100f78c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-22mb/intel/mtlrvp: Include fw_config.c fileAnil Kumar
Update Makefile to include fw_config file for mtlrvp board. Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: Id41cd8b015a796f7a959ceccf85106a48d15ae35 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82559 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-22Revert "mb/google/brox: Update verb table to fix headset detection"Terry Cheong
This reverts commit f867c9c5473156617691d78350c362cd993bfcdd. The new verb table breaks external mic detection on brox. Revert and use old verb tables instead. BUG=b:330433089 BRANCH=main TEST=Verified headset on Brox When connected to audiojack in power_save state of legacy hda driver, headset is detected and audio is resumed. Change-Id: I0d8c092de6166b2c62f5ecc3deaf4960128e6106 Signed-off-by: Terry Cheong <htcheong@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82273 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-21mb/google/brya/var/nova: Add SOLDERDOWN supportKenneth Chan
Nova will use SOLDERDOWN. Add memory.c to override baseboard. Update dram id table for correct platform parameter. BUG=b:328711879 Change-Id: I6fbce991ef5ab9f0e6216ad1a5af73fcc1996a2a Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82474 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-21mb/google/brox/var/greenbayupoc: Update verb table from ALC256 to ALC236Wu Garen
On GreenbayPOC, HDA Codec used is ALC236, different with Brox (ALC256) Update to Realtek provided verb table for ALC236 audio codec. BUG=b:336967284 TEST=Verified headset and audio workable on DUT with "rec" and "aplay" command. Change-Id: I9fbe57a0acab20387754f6b6cb5705e34c1c149b Signed-off-by: Wu Garen <wu.garen@inventec.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82413 Reviewed-by: Ivan Chen <yulunchen@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-21lib/device_tree: Add some FDT helper functionsMaximilian Brune
This adds some helper functions for FDT, since more and more mainboards seem to need FDT nowadays. For example our QEMU boards need it in order to know how much RAM is available. Also all RISC-V boards in our tree need FDT. This also adds some tests in order to test said functions. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I2fb1d93c5b3e1cb2f7d9584db52bbce3767b63d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81081 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-21soc/intel/meteorlake: Add PsysPL2 configurationTony Huang
psys_pl2_watts is configured in SoC node of devicetree. Value represents Watts. BUG=b:320410462 BRANCH=firmware-rex-15709.B TEST=emerge-ovis coreboot Change-Id: I9c4d62b93fc751db9e0ea04e475acb8861a844f8 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-05-21mb/google/brya/var/bujia: Add devicetree based on schematicsShon Wang
Add devicetree settings per the schematic. Differences to gladios: 1. remove SD reader 2. remove EMMC setting 3. modify USB port distribution FRONT ------------------------------------------------------- | A3 A1 | | C0 A2 A0 | ------------------------------------------------------- BACK ------------------------------------------------------- | --------------- | | | TX25A | | ------------------------------------------------------- BUG=b:327549688 TEST= USE="-project_all project_bujia" emerge-brask coreboot Change-Id: Ia010e99c21e8d6088f6bb873f79dc19cadc9e455 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81447 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-05-20mb/prodrive/hermes/hda_verb.c: Refactor port B Vref cfgAngel Pons
Refactor the `get_port_b_vref_cfg()` function to only return the variable bits of the value. The NID itself is not connected, and the `misc` field in the verb conveys the Vref value. Change-Id: I5108f5339c5b002403a4e5339da6d52046c8bcbe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82395 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-17mb/google/dedede/var/kracko: Disable un-used C1 port by daughterboardRobert Chen
Probe C1 port in devicetree and disable un-used C1/A1 port by FW_CONFG. BUG=b:339534479 BRANCH=firmware-dedede-13606.B TEST=emerge-dedede coreboot chromeos-bootimage flash and check boot log on DUT. Change-Id: I944ff6f2fa712e7579ed1c9879f75835adc3ac4c Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82263 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-05-17mb/google/brask/var/nova: Remove unused retimerKenneth Chan
Remove unused setting for retimer. BUG=b:328711879 Change-Id: I48d8680d43a07aa3408dfbf5b25b568c2b51b343 Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82475 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-17cr50: Replace "cr50" to "GSC" in debug messagesTyler Wang
The cr50.c file currently prints "cr50" in debug messages no matter the system is using Cr50 or Ti50. This can be confusing for developers. This patch replaces "cr50" with "GSC" in debug messages. Using "GSC" makes the messages more clear and easier to search via `grep`. BUG=none TEST=Build and test on karis Change-Id: I21f66cf8b608ca4e4dc82d7a55a851ec996c8bb3 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82420 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2024-05-16mb/intel/beechnutcity_crb: Add GNR/SRF-SP 2S server board Beechnut CityShuo Liu
Beechnut City CRB is the 2 socket reference board for 6th Gen Xeon-SP SP SoCs (Granite Rapids SP and Sierra Forest SP). This patch initially sets the code set up as a compilation target with GNR N-1 FSP, and with basic feature supports (Integrated IO Controller (IIO) configuration, BMC, UART, HPET). TEST=Build on intel/beechnutcity CRB Change-Id: I3f6a0fb97b62baadb438fb9f11fdd78fccb3f89a Signed-off-by: Shuo Liu <shuo.liu@intel.com> Co-authored-by: Gang Chen <gang.c.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-05-16mb/intel/avenuecity_crb: Add GNR/SRF-AP 2S server board Avenue CityGang Chen
Avenue City CRB is the 2 socket reference board for 6th Gen Xeon-SP AP SoCs (Granite Rapids AP and Sierra Forest AP). This patch initially sets the code set up as a compilation target with GNR N-1 FSP, and with basic feature supports (Integrated IO Controller (IIO) configuration, BMC, UART, HPET). TEST=Build on intel/avenuecity CRB Change-Id: I64fdd5388aadf7732f6d3daa600c1455d3672a46 Signed-off-by: Gang Chen <gang.c.chen@intel.com> Co-authored-by: Shuo Liu <shuo.liu@intel.com> Co-authored-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-05-16soc/intel/xeon_sp/gnr: Add IIO config utilsGang Chen
Add IIO configuration utils shared in GNR boards to handle the complex IIO configuration settings. Change-Id: If7146761db6f73a0c4b0d31b010c0d30a42bf690 Signed-off-by: Gang Chen <gang.c.chen@intel.com> Co-authored-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-05-16chromeec/ec_acpi: Convert TK_DICTATE to ps2_action_keyAseda Aboagye
When support for the dictation key was added in commit f2782b8328d5 (acpigen_ps2_keybd: Add support for dictation key), I had failed to include this portion of the change in that commit. The top row key of `TK_DICTATE` needs to be converted to the ps2_action_key. This commit simply adds that mapping so that it can be translated. BUG=b:333101631 TEST=Flash DUT that emits a scancode for a dictation key, verify that it is mapped to KEY_DICTATE in the Linux kernel using `evtest`. Change-Id: I1be8c0a96931cca36e6bbbfa0be7d36c4cd93768 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82274 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-16mb/amd/birman/update_devicetree_phoenix_opensil: use common header fileFelix Held
Instead of including stub/mpio/chip.h, include chip/mpio/chip.h that will include the correct implementation to be able to use the same file with both the openSIL stub and the actual openSIL implementation glue code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaae26a0dfe0ba96842e72582c06f1b0b3f29871c Reviewed-on: https://review.coreboot.org/c/coreboot/+/82472 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-16mb/google/rex: Remove redundant VPU enablement codeSubrata Banik
This patch removes VPU enablement code that is no longer needed because the VPU is already enabled by default in the baseboard devicetree. BUG=b:332488817 TEST=Able to see VPU PCI device in lspci list after booting google/screebo to OS Change-Id: I94de92e970be1548068ed4e19309a95129f041ff Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82423 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-16mb/google/rex: Enable VPU device for Rex/Ovis baseboardSubrata Banik
This patch enables the Versatile Processing Unit (VPU) by default for Rex/Ovis baseboard. VPU is a dedicated AI engine that is included in the 14th generation "Meteor Lake" Core processors. The VPU is designed to efficiently run AI models directly on the system on chip (SoC). There is no power regression observed while keeping the VPU default enabled to run AI models natively hence, this patch enables the VPU by default. BUG=b:332488817 TEST=Able to see VPU PCI device in lspci (0:11:0) list after booting google/screebo to OS. Change-Id: I8b3521c8ec613b002f971eaf9d346927fe8cd656 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-16include/device/pci_ids.h: Update TWL device IDsSaurabh Mishra
Set lowercase hex format for IGD DIDs. BUG=b:326901448 TEST=Build tivviks and verify the IGD IDs. Change-Id: I1299512d1c48eba854fea2ec394cef40d44a87d7 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82414 Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-16mb/google/rex/var/baseboard/ovis: Support CPU power limits per variantTony Huang
There is no direct way to override CPU default power_limits for different SKUs. This CL add structure variant_get_soc_power_limit_config() for variants to define and configure the values of soc_power_limits_config for current CPU SKU. Variants can override these values i.e. pl1, pl2, psyspl2 in variant_devtree_update(). BUG=b:320410462 BRANCH=firmware-rex-15709.B TEST=FSP debug emerge-ovis coreboot intelfsp check overrides setting Change-Id: Ib60fa4e3fc502d0aeb0c94ad46ba5a55b4dd027c Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82199 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-16mb/google/brask/var/bujia: Update gpio tableShon Wang
Based on latest schematic to update the gpio table. BUG=b:327549688 TEST= USE="-project_all project_bujia" emerge-brask coreboot Change-Id: I3d01e3b9eaef72d9e143f5163ee49d8c8f455b5f Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82412 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-15cpu/x86/pae/pgtbl.c: remove dead paging_identity_map_addr()Krystian Hebel
This function had roughly the same use (except PAT) as part of memset_pae(), however the latter is able to make use of PAE and map physical memory located above 4 GB. Remove paging_identity_map_addr() to avoid semi-duplicated code. The function has been unused since CB:26745. Change-Id: I7a4ebd84a6f5d222c3b2c6c6e3d26d6464cf01b8 Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82248 Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-15mb/amd/birman: add function to update MPIO config in devicetreeFelix Held
Phoenix 2 has less PCIe lanes than Phoenix, so some of the lane end numbers need to be adjusted to take that into account. When the Kconfig options WLAN01 or WWAN01 are set, either the WLAN or the WWAN card uses both PICe lanes that are available for those two devices, so the MPIO descriptor information the devicetree needs to be updated accordingly and the bridge to the PCIe port that doesn't have any lane left needs to be disabled. Two other PCIe devices will be disabled when the corresponding Kconfig options ENABLE_EVAL_CARD and DISABLE_DT_M2 have the value that results in the device being disabled via some GPIO driven by the EC. Since the code is specific to the openSIL case, only include it in the build in the CONFIG_BOARD_AMD_BIRMAN_PHOENIX_OPENSIL case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I23c14cc03980ea1e39f7e5aec551b975c237e487 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-05-15mb/amd/birman/devicetree_phoenix_opensil: add stub MPIO chipsFelix Held
Add the stub MPIO chips that contain the PCIe engine configuration for the external PCIe interfaces to the devicetree. Birman's port_descriptors_phoenix.c was used as a reference. The static configuration in the devicetree assumes that the default WLAN0_WWAN0 is selected; for the other cases we'll still need to fix up things accordingly in the mutable devicetree. The WLAN01 and WWAN01 cases still need to be handled in a follow-up patch. Since openSIL currently doesn't use the info from the gpio_group struct element, but deasserts both PCIe reset pins GPIO 26 and 27, the gpio_group isn't specified in the chip configuration in the devicetree. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icabe60322d46c1195284dd77ec39f9d143e3d2cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/81101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-05-15mb/google/brya: Create orisa variantEricKY Cheng
Create the orisa variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:337178014 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_ORISA Change-Id: I0cd8d763ffd8864b455a7f8909e95f6aee8bb23e Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-14soc/intel/xeon_sp: Add Granite Rapids initial codesShuo Liu
coreboot GNR (Granite Rapids) is a FSP 2.4 based, no-PCH, single IO-APIC Xeon-SP platform. The same set of codes is also used for SRF (Sierra Forest) SoC. This patch initially sets the code set up as a build target with Granite Rapids N-1 FSP (src/vc/intel/fsp/fsp2_0/graniterapids). 1. All register definitions are forked from SPR (Sapphire Rapids) and EBG (Emmitsburg PCH)'s codes are reused. 2. src/soc/intel/xeon_sp/chip_gen6.c is newly added as chip common codes for 6th Gen Xeon-SP SoC (Granite Rapids) and later. Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Signed-off-by: Shuo Liu <shuo.liu@intel.com> Co-authored-by: Gang Chen <gang.c.chen@intel.com> Co-authored-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-05-14soc/intel/common: Add RPL tracehub supportAshish Kumar Mishra
Add PCI ID for RPL tracehub and update the PCI ID in the pci_device_ids[] in tracehub.c. Reference: Raptor Lake External Design Specification Volume 1 (640555) BUG=None TEST=Verified on brox Change-Id: I5d5c6c8ff44bcb5a7bbbd3e27a1577c169ecd6a9 Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-05-14soc/intel/common: Add Panther Lake DIDsSaurabh Mishra
Reference: Panther Lake External Design Specification Volume 0.51 (815002) BUG=b:329787286 TEST=verified on Panther Lake Simics Platform. Change-Id: I941d6e1c8a697234b8e64a2523e60587897d7f7a Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81848 Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-14soc/intel: Add Panther Lake PCIE device IDsSaurabh Mishra
Add Panther Lake specific CPU and PCIE device IDs Reference: Panther Lake External Design Specification Volume 0.51 (815002) BUG=b:329787286 TEST=verified on Panther Lake Simics Platform. Change-Id: I82f47b6077e28a01f34c59b7e7697323b3d5f990 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81849 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-14soc/intel/common: Add Lunar Lake IAA and TBTRP3 device IDsSaurabh Mishra
Reference: Lunar Lake External Design Specification Volume 1 (734362) BUG=b:329787286 TEST=verified on Lunar Lake RVP board (lnlrvp). Change-Id: I92b65c946682387cbb841d558c6f0a7cb0fcd4ac Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81850 Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-14mb/google/nissa/var/glassway: Set VccIn Aux Imon IccMax to 25 AFrank Chu
Iccmax of VccIn_Aux is 25A with MBVR design. BUG=b:330117043 BRANCH=firmware-nissa-15217.B TEST=Local build successfully and boot to OOBE normally. Change-Id: I105dc9df53c624fd7fc697408a1097e023a3cd68 Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81445 Reviewed-by: Simon Yang <simon1.yang@intel.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-14mb/google/nissa/var/quandiso: Add stop pin for G2 touchscreenRobert Chen
Add stop pin control for G2 touchscreen refer to G7500_Datasheet_Ver.1.2. BUG=b:335803573 TEST=build and verified touchscreen works normally Change-Id: I4f085c67c0cdb8b9ca3ff03993fda69cca6319ef Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82254 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-14mb/google/brox/var/greenbayupoc: Add vbt from broxEren Peng
Copy the data.vbt from brox to greenbayupoc BUG=b:326413034 TEST=emerge-brox coreboot chromeos-bootimage, flash and boot on DUT Change-Id: I1e8101519ab2ecbb4654c20485fbe83c90656e4d Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82108 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-14mb/google/brox/var/greenbayupoc: Update devicetree and gpio settingsEren Peng
Based on latest schematics GREENBAY_0412.SCH update the gpio and devicetree settings. BUG=b:326413034 TEST=emerge-brox coreboot chromeos-bootimage, flash and boot on DUT Cq-Depend:chrome-internal:7218819 Change-Id: I59f25b8abb7dd8a2dff7ff567b231bddc9db8455 Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-05-14arch/x86: Remove unused `protected_mode_jump` APISubrata Banik
This patch removes all instances of the `protected_mode_jump` API and its associated header file. The API is no longer used by any code within the tree. BUG=b:332759882 TEST=Built and booted 64-bit coreboot with 32-bit payload successfully. Change-Id: I3eb31b09c92512338ccc540f60289960bd6bf439 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82372 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-14x86: Switch to protected_mode_call_1arg for correct argument passingSubrata Banik
The payload execution process has been updated to utilize protected_mode_call_1arg in order to guarantee proper handling of function parameters. The previous use of protected_mode_jump with a "jmp" instruction did not allow for proper stack setup for argument passing, as the calling convention was not aligned with the System V ABI calling convention. This patch ensures that calling into the libpayload entry point using protected mode is now aligned with the System V ABI calling convention. This resolves an issue where retrieving the "pointer to coreboot tables" from within the libpayload entry point was failing due to incorrect argument passing. BUG=b:332759882 TEST=Built and booted 64-bit coreboot with 32-bit payload successfully. Change-Id: Ibd522544ad1e9deed6a11015b0c0e95265bda8eb Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82294 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-05-14mb/google/nissa/var/sundance: Update HID offset to 0x01 for Focal touchpadLeo Chou
Currently the Focal touchpad does not work. Based on the Focal touchpad vendor, upadet the HID descriptor address from 0x20 to 0x01. BUG=b:339756281 TEST=Build and check Focal touchpad can work. Change-Id: I383ad907e6a23c34ab1bd0f6594a87564e21181d Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-14mb/google/dedede/var/pirika: Add SPD IDs for two new memory partsDaniel_Peng
Support Memory of Micron MT53E512M32D1NP-046 WT:B and Hynix H54G46CYRBX267 in mem_parts_used list, and generate SPD ID for these parts. DRAM Part Name ID to assign MT53E512M32D1NP-046 WT:B 0 (0000) H54G46CYRBX267 0 (0000) BUG=b:337173071 BRANCH=firmware-dedede-13606.B TEST=Run command "go run \ ./util/spd_tools/src/part_id_gen/part_id_gen.go \ JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ \ src/mainboard/google/dedede/variants/pirika/memory/\ mem_parts_used.txt" Change-Id: I9b1a2a622d0ca1298671b1da58beacc1b4244769 Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82094 Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-13mb/asus/p8z77-m: Support AC97 front audio panelKeith Hui
Add a nvram option for front audio panel type. If it is set to AC97, reprogram front line out and microphone pins to match vendor firmware under same configuration. TEST=On asus/p8z77-m housed in an AOpen H340D case with an AC97 front audio panel, front panel line out port is now available as headphone port in Fedora 39 with this patch applied and option set correctly. And it works. Without the patch (or with this option set to HD Audio), front audio ports are completely inoperable. Change-Id: I39ccf066d87c5744a697599861719182768e0728 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-05-13nb/intel/haswell: Use <device/dram/ddr3.h>Elyes Haouas
Change-Id: I353ceb7ab5ec0c82f5e717c856ad7934fcbd03b6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82355 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-13mb/google/rambi: Use <device/dram/ddr3.h>Elyes Haouas
Change-Id: I3aa669042908b92d7b270df077a352e197071780 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82354 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-13soc/intel/xeon_sp: Use <spd.h>Elyes Haouas
Change-Id: Ib86df42c74474ab6d0bd389073c36ca0761748af Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-05-13mb/intel/{harcuvar,kunimitsu}: Use <spd.h> and <dram/ddr{3,4}.h>Elyes Haouas
Change-Id: I2d73f7815e83e8bf0c6d0a402d32bc99c32c7d90 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82243 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-13mb/google/{eve,glados}: Use <spd.h> and <dram/ddr3.h>Elyes Haouas
Change-Id: I48b833a3727d4b7d7c50371dbe8f090983d80e36 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-13soc/amd/common/block/psp: Comment unused symbolElyes Haouas
This adds a comment for unused AMD_FWM_POSITION_20000_DEFAULT. Change-Id: Id8369f488893e7e5b2e7e7126d1b53199ed1aa77 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-05-13mb/google/brya/var/riven: Copy VBT data file from nivviksDavid Wu
Add data.vbt file for riven recovery image. Select INTEL_GMA_HAVE_VBT for riven as it has a VBT file now. The VBT file is copied from the nivviks reference board. BUG=b:337169542 TEST=build pass Change-Id: I499c1b3e61581483a1640375270f7707ebe8deeb Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82269 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-13cpu/x86/pae/pgtbl.c: remove dead map_2M_page()Krystian Hebel
This function isn't used anywhere. It probably wouldn't work with current coreboot anyway, as it identity mapped lower 2GB of RAM, while ramstage is run from CBMEM, which is usually just below top of memory. It was last used in K8 code that is long gone. Change-Id: I97e2830f381181d7f21ab5f6d4c544066c15b08c Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
2024-05-13mb/google/brox: Disable c1 state auto-demotionAshish Kumar Mishra
Disable c1 state auto-demotion support for brox BUG=None BRANCH=None TEST=Boot brox and verify in fsp debug logs Change-Id: I18d40cd721d46fce4702cf1a943583cd41c03cf4 Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82104 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-12soc/intel/lunarlake: Support stepping A0_2Saurabh Mishra
Details: - Add support for new Lunar Lake MCH ID 0x6410 - Add new CPU id 0xb06d1 Reference: Lunar Lake External Design Specification Volume 1 (734362) TEST=Build, boot the system and verfiy MCH-ID prints in bootblock stage. Below prints verified on Lunar Lake RVP board (lnlrvp). [DEBUG] MCH: device id 6410 (rev 02) is LunarLake M Change-Id: I976d7f269485633d835d204afa224736d71baaa8 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81847 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-12soc/intel/common: Add Lunar Lake CNVI device IDsSaurabh Mishra
Without this patch, ACPI SSDT does not supports and lists CNVW. With this patch, verified "CNVW" in ACPI SSDT listing. Scope (\_SB.PCI0) { Device (CNVW) { Name (_ADR, 0x0000000000140003) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } } } Reference: Lunar Lake External Design Specification Volume 1 (734362) BUG=b:329787286 TEST=verified on Lunar Lake RVP board (lnlrvp). Change-Id: I5a0a3fbc9f43a6a573e33fcf3901055e10faaed1 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81846 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-12mb/google/rex/var/deku: Correct FVM Itrip for GT VR domainTony Huang
Previous CL misspelling VR domain to IA not GT which cause FVM Itrip(GT) not set correctly. This CL corrects it to VR_DOMIAN_GT and confirm FVM Itrip(GT) has set to 54. BUG=b:320410462 BRANCH=firmware-rex-15709.B TEST= FSP debug emerge-ovis coreboot intel-mtlfsp check overrides setting IccLimit[1] = 216 ( 1/4 A) Change-Id: I99df053869aa11b7c82aa0b7f7ec0acf73467a76 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-05-12vc/amd/opensil: introduce common mpio/chip.h header fileFelix Held
The chip drivers in the devicetree use the path where the corresponding chip.h file resides both to include this chip.h file in the static.c generated by util/sconfig from the devicetree and also for the names of the chip config and chip ops struct. To be able to build a SoC using either the MPIO chip driver from the openSIL stub or from the actual openSIL glue code without needing different devicetree files for the different cases, introduce a common MPIO chip.h file that then includes the correct MPIO header file. The chip config and ops structures also need to be renamed to take this change into account. Thanks to Matt for pointing out how to make the path to the actual MPIO chip.h file configurable via a Kconfig setting. This allows overriding this path from site-local without the need to have any reference to site-local in the upstream code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iead97d1727569ec0d23a2b9c4fd96daff4bebcf6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82262 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-12vc/amd/opensil/*/mpio/chip.h: add missing include guardsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idef3b661b1cf3008373e61e0760a7dd3b9e9fede Reviewed-on: https://review.coreboot.org/c/coreboot/+/82261 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-12mb/protectli/vault_cml: use combo v1/v2 FSPMichał Kopeć
Also switch configs to use combo v1/v2 FSP The reason for this change is to simplify configuration - instead of multiple targets for VP4630 and VP4650 or VP4670, it's now possible to have one target covering all VP46x0. Change-Id: I1a6f6e873e4ec35b9777dc17c0495151348d1d88 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81963 Reviewed-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-12mb/google/brox/var/greenbayupoc: Configure board for SODIMM useEren Peng
Configure SODIMM settings for greenbayupoc. The SODIMM settings are copied from mainboard/google/brya/variants/baseboard/brask/memory.c. BUG=b:336955026, b:332230842 TEST=emerge-brox coreboot chromeos-bootimage, flash and boot to OS using Hynix HMAG56EXNSA051N 4G and Micron MTA8AFT1G64HZ-3G2R1 8G SODIMM. Change-Id: I1552cadfa81c48fe561947ded078bcca2e6bc6ad Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82085 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-05-12mb/google/brya/var/riven: Generate SPD ID for supported partsDavid Wu
Add supported memory parts in mem_parts_used.txt, and generate SPD id for these parts. 1. MT62F1G32D4DR-031 WT:B (Mircon) 2. MT62F512M32D2DR-031 WT:B (Mircon) 3. H9JCNNNBK3MLYR-N6E (Hynix) 4. K3LKLKL0EM-MGCN (Samsung) 5. K3LKBKB0BM-MGCP (Samsung) 6. H9JCNNNCP3MLYR-N6E (Hynix) BUG=b:337169542 TEST=build pass Change-Id: I0ff3b1e14fb8bb87d8fc9cbe0e177a5bcedef08c Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82255 Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-05-11include/efi: Override EFIAPI macro for x86_64Subrata Banik
This commit overrides the EFIAPI macro definition when using FSP on x86_64 to ensure the correct calling convention is used. On i386, there is no side-effect since the C calling convention used by coreboot and FSP are the same. However, on x86_64, FSP/UEFI uses the Microsoft x64 calling convention while coreboot uses the System V AMD64 ABI. This change resolves this incompatibility by setting EFIAPI to attribute((ms_abi)) on x86_64 when using FSP. TEST=Able to build google/rex0 in 32-bit and 64-bit mode. Change-Id: Ifae910be66d550af04cce5136d186a7e9dd085b3 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82266 Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-11driver/intel/fsp2_0: Update soc_binding.h for coreboot compatibilitySubrata Banik
Included <efi/efi_datatype.h> to address coreboot style header definitions rather using EDK2 header <Base.h>. TEST=Able to build google/rex0. Change-Id: I66559872c8d137d1baef5860fb98cad2a5214368 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82265 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-10drivers/mipi: Update init code for IVO_T109NW41 panelZhongtian Wu
1. VCOM OTP burning, initial code Settings can be deleted, B6h 2. Fine-tune VGH, VGL, VGHO, VGLO voltage, B1h PA6 3. Boot CLK performance change: add E9h, C7h, E9h 4. Extend TFT life: D5h PA25~PA32,D3h PA1~PA5; 5. Gamma optimization: E0h 6. Improve picture quality, add EQ: D2h to CLK 7. Press mura to improve and modify B1h PA4 and PA5 BUG=b:320892589 TEST=boot ciri with IVO_T109NW41 panel and see firmware screen Change-Id: I13421660faba9ef8e33a51c5ab28aeb1388aff40 Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82240 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
2024-05-09include/spd.h: Add SPD_MEMORY_TYPE_LPDDR3_INTEL into spd_memory_typeElyes Haouas
Change-Id: I694af163fb530be49561e74e74d9c08e04986a44 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82223 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-09include/spd.h: Add new spd_memory_type valuesElyes Haouas
This adds LPDDR4X, DDR5,LPDDR5, DDR5_NVDIMM_P and LPDDR5X, according to revision of JESD400-5A.01, January 2023. Change-Id: I15802da03dc748c0e7f6b035fed25371afe3eed4 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82217 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-09arch/arm64/Makefile.mk: Switch linker to GNU GCCYidi Lin
TF-A migrates the default choice of linker to GCC in order to enable LTO. Change BL31_LDFLAGS from `--emit-relocs` to '-Wl,--emit-relocs', so that GCC is able to pass `--emit-relocs` to the linker. [1]: https://review.trustedfirmware.org/c/26703 BUG=b:338420310 TEST=emerge-geralt coreboot TEST=./util/abuild/abuild -t google/geralt -b geralt -a TEST=./util/abuild/abuild -t google/oak -b elm -a Change-Id: I65b96aaa052138592a0f57230e1140a1bb2f07ac Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82189 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-09mb/google/brox: Sending End of Post (EOP) asynchronouslyKarthikeyan Ramasubramanian
Currently EOP message is sent to CSE late in the boot flow. Instead send it asynchronously to save ~10 ms in boot time. BUG=b:337330958 TEST=Build Brox BIOS Image and boot to OS. Change-Id: I229d16a5dcd072958db3f59a9c364bf7508b3047 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-09arch/arm64/Makefile.mk: Unset toolchain vars for BL31Yidi Lin
This change is for upcoming arm-trusted uprev commit. TF-A refactors the toolchain detection in [1][2]. After that `AR`, `CC`, `LD` and other toolchain variables have precedence over `CROSS_COMPILE`. Since ChromeOS build system also sets those toolchain variables when building coreboot, it results that TF-A uses CrOS GCC instead of coreboot SDK. It needs to unset those variables in order to make `CROSS_COMPILE` effective. TF-A upstream changes the default linker from BFD to GCC in [3]. Therefore, temporarily overriding LD as $(LD_arm64} to fix the below build error. aarch64-elf-gcc: error: unrecognized command-line option '--emit-relocs' In addition, TF-A wrapped LD with single quotes to solve Windows path issue[4]. On MT8173 platform, `--fix-cortex-a53-843419` is appended to $(LD_arm64} for ERRATA_A53_843419. It results in the below build error. /bin/sh: 1: --fix-cortex-a53-843419: not found Since `--fix-cortex-a53-843419` is never passed to TF-A, simply extract the LD command from $(LD_arm64) by $(word 1, $(LD_arm64)). [1]: https://review.trustedfirmware.org/c/24921 [2]: https://review.trustedfirmware.org/c/25333 [3]: https://review.trustedfirmware.org/c/26703 [4]: https://review.trustedfirmware.org/c/26737 BUG=b:338420310 TEST=emerge-geralt coreboot TEST=./util/abuild/abuild -t google/geralt -b geralt -a -x TEST=./util/abuild/abuild -t google/oak -b elm -a -x TEST=./util/abuild/abuild -t google/cherry -x -a Change-Id: Ieac9f96e81e574b87e20cd2df335c36abcb8bb5c Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-09soc/mediatek/mt8188: devapc: set devapc permission for MFGFei Yan
In order to support SVP Feature, EMI-MPU has to give MFG permissions to allow MFG to access secure buffer by secure read and write. Currently MFG is in domain 0, which include many other masters. Move MFG to domain 6. Set MFG remap, so that MFG can switch to protect mode by MFG register. Change MFG permission from NO_PROTECTION to SEC_RW_ONLY for domain 0, so that only AP in secure mode can access MFG_S_S-2 and MFG_S_S-5. BUG=b:313855815 TEST=emerge-geralt coreboot Change-Id: Ic6fb7d85bf9d4d92946a045a274b274abc440e1d Signed-off-by: Fei Yan <fei.yan@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-08mb/google/brox: Fix the pad reset config for WLAN Wake interruptKarthikeyan Ramasubramanian
Update the pad reset config for WLAN Interrupt from PLTRST to DEEP so that it can still act as a wake source during S3 suspend. BUG=b:336398012 TEST=Build Brox BIOS image and boot to OS. Suspend to S0ix & S3 and wakeup successfully using Wake on WLAN. 268 | 2024-05-07 13:56:44-0700 | S0ix Enter 269 | 2024-05-07 13:57:07-0700 | S0ix Exit 270 | 2024-05-07 13:57:07-0700 | Wake Source | GPE # | 3 271 | 2024-05-07 13:59:01-0700 | ACPI Enter | S3 273 | 2024-05-07 13:59:26-0700 | Wake Source | PME - WIFI | 0 274 | 2024-05-07 13:59:26-0700 | ACPI Wake | S3 275 | 2024-05-07 13:59:26-0700 | Wake Source | GPE # | 3 Change-Id: Ie0d6e6c8fefdd081e252ea99d6e3c559a5330b0e Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82234 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-08mb/google/brox/var/brox: increase PsysPmax from 21.5W to 208WLawrence Chang
According to Brox HW design, the PsysPmax is supposed to be 208W. This patch changes PsysPmax setting from 21.5W to 208W. Change-Id: I43f4b00a54dc0dfe6bd690492f9ef92698c9b903 Signed-off-by: Lawrence Chang <lawrence.chang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Shelley Chen <shchen@google.com>
2024-05-08soc/intel/xeon_sp/spr: Refine return value checksShuo Liu
mp_init_with_smm returns cb_err type, where 0 means success and negative values represent error (see cb_err.h). However, failure checks in form of "ret < 0" is not straightforward. Use "ret != CB_SUCCESS" instead. Change-Id: I7e57f2da0361f3109051e9a35b1cce81d559b261 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-05-08mb/asrock/z97_extreme6: Add new mainboardAngel Pons
That's an ATX mainboard with a LGA1150 socket and four DDR3 DIMM slots. Porting was done using autoport and then doing a bunch of manual edits. This board has two socketed DIP-8 SPI flash chips and a physical switch to choose which one should the system boot from. As long as one of them contains a bootable firmware image, it is possible to reflash the other chip using the internal programmer by flipping the switch after booting to OS. Even if one somehow manages to flash unbootable firmware to both chips, they are socketed: one can carefully remove them from the socket and reflash them externally, which is a relatively safe procedure (when compared to in-circuit flashing, especially if the board isn't designed to safely be flashed in-circuit). In short, the board is hard to brick. Haswell MRC.bin cannot be used because it lacks support for the Z97 PCH found on this mainboard. Broadwell MRC.bin only works with Haswell CPUs so far, as raminit fails on Broadwell CPUs for an unknown reason. Maybe it's something about RcvEn, but it's unlikely it can easily be fixed. Working: - All four DIMM slots - Broadwell MRC.bin for raminit purposes - Serial port to emit spam - POST code display - S3 suspend/resume - All rear USB 3.0 ports - Internal USB 2.0 port - Audio output (green jack) - Integrated graphics (libgfxinit) - HDMI - VBT - Intel GbE (I218-V PHY and PCH MAC) - Realtek RTL8111E GbE - At least one SATA port - M2_1 slot (Gen3 x4, bifurcated from CPU) - Flashing internally with flashrom - SeaBIOS (current version) to boot Arch Linux - NCT6791D Super I/O software-based fan control tested using `sensors` and `pwmconfig`, all 6 fan tachometers and 5 PWM outputs work fine. Untested for now (i.e. should work, will eventually test): - DVI-I, DisplayPort - EHCI debug - Front USB 2.0 and 3.0 ports - The other audio jacks (as well as SPDIF) - The other PCIe and M.2 ports - Non-Linux OSes - PS/2 combo port (can only test with a keyboard) Untestable (i.e. cannot test due to unavailable hardware): - Thunderbolt AIC (Add-In Card) support Not working: - Broadwell CPUs, they require more magic to work (working on it). - Booting from ASM1062 SATA ports with SeaBIOS. Other payloads were not tested. It seems that the problem is with the controllers. - Super I/O automatic fan control: not yet implemented in coreboot. To control fans, use software fan control methods in the meantime. - Acer B247Y board driving a FHD panel of a Samsung S24E650 monitor, connected to the board's HDMI output says "Unsupported resolution" after libgfxinit configured the iGPU outputs in linear framebuffer mode. HDMI output works fine after Linux's i915 driver takes over. Not sure if it's specific to the monitor: the HDMI cable is beaten up, and it is hard to replace (need to relocate the logic board so that the ports are accessible). Change-Id: If1d22547725e59f435de36b973e1bf4f334269a9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Máté Kukri <kukri.mate@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-05-08commonlib/timestamp_serialized: Define VB_AUXFW_SYNC_DONE timestampKarthikeyan Ramasubramanian
Define a new timestamp to identify the completion of Auxiliary Firmware Sync. Without that, it gets accounted into a different timestamp ID in a misleading way. BUG=None TEST=Build Brox BIOS image and boot to OS. Confirm the timestamp is recorded in cbmem. Change-Id: Icd01c68a5848e2aed7bbdcc794987bc780e78dab Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com>
2024-05-08mb/samsung/lumpy: Fix smbus subsystem IDMatt DeVillier
The smbus subsystem ID was inadvertently reversed when added in commit eb2897b113a0 ("mb/samsung/lumpy: override SMBus subsystem ID"), so correct it. TEST=build/boot Win10 on lumpy, verify touchpad driver functional. Change-Id: I7520041ea113dff8f2abebfc71a1de6d0f9fc91f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-08mb/google/parrot: Fix smbus subsystem IDMatt DeVillier
The smbus subsystem ID was inadvertently reversed when added in commit 6974bcd28e74 ("mb/google/parrot: override SMBus subsystem ID"), so correct it. TEST=build/boot Win10 on parrot, verify touchpad driver functional. Change-Id: I93d4812e24a6fc7419887e364974fcfae2465ea3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-08mb/google/butterfly: Fix smbus subsystem IDMatt DeVillier
The smbus subsystem ID was inadvertently reversed when added in commit a6076cfcfdbe ("mb/google/butterfly: override SMBus subsystem ID"), so correct it. TEST=build/boot Win10 on butterfly, verify touchpad driver functional. Change-Id: If4a0eae06bbe4dcba893a42797e371bbf9f899b9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82225 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-07mb/google/corsola: Add new board variant SquirtleYang Wu
Add a new Kingler follower 'Squirtle'. BRANCH=corsola BUG=b:333826091 TEST=emerge-corsola coreboot Change-Id: I393738fc470ffc907f125647a46bf81c243708d7 Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-05-07mb/adlink: Remove leftover directoryAngel Pons
These boards are clones of LiPPERT boards, which are no longer in this branch (they were AMD AGESA boards). So, drop the ADLINK placeholders. Change-Id: Idfd77daf4a5b3d1e120ed22f9a48fa1bf884de9e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-05-07soc/intel/meteorlake: Determine TBT controllers exist by VID/DIDKane Chen
The original code uses TRE0-TRE3 register to determine whether or not the TBT controller exists. However, there is a remap in fsp could confuse the TRPx._STA. Ex: Disable TBT controller 0 on b:0 d:7 f:0 Enable TBT controller 1 on b:0 d:7 f:1 The FSP will do the remap and after the remap: TBT controller 1 is on b:0 d:7 f:0 TBT controller 0 is on b:0 d:7 f:1 This is becuase func 0 must exist per pci spec. However, the TRE0-TRE3 will not be remapped so that the ACPI TRPx._STA method could be confused. In such scenario, TRP0._STA will return 0x0, TRP1._STA will return 0xf which is wrong because TBT controller 1 is now at b:0 d:7 f:0 TEST=tested on rex and _TRPx._STA returns correctly. TBT function OK Change-Id: I54f2ea99cd1ec73dd0b71a6ba738aa927b0ae80f Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-05-07soc/intel/mtl: Fixed TBT PCIe devtree remappingKane Chen
The TBT PCIe devicetree settings are not remapped properly when TBT PCIe port 0 is disabled. This code refer SHA:58bc5d937 to remap the PCIe devtree settings properly in case of TBT PCIe port0 is disabled, TEST=Tested on screebo and found "Remapping PCIe Root Port #2 msg" showed up in coreboot log Change-Id: I7c7549ddf8ccdd67d7af7c69f51a84614cff9a03 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81841 Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-07dram/ddr3: Use the same naming convention as DDR4Elyes Haouas
Change-Id: Ifaff19c0117b5247d3321605ccc2e97bf8226ca8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82216 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-07dram/ddr5: Use the same naming convention as DDR{2,3,4}Elyes Haouas
Change-Id: I2cc38926b56315d4a828311917ff58051b34b777 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-07spd.h: Move enum ddr4_module_type to ddr4.hElyes Haouas
Move specific enum ddr4_module_type to <device/dram/ddr4.h>. Change-Id: Ia538d2c73affa6560fa1533a40c02b3677588f5a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-07device/dram/ddr{3,4}: Rename spd_raw_data for specific DDRElyes Haouas
Rename different spd_raw_data[] for DDR3 and DDR4. This is to solve the conflict when we include both "ddr3.h" and ddr4.h" for example here: src/device/dram/spd.c. Otherwise, it won't compile as DDR3 and DDR4 have different spd_raw_data[] size. Change-Id: I46597fe82790410fbb53d60e04b7fdffb7b0094a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 09:37:40 +0000