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2015-06-02vboot: Increase max parsed fw components to 6Furquan Shaikh
With addition of bl31 and trusty, we need to increase the number of parsed fw components in vboot to 6. CQ-DEPEND=CL:273866 BUG=chrome-os-partner:40713 BRANCH=None TEST=Compiles successfully and vboot finds trusty and bl31. Change-Id: I3597e98370bbaef4d2e563c868eed59b2e18adca Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0ff87fdbc7779e6ee410905d1618281411b38a93 Original-Change-Id: Ia403f895b50cc5349bb700d01f62e13c679f68f4 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/273865 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10391 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-06-01amd/torpedo: Remove stale ssdt*.aslVladimir Serbinenko
They're not referenced in the code anywhere. Change-Id: I4805e11523ca7d3cffb484c719f479b7a6ba3e15 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10384 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-01SLIC: Check SLIC signature.Vladimir Serbinenko
Change-Id: I79fd4d17b534274b1e84bc97ca5a2a6ee55e3114 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10383 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-29UEFI: Conditionally define the ASSERT macroLee Leahy
Only define the ASSERT macro when it is not already defined. This change allows the UEFI/FSP definitions to be included with most other coreboot includes. BRANCH=none BUG=None TEST=Build and run on sklrvp Change-Id: Iccfeb83eb1e52623ae0a0fe2a96b587ce61f82d7 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10334 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-29tpm: Add Infineon TPM 1.2 supportSubrata
This patch provides support for TPM Infineon TT1.2 devices by enumerating the TT1.2 ID in the Infineon device list. BRANCH=None BUG=None TEST=Built for sklrvp and tested on RVP3. Change-Id: I9daecc09311477fd9947e829d80abc040b2c9e3d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3ff86f96cb3e2f203dbc86e7004f1a037b98b90a Original-Change-Id: I8b59eba348fc44632e22600646eb0b10eb2f4901 Original-Signed-off-by: Subrata <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/271256 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch@intel.com> Original-Tested-by: Naveenkrishna Ch <naveenkrishna.ch@intel.com> Reviewed-on: http://review.coreboot.org/10302 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
2015-05-29tpm: Fix multiple device supportSubrata
Current TPM driver does not support multiple devices for a given vendor. As the device object never takes the 2nd ID in the list. This patch fixes the same. BRANCH=None BUG=None TEST=Built for sklrvp and tested on RVP3. Change-Id: I82c3267c6c74b22650fc53dc6abdc2eb3daa138e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ff42613f11b4f1a79e907601f1ecb7b83a3aeaab Original-Change-Id: Ieb44735c37208bfe90a8e22e0348dd41c8c642d2 Original-Signed-off-by: Subrata <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/271727 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch@intel.com> Original-Tested-by: Naveenkrishna Ch <naveenkrishna.ch@intel.com> Original-Commit-Queue: Pravin K Angolkar <pravin.k.angolkar@intel.com> Original-Tested-by: Pravin K Angolkar <pravin.k.angolkar@intel.com> Reviewed-on: http://review.coreboot.org/10303 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
2015-05-29intel/broadwell: Hide use of acpi_slp_typeKyösti Mälkki
Change-Id: I106779571df5168ec358ad1cc4dc4195639a7a7d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10359 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-29binaryPI: Hide use of acpi_slp_typeKyösti Mälkki
Change-Id: I867932db4388eb078b69b6f42c82967777d45d79 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10358 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-29x86 SMM: Merge recipesKyösti Mälkki
Change-Id: I35244ebd56e1653109f7cf68ed26a42035c17cc2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10367 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-29x86 SMM: We have single SMM linker script nowKyösti Mälkki
Change-Id: I0c20b674b536a2964962f84228f681b53dc114dc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10366 Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Tested-by: build bot (Jenkins)
2015-05-29bd82x6x: Move calling of finalize() on resume to southbridge codeVladimir Serbinenko
Change-Id: I6416cd5780fbda0b3c2e236ce98a9f9a508e70c6 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10293 Tested-by: build bot (Jenkins) Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2015-05-29smm: Remove dead smm_tseg.ldVladimir Serbinenko
Change-Id: I231e59d3b9c3ebf6e058917613221892fc880fa1 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10365 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-05-29Remove whitespace at the end of line.Vladimir Serbinenko
Change-Id: Ie9c3ef9fb4b3b2a0450a56e1d752b6509fa72a86 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10364 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2015-05-29intel/nehalem/raminit.c: Remove space in `timestamp_add_now(104)`Paul Menzel
Fix up commit c6f6be09 (Support for nehalem northbridge) to follow the coreboot/Linux kernel coding style. Change-Id: Ibf4f272ad54e6fef0b297189651f2bcf888b5b26 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/10347 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-05-29smmrelocate: Remove dead TSEG code.Vladimir Serbinenko
Change-Id: I786dd8295d310bfd21db49cfbe5ea39675b25b68 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10361 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-05-29i82801gx: Reserve LPC decodes.Vladimir Serbinenko
This change makes sure that LPC controller declares resources that it actually decodes. bd82x6x already does it but i82801gx doesn't leading to allocator potentially allocating something else to the same range. Change-Id: Ieca9852e54c08e31d4d41aea97f317d9a6919806 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7662 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-29x230: Clean up smihandler.cVladimir Serbinenko
Remove dead code and dead includes. Change-Id: I5564ebfbbef6f65c275c2f94f75724f4e36472db Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10349 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-29lenovo: Move pc_keyboard_init to h8 init.Vladimir Serbinenko
PS/2 emulation is part of H8, so should be inited in relevant files. Change-Id: Ie873ea7f6f88f68f622351799462d0b000d17585 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10348 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-05-29nvs: Add missing stdint.h include.Vladimir Serbinenko
nvs.h uses u8 without including stdint.h. Change-Id: I4ffcbb850cb7b8f47126ee1906b9e0960dd449e8 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10331 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-29h8: Add missing include of stdint.hVladimir Serbinenko
h8.h uses u8 without including stdint.h. Change-Id: I7e46f6b8ca92ed23af93597fe2f08add464eb176 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10330 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-29Remove leftover smi_get_tseg_baseVladimir Serbinenko
Change-Id: I8e694f37c8709efd702208aa005096ebf1f3abb5 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10356 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-29chromeos: always enable timestampsStefan Reinauer
Timestamps should not be forced on by a subset of chipsets. However, they are a requirement on Chrome OS platforms, so have CONFIG_CHROMEOS select it. Change-Id: I408c6b17aa8721a3abec69020084174e414a8940 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/10357 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-05-28smm: Merge configs SMM_MODULES and SMM_TSEGVladimir Serbinenko
SMM_TSEG now implies SMM_MODULES and SMM_MODULES can't be used without SMM_TSEG Remove some newly dead code while on it. Change-Id: I2e1818245170b1e0abbd853bedf856cec83b92f2 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10355 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-28Remove leftover tseg_relocateVladimir Serbinenko
Change-Id: I534f992ed479c7cdc049bd598259b1f1cf2953b9 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10354 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-28Migrate fsp_206ax to SMM_MODULESVladimir Serbinenko
This gets rid of ugly tseg_relocate for fsp_bd82x6x. This is adaptation of a3e41c089602c58409e8dfd4aceecbdd7d4f4a5b Change-Id: I4e80e6e98d3a6da3e3e480e9368fae1b3ed67cd6 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10353 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-28Migrate 2065x to SMM_MODULESVladimir Serbinenko
This gets rid of ugly tseg_relocate for ibexpeak. This is backport of 29ffa54969414b833de5c61b507b061f920d650b to ibexpeak. Change-Id: I456d85abdbadb2fdccf77ca771e2518cf8b8c536 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10352 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-28Migrate 206ax to SMM_MODULESVladimir Serbinenko
This gets rid of ugly tseg_relocate for bd82x6x. This is backport of 29ffa54969414b833de5c61b507b061f920d650b to bd82x6x. Change-Id: I0f52540851ce8a7edaac257a2aa83d543bb5e530 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10351 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-28x230: Fix headset microphone support.Vladimir Serbinenko
Previously only internal mic really worked but since it's of good quality it's not really noticeable. Change-Id: Ie14c377b0370302d97e1f89eae5787e05e73b7d2 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10286 Tested-by: build bot (Jenkins) Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2015-05-28intel: Remove pstate_coord_type.Vladimir Serbinenko
Not used anywhere. Change-Id: I9bab092d285aaebdf9283ba08e23197f9785b3a6 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10329 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2015-05-28igd.asl rewriteVladimir Serbinenko
Old igd.asl had inconsistent addresses (between _DOD and actual device) and ghost devices. Any of those is enough to make brightness on windows fail and make igd.asl out-of-ACPI-spec. Also old code favoured ridiculous copying of the same thing 6 times per chipset. Leave only hooking up and chipset-specific part in chipset directory. Move NVS handling and ACPI-spec parts to a common file. Change-Id: I556769e5e28b83e7465e3db689e26c8c0ab44757 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7472 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-05-28Add TCPA table.Vladimir Serbinenko
This allows SeaBIOS to fill it as necessary. This is needed to make BitLocker work. Change-Id: I35858cd31a90c799ee1a240547c4b4a80fa13dd8 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10274 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-28Remove address from GPLv2 headersPatrick Georgi
Follow up for commit b890a12, some contributions brought back a number of FSF addresses, so get rid of them again. Change-Id: I0ac0c957738ce512deb0ed82b2219ef90d96d46b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10322 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-05-27Deactivate TPMVladimir Serbinenko
Just not exporting TPM isn't good enough as it can still be accessed. You need to send it a deactivate command. Change-Id: I3eb84660949c2d1e2b492d541e01d4ba78037630 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10270 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-27x201: Add TPM declaration.Vladimir Serbinenko
This allows to deactivate TPM on X201. Change-Id: Ic085db6cc2c57668e7a4fdbc7440735c806cc256 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10278 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
2015-05-27x230: Add TPM declaration.Vladimir Serbinenko
This allows to deactivate TPM on X230. Change-Id: I73d4272da62335ec3766ce4814d5b46538b190fe Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10273 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
2015-05-27sandybridge native: Add call to TPM code.Vladimir Serbinenko
This allows to deactivate TPM on boards using native sandy/ivy init. Change-Id: I9455179c7b51097a3a9554c16a407365fbc65e6f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10272 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
2015-05-27Move TPM code out of chromeosVladimir Serbinenko
This code is not specific to ChromeOS and is useful outside of it. Like with small modifications it can be used to disable TPM altogether. Change-Id: I8c6baf0a1f7c67141f30101a132ea039b0d09819 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10269 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-27AGESA binaryPI: Drop XIP_ROM_BASEKyösti Mälkki
Did we not get rid of this in 2011? Change-Id: I82cd7f0989e5d38e4a3b0067e471f7acdfd47543 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10321 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-27Copy gizmosphere/gizmo2 as bap/ode_e20XXKyösti Mälkki
Change-Id: I54a4719c571e18eb38a47e50ea69a4a85195d4dc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10320 Tested-by: build bot (Jenkins)
2015-05-27AGESA: Reduce SPI use by 24kB for S3 supportKyösti Mälkki
There is no need to backup VolatileStorage in SPI flash at all. At the time we need it, we have CBMEM available. Change-Id: If0ca57b314140a833d6d59fe9e236e07816f05a4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10318 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-27AGESA: Separate HeapManager declarations from BiosCallOutsKyösti Mälkki
Change-Id: I168db92b10d5abc05be2dc374df3f892003d5255 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10317 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-27AGESA: Split S3 backup in CBMEMKyösti Mälkki
Use separate CBMEM allocations for stack and heap on S3 resume path. The allocation of HIGH_SCRATCH_MEMORY is specific to AGESA and is moved out of globals and ACPI. This region is a replacement for BIOS_HEAP_SIZE used on non-resume paths. Change-Id: I6658ce1c06964de5cf13b4e3c84d571f46ce76f3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10316 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-27arm64: Add weak implementation of soc_get_bl31_plat_paramsFurquan Shaikh
This function is required to be implemented by SoC only if some platform specific parameters are to be passed in from the early bootloader to bl31 component. BUG=chrome-os-partner:40414 BRANCH=None TEST=Compiles successfully. Change-Id: I6e76a0b6735267971e12aa72a987e8d83f5ad102 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6ab8bc12ffc2ee5bf69cef68bae852dcbf7ccb98 Original-Change-Id: If55aaee8d18a8045a5d842145c0e2c97a37a8bca Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/272377 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10308 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-05-27arm64: Remove PLAT= variable initialization based on Kconfig variableFurquan Shaikh
Each SoC should have a BL31_MAKEARGS += ... defining all the make arguments required for bl31 component compilation. BUG=chrome-os-partner:40414 BRANCH=None TEST=Compiles successfully and boots into bl31. Change-Id: I20383ab61d012f7294d969f196044a5f1c07dfc1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 72bd297994248a9d96acc6f21d06bb6ff0d5292c Original-Change-Id: I1ddd5c38e9214021d857d9d586310e23fa4114e0 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/272430 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10309 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-05-27arm64: Pass in CROSS_COMPILE_arm64 for ARM TF compilationFurquan Shaikh
BUG=chrome-os-partner:40414 BRANCH=None TEST=ATF compilation successful Change-Id: Ib4eeced911181f756bd47c19eeb2d196ab5a0a2f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3061a219c24294a9fec4f26fc60b02f67bb55d66 Original-Change-Id: I39849d4048d7333eeab9bd698b4fd496181081a2 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/272374 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10307 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-05-27veyron_brain: Remove unused USB GPIOsDavid Hendricks
Brain doesn't have HOST1_PWR_EN (GPIO0_B3) and 5V_DRV (GPIO7_C5). The only USB power enable pin connected to the AP is USB2_PWR_EN (GPIO0_B4) which controls power for both the physical type-A ports. BUG=none BRANCH=none TEST=built and booted on Brain, both USB host mode ports work Change-Id: Iea371926c7dcd111aa2e671a15fe97a3519bfc04 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4db71095a5116666cd27aedb09b4f02557362346 Original-Change-Id: Ibbb4b9b424156eb3db1ccfdd948050c1c067ad3c Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/271309 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10305 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@google.com>
2015-05-26vboot: move to region_devicesAaron Durbin
Now that vboot is using offsets for everything remove the pass through vboot_get_region() and use region_devices as first class citizens. Change-Id: I1a86f3725e5bce38e6ca31e9641b1a8f4ac50e96 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10225 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-26fmap: new API using region_deviceAaron Durbin
Instead of being pointer based use the region infrastrucutre. Additionally, this removes the need for arch-specific compilation paths. The users of the new API can use the region APIs to memory map or read the region provided by the new fmap API. Change-Id: Ie36e9ff9cb554234ec394b921f029eeed6845aee Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9170 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-26vboot: use only offsets for tracking firmware componentsAaron Durbin
Because of the fmap API returning pointers to represent regions within the boot device a vboot_region structure was used to track the case where offsets could be pointers on x86 but not on !x86. Normalize this tracking to use offsets only as it provides consistency in the code. Change-Id: I63c08b31ace3bd0e66ebc17e308f87eb5f857c86 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10221 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-26cbfs: remove unused CBFS_HEADER_ROM_OFFSET optionAaron Durbin
The CBFS_HEADER_ROM_OFFSET went away. Remove remaining defintions that are not used. Change-Id: Ibedce988143f0b7167cea1b27de5b33698b5d82b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10217 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-26coreboot: introduce boot_deviceAaron Durbin
The boot_device is a region_device that represents the device from which coreboot retrieves and boots its stages. The existing cbfs implementations use the boot_device as the intermediary for accessing the CBFS region. Also, there's currently only support for a read-only view of the boot_device. i.e. one cannot write to the boot_device using this view. However, a writable boot_device could be added in the future. Change-Id: Ic0da796ab161b8025c90631be3423ba6473ad31c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10216 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-26pistashio: bump up romstage sizeAaron Durbin
Making large changes in pieces is leading to a little bloat. Bump up the romstage size temporarily so that jenkins will be happy. Change-Id: I6f9facb4ca488cf41741a3ed6d0ed7f66d4778b3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10220 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-26Make acpi_fill_hest into parameterVladimir Serbinenko
This avoids the need to supply weak function and avoids associated risks of forgetting to link in relevant files. Change-Id: Ie96475babb4aa4ea8db49023af5b31bfa63b21dc Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7373 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2015-05-26acpigen: Remove all explicit length trackingVladimir Serbinenko
Change-Id: I88248d78c01b4b4e42a097889b5f4ddfdac3d966 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7367 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2015-05-26acpigen: Remove acpigen_patch_lenVladimir Serbinenko
Change-Id: I77276342b3f44c7c845a10682ff1f15599c4c721 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7365 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2015-05-26pcengines/apu1: Enable HAVE_ACPI_RESUMEKyösti Mälkki
Note: apu1c models do not support this. That we expose S3 in ACPI table while it is not available, is a wider issue to solve. Change-Id: I9b07550d0523593f51c1882a40cccd783115057b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10315 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-26AGESA: Halt on S3 resume failureKyösti Mälkki
Change-Id: Ib6ac8ab3aca991fa623fedcd87a20470248d58e4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10298 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-26AGESA: Split S3 support fileKyösti Mälkki
Separate it to low-memory backup in romstage and MTRR recovery in ramstage. How much of the MTRR part we really need will be resolved later. Change-Id: Ic64b3f74cf6ef0954eda6e84754745de81c465b2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8607 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-26AGESA: Refactor OEM S3 storageKyösti Mälkki
Use function prototypes that match more closely with the structure of other OEM hooks in agesawrappers. Change-Id: Id241fdce78a21a5138ef60ac2f841b694da92241 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8606 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-26AGESA: Move S3 related SPI writes againKyösti Mälkki
This is more agesawrapper-related code than CPU. Change-Id: I3058ef965a83aed1972e02f0f566f81d5dbd7adf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10295 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-26cbmem: remove cbmem_set_top()Aaron Durbin
Now that the users of cbmem_set_top() always provide a consistent cbmem_top() value there's no need to have cbmem_set_top() around. Therefore, delete it. Change-Id: I0c96e2b8b829eddbeb1fdf755ed59c51ea689d1b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10314 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-05-26CBMEM console: Fix buffer without EARLY_CBMEM_INITKyösti Mälkki
On S3 resume, CBMEM_ID_CONSOLE from previous boot is found in ramstage, even when romstage did not create it. So buffer did not get cleared on S3 resume path. Also do not allocate for preram_cbmem_console in CAR when there are no means to back it up to ram. Change-Id: I175cebbb938adf2a7414703fefffb8da796e9fa9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10301 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-05-26timestamp: Fix collection without EARLY_CBMEM_INITKyösti Mälkki
With LATE_CBMEM_INIT, do not search for the initial collection from CBMEM in ramstage. On S3 resume this would find the non-empty collection from previous run of ramstage. Start with an empty table instead. Remove a spurious error message as the stamps get stashed and will be copied to CBMEM later. Change-Id: Ib94049531c0ac23af25407bd2ca7644ee0163d69 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10300 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-26CBMEM: Fix S3 resume path without EARLY_CBMEM_INITKyösti Mälkki
Implementation for cbmem_find() did not work for boards without EARLY_CBMEM_INIT in romstage. This is required for S3 resume to work on AGESA plaforms. First broken with commit 0dff57d cbmem: switch over to imd-based cbmem Change-Id: I9c1a4f6839f5d90f825787baad2a3824a04b5bdc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10299 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-05-26x86: provide consistent cbmem_top() for CONFIG_LATE_CBMEM_INITAaron Durbin
For x86 systems employing CONFIG_LATE_CBMEM_INIT, set_top_of_ram() is called in ramstage to note the upper address of the 32-bit address space. This in turn is consumed by cbmem. However, in this scenario cbmem_top() cannot always be relied upon because get_top_of_ram() doesn't return the same value provided to set_top_of_ram(). To fix the inconsistency in ramstage save the value passed in to set_top_of_ram() and defer to it as the return value for cbmem_top(). Change-Id: Ida796fb836c59b9776019e7f8b3f2cd71156f0e5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10313 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2015-05-26consoles: remove unused infrastructureAaron Durbin
The __console attribute as well as linker binding was dropped at some point. Kill of the dead code and infrastructure. Change-Id: I15e1fb4468fffe2e148ec9ac8539dfd958551807 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10279 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-05-26AGESA f16kb: Fix PCI device notationFabian Kunkel
Old file defines wrong PCI devices (1.2 2.2 3.2 4.2 5.2). Wrong defines cause PCI devices not to be found in the pirq_data table. Example error output: PCI IRQ: Found device 0:02.01 using PIN A PCI Devfn (0x11) not found in pirq_data table PCI IRQ: Found device 0:02.02 using PIN B Found this device in pirq_data table entry 3 Orig INT_PIN : 2 (PIN B) PCI_INTR idx : 0x02 (INTC# ) INT_LINE : 0xA (IRQ 10) PCI IRQ: Found device 0:02.03 using PIN C PCI Devfn (0x13) not found in pirq_data table PCI IRQ: Found device 0:02.04 using PIN D PCI Devfn (0x14) not found in pirq_data table PCI IRQ: Found device 0:02.05 using PIN A PCI Devfn (0x15) not found in pirq_data table Patch fixes, that pirq_data entries for pci devices 2.1 - 2.5 get found. Change-Id: I4503433427f4ec90d022b65084c52077ba4f3511 Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com> Reviewed-on: http://review.coreboot.org/10289 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2015-05-26speedstep: Don't supply weak get_cst_entries.Vladimir Serbinenko
This should be overriden by mobo even if it's no-op override. weak function in this case would only hide real problems. Change-Id: I30dd671eb605b490a51153d00ae308c4bdef3d05 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7368 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-26ACPI: slic supportVladimir Serbinenko
Export SLIC table from file in CBFS. Change-Id: Id0e7fe0a49b9cd50b5e43cd15030e1c2098728ec Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7202 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-05-26gm45: Link cstates.c rather than including it.Vladimir Serbinenko
The comment about necessity of include isn't true anymore as get_cst_entries is not weak anymore so if it's not found, the linking would fail. Change-Id: I4bf88208d63ac3e625f464c3907e2e1ea575dd9f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7375 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-05-26acpi: Remove monolithic ACPIVladimir Serbinenko
All boards now use per-device ACPI. This patch finishes migration by removing transitional kludges. Change-Id: Ie4577f89bf3bb17b310b7b0a84b2c54e404b1606 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7372 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-05-26bd82x6x: Merge common platform ASL code.Vladimir Serbinenko
This code in reality just describes the southbridge features, don't put a copy in every mainboard. Change-Id: I8cf3019a36b1ae6a17d502e7508f36ea9fa62830 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10231 Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Tested-by: build bot (Jenkins)
2015-05-24binaryPI boards: Minor fixups to unify boardsKyösti Mälkki
Some missing static declarations and whitespace on the console. Change-Id: I1af59dbfb1396297bd671b43d9326dffdd7f59d4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10284 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-24AGESA binaryPI boards: Drop annoying commentaryKyösti Mälkki
Same comments were already removed for the latest board, the amd/lamar. Change-Id: Ie244f838409c567c11f7444c9cf17de72e49dbb0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10283 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-23baytrail: Switch to per-device ACPIVladimir Serbinenko
Change-Id: I6a1b1daa291298c85e14f89aa47a0693837cec6f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7037 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2015-05-23Hide TPM_TIS_BASE_ADDRESSVladimir Serbinenko
TPM_TIS_BASE_ADDRESS is technical setting, shouldn't be user-visible. Change-Id: Ibf74f52be16fb7d2cfa78419087a4c3e7607368a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10271 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
2015-05-23AGESA fam15x fam16x: Remove HAVE_ACPI_RESUMEKyösti Mälkki
Implementation corrupts low-memory on S3 resume path, rendering OS unstable. AMD was never able to pinpoint a revision that did not have the issue. Change-Id: I9656ac1bfe1412775a6152b9f995c4d4ebf57159 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10285 Reviewed-by: Rudolf Marek <r.marek@assembler.cz> Tested-by: build bot (Jenkins)
2015-05-23AGESA: Drop CPU_SOCKET_TYPEKyösti Mälkki
Not referenced anywhere. Change-Id: I5d1dd8d712d5443f30c96043c223d2fc844b587f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10282 Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-23AGESA: Drop EXT_RT_TBL_SUPPORTKyösti Mälkki
Not referenced anywhere. Change-Id: I66c5f2948145666721c9033b82f23f7c37ac1884 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10281 Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-23AGESA: Drop DIMM_SUPPORT, _DDR3 and _REGISTEREDKyösti Mälkki
Not referenced anywhere. Change-Id: I57180ccfab93e45df9982d08bad71834a04eb9f9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10280 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-23Braswell: Use Baytrail as Comparison BaseLee Leahy
Add baytrail source for comparison with Braswell. BRANCH=none BUG=None TEST=None Change-Id: I5170addf41676d95a3daf070a32bcee085f8156d Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10117 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-23drivers/intel: Update FSP 1.1 DriverLee Leahy
Update the FSP driver files from 1.0 to 1.1. Updates will occur manually to these files only for FSP 1.1 support. An fsp_x_y should be added in the future to support newer versions of the FSP specification. Please note that due to the interface with EDK2, these files make references to data structures and fields that use CamelCase. BRANCH=none BUG=None TEST=Build for Braswell or Skylake boards using FSP 1.1. Change-Id: I2914c047d786a3060075356783ac9758bc41f633 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10049 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-21Kill ENABLE_TPM.Vladimir Serbinenko
It's used only in P470 and lynxpoint machines. Remove it from other southbridges. New machines should use src/drivers/pc80/tpm. Change-Id: I4741e76df4c6204d65562f016abac9ed60558432 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10268 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-05-21lenovo: Remerge smbios_mainboard_bios_version.Vladimir Serbinenko
Change-Id: I8df5b7f6707957b925f7bb4dc06a717252c70868 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10275 Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Tested-by: build bot (Jenkins)
2015-05-21Remove unused functionsPatrick Georgi
acpi_fill_slit and acpi_fill_srat were removed in commit 5e597572e. Take care of the boards that were added in the mean time. Change-Id: I907e51de5d4ce9acfcce82e6bb30eefff312d35d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10266 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-05-20acpi: make fill_slit and fill_srat into arguments.Vladimir Serbinenko
SLIT and SRAT are created this way only on amdk8 and amdfam10. This saves the need of having a lot of dummies. Change-Id: I76d042702209cd6d11ee78ac22cf9fe9d30d0ca5 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7052 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-20Remove noop smihandler.c in several mainboards.Vladimir Serbinenko
Change-Id: I14e381e1f1c825699063ca3df20e450f7510b040 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10263 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-20bd82x6x: Merge common apmc finalize procedure.Vladimir Serbinenko
Change-Id: I9c938b8a69479fae6b0eb99d1135f1caaf26d0e2 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10227 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-20build system: use archives, not linker action to shorten command linesPatrick Georgi
Intermediate linking may distort linker behavior (in particular related to weak symbols). The idea is that archives are closer to 'just a list of object files', and ideally makes the linker more predictable. Using --whole-archive, the linker doesn't optimize out object files just because their symbols were already provided by weak versions. However it shouldn't be used for libgcc, because that one has some unexpected side-effects. Change-Id: Ie226c198a93bcdca2d82c02431c72108a1c6ea60 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10139 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-05-19superio/nuvoton: Add support for Nuvoton NCT6779DMatt DeVillier
Add support for Nuvoton NCT6779D, using NCT6776 as a baseline Change-Id: I020a21267f7e30bdea4bb5f83d67bd94082fdf05 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: http://review.coreboot.org/10232 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-05-19intel/haswell: Drop MONOTONIC_TIMER_MSRPatrick Georgi
The variable was set on all haswell boards, so we can do it like on broadwell where the MSR based timer is assumed to be around, too. Change-Id: Id48ad7454d4cf83c3b1616b64687cdcfee4baa10 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10256 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-05-19Remove Kconfig variable that has no effectPatrick Georgi
DYNAMIC_CBMEM is only selected a couple of times but never declared or read. Remove it. Change-Id: I5016dac2c935d3f261001e9f388a8989540e93ae Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10255 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-05-19Remove Kconfig variable that has no effectPatrick Georgi
MAINBOARD_HAS_BOOTBLOCK_INIT is only declared once and selected elsewhere (with no overlap), and never read. Remove it. Change-Id: Ica1f16182b556dbf4a3b747237af74bcc4c0608c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10254 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-05-19Remove Kconfig variable that has no effectPatrick Georgi
CPU_HAS_BOOTBLOCK_INIT is only declared once and selected elsewhere (with no overlap), and never read. Remove it. Change-Id: I3f294b0724a87876a7e2f274e6933fe10321a69d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10253 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-05-19arm64: Make SPSR exception masking on EL2 transition explicitJulius Werner
The configuration of SPSR bits that mask processor exceptions is kinda oddly hidden as an implict part of the transition() function right now. It would be odd but not impossible for programs to want to be entered with enabled exceptions, so let's move these bits to be explicitly set by the caller like the rest of SPSR instead. Also clear up some macro names. The SPSR[I] bit is currently defined as SPSR_IRQ_ENABLE, which is particularly unfortunate since that bit actually *disables* (masks) interrupts. The fact that there is an additional SPSR_IRQ_MASK definition with the same value but a different purpose doesn't really help. There's rarely a point to have all three of xxx_SHIFT, xxx_MASK and xxx_VALUE macros for single-bit fields, so simplify this to a single definition per bit. (Other macros in lib_helpers.h should probably also be overhauled to conform, but I want to wait and see how many of them really stay relevant after upcoming changes first.) BRANCH=None BUG=None TEST=None Change-Id: Id126f70d365467e43b7f493c341542247e5026d2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 715600c83aef9794d1674e8c3b62469bdc57f297 Original-Change-Id: I3edc4ee276feb8610a636ec7b4175706505d58bd Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/270785 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10250 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-19arm64: Add support for using ARM Trusted Firmware as secure monitorJulius Werner
This patch adds support for integrating the runtime-resident component of ARM Trusted Firmware (github.com/ARM-software/arm-trusted-firmware) called BL31. It expects the ARM TF source tree to be checked out under $(top)/3rdparty/arm-trusted-firmware, which will be set up in a later patch. Also include optional support for VBOOT2 verification (pretty hacky for now, since CBFSv1 is just around the corner and will make all this so much better). BRANCH=None BUG=None TEST=Booted Oak with ARM TF and working PSCI (with additional platform patches). Change-Id: I8c923226135bdf88a9a30a7f5ff163510c35608d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a1b3b2d56b25bfc1f3b2d19bf7876205075a987a Original-Change-Id: I0714cc10b5b10779af53ecbe711ceeb89fb30da2 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/270784 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10249 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-19arm64: Reorganize payload entry code and related KconfigsJulius Werner
This patch slightly reorganizes arm64/boot.c with the aim of being more readable: Make more obvious that there's no code execution here after payload_entry. [pg: taken from patch linked below] Change-Id: Ia341e5d290b10ad5ba3edb349b8a7f619022d99f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/270783 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10247 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-19arm64: Reorganize payload entry code and related KconfigsJulius Werner
This patch slightly reorganizes arm64/boot.c with the aim of being more readable: we need to sync the i-cache in both code paths, so do it in a single location. [pg: taken from patch linked below] Change-Id: Iab173acfc6d66e4dccb6f6ab916aea2007632bfd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/270783 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10246 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-19arm64: Reorganize payload entry code and related KconfigsJulius Werner
This patch slightly reorganizes arm64/boot.c with the aim of being more readable: Make spintable handling optional through a kconfig flag. [pg: taken from patch linked below] Change-Id: I64610640835473fcc3d9eff01feb5f861b753eb8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/270783 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10245 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 12:04:30 +0000